CN117949803A

CN117949803A - ZQ calibration method, circuit, semiconductor device and test equipment

Info

Publication number: CN117949803A
Application number: CN202211281254.6A
Authority: CN
Inventors: 刘志扬; 田凯; 顾勋
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2024-04-30
Also published as: WO2024082566A1

Abstract

The application relates to a ZQ calibration method, a circuit, a semiconductor device, a test apparatus, and a computer-readable storage medium. When the ZQ calibration method is applied to a wafer-level semiconductor chip, the method comprises the following steps: after the target chip is powered on, identifying whether the target chip is set as a main chip; selecting a corresponding calibration mode to perform ZQ calibration on the target chip according to the identification result of the target chip; switching master-slave chip settings of the target chip in a test mode; and performing calibration again on the target chip. The application can effectively improve the calibration function.

Description

ZQ calibration method, circuit, semiconductor device and test equipment

Technical Field

The present application relates to the field of integrated circuit technology, and in particular, to a ZQ calibration method, a circuit, a semiconductor device, a test apparatus, and a computer readable storage medium.

Background

In order to realize stronger system operation, the requirements on the capacity and the operation speed of the memory device are higher and higher, so as to solve the problem that the capacity and the processing speed of a single memory chip are limited, a multi-chip parallel transmission and a multi-channel high-bandwidth memory system are generated, but the multi-channel memory system can reduce the signal quality, and in order to reduce the influence of the reflection and the crosstalk of IO on the signal integrity, an on-chip terminal circuit is used for reducing the signal noise, improving the impedance matching degree on a signal path and preventing the signal from forming reflection on the circuit.

However, the resistance value of ODT resistance varies greatly with factors such as temperature, so ZQ calibration needs to be introduced into a memory chip to calibrate ODT resistance, but the conventional ZQ calibration method has poor calibration function, and the ZQ calibration method needs to be improved.

Disclosure of Invention

Based on this, it is necessary to provide a ZQ calibration method, a circuit, a semiconductor device, a test apparatus, and a computer-readable storage medium in view of the above-described technical problems.

A ZQ calibration method applied to a wafer level semiconductor chip, the method comprising:

After the target chip is powered on, identifying whether the target chip is set as a main chip;

selecting a corresponding calibration mode to perform ZQ calibration on the target chip according to the identification result of the target chip;

switching master-slave chip settings of the target chip in a test mode;

And performing calibration again on the target chip.

In one embodiment, the identifying whether the target chip is set as the master chip after the target chip is powered up includes:

And identifying a first parameter value of the target chip, and determining whether the target chip has completed the main chip programming setting.

In one embodiment, the selecting a corresponding calibration mode to perform ZQ calibration on the target chip according to the identification result of the target chip includes:

When the target chip is set as a main chip, performing main chip ZQ calibration on the target chip in a first parameter triggering mode;

And when the target chip is not set as the master chip, executing slave chip ZQ calibration on the target chip in a receiving triggering mode.

In one of the embodiments of the present invention,

The switching of the master-slave chip setting of the target chip in the test mode includes:

when the target chip is not set as the master chip, the target chip is switched from the slave chip to the master chip by changing a second parameter value of the target chip in a test mode.

In one of the embodiments of the present invention,

The performing calibration again on the target chip includes:

And after the target chip is switched from the slave chip to the master chip, executing master chip ZQ calibration on the target chip in a second parameter triggering mode.

In one embodiment, after performing the master chip ZQ calibration on the target chip, the method further includes:

in a background mode, executing main chip ZQ calibration on the target chip in a clock triggering mode at intervals of preset time intervals; and/or the number of the groups of groups,

And in a command mode, executing main chip ZQ calibration on the target chip in a calibration command triggering mode.

In one of the embodiments of the present invention,

The switching of the master-slave chip setting of the target chip in the test mode further includes:

When the target chip is set as a master chip, in a test mode, switching the target chip from the master chip to a slave chip by changing a third parameter value of the target chip;

the performing calibration again on the target chip further includes:

And after the target chip is switched from the master chip to the slave chip, executing the slave chip ZQ calibration on the target chip in a receiving triggering mode.

A ZQ calibration method applied to a multi-chip package structure, the method comprising:

After the packaging structure is powered on, determining a main chip from a plurality of chips of the packaging structure;

performing primary master chip ZQ calibration on the master chip;

After the main chip ZQ calibration is completed, performing secondary chip ZQ calibration on other chips until all chips complete one-time ZQ calibration;

Switching the master chip to a slave chip, and switching any other slave chip to the master chip;

after the master-slave chip setup switch is completed, ZQ calibration is performed once again for all chips.

In one of the embodiments of the present invention,

After powering up the package structure, determining a master chip from a plurality of chips of the package structure, comprising:

Identifying a first parameter value of a chip in the packaging structure, and determining whether a main chip programming setting is finished for the chip in the packaging structure;

When the main chip programming setting is finished by chips in the packaging structure, determining the chips which are finished by the main chip programming setting as main chips;

when all the chips do not complete the programming setting of the master chip, under the test mode, changing the second parameter value of one chip in the packaging structure to set the second parameter value as the master chip, and the other chips as the slave chips.

In one of the embodiments of the present invention,

The performing primary chip ZQ calibration on the primary chip includes:

when a chip with the completed main chip programming setting is determined to be a main chip, performing primary main chip ZQ calibration on the main chip in a first parameter triggering mode;

When the main chip is set through the test mode, the main chip ZQ calibration is executed once on the main chip through a second parameter triggering mode.

In one embodiment, all chips in the packaging structure are sequentially cascaded, and the last chip is connected with the first chip;

After the master chip ZQ calibration is completed, performing slave chip ZQ calibration on other chips until all chips complete once ZQ calibration, including:

When the master chip ZQ calibration is finished, the master chip sends a ZQ calibration pulse signal to a next chip, the next chip executes a secondary chip ZQ calibration in a receiving triggering mode, and after the secondary chip completes the secondary chip ZQ calibration, the next chip sends a ZQ calibration pulse signal to an adjacent next chip to instruct the adjacent next chip to execute the secondary chip ZQ calibration once;

and repeating the transmission process of the ZQ calibration pulse signals among the cascaded chips until the main chip receives the ZQ calibration pulse signals transmitted by the previous stage of chips, and indicating all the chips to finish one-time ZQ calibration.

In one embodiment, after performing the primary chip ZQ calibration on the primary chip and before switching the primary chip to a secondary chip and any other secondary chip to a primary chip, the method further includes:

In a background mode, executing master chip ZQ calibration on a current master chip in a clock triggering mode at preset time intervals, and sequentially executing slave chip ZQ calibration on other chips; and/or the number of the groups of groups,

In the command mode, the master chip ZQ calibration is executed on the current master chip in a calibration command triggering mode, and the slave chips ZQ calibration is sequentially executed on other chips.

In one embodiment, the switching the master chip to the slave chip and any other slave chip to the master chip includes:

And under a test mode, changing a third parameter value in the master chip mode register, switching the master chip into a slave chip, selecting any slave chip as a target slave chip, and changing a second parameter value in the target slave chip mode register to switch the target slave chip into the master chip.

In one of the embodiments of the present invention,

And sequentially switching all chips in the packaging structure into main chips, respectively starting from the switched main chips after each switching, and executing ZQ calibration on all the chips once.

In one embodiment, after completing the master-slave chip setup switch, the ZQ calibration is performed once again for all chips, including:

After the master-slave chip setting switching is completed, the master chip ZQ calibration is executed once on the switched master chip, and the slave chips ZQ calibration is executed on other chips in sequence until all the chips complete the ZQ calibration once.

A ZQ calibration circuit comprising:

the identification module is used for identifying master-slave chip arrangement of the chips;

the calibration module is used for executing master chip ZQ calibration and slave chip ZQ calibration;

and the switching module is used for switching the master-slave chip settings of the chip.

In one of the embodiments of the present invention,

The switching module comprises a mode register, wherein the mode register is used for storing a first parameter value, a second parameter value and a third parameter value of the chip;

The identification module comprises a reading circuit, wherein the reading circuit is connected with the mode register and is used for reading the first parameter value, the second parameter value and the third parameter value to identify master-slave chip settings;

The calibration module includes:

The calibration control unit is connected with the reading circuit and used for generating a calibration control signal according to the first parameter value, the second parameter value and the third parameter value; when the first parameter value and the third parameter value are both first level values, or the second parameter value is the first level value, the calibration control signal generated by the calibration control unit is a first enabling signal; otherwise, the calibration control signal generated by the calibration control unit is a second enabling signal;

The main chip triggering unit is connected with the calibration control unit and is used for receiving the first enabling signal to trigger and execute the main chip ZQ calibration;

the slave chip triggering unit is connected with the calibration control unit and is used for receiving the second enabling signal to trigger the execution of the slave chip ZQ calibration;

And the calibration unit is connected with the master chip trigger unit and the slave chip trigger unit and is used for receiving the enabling signal of the master chip trigger unit or the slave chip trigger unit so as to execute master chip ZQ calibration or slave chip ZQ calibration.

In one embodiment, the master chip trigger unit includes a power-up detection circuit, a test mode transition detection circuit, an internal pulse trigger, a clock trigger, and a command trigger, and the slave chip trigger unit includes an external pulse trigger.

A semiconductor device comprising a semiconductor chip comprising the ZQ calibration circuit of any preceding claim.

Test equipment connected to a ZQ calibration circuit for implementing the steps of the method of any one of the preceding claims with said ZQ calibration circuit.

A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any of the preceding claims.

The ZQ calibration method, circuit, semiconductor device, test apparatus, and computer-readable storage medium described above, by switching master-slave chip settings of a chip, perform both master-chip ZQ calibration and slave-chip ZQ calibration on the chip, thereby expanding the application range thereof. Meanwhile, the master chip ZQ calibration and the slave chip ZQ calibration are realized through different circuits, so that whether the reason for the abnormal calibration is the chip or other problems can be conveniently determined, and the ZQ calibration function is effectively improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flow chart of a ZQ calibration method in one embodiment;

FIG. 2 is a schematic diagram of a ZQ calibration flow when the target chip is the master chip in one embodiment;

FIG. 3 is a schematic diagram of a ZQ calibration flow when the target chip is a slave chip in one embodiment;

FIG. 4 is a flow chart of a ZQ calibration method according to another embodiment;

FIG. 5 is a block diagram of the ZQ calibration circuit in one embodiment;

FIG. 6 is a block diagram of a ZQ calibration circuit in another embodiment;

FIG. 7 is a schematic diagram of a portion of a ZQ calibration circuit according to another embodiment;

FIG. 8 is a schematic diagram of ZQ calibration logic for multiple chips in a package structure in one embodiment;

FIG. 9 is a schematic diagram of ZQ calibration logic after switching master-slave chips in the package structure of FIG. 8;

fig. 10 is a timing diagram of ZQ calibration of multiple chips in a package structure in one embodiment.

Reference numerals illustrate: 100-identification module, 110-read circuit, 200-calibration module, 210-calibration control unit, 220-master chip trigger unit, 221-power-on detection circuit, 222-test mode transition detection circuit, 223-internal pulse trigger, 224-clock trigger, 225-command trigger, 230-slave chip trigger unit, 231-external pulse trigger, 240-calibration unit, 300-switch module, 310-mode register

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It is to be understood that the terms "first," "second," and the like, as used herein, may be used to describe various parameter values, level values, etc., but these parameter values, level values, etc., are not limited by these terms. These terms are only used to distinguish a first parameter value, level value, etc. from another parameter value, level value, etc.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

In one embodiment, referring to fig. 1, a ZQ calibration method is provided for wafer level semiconductor chips. The method comprises the following steps:

step S110, after the target chip is powered on, identifying whether the target chip is set as a main chip;

Step S120, according to the identification result of the target chip, selecting a corresponding calibration mode to perform ZQ calibration on the target chip;

step S130, switching the master-slave chip setting of the target chip in the test mode;

In step S140, calibration is performed again on the target chip.

During semiconductor processing, multiple semiconductor chips may be formed on the same wafer. The chips are arranged at intervals. In a subsequent process, the individual chips may be separated by a dicing process, thereby forming individual chips. The individual chips may then be packaged (e.g., stacked) to form a package structure.

The target chip is a chip to be tested on the wafer. For example, each chip on the wafer may be a target chip. Alternatively, a part of the chips may be selected from the wafer as the target chips, which is not limited herein.

The target chip may be provided with a ZQ calibration circuit. The ZQ calibration circuit may include an identification module 100, a calibration module 200, and a switching module 300.

In step S110, it is possible to recognize whether the target chip has been set as the master chip by the recognition module 100.

The initial set-up of the chip may be performed in advance before the ZQ calibration of the chip. The identification module 100 may identify the initial setting of the target chip, thereby identifying whether the target chip has been set as the master chip.

In step S120, the master chip ZQ calibration and the slave chip ZQ calibration may be performed by the calibration module 200.

When the target chip is the main chip, a corresponding main chip ZQ calibration mode can be selected, and the main chip ZQ calibration can be performed on the target chip. When the target chip is a slave chip, a corresponding slave chip ZQ calibration mode can be selected, and the slave chip ZQ calibration is performed on the target chip.

In step S130, in the test mode, the master-slave chip setting of the target chip may be switched by the switching module 300.

Specifically, when the target chip is set as the master chip, it may be switched to be set as the slave chip in the test mode. When the target chip is set as the slave chip, it can be switched to be set as the master chip in the test mode.

In step S140, after switching the master-slave chip setting of the target chip, the calibration mode may be replaced, and the calibration may be performed again on the target chip.

The method of the embodiment can perform ZQ calibration on the wafer-level semiconductor chip, so that whether the wafer-level chip has the abnormal ZQ calibration function or not can be determined according to the ZQ calibration condition. Meanwhile, the master chip ZQ calibration and the slave chip ZQ calibration are performed on the target chip, so that the application range of the target chip is expanded. Meanwhile, since the master chip ZQ calibration and the slave chip ZQ calibration are implemented by different circuits, it is possible to facilitate determination of whether the cause of the calibration function abnormality is the chip itself or another problem.

In one embodiment, step S110 includes:

In step S111, the first parameter value of the target chip is identified, and it is determined whether the target chip has completed the master chip programming setting.

At this time, in the ZQ calibration circuit of the chip, the identification module 100 may include the read circuit 110.

The first parameter value may be stored in the mode register 310 of the target chip. As an example, the first parameter value may be a fuse parameter value.

The initial set-up of the chip may be performed in advance before the ZQ calibration of the chip. When one chip is set as the master chip, it may be programmed such that the first parameter value of the chip is the first level value. And the chip which is not subjected to the first parameter programming setting can be identified as the slave chip when the first parameter value of the chip is the second level value. The first level value may be, for example, "1", where the second level value is "0". Alternatively, the first level value may be "0", for example, and the second level value may be "1".

At this time, when the first parameter value of the target chip is identified, the first parameter value in the mode register 310 of the target chip may be read by the reading circuit 110 to determine whether the target chip has completed the first parameter programming setting. According to the first parameter programming setting condition of the target chip, whether the target chip is set as the main chip or not can be judged.

Specifically, when the first parameter value is the first level value, it may be determined that the target chip has completed the first parameter programming setting, thereby determining that the target chip has been set as the master chip. When the first parameter value is the second level value, it can be determined that the target chip does not complete the first parameter programming setting, thereby judging that the target chip is not set as the main chip.

In this embodiment, by the first parameter value of the target chip, it can be effectively determined whether the target chip has been set as the master chip.

In one embodiment, step S120 includes:

Step S121, when the target chip is set as the main chip, executing the main chip ZQ calibration on the target chip in a first parameter triggering mode;

In step S122, when the target chip is not set as the master chip, the slave chip ZQ calibration is performed on the target chip by the reception trigger mode.

At this time, in the ZQ calibration circuit of the chip, the identification module 100 may include the read circuit 110, and the calibration module 200 may include the calibration control unit 210, the master chip trigger unit 220, the slave chip trigger unit 230, and the calibration unit 240.

In step S121, the process of the master ZQ calibration may be performed on the target chip in the background mode by the first parameter trigger mode. Referring to fig. 7, when the target chip is set as the master chip, the process of performing ZQ calibration on the target chip by the first parameter triggering manner may be:

When the first parameter value of the target chip is read, a signal corresponding to the read first parameter value is transmitted to the calibration control unit 210. When the signal corresponding to the first parameter value is a first level (e.g., high level) signal, the calibration control unit 210 generates a calibration control signal (e.g., high level signal) that enables the main chip trigger unit 220. The main chip trigger unit 220 may include a power-up detection circuit 221 and an internal pulse trigger 223.

When the first parameter value of the target chip is read, a signal corresponding to the read first parameter value may also be transmitted to the power-on detection circuit 221. After the reading of the first parameter value of the target chip is completed, the power-on detection circuit 221 may detect a level jump of the signal. The input end of the power-on detection circuit 221 has an initial value of "0", and when the read first parameter value is "1", the level jumps from low level to high level; or the input of the power-up detection circuit 221 is initially "1", and when the read first parameter value is "0", the level jumps from high to low. After the power-on detection circuit 221 detects the level jump of the signal, a ZQ calibration pulse signal is generated and sent to the internal pulse trigger 223. The internal pulse trigger 223 may transmit an enable signal to the calibration module 200 after receiving the ZQ calibration pulse signal, so that the calibration module 200 performs the master chip ZQ calibration.

In step S122, when the target chip is not set as the master chip, the process of performing the slave chip ZQ calibration on the target chip by the reception trigger (Rx trigger) manner may be:

When the first parameter value of the target chip is read, a signal corresponding to the read first parameter value is transmitted to the calibration control unit 210. When the signal corresponding to the first parameter value is a second level (e.g., low level) signal, the calibration control unit 210 generates a calibration control signal (e.g., low level signal) that enables the slave chip trigger unit 230. The slave chip trigger unit 230 may include an external pulse trigger 231.

As an example, an inverter may be provided between the external pulse trigger 231 and the calibration control unit 210, and the calibration control signal (e.g., a low level signal) transmitted from the calibration control unit 210 may pass through the inverter to implement high-low level conversion, thereby enabling the external pulse trigger 231. Of course, in some examples, an inverter may not be provided, and the external pulse trigger 231 may be provided as the external pulse trigger 231 that may be directly enabled by a calibration control signal (e.g., a low level signal) transmitted from the calibration control unit 210.

After the external pulse trigger 231 is enabled by the calibration control signal transmitted from the calibration control unit 210, an external ZQ calibration pulse signal may be input thereto through a reception (Rx) pin of the chip. The external pulse trigger 231 transmits an enable signal to the calibration module 200 after receiving an external ZQ calibration pulse signal, so that the calibration module 200 performs slave chip ZQ calibration.

In an embodiment, the internal pulse generated by the power-on detection circuit 221 and the received external pulse respectively realize the master chip ZQ calibration and the slave chip ZQ calibration of the target chip, so that verification of ZQ calibration functions can be completed on target chips with different settings.

In one embodiment, referring to fig. 3, step S130 includes:

in step S132, when the target chip is not set as the master chip, the target chip is switched from the slave chip to the master chip by changing the second parameter value of the target chip in the test mode.

At this time, in the ZQ calibration circuit of the chip, the switching module 300 may include a mode register 310. The mode register 310 may store a first parameter value, a second parameter value, and a third parameter value of the chip, which may be configured at the initial setting. Wherein the second parameter value and the third parameter value may be changed in the test mode. The first parameter may be, for example, a fuse parameter, the second parameter may be, for example, a TM parameter, and the third parameter may be, for example, an MR parameter.

When a chip is initially set, when the first parameter value and the third parameter value are initially set to the same value, the mode register 310 may be programmed with a first parameter (e.g., fuse parameter) so that the first parameter value of the chip is a first level value, and simultaneously, the mode register 310 may be programmed with a third parameter (e.g., MR parameter) so that the first level value is the first level value. When one chip is not set as the master chip, the first parameter is not programmed into the mode register 310, so that the first parameter of the chip is a second level value, and at the same time, the third parameter can be programmed into the mode register 310 to be a second level value.

And the second parameter value of the mode register 310 may be set to a second level value at start-up for all chips. The first level value may be, for example, "1", and the second level value may be, for example, "0".

When the target chip is not set as the master chip, the first parameter value, the second parameter value and the third parameter value may be the second level value. At this time, in the test mode, the target chip can be switched from the slave chip to the master chip by changing the second parameter value of the target chip from the second level value to the first level value. It is understood that at this time, the first parameter value and the third parameter value of the target chip are unchanged.

In this embodiment, by changing the parameter value of the mode register 310, the slave chip can be switched to the master chip, and the master chip ZQ calibration is performed after the switching, so that verification of both the master chip ZQ calibration function and the slave chip ZQ calibration function of each chip is facilitated.

In one embodiment, referring to fig. 3, when the target chip is not set as the master chip, in the test mode, by changing the second parameter value of the target chip, the step S140 includes:

In step S142, after the target chip is switched from the slave chip to the master chip, the master chip ZQ calibration is performed on the target chip by the second parameter triggering mode.

The process of master chip ZQ calibration may be performed on the target chip in a background mode, by means of a second parameter trigger.

The main chip trigger unit 220 may include a test mode transition detection circuit 222 and an internal pulse trigger 223.

Referring to fig. 7, after the target chip is switched from the slave chip to the master chip, the process of performing the master chip ZQ calibration on the target chip by the second parameter triggering mode may be:

After changing the second parameter value of the target chip from the second level value to the first level value, the second parameter value of the mode register 310 may be read. The signal corresponding to the read first level value is transmitted to the test mode switch detection circuit 222, so that the test mode switch detection circuit 222 (for example, the initial value of the input end is low level) can generate a ZQ calibration pulse signal after detecting the level jump of the signal (for example, the level jump from low level to high level), and send the ZQ calibration pulse signal to the internal pulse trigger 223. The internal pulse trigger 223 may transmit an enable signal to the calibration module 200 after receiving the ZQ calibration pulse signal, so that the calibration module 200 performs the master chip ZQ calibration.

In one embodiment, referring to fig. 2 and fig. 3, step S121 performs the master chip ZQ calibration on the target chip in the first parameter triggering manner, or step S142 further includes, after performing the master chip ZQ calibration on the target chip in the second parameter triggering manner:

step S150, in a background mode, executing main chip ZQ calibration on a target chip in a clock triggering mode at intervals of preset time; and/or the number of the groups of groups,

In step S160, in the command mode, the master chip ZQ calibration is performed on the target chip in a calibration command triggering manner.

It is understood that when step S150 and/or step S160 are included after step S121, step S150 and/or step S160 are performed before step S130.

At this time, the main chip trigger unit 220 may further include a clock trigger 224 and/or a command trigger 225.

In step S150, a ZQ calibration pulse signal may be issued to the clock trigger 224 at preset time intervals in the background mode. The preset time interval may be configured by a parameter of the mode register.

The clock flip-flop 224, after receiving the ZQ calibration pulse signal, may send an enable signal to the calibration module 200 to cause the calibration module 200 to perform master chip ZQ calibration.

In step S160, a ZQ calibration pulse signal may be issued to the command flip-flop 225 according to a command in the command mode. The command flip-flop 225 may transmit an enable signal to the calibration module 200 after receiving the ZQ calibration pulse signal to cause the calibration module 200 to perform master chip ZQ calibration.

In one embodiment, referring to fig. 2, step S130 further includes:

In step S131, when the target chip has been set as the master chip, in the test mode, the target chip is switched from the master chip to the slave chip by changing the third parameter value of the target chip.

As previously described, in the ZQ calibration circuit of the chip, the switching module 300 may include a mode register 310. The mode register 310 may store therein a first parameter value, a second parameter value, and a third parameter value of the target chip. Wherein the second parameter value and the third parameter value may be changed in the test mode. The first parameter may be, for example, a fuse parameter, the second parameter may be, for example, a TM parameter, and the third parameter may be, for example, an MR parameter.

When the target chip is set as the main chip, the first parameter value and the third parameter value can be the first level value, and the second parameter value is the second level value. At this time, in the test mode, the target chip can be switched from the master chip to the slave chip by changing the third parameter value of the target chip from the first level value to the second level value. It is understood that at this time, the first parameter value and the second parameter value of the target chip are unchanged.

At this time, by changing the third parameter value of the mode register 310, it is possible to switch the master chip to the slave chip and perform the slave chip ZQ calibration after the switching, facilitating verification of both the master chip ZQ calibration function and the slave chip ZQ calibration function of each chip.

As an example, step S140 may include:

in step S141, after the target chip is switched from the master chip to the slave chip, the slave chip ZQ calibration is performed on the target chip by receiving the trigger mode.

At this time, in the ZQ calibration circuit of the chip, the identification module 100 may include the read circuit 110, and the calibration module 200 may include the calibration control unit 210, the master chip trigger unit 220, the slave chip trigger unit 230, and the calibration unit 240 mode register 310. The slave chip triggering unit 230 includes an external pulse trigger 231.

The reading circuit 110 may be connected to the mode register 310, and may further read the first parameter value, the second parameter value, and the third parameter value. The calibration control unit 210 may be connected to the reading circuit 110, and may generate a calibration control signal according to the first parameter value, the second parameter value, and the third parameter value.

When the first parameter value and the third parameter value are both the first level value, the chip is set as the master chip in the initial setting stage. At this time, the calibration control signal generated by the calibration control unit 210 is the first enable signal. The first enable signal may enable the main chip trigger unit 220. In addition, when the second parameter value is the first level value, the chip is switched from the slave chip to the master chip. At this time, the calibration control signal generated by the calibration control unit 210 is also the first enable signal.

In other cases, the slave chip is set, and the calibration control signal generated by the calibration control unit 210 is the second enable signal. The first enable signal may enable the slave chip trigger unit 230.

At this time, by reading the first parameter value, the second parameter value, and the third parameter value of the mode register 310, the calibration control unit 210 may automatically respond to the chip master-slave setting condition by responding to the calibration control signal to enable the corresponding calibration trigger unit (the master chip trigger unit 220 or the slave chip trigger unit 230), thereby performing the corresponding ZQ calibration function verification.

Referring to fig. 7, after the target chip is switched from the master chip to the slave chip, the process of performing ZQ calibration on the target chip by the receiving triggering mode may be:

After the target chip is switched from the master chip to the slave chip, the first, second and third parameter values in the mode register 310 are read. At this time, the first parameter value is a first level value, and the third parameter value is a second level value, so that the first parameter value and the third parameter value are both not satisfied. Meanwhile, the second parameter value is a second level value, so that the second parameter value is not satisfied as the first level value. As an illustration, the calibration control unit 210 may include an and gate and an or gate. The read first parameter value and the third parameter value may be connected to an and gate, and the output of the and gate and the read second parameter value may be connected to an or gate, and the output of the or gate may be used as the output of the calibration control unit 210. Therefore, when the read first parameter value is the first level value, the third parameter value is the second level value, and the second parameter value is the second level value, the calibration control unit 210 generates a second enable signal (calibration control signal) that enables the external pulse trigger 231 of the slave chip trigger unit 230.

After the external pulse trigger 231 is enabled, an external ZQ calibration pulse signal may be input thereto through a receive (Rx) pin of the chip. The external pulse trigger 231 transmits an enable signal to the calibration module 200 after receiving an external ZQ calibration pulse signal, so that the calibration module 200 performs slave chip ZQ calibration.

As an example, after step S140, the setting of the target chip may be restored to the initial setting (the first parameter value, the second parameter value, and the third parameter value are all restored to the initial setting.

In one embodiment, referring to fig. 4 and 10, a ZQ calibration method is further provided, which is applied to a multi-chip package structure. The method comprises the following steps:

step S210, after the packaging structure is powered on, determining a main chip from a plurality of chips of the packaging structure;

step S220, performing primary master chip ZQ calibration on the master chip;

Step S230, after the calibration of the master chip ZQ is completed, the slave chip ZQ is calibrated for other chips until all chips complete one time of ZQ calibration;

Step S240, switching the master chip to the slave chip, and switching any other slave chip to the master chip;

Step S250, after the master-slave chip setting switching is completed, ZQ calibration is performed once again for all chips.

In step S210, after the plurality of chips are packaged to form a package structure, one of the chips is a master chip and the other chips are slave chips.

All chips (including master and slave) on the package structure may be provided with ZQ calibration circuits. The ZQ calibration circuit may include an identification module 100, a calibration module 200, and a switching module 300.

The identification module 100 on each chip can identify whether the chip on which it is located has been set as a master chip, so that the master chip can be determined from among a plurality of chips of the package structure.

In step S220, each on-chip calibration module 200 has a master chip ZQ calibration function and a slave chip ZQ calibration function.

The master chip ZQ calibration may be performed once on it by the calibration module 200 on the master chip.

In step S230, after the master chip ZQ calibration is completed, the slave chip ZQ calibration may be performed on other chips by the calibration module 200 on the other chips.

As an example, referring to fig. 8 or 9, all chips in the package structure may be cascaded in sequence, and the last chip is connected to the first chip.

At this time, referring to fig. 8 to 10, step S230 may include:

After the master chip ZQ calibration is finished, the master chip sends a ZQ calibration pulse signal to a next chip, the next chip executes a secondary chip ZQ calibration in a receiving triggering mode, and after the next chip completes the secondary chip ZQ calibration, the next chip sends a ZQ calibration pulse signal to an adjacent next chip to instruct the adjacent next chip to execute the secondary chip ZQ calibration; and repeating the transmission process of the ZQ calibration pulse signals among the cascaded chips until the main chip receives the ZQ calibration pulse signals transmitted by the previous stage chip, and indicating all the chips to finish one time of ZQ calibration.

Specifically, each chip of the package structure is provided with a receiving (Rx) pin and a transmitting (Tx) pin. When the front chip sends the ZQ calibration pulse signal to the back chip, the ZQ calibration pulse signal can be sent to the Rx pin of the back chip through the Tx pin on the front chip. When the subsequent chip is a slave chip, the Rx pin may transmit the ZQ calibration pulse signal to the external pulse trigger 231 after receiving it. For example, in fig. 8, chip 0 (master chip) transmits a ZQ calibration pulse signal to the Rx pin of chip 1 (slave chip) through the Tx pin. After the Rx pin of the chip 1 receives the ZQ calibration pulse signal, it may be transmitted to the external pulse trigger 231. The external pulse trigger 231 transmits an enable signal to the calibration module 200 after receiving the ZQ calibration pulse signal, so that the calibration module 200 performs slave chip ZQ calibration.

In step S240, one of the slave chips may be switched to the master chip while the master chip is switched to the slave chip.

As an example, step S250 may perform primary chip ZQ calibration on the primary chip after the primary-secondary chip setting switching is completed, and then perform secondary chip ZQ calibration on the other chips in sequence until all the chips complete once ZQ calibration.

Further, as an example, all chips in the package structure may be sequentially switched to the master chip, and each time after each switching is initiated by the switched master chip, ZQ calibration is performed once on all chips.

It can be understood that after all the other chips except the main chip determined after power-up in the package structure are sequentially switched to the main chip, the master-slave chip setting switching can be performed again, so that the chip determined to be the main chip is switched back to the setting of the main chip again.

After each primary chip is switched, primary chip ZQ calibration can be firstly carried out on the current primary chip after the switching, and then secondary chip ZQ calibration is carried out on other chips after the primary chip ZQ calibration is finished until all chips finish ZQ calibration once.

In the present embodiment, for each chip in the multi-chip package structure, both the master chip ZQ calibration and the slave chip ZQ calibration are performed, thereby expanding the application range thereof. Meanwhile, the main chip ZQ calibration and the slave chip ZQ calibration are realized through different circuits, so that whether the cause of the abnormality of the ZQ calibration is the problem of the circuit of the chip or other problems such as pulse signal transmission among chips can be conveniently determined.

For example, when one chip performs calibration because the Rx pin cannot receive the signal output by the Tx pin of the previous chip, the slave chip ZQ calibration is abnormal, but the master chip ZQ calibration is normal, the problem of the calibration abnormality can be primarily determined to be the connection problem of the Tx pin and the Rx pin, rather than the ZQ function problem of the chip itself.

Further, in the present embodiment, the master-slave chip calibration function is completed for each chip. Therefore, in the subsequent use, if the master chip and the slave chip need to be switched, the normal execution of the ZQ calibration function after the switching can be ensured.

In one embodiment, step S210 includes:

Step S211, identifying a first parameter value of a chip in the packaging structure, and determining whether the main chip programming setting is completed for the chip in the packaging structure;

step S212, when the chip in the packaging structure has completed the programming setting of the main chip, determining the chip which has completed the programming setting of the main chip as the main chip;

In step S213, when all the chips have not completed the master chip programming setting, in the test mode, the second parameter value of one of the chips in the package structure is changed to set it as the master chip, and the other chips are slave chips.

At this time, in the ZQ calibration circuit of each chip, the identification module 100 may include the reading circuit 110. The switching module 300 may include a mode register 310.

The mode register 310 may store therein a first parameter value, a second parameter value, and a third parameter value of the chip. Wherein the second parameter value and the third parameter value may be changed in the test mode. The first parameter may be, for example, a fuse parameter, the second parameter may be, for example, a TM parameter, and the third parameter may be, for example, an MR parameter.

The chips used to form the package structure may be initially placed prior to packaging. When one chip is set as the master chip, the first parameter value and the third parameter value thereof are initially set to the same value, and the first parameter (e.g., fuse parameter) may be programmed into the mode register 310 thereof, so that the first parameter value of the chip is a first level value, and at the same time, the value of the third parameter (e.g., MR parameter) may be programmed into the mode register 310 thereof, so that the first level value is a first level value. When one chip is not set as the master chip, the first parameter is not programmed into the mode register 310, so that the first parameter of the chip is a second level value, and at the same time, the third parameter can be programmed into the mode register 310 to be a second level value. And the second parameter value of the mode register 310 may be set to a second level value at start-up for all chips. The first level value may be, for example, "1", and the second level value may be, for example, "0".

Each chip of the package structure may or may not have one main chip. For each chip, the first parameter value in the mode register 310 may be read by its read circuit 110 to determine whether the chip has completed the first parameter programming setting, thereby determining whether the target chip has been set as the master chip.

Specifically, when the first parameter value of a chip is the first level value, it may be determined that the chip has completed the first parameter programming setting, thereby determining that the chip has been set as the master chip. When the first parameter value of a chip is the second level value, the fact that the chip does not complete the first parameter programming setting can be determined, and therefore the chip is judged not to be set as the main chip.

When determining whether the main chip programming setting is completed by the chips in the packaging structure, the first parameter values of the chips can be sequentially read. When the first parameter value read from one of the chips is a first level value, the first parameter value indicates that the chip in the packaging structure has completed the main chip programming setting. At this time, the completed chip may be determined as the master chip. When the first parameter values of all the chips of the packaging structure are read to be the second level values, the fact that all the chips are not finished in the master chip programming setting is indicated, at this time, the second parameter value of one chip in the packaging structure can be changed from the second level value to the first level value in a test mode, so that the second parameter value is set as the master chip, and the other chips are slave chips.

In this embodiment, whether the main chip is preset in the package structure may be determined in the ZQ calibration process.

In one embodiment, step S220 includes:

step S221, when the chip with the completed master chip programming setting is determined to be the master chip, performing primary master chip ZQ calibration on the master chip in a first parameter triggering mode;

In step S222, when the main chip is set in the test mode, the main chip ZQ calibration is performed once on the main chip in the second parameter triggering manner.

At this time, in the ZQ calibration circuit of each chip, the identification module 100 may include the read circuit 110, and the calibration module 200 may include the calibration control unit 210, the master chip trigger unit 220, the slave chip trigger unit 230, and the calibration unit 240. The main chip trigger unit 220 may include a power-up detection circuit 221, a test mode transition detection circuit 222, and an internal pulse trigger 223.

In step S221, in the background mode, the process of performing the ZQ calibration of the master chip by the first parameter triggering manner may be:

When the first parameter value of the main chip is read, a signal corresponding to the read first parameter value is transmitted to the calibration control unit 210. When the signal corresponding to the first parameter value is a first level (e.g., high level) signal, the calibration control unit 210 generates a calibration control signal (e.g., high level signal) that enables the main chip trigger unit 220.

When the first parameter value of the main chip is read, a signal corresponding to the read first parameter value may also be transmitted to the power-on detection circuit 221. After the reading of the first parameter value of the main chip is completed, the power-on detection circuit 221 may detect a level jump of the signal. The input end of the power-on detection circuit 221 has an initial value of 0, and when the read first parameter value is "1", the level jumps from low level to high level; or the input of the power-up detection circuit 221 has an initial value of 1, and the level transitions from a high level to a low level when the read first parameter value is "0". After the power-on detection circuit 221 detects the level jump of the signal, a ZQ calibration pulse signal is generated and sent to the internal pulse trigger 223. The internal pulse trigger 223 may transmit an enable signal to the calibration module 200 after receiving the ZQ calibration pulse signal, so that the calibration module 200 performs the master chip ZQ calibration.

In step S222, in the background mode, the primary chip ZQ calibration may be performed on the primary chip in a second parameter triggering manner, and the specific calibration process may be:

The second parameter value of the mode register 310 of the main chip may be read as the first level value. The signal corresponding to the read first level value is transmitted to the test mode switch detection circuit 222, so that the test mode switch detection circuit 222 (for example, the initial value of the input end is low level) can generate a ZQ calibration pulse signal after detecting the level jump of the signal (for example, the level jump from low level to high level), and send the ZQ calibration pulse signal to the internal pulse trigger 223. The internal pulse trigger 223 may transmit an enable signal to the calibration module 200 after receiving the ZQ calibration pulse signal, so that the calibration module 200 performs the master chip ZQ calibration.

In one embodiment, after step S220, before step S240, the method further includes:

Step S260, in the background mode, executing main chip ZQ calibration on the current main chip in a clock triggering mode at intervals of preset time, and sequentially executing slave chip ZQ calibration on other chips; and/or the number of the groups of groups,

In step S270, in the command mode, the master chip ZQ calibration is performed on the current master chip in a calibration command triggering manner, and the slave chips ZQ calibration is performed on the other chips in sequence.

In step S260, a ZQ calibration pulse signal may be sent to the clock trigger 224 of the master chip at preset time intervals in the background mode. The clock flip-flop 224, after receiving the ZQ calibration pulse signal, may send an enable signal to the calibration module 200 to cause the calibration module 200 to perform master chip ZQ calibration.

In step S270, a ZQ calibration pulse signal may be issued to the command flip-flop 225 of the master chip according to a command in the command mode. The command flip-flop 225 may transmit an enable signal to the calibration module 200 after receiving the ZQ calibration pulse signal to cause the calibration module 200 to perform master chip ZQ calibration.

In some embodiments, switching of master-slave chip settings may be performed multiple times. After each switching is completed and before the next switching is performed, the master chip ZQ calibration may be performed on the master chip after switching, then the slave chip ZQ calibration may be performed on the other chips sequentially until all the chips complete the ZQ calibration once, and then step S260 and/or step S270 may be performed.

In one embodiment, step S240 includes:

in step S241, in the test mode, the third parameter value in the master chip mode register 310 is changed, the master chip is switched to the slave chip, and any one of the slave chips is selected as the target slave chip, and the second parameter value in the target slave chip mode register 310 is changed to switch the target slave chip to the master chip, see fig. 8 and 9.

As described above, in this case, the identification module 100 may include the reading circuit 110 in the ZQ calibration circuit of each chip. The switching module 300 may include a mode register 310.

The chips used to form the package structure may be initially placed prior to packaging. When a chip is set as the master chip, the first parameter value of the chip is the first level value, while the third parameter (e.g. MR parameter) value is the first level value, i.e. the first parameter value and the third parameter value are initially set to the same value. Specifically, the present invention relates to a method for manufacturing a semiconductor device. When one chip is not set as the main chip, the first parameter value of the chip is the second level value, and the third parameter value is the second level value. And the second parameter value of the mode register 310 may be set to a second level value at start-up for all chips. The first level value may be, for example, "1", and the second level value may be, for example, "0".

At this time, step S240 may change the third parameter value in the master chip mode register 310 from the first level value to the second level value, thereby switching the master chip to the slave chip. Meanwhile, any one slave chip is selected as a target slave chip, and the second parameter value in the target slave chip mode register 310 is changed from the second level value to the first level value, so that the target slave chip is switched to the master chip.

In this embodiment, in the test mode, by changing the parameter values in the mode register 310, the master-slave chip setting switching can be simply and effectively performed, and ZQ calibration is performed once for all chips after the switching, so that verification is conveniently performed on the master chip ZQ calibration function and the slave chip ZQ calibration function of each chip.

It should be understood that, although the steps in the flowcharts of fig. 1-4 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps of fig. 1-4 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.

In one embodiment, referring to fig. 5, a ZQ calibration circuit is provided and includes an identification module 100, a calibration module 200, and a switching module 300.

The identification module 100 is used for identifying master-slave chip settings of the chip.

The calibration module 200 is used for performing master chip ZQ calibration and slave chip ZQ calibration;

The switching module 300 is used for switching the master-slave chip settings of the chip.

In one embodiment, referring to fig. 6, the switching module 300 includes a mode register 310, where the mode register 310 is used to store a first parameter value, a second parameter value, and a third parameter value of the chip.

The identification module 100 comprises a reading circuit 110, the reading circuit 110 being connected to a mode register 310 for reading the first parameter value, the second parameter value and the third parameter value to identify the master-slave chip setting.

The calibration module 200 includes a calibration control unit 210, a master chip trigger unit 220, a slave chip trigger unit 230, and a calibration unit 240.

The calibration control unit 210 is connected to the reading circuit 110, and is configured to generate a calibration control signal according to the first parameter value, the second parameter value, and the third parameter value; when the first parameter value and the third parameter value are both the first level value, or the second parameter value is the first level value, the calibration control signal generated by the calibration control unit 210 is the first enable signal; otherwise, the calibration control signal generated by the calibration control unit 210 is the second enable signal.

As an example, the first level value is "1", and the second level value is "0". At this time, the calibration control unit 210 may include an and gate and an or gate. The read first parameter value and the third parameter value may be connected to an and gate, and the output of the and gate and the read second parameter value may be connected to an or gate, and the output of the or gate may be used as the output of the calibration control unit 210. The AND gate outputs a "1" when the first parameter value and the third parameter value are both a first level value ("1"), otherwise the AND gate outputs a "0". The output of the AND gate and the read second parameter value may be accessed into an OR gate. Therefore, when the second parameter value is the first level value ("1"), the calibration control signal generated by the calibration control unit 210 is the first enable signal (high level signal). And when the second parameter value is the second level value ("0"), if the first parameter value and the third parameter value are both the first level value ("1"), the calibration control signal generated by the calibration control unit 210 is the first enable signal (high level signal), otherwise, the calibration control signal generated by the calibration control unit 210 is the second enable signal (low level signal).

The master chip triggering unit 220 is connected to the calibration control unit 210, and is configured to receive a first enable signal to trigger the master chip ZQ calibration.

The slave chip triggering unit 230 is connected to the calibration control unit 210, and is configured to receive a second enable signal to trigger the execution of the slave chip ZQ calibration.

The calibration unit 240 is connected to the master chip trigger unit 220 and the slave chip trigger unit 230, and is configured to receive an enable signal of the master chip trigger unit 220 or the slave chip trigger unit 230, so as to perform chip ZQ calibration.

In one embodiment, referring to fig. 7, the master chip trigger unit 220 includes a power-up detection circuit 221, a test mode transition detection circuit 222, an internal pulse trigger 223, a clock trigger 224, and a command trigger 225, and the slave chip trigger unit 230 includes an external pulse trigger 231.

Wherein the internal pulse trigger 223, the clock trigger 224, the command trigger 225, and the external pulse trigger 231 may all be connected to the calibration unit 240. Meanwhile, the internal pulse trigger 223 is connected to the power-on detection circuit 221 and the test mode conversion detection circuit 222. The power-on detection circuit 221 and the test mode conversion detection circuit 222 are connected to the read circuit 110. The read circuit 110 is coupled to the mode register 310.

The power up detection circuit 221 and the internal pulse trigger 223 may be used to implement a first parameter trigger mode. Test mode transition detection circuit 222 and internal pulse trigger 223 may be used to implement the second parameter trigger mode. The clock trigger 224 is used to implement a clock trigger mode. The command trigger 225 is used to implement a command trigger mode.

The process of performing the main chip ZQ calibration on the main chip by the first parameter triggering manner may be:

When the first parameter value of the main chip is read, a signal corresponding to the read first parameter value is transmitted to the calibration control unit 210. When the signal corresponding to the first parameter value is a first level (e.g., high level) signal, the calibration control unit 210 generates a calibration control signal (e.g., high level signal) that enables the main chip trigger unit 220. The main master chip trigger unit 220 may include a power-up detection circuit 221 and an internal pulse trigger 223.

The process of performing the master chip ZQ calibration on the master chip by the second parameter triggering manner may be:

The process of executing the ZQ calibration of the master chip by the clock triggering method may be:

And executing main chip ZQ calibration on the main chip in a clock triggering mode at preset time intervals.

The process of executing the ZQ calibration of the master chip on the master chip by the command triggering mode may be:

the ZQ calibration pulse signal is issued to the command flip-flop 225 of the master chip in accordance with the command.

For specific limitations of the ZQ calibration circuit, reference may be made to the above limitations of the ZQ calibration method, and no further description is given here.

In one embodiment, there is also provided a semiconductor device comprising a semiconductor chip comprising any of the ZQ calibration circuits described above.

Specifically, the semiconductor device may be a memory device, and may include a plurality of chips, or may include a single chip. When the memory device includes a plurality of chips, the plurality of chips may be stacked, for example.

In one embodiment, there is also provided a test apparatus connected to the ZQ calibration circuit to implement the steps of the method of any of the above with the ZQ calibration circuit.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements the steps of the method embodiments described above.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory. By way of illustration, and not limitation, RAM can be in various forms such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A ZQ calibration method applied to a wafer level semiconductor chip, the method comprising:

switching master-slave chip settings of the target chip in a test mode;

And performing calibration again on the target chip.

2. The ZQ calibration method of claim 1, wherein the identifying whether the target chip has been set as a master chip after powering up the target chip comprises:

3. The ZQ calibration method according to claim 2, wherein selecting a corresponding calibration mode to perform ZQ calibration on the target chip according to the identification result of the target chip includes:

4. The ZQ calibration method according to claim 1, wherein,

5. The ZQ calibration method according to claim 4, wherein,

The performing calibration again on the target chip includes:

6. The ZQ calibration method according to claim 3 or 5, characterized by further comprising, after performing master chip ZQ calibration on the target chip:

7. The ZQ calibration method according to claim 1, wherein,

the performing calibration again on the target chip further includes:

8. A ZQ calibration method applied to a multi-chip package structure, the method comprising:

performing primary master chip ZQ calibration on the master chip;

After the main chip ZQ calibration is completed, the secondary chip ZQ calibration is sequentially carried out on other chips until all the chips complete one-time ZQ calibration;

9. The ZQ calibration method according to claim 8, wherein,

10. The ZQ calibration method according to claim 9, wherein,

The performing primary chip ZQ calibration on the primary chip includes:

11. The ZQ calibration method of claim 8 wherein all chips in the package are cascaded in sequence and a last level chip is connected to a first level chip;

12. The ZQ calibration method according to claim 8, after the performing primary chip ZQ calibration on the primary chip and before the switching the primary chip to a secondary chip and any other secondary chip to a primary chip, further comprising:

13. The ZQ calibration method of claim 8, wherein the switching the master chip to a slave chip and any other slave chip to a master chip comprises:

14. The ZQ calibration method according to claim 8, wherein,

And sequentially switching all chips in the packaging structure into main chips, initiating by the switched main chips after each switching, and executing ZQ calibration on all the chips once.

15. The ZQ calibration method according to claim 8, wherein,

After the master-slave chip setup switch is completed, ZQ calibration is performed once again for all chips, including:

16. A ZQ calibration circuit, comprising:

17. The ZQ calibration circuit of claim 16 wherein,

The calibration module includes:

18. The ZQ calibration circuit of claim 17, wherein the master chip trigger unit includes a power-up detection circuit, a test mode transition detection circuit, an internal pulse trigger, a clock trigger, and a command trigger, and the slave chip trigger unit includes an external pulse trigger.

19. A semiconductor device comprising a semiconductor chip comprising the ZQ calibration circuit of any one of claims 16 to 18.

20. Test equipment, characterized in that a ZQ calibration circuit is connected for implementing the steps of the method according to any of claims 1 to 15 with the ZQ calibration circuit.

21. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 15.