CN117938172A - Hardware GZIP data compression system based on RISC-V architecture - Google Patents

Abstract

The invention discloses a hardware GZIP data compression system based on RISC-V architecture, which comprises: RISC-V module, hardware compression core and FPGA hardware platform, wherein: the RISC-V module comprises a high-speed bus and a low-speed bus and is used as a core processor for managing and scheduling an algorithm; the hardware compression core comprises a bit width conversion module, a first FIFO buffer module, a second FIFO buffer module, a first AXI-to-AHB bridge module, a second AXI-to-AHB bridge module and a hardware compression algorithm IP, and is used for compressing original data to obtain a GZIP compression packet; the RISC-V module is transplanted on the FPGA hardware platform, and performs corresponding operation according to each instruction sent by the RISC-V architecture. By using the method and the device, the GZIP compression algorithm of hardware can be realized, and the operation speed of the algorithm and the compression rate of data are improved. The invention can be widely applied to the technical field of data compression processing.

Description

Hardware GZIP data compression system based on RISC-V architecture

Technical Field

The invention relates to the technical field of data compression processing, in particular to a hardware GZIP data compression system based on a RISC-V architecture.

Background

With the rapid development of the information technology of the present society, users can realize various convenient services through intelligent equipment, the life style is greatly changed, and the data volume to be carried by each platform is increased explosively, so that the storage system in the modern processor needs to process more and more data. In face of such challenges, data compression is an effective way to increase the storage capacity of a system, providing both performance and power consumption advantages. However, most of the current compression algorithm implementation is based on the upper computer software, so that the defect that too much CPU is occupied exists, and the software can only be executed in series, so that the compression rate of the algorithm is greatly reduced.

Disclosure of Invention

In order to solve the technical problems, the invention aims to provide a hardware GZIP data compression system based on a RISC-V architecture, which can realize a GZIP compression algorithm of hardware and improve the operation speed of the algorithm and the compression rate of data.

The first technical scheme adopted by the invention is as follows: a hardware GZIP data compression system based on RISC-V architecture comprises a RISC-V module, a hardware compression core and an FPGA hardware platform, wherein:

the RISC-V module comprises a high-speed bus and a low-speed bus and is used as a core processor for managing and scheduling an algorithm;

The hardware compression core comprises a bit width conversion module, a first FIFO buffer module, a second FIFO buffer module, a first AXI-to-AHB bridge module, a second AXI-to-AHB bridge module and a hardware compression algorithm IP, and is used for compressing original data to obtain a GZIP compression packet;

the RISC-V module is transplanted on an FPGA hardware platform, and performs corresponding operation according to various instructions sent by a RISC-V architecture;

the high-speed bus of the RISC-V module is connected with a first AXI-to-AHB bridge module and a second AXI-to-AHB bridge module; the first AXI-to-AHB bridge module is connected with the first FIFO buffer module; the first FIFO buffer module is connected with the bit width conversion module; the bit width conversion module is connected with the IP input end of the hardware compression algorithm; the IP output end of the hardware compression algorithm is connected with the second FIFO buffer module; the second FIFO buffer module is connected with a second AXI-to-AHB bridge module.

Further, the hardware compression algorithm IP has the following packaging steps:

Based on a software GZIP open source algorithm, respectively carrying out hardware description language design on the LZ77 module and the Huffman module to obtain a GZIP algorithm hardware code;

simulating and verifying the GZIP algorithm hardware code based on the Vivado platform to obtain a verified error-free GZIP algorithm hardware code;

Based on the verification error-free GZIP algorithm hardware code, configuring corresponding constraint files to be laid out and wired into an FPGA hardware platform, and obtaining an initial hardware compression algorithm;

testing and verifying an initial hardware compression algorithm based on a Karl-Gari corpus data packet sent by a serial port to obtain a hardware compression algorithm with no testing error;

and packaging the hardware compression algorithm without error to obtain the hardware compression algorithm IP.

Through the optimization step, the hardware compression algorithm IP can execute a plurality of tasks in parallel in the same clock period, so that the execution time of a single task is reduced, the operation efficiency is greatly improved, and the parallel characteristic of hardware is exerted to the best; the diversity of the data packets of the Calgari corpus enables the test of compression performance to be more abundant.

Further, the step of compressing the original data to obtain a GZIP compressed packet specifically includes:

Inputting the original data into an LZ77 module in a hardware compression algorithm IP for hash processing to generate a hash chain table;

Performing matching inquiry on each byte based on the hash chain table to obtain a coding length parameter and a distance parameter;

Inputting the coded data carrying the coded length parameter and the distance parameter into a Huffman module in a hardware compression algorithm IP for coding compression to obtain serialized data;

and packaging the serialized data, and adding a header file and check bits to obtain the GZIP compressed packet.

By this preferred procedure, a higher compression rate is achieved than LZ77 and Huffman compression alone.

Further, the running of the RISC-V module is controlled by the upper computer software programming, commands in the upper computer software programming are converted into machine codes which can be identified by the RISC-V module through a cross compiling tool chain, and the programs are burnt into the CPU of the RISC-V module.

By this preferred step, the problem is solved that executable files generated in high-level languages cannot run directly on processors of the RISC-V architecture.

Furthermore, the high-speed bus is used for connecting a processor, high-performance peripherals and other components needing rapid data transmission, and is provided with a CPU core, a ISRAM module, an IMEM module, a DMEM module, a DRAM module and a DMA module.

Furthermore, the low-speed bus is used for connecting peripheral equipment with low performance and a sensor, and is provided with a WDT module, a PWM module, a TIM module, a USI module, a GPIO module and an RTC module.

By this preferred procedure, the demand setting of the high-speed bus and the low-speed bus is comprehensively considered, and high performance, low power consumption and appropriate resource allocation between the inside and the outside of the system are realized.

Further, the hardware compression algorithm IP includes a number of registers defined by software development tools and programming languages, and the CPU of the RISC-V module directly performs instruction operations on the registers.

Through the preferred steps, the CPU directly adopts the RISC-V module to directly perform instruction operation on the register without adding additional instructions, decoding the instructions and other links, so that the development efficiency is improved while hardware acceleration is ensured when the development of the instructions is greatly shortened.

The system has the beneficial effects that: the invention carries out code design, simulation and debugging on the LZ77 module and the Huffman module based on the GZIP open source algorithm, encapsulates the LZ77 module and the Huffman module to obtain a hardware compression algorithm IP, realizes that a plurality of tasks are executed in parallel in the same clock period, and brings the parallel characteristic of hardware into play to the best; the hardware compression algorithm IP is mounted through a high-speed bus of a RISC-V architecture, and the RISC-V is used as a core processor to manage and schedule the algorithm, so that the method has the advantages of being open in source, low in power consumption and high in flexibility; the command in the upper computer software programming is converted into the machine code which can be identified by the RISC-V module through the cross compiling tool chain, so that the problem that an executable file generated by a high-level language cannot be directly operated on a processor of a RISC-V architecture is solved; the register is defined by a software development tool and a programming language, so that the CPU of the RISC-V module directly carries out instruction operation on the register, and the development efficiency is improved while hardware acceleration is ensured.

Drawings

FIG. 1 is a schematic diagram of a hardware GZIP data compression system based on RISC-V architecture according to the present invention;

FIG. 2 is a schematic diagram of a RISC-V module architecture of a hardware GZIP data compression system based on a RISC-V architecture of the present invention;

FIG. 3 is a schematic diagram of a hardware compression algorithm IP of a hardware GZIP data compression system based on RISC-V architecture of the present invention;

FIG. 4 is a graph showing the compression rate of output data of a hardware compression core of a hardware GZIP data compression system based on a RISC-V architecture;

FIG. 5 is a schematic diagram of a hardware compression core mount of a hardware GZIP data compression system based on RISC-V architecture of the present invention;

FIG. 6 is a schematic diagram of data communication of a hardware GZIP data compression system based on RISC-V architecture according to the present invention;

description of the drawings: 1. a first AXI to AHB bridge module; 2. a second AXI to AHB bridge module; 3. a first FIFO buffer module; 4. a second FIFO buffer module; 5. a bit width conversion module; 6. the hardware compresses the algorithm IP.

Detailed Description

The invention will now be described in further detail with reference to the drawings and to specific examples. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.

Referring to fig. 1, the present invention provides a hardware GZIP data compression system based on RISC-V architecture, the system comprising a RISC-V (Reduced Instruction Set Computing, fifth generation reduced instruction set) module, a hardware compression core, and an FPGA (Field Programmable GATE ARRAY, programmable gate array) hardware platform, wherein:

the RISC-V module is transplanted on an FPGA hardware platform, and performs corresponding operation according to various instructions sent by a RISC-V architecture; RISC-V is an open-source reduced instruction set architecture designed by the university of Berkeley in California in 2010, compared with an x86 architecture, an ARM architecture, a MIPS architecture and the like which are proposed in the early years, RISC-V does not need to consider compatibility, various experiences can be drawn from the past instruction set, a reduced instruction set is perfected, meanwhile, the instruction set also reserves coding space which can be modified by a user, and the instruction set has enough self-defined instruction space. And as an open source instruction set, any institution or enterprise can directly develop without charge by using RISC-V without being limited by patent permissions such as ARM.

Referring to fig. 2, the RISC-V module includes a high-speed BUS AHB HS BUS and a low-speed BUS AHB LS BUS, and is used as a core processor to manage and schedule an algorithm;

The high-speed bus is typically used to connect processors, high-performance peripherals, and other components that require fast data transfer. These components may include high performance memory, graphics processing units, digital signal processors, etc., and high speed buses typically have high bandwidth and low latency to support large data transfers and fast response times. So the high-speed BUS AHB HS BUS is provided with RISC-V CPU core (Reduced Instruction Set Compute-V Central-Processing-Unit, fifth generation reduced instruction set CPU) in SoC design for Processing instruction, executing operation, controlling time and Processing data; ISRAM module (INTERNAL STATIC Random Access Memory ) is used to exchange data with CPU directly, so as to realize fast reading and writing; an IMEM module (Instruction Memory, instruction store) for holding instructions to be executed; the DMEM module (Data Memory) is used for reading and writing Data of the corresponding address according to the read-write control signal; a DRAM module (Dynamic Random Access Memory ) as a high-speed volatile memory for storing running programs and data; and the DMA module (Direct Memory Access ) is used for realizing direct transmission of data, reducing the load of a CPU and improving the performance and efficiency of the system.

The low-speed bus is typically used to connect low-performance peripherals and sensors to achieve a more energy-efficient, economical, and simplified design. Low-speed buses typically have lower bandwidth and higher latency because these peripherals typically do not require fast data transfer, and this hierarchical design can help reduce power consumption and system complexity, helping to balance system performance and resource utilization. Therefore, the low-speed BUS AHB LS BUS is provided with a WDT module (Watch Dog Timer) in the SoC design, and is used for avoiding dead loops caused by program running; a PWM module (Pulse Width Modulation ) for controlling the analog circuit, i.e. the pulse width, with the digital output of the microprocessor; a TIM module (Timer) for counting an input clock and triggering an interrupt when the count value reaches a set value; the USI module (Universal SERIAL INTERFACE ) is used for realizing communication between the CPU and the computer; the GPIO module (General Purpose Input Output, general input and output) is used for carrying out data interaction with hardware to realize the input and output functions; the RTC module (Real-time clock) is used as an independent timer and can continue counting after the power of the product is off.

In the SoC design of the present invention, the requirements of the high-speed bus and the low-speed bus are comprehensively considered so as to realize high performance, low power consumption and proper resource allocation between the inside and the outside of the system. And tradeoffs various factors including performance, power consumption, physical size, cost, and application requirements to select the appropriate bus type and parameters.

Referring to fig. 5, the hardware compression core includes a bit width conversion module 5, a first FIFO (FIRST IN FIRST out) buffer module 3, a second FIFO buffer module 4, a first AXI (Advanced eXtensible Interface, one of Bus protocols) to AHB (ADVANCED HIGH-performance Bus) bridge module 1, a second AXI to AHB bridge module 2, and a hardware compression algorithm IP6, which are configured to compress original data to obtain a GZIP compression packet.

The high-speed bus of the RISC-V module is connected with a first AXI-to-AHB bridge module 1 and a second AXI-to-AHB bridge module 2; the first AXI-to-AHB bridge module 1 is connected with the first FIFO buffer module 3; the first FIFO buffer module 3 is connected with the bit width conversion module 5; the bit width conversion module 5 is connected with the input end of the hardware compression algorithm IP 6; the output end of the hardware compression algorithm IP6 is connected with the second FIFO buffer module 4; the second FIFO buffer module 4 is connected to the second AXI-to-AHB bridge module 2.

The RISC-V module adopts an AHB bus protocol, and the hardware compression algorithm IP adopts an AXIS bus protocol, so that a first AXI-to-AHB bridge module 1 and a second AXI-to-AHB bridge module 2 are built during mounting and are respectively connected with the data input end and the data output end of the hardware compression algorithm IP 6. Because the high-speed bus data is 32 bits and the data input end of the hardware compression algorithm IP6 is 8 bits, the front end of the hardware compression algorithm IP6 is also added with a bit width conversion module 5 which also accords with an AXIS bus protocol; a double-buffer design is also provided between the hardware compression algorithm IP6 and the RISC-V module, and two-stage FIFO buffer is constructed through the first FIFO buffer module 3 and the second FIFO buffer module 4, so that the efficiency of the high-performance data flow control system is improved. The design introduces two data buffer layers at the hardware level, allows parallel operation, provides hardware flow control, and provides synchronous reset at system start-up. The data stream processing module then splits the input stream into data blocks of a specified size and generates corresponding output signals to indicate the start, end, and whether the data ends of the output blocks.

In the specific embodiment of the invention, the FPGA hardware platform is Xilinx XCZ7020-2CLG400, and the clock frequency is 50Mhz; the software development platform was vivado2019.2 and sword pool CDK.

The hardware compression algorithm IP comprises the following packaging steps:

S1, respectively carrying out hardware description language design on an LZ77 (lossless compression algorithm) module and a Huffman (Huffman compression algorithm) module based on a software GZIP open source algorithm to obtain a GZIP algorithm hardware code;

S2, simulating and verifying the GZIP algorithm hardware code based on the Vivado platform to obtain a verified error-free GZIP algorithm hardware code;

Specifically, RTL code design is carried out on a Vivado platform, testbench is written to carry out simulation test on each module, a random data generation module is adopted for exciting original compressed data, a series of tasks are defined in the module to generate different types of random data, each task has different parameters for controlling the mode and the length of the generated data, one of the tasks is randomly selected to generate data flow to serve as simulation test data according to different conditions, tvalid signals in an AXIS signal simulation module are pulled up to represent valid data output currently when a data block is generated, and meanwhile, the AXIS signal simulation module also ensures that the behaviors of a signal sender and a signal receiver meet expectations, so that inconsistent or wrong data transmission cannot occur in the communication process. In this embodiment, 100 groups of original data are randomly generated for simulation, and it is observed from a simulation waveform that both an excitation signal and data are performed according to a design scheme, a generated GZIP compression packet is detected from a specified path, decompression verification processing is performed on the generated compression packet by using a script, and the result shows that the compression is correct.

S3, configuring corresponding constraint file layout and wiring to an FPGA hardware platform based on the GZIP algorithm hardware code without errors to obtain an initial hardware compression algorithm;

specifically, corresponding constraint files are configured for RTL design which passes simulation verification, the constraint files are laid out and wired, bit streams are generated and then downloaded to an FPGA platform, and Xilinx Artix-7 series chips are adopted for hardware testing.

S4, testing and verifying an initial hardware compression algorithm based on a Karl-Garland corpus data packet sent by a serial port to obtain a hardware compression algorithm with no testing error;

Specifically, the corresponding constraint file is configured to be laid out and wired into a hardware platform, a low-power-consumption and high-performance Xilinx Artix-7 series FPGA is adopted to carry out hardware test, the communication mode is that a serial port sends a data packet of a Karl-Gal corpus to the hardware platform to carry out compression operation, the compressed data is sent to an appointed path of an upper computer by the serial port, when transmission is completed, a GZIP compression packet of original data can be generated in the appointed path, the data packet is decompressed in the upper computer to verify the accuracy of the data, a script is also used for verification, the result shows that compression is correct, and then the GZIP algorithm is packaged into a custom IP, so that the IP is convenient to call when the subsequent mounting is used. The adopted Calgari corpus contains 18 sample files, and the 18 sample files respectively represent information source samples with different statistical properties, such as news articles, computer codes, poems, pictures, documents and the like, so that the compression performance is tested more abundantly.

Referring to fig. 4, the hardware compression algorithm also presents different compression results according to the data characteristics, because matching character characteristics, such as pic picture data, included in the algorithm principle are higher in data redundancy, and the same number of characters is large, so that an optimal compression result can be achieved through compression, and redundancy of common text documents and the like is lower, so that the compression rate is limited, but compared with independent LZ77 and Huffman compression, the invention achieves higher compression rate.

The compression rate is the percentage of the size of the data bytes after compression to the size of the original data bytes, and the calculation formula of the compression rate is as follows:

CR＝(cmp_size)/(org_size)×100％

Where CR represents compression rate (Compression Ratio), cmp_size represents the compressed data byte size, and org_size represents the original data byte size.

S5, packaging the hardware compression algorithm without error to obtain a hardware compression algorithm IP.

Referring to fig. 3, the algorithm of the hardware compression algorithm IP is formed by combining an LZ77 algorithm and a Huffman algorithm, and the hardware compression algorithm IP is used for compressing original data to obtain a GZIP compression packet. The original data is continuously read into a buffer zone with the size of 16k in the LZ77 algorithm module for processing, each byte is operated in sequence within the range, the current byte is output when the current byte fails to be matched successfully, the two values of the distance between the same character segments and the character segment length in the data are output when the matching is successful, the establishment of a hash table is further included in the processing process, and the matching search of the character strings is facilitated through the hash table. The input end of the Huffman algorithm module receives the data output by the LZ77 module, a corresponding Huffman binary tree is constructed according to the occurrence frequency of characters, the characters with high occurrence frequency are replaced by short sequences, the characters with low occurrence frequency are replaced by longer sequences, the further compression of the data is realized, the Huffman coding comprises static and dynamic codes, the dynamic codes are obtained by counting the frequency of the characters, the compression rate can be further optimized, the static codes can improve the compression speed, the design can reduce the circuit area and the compression time, and the serialized data can be output after the codes; after compression, each data packet is encapsulated, a header file and a check bit are added, and the data packet is encapsulated into a GZIP module which accords with the RFC1952 standard, and a compressed GZIP data stream is output; the data can be rewritten to the corresponding position through the bus according to the appointed processor address, and the data content can be obtained at any time through communication modes such as serial ports, ethernet and the like when the data is to be read. Can be compressed into a separate GZIP data stream when the data length input via the bus is greater than 32 bytes, and will not produce any output when the input data length is less than 32 bytes.

The LZ77 algorithm module adopts a multi-stage pipeline structure for encoding the original data, and executes a plurality of tasks in the same clock period according to the division of different functional modules:

The first stage is global pipeline control, which is used for determining whether to process in a block, if not, the module continuously operates to refresh the residual data in the pipeline, and a data delay stage is additionally arranged to ensure that the data and the enabling signals can be transmitted step by step so as to prepare for subsequent processing.

The second stage is hash computation and hash table reading, which is used to maintain byte counts to determine the length of the data block and to perform hash table operations, including the computation, storage and querying of hash values. Maintaining the validity of the current byte at this stage, detecting end of block and end of block flags, calculating hash values to support lookup of duplicate data blocks, and managing byte counts. In byte counting, if the module is not within the data block or the current byte is the last byte of the data block, the byte counter is cleared because it is no longer within the data block. Otherwise, the byte counter is incremented one by one, and the number of bytes in the current data block continues to be recorded. The module calculates a hash value from the first three bytes of data by means of a hash function, which hash value will be used in a subsequent step to look up the previous data block with the same hash value in the hash table. The calculated hash value is stored in a register for later use. The validity of the hash value depends on whether the first three bytes are all valid and whether none of them is the last byte of the data block. Based on the calculated hash value, the module queries the hash table to see if there is a previous block of data with the same hash value. This query operation is to help the module identify and compress duplicate data blocks, which is one of the core functions of LZ77 coding. These operations provide critical information for subsequent LZ77 encoding to effectively identify and compress repeated data blocks, thereby enabling efficient compression of data. Meanwhile, through careful state management, the correct flow of data and the accuracy of byte counting are ensured.

The third stage is data matching for identifying repeated blocks, including data stream output and status storage, record and match determination of past data, selection and reading of past data, and repeated block identification by comparing current byte data with past occurring data, which is important for reducing data stream size and improving transmission efficiency. At the same time, with proper storage and matching state management, this phase is able to accurately capture the beginning and ending states of the data match, thus preparing for LZ77 encoding generation.

The fourth stage is LZ77 coding generation, for LZ77 coding generation and management of consecutive bytes, ensuring efficient data compression coding by reasonable state management, so as to save space when storing and obtaining transmissions. When the module is in the encoding state, two key parameters of LZ77 encoding length and distance are generated and are used for representing the length and distance of the repeated blocks. And meanwhile, the method is also responsible for processing the ending condition of the data stream so as to ensure that the module can be correctly switched to process the next data stream.

The flow is carried out according to a pipeline structure, a plurality of tasks are executed in parallel in the same clock period, the execution time of a single task is reduced, the operation efficiency is greatly improved, and the parallel characteristic of hardware is exerted to the best.

After the hardware GZIP data compression system based on the RISC-V architecture is constructed, the system is applied to compress the original data, and the steps are as follows:

The method selects an FPGA development platform with sufficient hardware resources to carry out RISC-V SoC transplantation, and adopts an Xilinx ZYNQ 7020 series chip as a hardware development platform master control after the resources are occupied by an evaluation system. Hardware conditions such as a clock, a constraint file and the like are configured according to RISC-V CPU characteristics, the hardware conditions are comprehensively realized in Vivado, and the resource utilization rate and the power consumption of the hardware platform are verified. The FPGA can be debugged in CDK software after deployment is completed, and RISC-V CPU can be detected in the software after successful deployment and related peripheral equipment can be used.

Modifying RTL design, calling the hardware compression algorithm IP to connect with the reserved expansion port on RISC-V SoC BUS, selecting two reserved ports on AHB HS BUS, and respectively connecting with the data input port and the data output port of the hardware compression algorithm IP.

The upper computer software writes a program to control the operation of the processor, the cross compiling tool chain converts commands in the program into machine codes which can be identified by RISC-V, and the program is burnt into the CPU to enable the FPGA to operate according to corresponding instructions. Because executable files generated using high-level languages generally cannot run directly on processors of other architectures, instructions of the RISC-V architecture can be generated through a tool chain compilation process. The special software development tool CDK is adopted, a plurality of registers of the hardware IP are defined by using a C language, the purpose of directly processing corresponding operations by a RISC-VCPU processor without adding additional instructions, decoding the instructions and other links can be achieved after the definition, the development time of the instructions is greatly shortened, and the development efficiency is improved while the acceleration of the hardware is ensured.

The upper computer sends original data to a designated address of the processor, the data is written into the designated address along a transmission path of the bus, the address is a RISC-V SoC empty port defined in a program, the hardware compression acceleration IP is mounted on the position in RTL design, and after the program defines the address, the data is written into the position according to a set flow. When data is generated, the Valid and Ready signals in the AXIS protocol are successfully handshaked, the data of the previous stage is written into the current module, the operation of hardware IP is started, and when the IP operation is finished and output data is started, the data is written into the appointed position of the output data of the CPU through an AXI-AHB bridge of the output end, so that the data can be conveniently read out from the address at any time.

Referring to fig. 6, the upper computer program of RISC-V is burned and debugged through CK-Link, the upper computer sends the original data, and analyzes the experimental result and system performance, and the SoC end configures a communication interface to complete data input, processing and export.

While the preferred embodiment of the present application has been described in detail, the application is not limited to the embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.

Claims (7)

1. The hardware GZIP data compression system based on the RISC-V architecture is characterized by comprising a RISC-V module, a hardware compression core and an FPGA hardware platform, wherein:

the RISC-V module comprises a high-speed bus and a low-speed bus and is used as a core processor for managing and scheduling an algorithm;

The hardware compression core comprises a bit width conversion module, a first FIFO buffer module, a second FIFO buffer module, a first AXI-to-AHB bridge module, a second AXI-to-AHB bridge module and a hardware compression algorithm IP, and is used for compressing original data to obtain a GZIP compression packet;

the RISC-V module is transplanted on an FPGA hardware platform, and performs corresponding operation according to various instructions sent by a RISC-V architecture;

the high-speed bus of the RISC-V module is connected with a first AXI-to-AHB bridge module and a second AXI-to-AHB bridge module; the first AXI-to-AHB bridge module is connected with the first FIFO buffer module; the first FIFO buffer module is connected with the bit width conversion module; the bit width conversion module is connected with the IP input end of the hardware compression algorithm; the IP output end of the hardware compression algorithm is connected with the second FIFO buffer module; the second FIFO buffer module is connected with a second AXI-to-AHB bridge module.

2. The hardware GZIP data compression system according to claim 1, wherein the hardware compression algorithm IP comprises the following packaging steps:

Based on a software GZIP open source algorithm, respectively carrying out hardware description language design on the LZ77 module and the Huffman module to obtain a GZIP algorithm hardware code;

simulating and verifying the GZIP algorithm hardware code based on the Vivado platform to obtain a verified error-free GZIP algorithm hardware code;

Based on the verification error-free GZIP algorithm hardware code, configuring corresponding constraint files to be laid out and wired into an FPGA hardware platform, and obtaining an initial hardware compression algorithm;

testing and verifying an initial hardware compression algorithm based on a Karl-Gari corpus data packet sent by a serial port to obtain a hardware compression algorithm with no testing error;

and packaging the hardware compression algorithm without error to obtain the hardware compression algorithm IP.

3. The hardware GZIP data compression system based on RISC-V architecture according to claim 2, wherein the step of compressing the original data to obtain GZIP compression packets specifically includes:

Inputting the original data into an LZ77 module in a hardware compression algorithm IP for hash processing to generate a hash chain table;

Performing matching inquiry on each byte based on the hash chain table to obtain a coding length parameter and a distance parameter;

Inputting the coded data carrying the coded length parameter and the distance parameter into a Huffman module in a hardware compression algorithm IP for coding compression to obtain serialized data;

and packaging the serialized data, and adding a header file and check bits to obtain the GZIP compressed packet.

4. The system of claim 1, wherein the running of the RISC-V module is controlled by a host software programming, and commands in the host software programming are converted into machine codes recognizable by the RISC-V module by cross compiling tool chains, and the programs are burned into the CPU of the RISC-V module.

5. The hardware GZIP data compression system according to claim 1, wherein the high-speed bus is used to connect a processor, a high-performance peripheral and other components requiring fast data transmission, and is equipped with a CPU core, ISRAM module, IMEM module, DMEM module, DRAM module, and DMA module.

6. The hardware GZIP data compression system based on RISC-V architecture according to claim 1, wherein the low-speed bus is used for connecting with a peripheral device with low performance and a sensor, and is equipped with a WDT module, a PWM module, a TIM module, a USI module, a GPIO module, and an RTC module.

7. The hardware GZIP data compression system according to claim 1, wherein the hardware compression algorithm IP includes a plurality of registers, the registers being defined by a software development tool and a programming language, and the CPU of the RISC-V module directly performing instruction operations on the registers.