CN117936575A

CN117936575A - Semiconductor structure

Info

Publication number: CN117936575A
Application number: CN202211259397.7A
Authority: CN
Inventors: 陈志濠; 沈依如; 林诣超
Original assignee: Jiahe Semiconductor Co ltd
Current assignee: Jiahe Semiconductor Co ltd
Priority date: 2022-10-14
Filing date: 2022-10-14
Publication date: 2024-04-26

Abstract

The invention discloses a semiconductor structure, which comprises a first channel layer and a first barrier layer positioned on the first channel layer, wherein a first potential well is arranged in the first channel layer adjacent to the interface with the first barrier layer. The semiconductor structure further includes a second channel layer over the first barrier layer, a second barrier layer over the second channel layer, and an intermediate layer between the second channel layer and the second barrier layer, wherein the second channel layer has a second potential well adjacent to an interface with the intermediate layer. The energy gap of the intermediate layer is larger than that of the first barrier layer and the second barrier layer, and the energy gap of the first barrier layer is not smaller than that of the second barrier layer.

Description

Semiconductor structure

Technical Field

The present invention relates to semiconductor structures, and more particularly to high current density structures.

Background

In recent years, due to the increasing demand for high frequency and high power products, semiconductor power devices using gallium nitride (GaN) as a material, such as high-speed electron mobility transistor (high electron mobility transistor; HEMT) devices including aluminum gallium nitride-gallium nitride (AlGaN/GaN), have been widely used in applications such as power supplies (power supplies), DC/DC rectifiers (DC/DC converters), DC/AC converters (AC/DC INVERTER), and industrial applications because of their high electron mobility, high switching speed, and device characteristics that can operate in high frequency, high power, and high temperature operating environments, and the fields of use of high-speed electron mobility transistor devices include electronic products, uninterruptible power systems, automobiles, motors, wind power generation, and the like.

In order to pursue higher current density in the high-speed electron mobility transistor element, it is necessary to further improve the existing high-speed electron mobility transistor element.

Disclosure of Invention

The embodiment of the invention provides a semiconductor structure, which comprises a first channel layer and a second channel layer, wherein the first channel layer comprises a III-nitride semiconductor; a first barrier layer on the first channel layer, the first barrier layer comprising a group III nitride semiconductor, wherein a first potential well is provided in the first channel layer adjacent to an interface with the first barrier layer, wherein a two-dimensional electron gas is present in the first potential well; a second channel layer on the first barrier layer, wherein the second channel layer comprises a group III nitride semiconductor; a second barrier layer on the second channel layer, the second barrier layer comprising a group III nitride semiconductor; and an intermediate layer between the second channel layer and the second barrier layer, the intermediate layer comprising a group III nitride semiconductor, wherein a second potential well is present in the second channel layer adjacent to an interface with the intermediate layer, wherein a two-dimensional electron gas is present in the second potential well, wherein an energy gap of the intermediate layer is greater than an energy gap of the first barrier layer, and an energy gap of the second barrier layer, wherein the energy gap of the first barrier layer is not less than the energy gap of the second barrier layer, and is lower than the energy gap of the intermediate layer, and wherein a depth of the second potential well is greater than a depth of the first potential well in the energy band diagram.

The embodiment of the invention further provides a semiconductor structure, which comprises a plurality of channel structures, wherein the channel structures are sequentially stacked along a first direction, and each channel structure comprises a channel layer; and a barrier layer on the channel layer, wherein the channel layer and the barrier layer each comprise a group III nitride semiconductor, and a potential well is provided at an interface of the channel layer adjacent to the barrier layer, wherein the potential well is provided with a two-dimensional electron gas, wherein an energy gap of an nth barrier layer along a first direction is not greater than an energy gap of an n+1th barrier layer, and an energy gap of a topmost barrier layer is greater than an energy gap of any other barrier layer, wherein n is a natural number, and wherein in the energy band diagram, a depth of an nth potential well along the first direction is not greater than a depth of an n+1th potential well, and a depth of a topmost potential well is greater than a depth of any other potential well; and a contact layer over the channel structure, wherein the contact layer comprises a group III nitride semiconductor and the energy gap of the contact layer is not greater than the energy gap of any of the barrier layers.

Drawings

Embodiments of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale and are for illustration only, in accordance with practice standard in the industry. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced to improve the clarity of understanding for the invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention;

FIG. 2 is a band diagram of a semiconductor structure along the section line A-A' of FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

Symbol description

100 Semiconductor structure

102 Substrate

104 Buffer structure

106 Channel structure

106C contact layer

110 Interlayer(s)

116 First channel layer

116H depth

116W first potential energy well

118 First barrier layer

126 Second channel layer

126H depth

126W second potential energy well

128 Second barrier layer

128C second barrier layer

136 Third channel layer

136W third potential energy well

138 Third barrier layer

150 Source/drain electrode

160 Gate electrode

170 Dielectric layer

1N _max to N _max channel layer

1N _max W, N _max potential energy well

1N _max 8:N _max barrier layer

200 Semiconductor structure

300 Semiconductor structure

1061 First channel structure

1062 Second channel structure

106N _max N _max channel structure

A-a': line of section

EC conduction band edge

EF fermi level

Z is coordinate axis

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of the respective elements and their configurations are described below to simplify the explanation of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit embodiments of the present invention. For example, references to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "below" … …, "below," "lower," "upper," "higher," and the like may be used herein to facilitate a description of a relationship between one element(s) or feature(s) and another element(s) or feature(s) in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation and the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatial relative adjective used will also be interpreted in terms of the turned orientation.

The term "about" as used herein means that a given amount of value may vary based on the particular technology node with which the target semiconductor device is associated. In some embodiments, the term "about" may mean that a given amount of a value is, for example, in the range of 10% to 30% of the value (e.g., 10%, 20%, or 30% of the value) based on the particular technology node.

Embodiments of the present invention relate to high-speed electron mobility transistor (HEMT) devices having multiple channel numbers, and more particularly to superlattice (super lattice) structures having a gradient of aluminum (Al) concentration. The semiconductor structures of embodiments of the present invention may be included in an integrated circuit (INTEGRATED CIRCUIT; IC) such as a microprocessor, memory device, and/or other device. The integrated circuits described above may also include various passive (passive) and active (active) microelectronic elements, such as thin film resistors (thin-film resistors), other types of capacitors such as metal-insulator-metal capacitor (MIMCAP), inductors, diodes, metal-oxide-semiconductor field effect transistors (metal-oxide-semiconductor field-effect transistors; MOSFETs), complementary metal-oxide-semiconductor (complementary metal-oxide-semiconductor; CMOS) transistors, bipolar junction transistors (bipolar junction transistors; BJTs), laterally diffused metal-oxide-semiconductor (LATERALLY DIFFUSED METAL-oxide-semiconductor; LDMOS) transistors, high-power metal-oxide-semiconductor transistors, or other types of transistors.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure 100 according to an embodiment of the invention. In one embodiment, the semiconductor structure 100 includes a substrate 102. In some embodiments, the material of the substrate 102 may include a semiconductor material, which may include silicon (Si), gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), or a non-semiconductor material, which may include sapphire (sapphire). In some embodiments, if distinguished by conductivity, the base 102 may be a conductive substrate, which may include a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, etc., or an insulating substrate, which may include a sapphire substrate, a semiconductor-on-insulator (SOI) substrate, etc. In one embodiment, the substrate 102 is a silicon substrate.

With continued reference to fig. 1, in one embodiment, the semiconductor structure 100 includes a buffer structure 104 formed on a substrate 102. Forming the buffer structure 104 on the substrate 102 ensures epitaxial quality of a channel layer (e.g., the channel layer 116) or a barrier layer (e.g., the barrier layer 118) subsequently formed over the substrate 102, and relieves stress (stress) between the substrate 102 and the channel layer (e.g., the channel layer 116) due to a difference in thermal expansion coefficient from each other or relieves strain (strain) due to lattice constant mismatch (mismatch), thereby reducing lattice defects. The buffer structure 104 may be a single layer or a multi-layer structure. In some embodiments, the buffer structure 104 is a multi-layer structure and may include, for example, a graded layer (GRADING LAYER), a superlattice stack, or a stack of two or more different materials. In some embodiments, the buffer structure 104 may be a combination of a nucleation layer and a transition layer, the nucleation layer may comprise a single layer (mono layer) or a composite layer, for example, the single layer may comprise AlN, and the composite layer may comprise an alternating stack of AlN sublayers grown by low temperature epitaxy and AlN sublayers grown by high temperature epitaxy. In some embodiments, the buffer structure 104 may be formed by chemical vapor deposition (chemical vapor deposition; CVD), metal organic chemical vapor deposition (metal organic chemical vapor deposition; MOCVD), molecular beam epitaxy (molecular beam epitaxy; MBE), physical vapor deposition (physical vapor deposition; PVD), atomic layer deposition (atomic layer deposition; ALD), or other suitable fabrication process. In some embodiments, the material of the buffer structure 104 may include GaN, alN, alGaN, alInN, or AlInGaN, etc. In other embodiments, the buffer structure 104 may be doped with other elements, for example, silicon (Si), carbon (C), hydrogen (H), oxygen (O), or a combination thereof may be doped into the buffer structure 104, and the doping concentration may be graded or fixed according to the growth direction of the buffer structure 104.

With continued reference to fig. 1, in one embodiment, the semiconductor structure 100 further includes a first channel layer 116 and a first barrier layer 118, wherein the first channel layer 116 is formed on the buffer structure 104, and the first barrier layer 118 is formed on the first channel layer 116. The first channel layer 116 is in direct contact with the first barrier layer 118. Because of the work function difference between the first channel layer 116 and the first barrier layer 118, the first channel layer 116 and the first barrier layer 118 form spontaneous polarization (spontaneous polarization), and the first channel layer 116 and the first barrier layer 118 are further affected by the sum of the interactions between the different lattice constants of the first channel layer 116 and the underlying stack (e.g., buffer structure 104), thereby forming piezoelectric polarization (piezoelectric polarization) for the first barrier layer 118. Thus, the first channel layer 116 has a first potential well 116W adjacent to the interface with the first barrier layer 118 (i.e., heterojunction (heterojunction)), and the first potential well 116W has two-dimensional electron gas (two-dimensional electron gas;2 DEG) present. It is noted that the intensity of the two-dimensional electron gas is related to the thickness of the first barrier layer 118, and the larger the thickness of the first barrier layer 118 is, the higher the electron concentration of the two-dimensional electron gas is. In addition, the composition of the first barrier layer 118 also affects the polarity (e.g., in one embodiment, the first barrier layer 118 may comprise aluminum gallium nitride (AlGaN), the greater the aluminum content, the more polar the first barrier layer 118), the more polar the piezoelectric field generated between the first channel layer 116 and the first barrier layer 118, and the higher the electron concentration of the two-dimensional electron gas.

In some embodiments, the first channel layer 116 and the first barrier layer 118 may be formed by Chemical Vapor Deposition (CVD), metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other suitable fabrication process. In some embodiments, the first channel layer 116 may include a group III nitride semiconductor, and the first barrier layer 118 may include a group III nitride semiconductor having a different composition than the first channel layer 116. In one embodiment, the first channel layer 116 may comprise intrinsic gallium nitride (INTRINSIC GALLIUM NITRIDE; i-GaN, i.e., gallium nitride without impurities mixed therein), and the thickness of the first channel layer 116 may be about 250 nanometers to about 350 nanometers. In other embodiments, the first channel layer 116 may alternatively be formed by adding a minor proportion of other group III elements, such as aluminum (Al) or indium (In), to the intrinsic gallium nitride as the material of the first channel layer 116, without affecting the concentration of the two-dimensional electron gas (2 DEG). In one embodiment, the first barrier layer 118 may comprise aluminum gallium nitride (AlGaN), and the thickness of the first barrier layer 118 may be about 5 nanometers to about 10 nanometers. If the thickness of the first barrier layer 118 is too small, it may not be possible to effectively enhance the polarization formation of the two-dimensional electron gas (2 DEG), and if the thickness of the first barrier layer 118 is too large, it may be possible to concentrate the electric field too much under the edge of the gate electrode of the semiconductor device. In one embodiment, the atomic percent of Al in the group III element of the first barrier layer 118 is no greater than 50% and the atomic percent of Al in the group III element of the first barrier layer 118 is no less than 20%.

With continued reference to fig. 1, in one embodiment, the semiconductor structure 100 has a second channel to increase the current density of the device. In one embodiment, the semiconductor structure 100 further includes a second channel layer 126, an intermediate layer 110, and a second barrier layer 128C, wherein the second channel layer 126 is formed on the first barrier layer 118, the second barrier layer 128C is formed over the second channel layer 126, and the intermediate layer 110 is formed between the second channel layer 126 and the second barrier layer 128C. Similar to the first channel layer 116 and the first barrier layer 118, the second channel layer 126 has a second potential well 126W adjacent to the interface (i.e., heterojunction) with the intermediate layer 110 because of the work function difference between the second channel layer 126 and the intermediate layer 110, and the second potential well 126W has a two-dimensional electron gas (2 DEG) present. In one embodiment, the energy gap of the intermediate layer 110 is greater than the energy gap of the first barrier layer 118 and greater than the energy gap of the second barrier layer 128C. In one embodiment, the energy gap of the first barrier layer 118 is not less than the energy gap of the second barrier layer 128C and is lower than the energy gap of the intermediate layer 110. The above-described energy gap refers to an energy difference between a valence band (valance band) and a conduction band (conduction band). In one embodiment, the energy gap of the first barrier layer 118 is at most 0.25eV greater than the energy gap of the second barrier layer 128C, e.g., the energy gap of the first barrier layer 118 is 0.15eV greater than, or 0.05eV greater than, the energy gap of the second barrier layer 128C.

In some embodiments, the second channel layer 126, the intermediate layer 110, and the second barrier layer 128C may be formed by Chemical Vapor Deposition (CVD), metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other suitable fabrication process. In some embodiments, the second channel layer 126 may include a group III nitride semiconductor, the intermediate layer 110 may include a group III nitride semiconductor having a different composition than the second channel layer 126, and the second barrier layer 128C may include a group III nitride semiconductor having a different composition than the second channel layer 126 and the intermediate layer 110. In an embodiment, the second channel layer 126 is the same as the first channel layer 116, the second channel layer 126 may include intrinsic gallium nitride (i-GaN), and the thickness of the second channel layer 126 may be about 5 nanometers to about 30 nanometers. In one embodiment, the intermediate layer 110 may comprise aluminum nitride (AlN), and the thickness of the intermediate layer 110 is about 0.5 nm to about 2 nm. In one embodiment, similar to the first barrier layer 118, the second barrier layer 128C may comprise aluminum gallium nitride (AlGaN), but with the difference that: the Al concentration of the first barrier layer 118 is not less than the Al concentration of the second barrier layer 128C, and the thickness of the second barrier layer 128C may be greater than the thickness of the first barrier layer 118. In one embodiment, the thickness of the second barrier layer 128C may be greater than the thickness of the intermediate layer 110. In one embodiment, the thickness of the second barrier layer 128C may be about 6 nm to about 30 nm. In one embodiment, the Al concentration of the intermediate layer 110 is greater than the Al concentration of the first barrier layer 118 and greater than the Al concentration of the second barrier layer 128C.

With continued reference to fig. 1, in one embodiment, the semiconductor structure 100 further includes source/drain electrodes 150, a gate electrode 160, and a dielectric layer 170. Source/drain electrodes 150 and gate electrode 160 are formed on the second barrier layer 128C. The source/drain electrodes 150 are formed on both sides of the gate electrode 160, and the dielectric layer 170 separates the source/drain electrodes 150 and the gate electrode 160 from each other. In some embodiments, the source/drain electrodes 150 and the gate electrode 160 may be formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), or other suitable methods. In some embodiments, the dielectric layer 170 may be formed by Chemical Vapor Deposition (CVD), spin-on coating (spin-on coating), atomic Layer Deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or other suitable methods. In some embodiments, the gate electrode 160 may include polysilicon, aluminum, nickel, gold, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide (NICKEL SILICIDE), cobalt silicide (cobalt silicide), titanium nitride, tungsten nitride, tiAl, tiAlN, taCN, taC, taSiN, a metal alloy, or other suitable material. The source/drain electrodes 150 may comprise titanium, aluminum, or other suitable materials. Dielectric layer 170 may comprise silicon oxide, silicon nitride, or other suitable materials.

Fig. 2 is a band diagram illustrating a semiconductor structure 100 along a cross-section line A-A' of fig. 1, according to an embodiment of the present invention. In fig. 2, fermi (Fermi) energy level is denoted as E _F and conduction band edge is denoted as E _C. In one embodiment, multiple heterojunction is formed with a stack of multiple group III nitride semiconductors (e.g., first channel layer 116, first barrier layer 118, second channel layer 126, and intermediate layer 110), resulting in multiple bending of the energy band. The deep bend of the conduction band forms a potential well, for example, a first potential well 116W is formed in the first channel layer 116 adjacent to the interface with the first barrier layer 118, a second potential well 126W is formed in the second channel layer 126 adjacent to the interface with the intermediate layer 110, and two-dimensional electron gas (2 DEG) is present in the first and second potential wells 116W, 126W. The high energy band of the intermediate layer 110 facilitates the operation of the device in the OFF state (OFF state), effectively avoiding the generation of leakage current. In some embodiments, changing the aluminum concentration may be used to change the work function of the group III nitride semiconductor, thereby controlling the depth of the potential well. In some embodiments, the depth 126H of the second bit-energy well 126W is greater than the depth 116H of the first bit-energy well 116W, i.e., the two-dimensional electron gas concentration of the second bit-energy well 126W is greater than the two-dimensional electron gas concentration of the first bit-energy well 116W. Because the energy band of the intermediate layer 110 is higher than the second barrier layer 128C, in one embodiment, the metal of the source/drain electrode 150 forms an ohmic contact with the second barrier layer 128C, indicating that there is no energy band difference at the metal-semiconductor interface, and the energy band of the intermediate layer 110 is higher than the second barrier layer 128C, but forms a tunneling energy barrier by the energy band matching of the second barrier layer 128C, the intermediate layer 110, and the first barrier layer 118. In addition, the depths of the second well 126W and the first well 116W decrease according to their depths in the semiconductor structure 100, so that the deep well can be effectively turned off even if the gate potential is affected by the series voltage drop, which facilitates the operation of the device in the off state. In some embodiments, the depth 126H of the second bit-well 126W is at least 0.5eV deeper than the depth 116H of the first bit-well 116W, e.g., 0.2eV deep, 0.3eV deep, 0.4eV deep, etc.

Fig. 3 is a schematic cross-sectional view of a semiconductor structure 200 according to another embodiment of the invention. The further embodiment is similar to the one embodiment, but differs in that the further embodiment further forms a third channel. In another embodiment, after the buffer structure 104 is formed, the third channel layer 136 and the third barrier layer 138 are formed, and then the first channel layer 116 is formed on the third barrier layer 138. Thus, the third barrier layer 138 is located between the first channel layer 116 and the substrate 102, and the third channel layer 136 is located between the third barrier layer 138 and the substrate 102. Other components of semiconductor structure 200 may be described with reference to semiconductor structure 100 above and for simplicity, will not be repeated here. Similar to the first channel layer 116 and the first barrier layer 118, because the third channel layer 136 and the third barrier layer 138 have work function differences, the third channel layer 136 has a third potential well 136W adjacent to the interface (i.e., heterojunction) with the third barrier layer 138, and the third potential well has two-dimensional electron gas (2 DEG) present. In the alternative embodiment, the energy gap of the third barrier layer 138 is no greater than the energy gap of the first barrier layer 118. In the alternative embodiment, the energy gap of the first barrier layer 118 is greater than the energy gap of the third barrier layer 138. In the other embodiment, the energy gap of the first barrier layer 118 is at least 0.2eV greater than the energy gap of the third barrier layer 138, such as 0.25eV greater, 0.3eV greater, 0.4eV greater, etc. In the other embodiment, the energy gap of the third barrier layer 138 is not smaller than the energy gap of the second barrier layer 128C.

In some embodiments, the third channel layer 136 and the third barrier layer 138 may be formed by Chemical Vapor Deposition (CVD), metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other suitable fabrication process. In some embodiments, the third channel layer 136 may include a group III nitride semiconductor, and the third barrier layer 138 may include a group III nitride semiconductor having a different composition than the third channel layer 136. In the other embodiment, the third channel layer 136 may include intrinsic gallium nitride (i-GaN), and the thickness of the third channel layer 136 may be about 5 nm to about 10 nm. In the other embodiment, the third barrier layer 138 may include aluminum gallium nitride (AlGaN), and the thickness of the third barrier layer 138 may be about 5 nanometers to about 10 nanometers. In the other embodiment, the Al concentration of the first barrier layer 118 is greater than the Al concentration of the third barrier layer 138, the atomic percent of Al in the group III element of the first barrier layer 118 is no greater than 50%, and the atomic percent of Al in the group III element of the first barrier layer 118 is no less than 20%. Thus, in the energy band diagram (not shown) of the other embodiment, the depth of the third potential well 136W is smaller than the depth 116H of the first potential well 116W. In the other embodiment, the Al concentration of the third barrier layer 138 is not less than the Al concentration of the second barrier layer 128C.

Fig. 4 is a schematic cross-sectional view of a semiconductor structure 300 according to another embodiment of the invention. The further embodiment is similar to the one embodiment, but differs in that the further embodiment has N _max channels. In yet another embodiment, after the buffer structure 104 is formed, a channel structure 106 is then formed on the buffer structure 104. Forming the channel structure 106 includes sequentially stacking the first channel structure 1061 and the second channel structure 1062 along a first direction (e.g., coordinate axis Z) until an N _max th channel structure 106N _max is formed. The first channel structure 1061 includes a first channel layer 116 and a first barrier layer 118 formed on the first channel layer 116. Similar to the embodiment, because the first channel layer 116 and the first barrier layer 118 have work function differences, the first channel layer 116 has a first potential well 116W at an interface (i.e., heterojunction) adjacent to the first barrier layer 118, and a two-dimensional electron gas (2 DEG) is present in the first potential well 116W. In the further embodiment, the first channel layer 116W and the first barrier layer 118 each include a group III nitride semiconductor of different composition. The second channel structure 1062 through the N _max channel structure 106N _max are similar to the first channel structure 1061 in that they include a channel layer (e.g., the channel layer 126/136 …/1N _max 6) and a barrier layer (e.g., the barrier layer 128/138 …/1N _max). In yet another embodiment, the energy gap of the N-th (N is a natural number) barrier layer 1N _n in the first direction (e.g., coordinate axis Z) is no greater than the energy gap of the n+1st barrier layer 1N _n+1 8, and the energy gap of the topmost barrier layer 1N _max is greater than the energy gap of any other barrier layer (e.g., barrier layer 118/128 …/1N _max-1 8). After forming the channel structure 106, a contact layer 106C may be formed on the channel structure 106, i.e., on the topmost barrier layer 1N _max, followed by forming source/drain electrodes 150, gate electrodes 160, and a dielectric layer 170 similar to the one described in the embodiment. In yet another embodiment, the contact layer 106C may comprise a III-nitride semiconductor, and the energy gap of the contact layer 106C is not greater than the energy gap of any of the barrier layers described above (e.g., barrier layer 118/128 …/1N _max- ₁).

In the energy band diagram of the further embodiment (not shown), the depth of the nth bit energy well 1N _n W along the first direction (e.g., coordinate axis Z) is not greater than the depth of the n+1st bit energy well 1N _n+1 W, and the depth of the topmost bit energy well 1N _max W is greater than the depth of any other bit energy well (e.g., bit energy wells 116W/126W …/1N _max-1 W). In yet another embodiment, the energy gap of the topmost barrier layer 1N _max 8 is at least 0.2eV greater than the energy gap of any of the other barrier layers described above (e.g., barrier layer 118/128 …/1N _max-1), such as 0.25eV greater, 0.3eV greater, 0.4eV greater, etc. In yet another embodiment, the energy gap of the n+1th barrier layer 1N _n+1 is at least 0.2eV greater than the energy gap of the N barrier layer 1N _n 8. In other embodiments, the energy gap of the n+1st barrier layer 1N _n+1 is equal to the energy gap of the N1N _n barrier layer in the other barrier layers described above (e.g., barrier layers 118/128 …/1N _max-1). In yet another embodiment, the atomic percent of Al in the group III element of the topmost barrier layer 1N _max is at least 20% greater than the atomic percent of Al in the group III element of the other barrier layers described above (e.g., barrier layer 118/128 …/1N _max-1). In yet another embodiment, the atomic percent of Al in the group III element of the n+1th barrier layer 1N _n+1 is at least 20% greater than the atomic percent of Al in the group III element of the N barrier layer 1N _n, i.e., the semiconductor structure 300 has a gradient of Al concentration. In other embodiments, the Al concentration of the n+1th barrier layer 1N _n+1 is equal to the Al concentration of the N barrier layer 1N _n in the other barrier layers described above (e.g., barrier layers 118/128 …/1N _max-1). In yet another embodiment, the channel layer (e.g., channel layer 116/126 …/1N _max-1 6) may have a thickness of about 5 nanometers to about 20 nanometers. In yet another embodiment, any of the other barrier layers described above (e.g., barrier layer 118/128 …/1N _max-1) may have a thickness of about 5 nanometers to about 10 nanometers. In yet another embodiment, the thickness of the topmost barrier layer 1N _max 8 may be between about 0.5 nm and about 2 nm.

In summary, the embodiments of the present invention provide a semiconductor structure with a plurality of channels, wherein the difference of work functions is caused by the variation of the Al concentration in the barrier layer, so as to control the energy band profile of the device, form a plurality of potential wells as required, obtain a high current density, and improve the leakage current problem of the device in the off state. It should be understood that not all advantages have necessarily been discussed herein, that all embodiments need not have particular advantages, and that other embodiments may provide different advantages.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present invention. Those skilled in the art will appreciate that other processes and structures can be readily utilized as a basis for designing or modifying other structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It will be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be determined from the following claims.

Claims

1. A semiconductor structure, comprising:

A first channel layer including a group III nitride semiconductor;

A first barrier layer on the first channel layer, the first barrier layer comprising a group III nitride semiconductor; wherein the first channel layer has a first potential well adjacent to an interface with the first barrier layer; wherein the first potential energy well has two-dimensional electron gas (two-dimensionalelectron gas;2 DEG);

a second channel layer on the first barrier layer, the second channel layer comprising a group III nitride semiconductor;

a second barrier layer on the second channel layer, the second barrier layer comprising a group III nitride semiconductor; and

An intermediate layer between the second channel layer and the second barrier layer, the intermediate layer comprising a group III nitride semiconductor, wherein a second potential well is provided in the second channel layer adjacent to an interface with the intermediate layer, wherein the second potential well has a two-dimensional electron gas present therein;

Wherein the energy gap of the intermediate layer is larger than the energy gap of the first barrier layer and the energy gap of the second barrier layer;

Wherein the energy gap of the first barrier layer is not less than the energy gap of the second barrier layer and is lower than the energy gap of the intermediate layer; and

Wherein in the energy band diagram, the depth of the second potential well is greater than the depth of the first potential well.

2. The semiconductor structure of claim 1, wherein an energy gap of the first barrier layer is at most 0.25eV greater than an energy gap of the second barrier layer.

3. The semiconductor structure of claim 1, wherein a depth of said second potential well is at least 0.5eV deeper than a depth of said first potential well.

4. The semiconductor structure of claim 1, wherein an Al concentration of the intermediate layer is greater than an Al concentration of the first barrier layer and an Al concentration of the second barrier layer.

5. The semiconductor structure of claim 1 wherein the Al concentration of the first barrier layer is not less than the Al concentration of the second barrier layer.

6. The semiconductor structure of claim 1 wherein the atomic percent of Al in the group III element of the first barrier layer is not greater than 50% and the atomic percent of Al in the group III element of the first barrier layer is not less than 20%.

7. The semiconductor structure of claim 1, wherein a thickness of the second channel layer is between 5 nm and 30 nm, a thickness of the first barrier layer is between 5 nm and 10 nm, a thickness of the intermediate layer is between 0.5 nm and 2 nm, and a thickness of the first channel layer is between 250 nm and 350 nm.

8. The semiconductor structure of claim 1, further comprising:

a substrate under the first channel layer;

A third barrier layer between the first channel layer and the substrate; and

A third channel layer between the third barrier layer and the substrate;

Wherein a third potential well is arranged in the third channel layer adjacent to the interface with the third barrier layer; wherein the third potential energy well has two-dimensional electron gas.

9. The semiconductor structure of claim 8, wherein in the energy band diagram, a depth of the third potential well is less than a depth of the first potential well, or an energy gap of the first barrier layer is greater than an energy gap of the third barrier layer, or an energy gap of the third barrier layer is not less than an energy gap of the second barrier layer.

10. A semiconductor structure, comprising:

The plurality of channel structures are sequentially stacked along the first direction; wherein each channel structure comprises:

A channel layer; and

A barrier layer on the channel layer; wherein the channel layer and the barrier layer each comprise a group III nitride semiconductor and the channel layer has a potential well adjacent an interface of the barrier layer; wherein the potential energy trap has two-dimensional electron gas;

Wherein the energy gap of the n-th barrier layer along the first direction is not greater than the energy gap of the n+1th barrier layer, and the energy gap of the topmost barrier layer is greater than the energy gap of any other barrier layer, wherein n is a natural number, and

In the energy band diagram, the depth of the nth bit energy well along the first direction is not greater than the depth of the n+1th bit energy well, and the depth of the topmost bit energy well is greater than the depth of any other bit energy well; and

And a contact layer over the channel structures, wherein the contact layer comprises a III-nitride semiconductor and has an energy gap not greater than an energy gap of any of the barrier layers.