CN117936553A

CN117936553A - Display substrate and display device

Info

Publication number: CN117936553A
Application number: CN202410096342.1A
Authority: CN
Inventors: 张超; 赵永亮
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2024-01-23
Filing date: 2024-01-23
Publication date: 2024-04-26

Abstract

A display substrate and a display device are provided. The display substrate comprises a base and at least one pixel driving circuit positioned on the base, wherein the at least one pixel driving circuit comprises at least one transistor, the at least one transistor comprises an active layer, and the active layer comprises a channel region, a first region and a second region which are positioned on two opposite sides of the channel region; the first region is provided with a first end and a second end which are oppositely arranged, the first end of the first region is connected with the channel region, and the second end extends along a second direction; the channel region has a first width along a first direction, the first region has a second width along the first direction, the first width is greater than the second width, and the display substrate further comprises a compensation line, a first end of the compensation line is connected with the channel region, and a second end of the compensation line is connected with a second end of the first region; wherein the first direction intersects the second direction. The display substrate provided by the embodiment of the disclosure can avoid the problem of threshold voltage divergence of the transistor by arranging the compensation line, and can improve the service performance of the transistor.

Description

Display substrate and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

Organic LIGHT EMITTING Diodes (OLED) and Quantum-dot LIGHT EMITTING Diodes (QLED) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high reaction speed, light weight, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and a thin film transistor (Thin Film Transistor, abbreviated as TFT) for signal control has become a mainstream product in the current Display field.

At present, there are problems such as threshold voltage dispersion of individual transistors in the conventional display substrate.

Disclosure of Invention

Embodiments of the present disclosure provide a display substrate and a display device, which can improve the problem of threshold voltage dispersion of individual transistors in the existing display substrate.

In one aspect, embodiments of the present disclosure provide a display substrate including a base and at least one pixel driving circuit on one side of the base, the at least one pixel driving circuit including at least one transistor including an active layer including a channel region and first and second regions on opposite sides of the channel region; the first region has a first end and a second end which are oppositely arranged, the first end of the first region is connected with the channel region, and the second end extends along a second direction;

The channel region has a first width along a first direction, the first region has a second width along the first direction, the first width is greater than the second width, and the display substrate further includes a compensation line, a first end of the compensation line is connected with the channel region, and a second end of the compensation line is connected with a second end of the first region; wherein the first direction intersects the second direction.

In some exemplary embodiments, the absolute value of the difference between the first width and the second width is greater than 10% of the first width.

In some exemplary embodiments, the display substrate further includes at least one capacitor, the at least one capacitor is closer to the substrate than the compensation line, and the capacitor is located at one side of the compensation line in the extending direction, and the capacitor includes two polar plates disposed oppositely, where an orthographic projection of the compensation line on the substrate and an orthographic projection of the two polar plates on the substrate do not overlap.

In some exemplary embodiments, the compensation line is disposed in the same layer as the active layer.

In some exemplary embodiments, the display substrate further includes a first connection bridge having a first end and a second end disposed opposite in the first direction, the first end of the first connection bridge being connected to the second end of the compensation line, the second end of the first connection bridge being connected to the second end of the first region of the active layer.

In some exemplary embodiments, the display substrate further includes at least one second connection bridge between the first connection bridge and the channel region, and the at least one second connection bridge between the first region and the compensation line; the second connecting bridge extends along the first direction and comprises a first end and a second end which are oppositely arranged; the first end of the second connecting bridge is connected with the compensation line, and the second end of the second connecting bridge is connected with the first region.

In some exemplary embodiments, the first connection bridge, the at least one second connection bridge, and the compensation line are an integral structure that is interconnected.

In some exemplary embodiments, the compensation line is located at a side of the active layer remote from the substrate.

In some exemplary embodiments, the display substrate further includes a semiconductor layer, a first source drain metal layer, and a second source drain metal layer sequentially located at one side of the base in a plane perpendicular to the display substrate;

The active layer is located on the semiconductor layer, and the compensation line is located on the first source drain metal layer or the second source drain metal layer.

In some exemplary embodiments, the display substrate further includes a first bridge electrode and a second bridge electrode; the front projection of the first bridging electrode at the substrate at least partially overlaps the front projection of the first end of the first region at the substrate, and the front projection of the second bridging electrode at the substrate at least partially overlaps the front projection of the second end of the first region at the substrate; the orthographic projection of the compensation line on the substrate is overlapped with the orthographic projection of the first bridging electrode and the second bridging electrode on the substrate;

Wherein the compensation line is connected to the first end of the first region via the first bridge electrode, and the compensation line is connected to the second end of the first region via the second bridge electrode.

In some exemplary embodiments, the first bridge electrode and the second bridge electrode are both located at the first source drain metal layer, and the compensation line is located at the second source drain metal layer.

In some exemplary embodiments, there is at least a partial overlap of the orthographic projection of the compensation line at the substrate with the orthographic projection of the first region at the substrate.

In some exemplary embodiments, the compensation line is located within the orthographic projection of the first region on the substrate.

In some exemplary embodiments, the at least one transistor is a drive transistor; the at least one pixel driving circuit further includes a light emission control transistor connected to the second end of the first region.

In another aspect, an embodiment of the present disclosure provides a display device including the display substrate according to any one of the foregoing embodiments.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the principles of the application, and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the principles of the application.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic plan view of a display substrate;

FIG. 3 is a schematic cross-sectional view of a display substrate;

Fig. 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an embodiment of the disclosure;

Fig. 4A is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to another embodiment of the disclosure;

Fig. 4B is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to still another embodiment of the disclosure;

FIG. 5 is a schematic view of a partial planar structure of a display substrate according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to an embodiment of the disclosure;

fig. 7A and 7B are schematic views of a display substrate after forming a second conductive layer pattern according to an embodiment of the disclosure;

Fig. 8A and 8B are schematic views of a display substrate after forming a semiconductor layer pattern according to an embodiment of the disclosure;

Fig. 9A and 9B are schematic views of a display substrate after forming a third conductive layer pattern according to an embodiment of the disclosure;

FIG. 10 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an embodiment of the disclosure;

fig. 11A and 11B are schematic views of a display substrate after forming a fourth conductive layer pattern according to an embodiment of the disclosure;

FIG. 12 is a schematic view of a partial planar structure of a display substrate according to another embodiment of the disclosure;

Fig. 13A and 13B are schematic views illustrating a display substrate after forming a semiconductor layer pattern according to another embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to another embodiment of the disclosure;

Fig. 15A and 15B are schematic views of a display substrate after forming a fourth conductive layer pattern according to another embodiment of the disclosure;

FIG. 16 is a schematic diagram of a display substrate after forming a fifth insulating layer pattern according to another embodiment of the disclosure;

fig. 17A and 17B are schematic diagrams illustrating a display substrate after forming a fifth conductive layer pattern according to another embodiment of the disclosure.

Reference numerals:

101-a substrate, 102-a driving circuit layer, 103-a light emitting structure layer, 104-a packaging structure layer;

11-first polar plate, 12-second polar plate, 12-1-first sub polar plate, 12-2-second sub polar plate, 13-third polar plate, 14-fourth polar plate, 14-1-first sub block, 14-2-second sub block, 14-3-third sub block and 15-polar plate connecting block;

24-fourth bottom gate electrode, 24-1-fourth bottom gate connection block, 26-sixth bottom gate electrode, 27-shielding line;

33-third active layer, 34-fourth active layer, 35-fifth active layer, 36-sixth active layer, 38-compensation line, 38-1-first connection bridge, 38-2-second connection bridge;

43-third top gate electrode, 44-fourth top gate electrode, 44-1-fourth top gate connection block, 46-sixth top gate electrode, 46-1-sixth top gate connection block, 48-light emitting signal line;

50-power supply connection lines, 51-first connection electrodes, 52-second connection electrodes, 53-third connection electrodes, 54-third scanning signal lines, 54-1-first connection blocks, 54-2-second connection blocks, 54-3-main body parts, 55-fourth scanning signal lines, 56-first bridge electrodes, 57-second bridge electrodes; 61-data signal line, 62-first power supply line.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the patterns and matters may be changed into one or more forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal terms such as "first," "second," "third," and the like in the present disclosure are provided to avoid intermixing of constituent elements, and are not intended to be limiting in number. The term "plurality" in this disclosure includes two as well as more than two numbers.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The meaning of the above terms in the present disclosure can be understood by one of ordinary skill in the art as appropriate.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In this disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having one or more functions, and the like.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and thus, may include a state in which the angle is-5 ° or more and 5 ° or less. Further, "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus may include a state in which an angle is 85 ° or more and 95 ° or less.

In this disclosure, "film" and "layer" may be interchanged. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

The embodiment of the disclosure provides a display substrate, which comprises a base and at least one pixel driving circuit positioned at one side of the base, wherein the at least one pixel driving circuit comprises at least one transistor, the at least one transistor comprises an active layer, and the active layer comprises a channel region, a first region and a second region positioned at two opposite sides of the channel region; the first region has a first end and a second end which are oppositely arranged, the first end of the first region is connected with the channel region, and the second end extends along a second direction;

According to the display substrate provided by the embodiment of the disclosure, the relation between the first width and the second width is limited, and the problem that the threshold voltage of the transistor diverges can be avoided by arranging the compensation line, and the service performance of the transistor can be improved.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller being connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver being connected to a plurality of data signal lines (D1 to Dn), the scan driver being connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver being connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected with a scan signal line, a light emitting signal line, and a data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide gray values and control signals suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray values and control signals received from the timing controller. For example, the data driver may sample the gray value using a clock signal, and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and may sequentially generate the scan signals in such a manner that the scan start signal supplied in the form of an on-level pulse is transmitted to the next stage circuit under the control of the clock signal, and m may be a natural number. The light emitting driver may generate the emission signals to be supplied to the light emitting signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission driver may sequentially supply the emission signal having the off-level pulse to the light emission signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate the emission signal in such a manner that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on the display substrate.

Fig. 2 is a schematic plan view of a display substrate. In an exemplary embodiment, the display substrate may include a display region and a bezel region located at a periphery of the display region. As shown in fig. 2, the display area of the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and a third sub-pixel P3 emitting light of a third color. Each sub-pixel may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line, the data signal line, and the light emitting signal line, respectively, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light emitting device under control of the scan signal line and the light emitting signal line. The light emitting unit may include at least light emitting devices respectively connected to the pixel driving circuits of the sub-pixels, the light emitting devices being configured to emit light of corresponding brightness in response to a current output from the pixel driving circuits of the sub-pixels.

In some exemplary embodiments, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light. In an example, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels may be arranged in a horizontal juxtaposition, a vertical juxtaposition, or a delta, which is not limited herein.

In some exemplary embodiments, the pixel unit may include four sub-pixels, which may be arranged in a horizontal juxtaposition, a vertical juxtaposition, or a square, etc., without limitation of the disclosure herein.

Fig. 3 is a schematic cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in fig. 3, on a plane perpendicular to the display substrate, the display region of the display substrate may include a driving circuit layer 102 disposed on a base 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base 101, and a package structure layer 104 disposed on a side of the light emitting structure layer 103 away from the base 101. In some possible implementations, the display substrate may further include other film layers, such as a touch structure layer, etc., which are not limited herein.

In some exemplary embodiments, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinylchloride, polyethylene, textile fibers.

In some exemplary embodiments, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, the materials of the first flexible material layer and the second flexible material layer may be Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water-oxygen resistance of the substrate, and the materials of the semiconductor layer may be amorphous silicon (a-si).

In some exemplary embodiments, the driving circuit layer 102 may include a plurality of circuit units, which may include at least a pixel driving circuit, which may include a plurality of transistors and capacitors. The light emitting structure layer 103 may include a plurality of light emitting units, the light emitting units may include at least a light emitting device, the light emitting device may include an anode, an organic light emitting layer, and a cathode, the anode is connected with the pixel driving circuit, the organic light emitting layer is connected with the anode, the cathode is connected with the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

In some exemplary embodiments, the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, where the first encapsulation layer and the third encapsulation layer may be made of an inorganic material, the second encapsulation layer may be made of an organic material, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stacked structure, so that external moisture may not enter the light emitting structure layer 103.

In some exemplary embodiments, the organic light emitting layer may include an emitting layer (EML) and any one or more of the following: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL).

Fig. 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an embodiment of the disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. As shown in fig. 4, the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 7T2C structure, and may include 7 transistors (first to seventh transistors T1 to T7) and 2 capacitors C, and is connected to 9 signal lines (first, second, third, fourth, and reference signal lines S1, S2, S3, and S4, and EM, and REF, initial signal lines INIT, DATA signal line DATA, and first power supply line VDD), respectively.

In some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second pole of the first transistor T1, the first pole of the sixth transistor T6, and the gate electrode of the third transistor T3, the second node N2 is connected to the second pole of the fourth transistor T4, the second pole of the sixth transistor T6, and the second end of the second capacitor C2, the third node N3 is connected to the second pole of the third transistor T3, the second pole of the seventh transistor T7, and the second end of the first capacitor C1, and the fourth node N4 is connected to the second pole of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2.

In some exemplary embodiments, the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the reference signal line REF, and a second electrode of the first transistor T1 is connected to the first node N1.

In some exemplary embodiments, the second transistor T2 may be referred to as a second reset transistor, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the reference signal line REF, and the second electrode of the second transistor T2 is connected to the fourth node N4.

In some exemplary embodiments, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first pole of the third transistor T3 is connected to a second pole of the fifth transistor T5, and a second pole of the third transistor T3 is connected to the third node N3.

In some exemplary embodiments, the fourth transistor T4 may be referred to as a DATA writing transistor, the gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the DATA signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

In some exemplary embodiments, the fifth transistor T5 may be referred to as a light emission control transistor, the gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

In some exemplary embodiments, the sixth transistor T6 may be referred to as a data control transistor, the gate electrode of the sixth transistor T6 is connected to the fourth scan signal line S4, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the second node N2.

In some exemplary embodiments, the seventh transistor T7 may be referred to as a third reset transistor, the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the third node N3.

In some exemplary embodiments, a first pole of the light emitting device EL is connected to the third node N3, and a second pole of the light emitting device EL is connected to the second power line VSS. The light emitting device EL may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

In some exemplary embodiments, seven transistors of the pixel driving circuit may be N-type transistors. The pixel driving circuit adopts the transistors of the same type, so that the process flow can be simplified, the process difficulty of the display substrate is reduced, and the yield of products is improved.

In some exemplary embodiments, six transistors of the pixel driving circuit may employ oxide transistors. An active layer of the Oxide transistor may employ an Oxide semiconductor (Oxide). The oxide transistor has the advantages of high electron mobility, low operating voltage, low leakage characteristic and the like, and the display substrate provided with the oxide transistor can realize low-frequency driving, reduce power consumption and improve display quality.

In some exemplary embodiments, the first power line VDD may be configured to supply a constant first voltage signal to the pixel driving circuit, the second power line VSS may be configured to supply a constant second voltage signal to the light emitting device, and the first voltage signal is greater than the second voltage signal. The reference signal and the initial signal may be constant voltage signals, and the disclosure is not limited herein.

Fig. 4A is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to another embodiment of the disclosure. As shown in fig. 4A, the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 7T2C structure, and may include 7 transistors (first to seventh transistors T1 to T7) and 2 capacitors C, and is connected to 10 signal lines (first, second, third, fourth, and first, second, and second light emitting signal lines S1, EM2, and REF, an initial signal line INIT, a DATA signal line DATA, and a first power supply line VDD), respectively.

In some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second pole of the first transistor T1 and the gate electrode of the third transistor T3, the second node N2 is connected to the second pole of the fourth transistor T4 and the second end of the second capacitor C2, the third node N3 is connected to the second pole of the third transistor T3, the second pole of the seventh transistor T7, the second pole of the sixth transistor T6 and the second end of the first capacitor C1, and the fourth node N4 is connected to the second pole of the second transistor T2, the first end of the first capacitor C1 and the first end of the second capacitor C2.

In some exemplary embodiments, the second transistor T2 may be referred to as a second reset transistor, the gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the reference signal line REF, and the second electrode of the second transistor T2 is connected to the fourth node N4.

In some exemplary embodiments, the fourth transistor T4 may be referred to as a DATA writing transistor, the gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, the first electrode of the fourth transistor T4 is connected to the DATA signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

In some exemplary embodiments, the fifth transistor T5 may be referred to as a first light emitting control transistor, a gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1, a first pole of the fifth transistor T5 is connected to the first power line VDD, and a second pole of the fifth transistor T5 is connected to a first pole of the third transistor T3.

In some exemplary embodiments, the sixth transistor T6 may be referred to as a second light emission control transistor, the gate electrode of the sixth transistor T6 is connected to the second light emission signal line EM2, the second electrode of the sixth transistor T6 is connected to the third node N3, and the first electrode of the sixth transistor T6 is connected to the light emitting device EL.

In some exemplary embodiments, the seventh transistor T7 may be referred to as a third reset transistor, the gate electrode of the seventh transistor T7 is connected to the third scan signal line S3, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the third node N3.

In some exemplary embodiments, a first pole of the light emitting device EL is connected to a first pole of the sixth transistor T6, and a second pole of the light emitting device EL is connected to the second power line VSS. The light emitting device EL may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

Fig. 4B is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to still another embodiment of the disclosure. As shown in fig. 4B, the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 5T1C structure, and may include 5 transistors (first to fifth transistors T1 to T5) and 1 capacitor C, and is connected to 8 signal lines (first, second, third, and light emitting signal lines EM, reference signal lines REF, initial, DATA signal lines INIT, and first power supply lines VDD), respectively.

In some exemplary embodiments, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second pole of the first transistor T1, the second pole of the second transistor T2, the gate electrode of the fifth transistor T5, and the first end of the first capacitor C1, and the second node N2 is connected to the second end of the first capacitor C1, the second pole of the fifth transistor T5, the second pole of the third transistor T3, and the first pole of the light emitting device EL, respectively.

In some exemplary embodiments, the first transistor T1 may be referred to as a DATA writing transistor, the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first pole of the first transistor T1 is connected to the DATA signal line DATA, and the second pole of the first transistor T1 is connected to the first node N1.

In some exemplary embodiments, the second transistor T2 may be referred to as a first reset transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the reference signal line REF, and a second electrode of the second transistor T2 is connected to the first node N1.

In some exemplary embodiments, the third transistor T3 may be referred to as a second reset transistor, the gate electrode of the third transistor T3 is connected to the third scan signal line S3, the second electrode of the third transistor T3 is connected to the second node N2, and the first electrode of the third transistor T3 is connected to the initial signal line INIT.

In some exemplary embodiments, the fourth transistor T4 may be referred to as a light emission control transistor, the gate electrode of the fourth transistor T4 is connected to the light emission signal line EM, the first electrode of the fourth transistor T4 is connected to the first power supply line VDD, and the second electrode of the fourth transistor T4 is connected to the first electrode of the fifth transistor T5.

In some exemplary embodiments, the fifth transistor T5 may be referred to as a driving transistor, the gate electrode of the fifth transistor T5 is connected to the first node N1, the first pole of the fifth transistor T5 is connected to the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5 is connected to the second node N2.

In some exemplary embodiments, a first pole of the light emitting device EL is connected to the second node N2, and a second pole of the light emitting device EL is connected to the second power line VSS. The light emitting device EL may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

Fig. 5 is a schematic view illustrating a partial planar structure of a display substrate according to an embodiment of the disclosure. The display substrate may include a driving circuit layer disposed on the substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer may include at least a plurality of circuit units, the light emitting structure layer may include at least a plurality of light emitting units, at least one circuit unit may include a pixel driving circuit, at least one light emitting unit may include a light emitting device, the light emitting device may include at least an anode, an organic light emitting layer, and a cathode, and the anode of the light emitting unit is connected with the pixel driving circuit of the corresponding circuit unit. The position of the orthographic projection of the light emitting unit on the substrate and the position of the orthographic projection of the circuit unit on the substrate may be corresponding, or the position of the orthographic projection of the light emitting unit on the substrate and the position of the orthographic projection of the circuit unit on the substrate may not be corresponding.

In a plane perpendicular to the display substrate, the display substrate may include a base and first, second, semiconductor, third and fourth conductive layers sequentially located at one side of the base. The display substrate may include a compensation line 38, and the compensation line 38 may be located at the semiconductor layer. The compensation line 38 may be linear extending in the second direction Y. A first end of the compensation line 38 may be connected to the channel region 33-3 of the third active layer 33, a second end of the compensation line 38 may extend in the second direction Y, and a second end of the compensation line 38 may be connected to a second end of the first region 33-1 of the third active layer. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, may reduce an on-resistance of the third transistor, and may improve a problem of threshold voltage dispersion of the third transistor. In the disclosed embodiment, the first direction X intersects the second direction Y.

An exemplary description will be made below by a manufacturing process of the display substrate. The "patterning process" referred to in this disclosure includes, for metallic materials, inorganic materials, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, photoresist stripping, and the like, and for organic materials, processes such as organic material coating, mask exposure, and development, and the like. The deposition may be any one or more of sputtering, evaporation, chemical vapor deposition, coating may be any one or more of spraying, spin coating, and ink jet printing, and etching may be any one or more of dry etching and wet etching, without limitation of the disclosure. "film" refers to a layer of film formed by depositing, coating, or other process a material on a substrate. The "film" may also be referred to as a "layer" if the "film" does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" prior to the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The term "a and B are arranged in the same layer" in the present disclosure means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of a" or "the orthographic projection of a includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of a or the boundary of the orthographic projection of a overlaps with the boundary of the orthographic projection of B.

The preparation process of the display substrate may include the steps of:

(11) A first conductive layer pattern is formed. Forming the first conductive layer pattern may include: a first conductive film is deposited on the substrate, and the first conductive film is patterned through a patterning process to form a first conductive layer pattern on the substrate, as shown in fig. 6. In an exemplary embodiment, the first conductive layer may be referred to as a first GATE metal (GATE 1) layer. The first conductive layer pattern may include at least a first plate 11 of a first capacitor, a second plate 12 of a second capacitor, and a plate connection block 15.

In some exemplary embodiments, the first plate 11 of the first capacitor may have a rectangular shape, corners of the rectangular shape may be provided with chamfers or grooves, and the first plate 11 may serve as a lower plate of the first capacitor.

In some exemplary embodiments, the second plate 12 of the second capacitor may be disposed at one side of the first plate 11 in the second direction Y, the second plate 12 may have a T shape, corners of the T shape may be provided with chamfers or grooves, and the second plate 12 may serve as a lower plate of the second capacitor. The second electrode plate 12 may include a first sub-electrode plate 12-1 and a second sub-electrode plate 12-2 connected, the first sub-electrode plate 12-1 may have a rectangular shape extending in the first direction X, and the second sub-electrode plate 12-2 may have a rectangular shape extending in the second direction Y. The first end of the first sub-plate 12-1 may be connected to a middle portion of the second sub-plate 12-2, which may be, for example, a midpoint of the second sub-plate 12-2 in the second direction Y, and the second end of the first sub-plate 12-1 extends in the opposite direction of the first direction X. A first end of the second sub-plate 12-2 may be connected with the plate connection block 15, and a second end of the second sub-plate 12-2 extends in the second direction Y. The plate connection block 15 may have a rectangular shape extending in the second direction Y.

In some exemplary embodiments, the first plate 11 and the second plate 12 may be an integrally connected structure, i.e., the lower plate of the first capacitor and the lower plate of the second capacitor are integrally connected to each other.

In some exemplary embodiments, the first plate 11, the second plate 12, and the plate connection block 15 may be an integrally connected structure, and the plate connection block 15 may be located between the first plate 11 and the second plate 12.

(12) And forming a second conductive layer pattern. Forming the second conductive layer pattern may include: on the substrate with the patterns, a first insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned by a patterning process to form a first insulating layer covering the first conductive layer pattern and a second conductive layer pattern disposed on the first insulating layer, as shown in fig. 7A and 7B, and fig. 7B is a schematic plan view of the second conductive layer in fig. 7A. In an exemplary embodiment, the second conductive layer may be referred to as a second GATE metal (GATE 2) layer.

In some exemplary embodiments, the second conductive layer pattern in the display substrate may include at least: the third plate 13 of the first capacitor, the fourth plate 14 of the second capacitor, the fourth bottom gate electrode 24, the sixth bottom gate electrode 26 and the shielding line 27.

In some exemplary embodiments, the third plate 13 of the first capacitor may have a rectangular shape, and corners of the rectangular shape may be provided with chamfers or grooves. There may be at least a partial overlap of the front projection of the third plate 13 of the first capacitance on the substrate with the front projection of the first plate 11 of the first capacitance on the substrate. For example, the orthographic projection of the third polar plate 13 on the substrate may be located within the orthographic projection of the first polar plate 11 on the substrate. The third pole plate 13 may be used as an upper pole plate of the first capacitor, and the first pole plate 11 and the third pole plate 13 may together form the first capacitor.

In some exemplary embodiments, the fourth plate 14 of the second capacitor may be disposed at one side of the third plate 13 in the second direction Y. There may be at least a partial overlap of the front projection of the fourth plate 14 onto the substrate and the front projection of the second plate 12 onto the substrate. For example, the orthographic projection of the fourth plate 14 onto the substrate may be located within the orthographic projection of the second plate 12 onto the substrate. In an exemplary embodiment, the second plate 12 and the fourth plate 14 may together comprise a second capacitance.

In some example embodiments, the fourth plate 14 may include a first sub-block 14-1, a second sub-block 14-2, and a third sub-block 14-3 connected. The first sub-block 14-1 may have a rectangular shape extending in the first direction X, the second sub-block 14-2 may have a rectangular shape extending in the second direction Y, and the third sub-block 14-3 may have a rectangular shape extending in the second direction Y. The first end of the first sub-block 14-1 may be connected with a middle portion of the second sub-block 14-2, which may be a center of the second sub-block 14-2 in the second direction Y, and the second end of the first sub-block 14-1 may extend in the opposite direction of the first direction X, as an example. The first end of the third sub-block 14-3 may be connected with the first end of the second sub-block 14-2, and the second end of the third sub-block 14-3 may extend in the opposite direction of the second direction Y, and the second end of the second sub-block 14-2 may extend in the second direction Y.

In some exemplary embodiments, the fourth bottom gate electrode 24 may be rectangular in shape. The fourth bottom gate electrode 24 may be disposed at one side of the second sub-block 14-2 in the opposite direction to the first direction X. The fourth bottom gate electrode 24 may serve as a bottom gate electrode of the fourth transistor T4, may serve as a shielding layer of the fourth transistor T4, may serve to shield a channel region of the fourth transistor T4, and may ensure electrical performance of the fourth transistor T4.

In some exemplary embodiments, a fourth bottom gate connection block 24-1 may be disposed on the fourth bottom gate electrode 24. The fourth bottom gate connection block 24-1 may have a block shape (e.g., rectangular shape), may be disposed at a side of the fourth bottom gate electrode 24 adjacent to the sixth bottom gate electrode 26, and is connected to the fourth bottom gate electrode 24, and the fourth bottom gate connection block 24-1 may be configured to be connected to a third scan signal line formed later.

In some exemplary embodiments, the sixth bottom gate electrode 26 may have a rectangular shape, and may be disposed at one side of the first sub-block 14-1 opposite to the second direction Y and at one side of the fourth bottom gate electrode 24 opposite to the second direction Y. The sixth bottom gate electrode 26 may be used as a bottom gate electrode of the sixth transistor T6, and may be used as a shielding layer of the sixth transistor T6, may be used to shield a channel region of the sixth transistor T6, and may ensure electrical performance of the sixth transistor T6.

In some exemplary embodiments, the shielding line 27 may have a shape of a straight line or a folded line extending along the first direction X, and may be disposed at a side of the fourth electrode plate 14 remote from the third electrode plate 13.

In some exemplary embodiments, the shielding line 27 may be a non-uniform width straight line, the width of the position where the shielding line 27 overlaps with the subsequently formed fifth active layer may be greater than the width of other positions, the shielding line 27 at the wider position may be used as a shielding layer of the fifth transistor T5, may be used to shield a channel region of the fifth transistor T5, and may ensure electrical performance of the fifth transistor T5. In some possible exemplary embodiments, the shielding line 27 may serve as a bottom gate electrode of the fifth transistor T5.

(13) A semiconductor layer pattern is formed. Forming the semiconductor layer pattern may include: a second insulating film and a semiconductor film are sequentially deposited on the substrate on which the foregoing patterns are formed, and the semiconductor film is patterned by a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in fig. 8A and 8B, fig. 8B being a schematic plan view of the semiconductor layer in fig. 8A.

In some exemplary embodiments, the semiconductor layer pattern in the display substrate may include at least the third active layer 33 of the third transistor T3 to the sixth active layer 36 of the sixth transistor T6. The third active layer 33 and the fifth active layer 35 may be an integral structure connected to each other, and the fourth active layer 34 and the sixth active layer 36 may be an integral structure connected to each other. In the first direction X, the fourth and sixth active layers 34 and 36 may be located at one side of the third and fifth active layers 33 and 35 in the opposite direction of the first direction X. The fourth active layer 34 may be located at one side of the sixth active layer 36 in the second direction Y, and the fifth active layer 35 may be located at one side of the third active layer 33 in the second direction Y.

In some example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. The orthographic projection of the third active layer 33 on the substrate may at least partially overlap with the orthographic projection of the third electrode plate 13 on the substrate, and the overlapping region may serve as a channel region of the third transistor T3. The orthographic projection of the fourth active layer 34 on the substrate may at least partially overlap with the orthographic projection of the fourth bottom gate electrode 24 on the substrate, and the overlapping region serves as a channel region of the fourth transistor T4. The front projection of the fifth active layer 35 on the substrate may at least partially overlap with the front projection of the shielding line 27 on the substrate, the overlapping region serving as a channel region of the fifth transistor T5.

In some exemplary implementations, the orthographic projection of the sixth active layer 36 onto the substrate may at least partially overlap with the orthographic projection of the sixth bottom gate electrode 26 onto the substrate, the overlapping region being the channel region of the sixth transistor T6.

In some exemplary embodiments, the first region 33-1 of the third active layer and the second region 35-2 of the fifth active layer may be connected to each other, and the first region 33-1 of the third active layer may serve as the second region 35-2 of the fifth active layer. The second region 34-2 of the fourth active layer and the second region 36-2 of the sixth active layer may be connected to each other, and the second region 34-2 of the fourth active layer may serve as the second region 36-2 of the sixth active layer. The first region 34-1 of the fourth active layer 34 and the first region 35-1 of the fifth active layer 35 may be separately provided. The first region 36-1 of the sixth active layer and the second region 36-2 of the sixth active layer are located at both sides of the channel region of the sixth active layer along the second direction Y, respectively.

In some exemplary embodiments, the channel region 33-3 of the third active layer may have a rectangular shape, and corners of the rectangular shape may be provided with chamfers or grooves. The channel region 33-3 of the third active layer has a first width W1 in the first direction X. In the embodiment of the present disclosure, the first width W1 is an average width of the channel region 33-3 of the third active layer along the first direction X. The first region 33-1 of the third active layer is located at one side of the channel region 33-3 of the third active layer in the second direction Y, a first end of the first region 33-1 of the third active layer is connected to the channel region 33-3 of the third active layer, and a second end of the first region 33-1 of the third active layer extends in the second direction Y. The first region 33-1 of the third active layer has a second width W2 in the first direction X. In the embodiment of the present disclosure, the second width W2 is an average width of the first region 33-1 of the third active layer along the first direction X. The absolute value of the difference between the first width W1 and the second width W2 is less than or equal to 10% of the first width W1, the problem of threshold voltage divergence of the third transistor can be avoided by limiting the difference between the first width W1 and the second width W2, and the usability of the third transistor can be improved. In some examples, the first region of the third active layer and the second region of the third active layer may be interchanged.

In the following table 1, a comparison is made between a plurality of performance parameters of two pixel driving circuits, in the embodiment of the present disclosure, W1 and W2 represent that the first width W1 is equal to the second width W2, or the absolute value of the difference between the first width W1 and the second width W2 is greater than zero and less than or equal to 10% of the first width W1, that is, in table 1, W1 and W2 represent that they are approximately equal. In the embodiment of the present disclosure, W1 being not equal to W2 represents that the absolute value of the difference between the first width W1 and the second width W2 in the pixel driving circuit is greater than 10% of the first width W1.

TABLE 1

As shown in table 1 above, the pixel driving circuit with W1 equal to W2 performs better than the pixel driving circuit with W1 not equal to W2. The second width W2 is relatively smaller, and the corresponding line resistance is larger, so that when the third transistor is turned on, the current needs to pass through a channel with relatively larger line resistance, and the number of carriers is reduced due to the blocking effect of the channel, so that the first region and the second region of the third transistor are not easy to conduct, the threshold voltage is shifted forward, and the electron mobility (Mob) and the on-state current (Ion) are reduced. The second width W2 is relatively large, the corresponding line resistance is small, when the third transistor is turned on, the current needs to pass through a channel with relatively small line resistance, the blocking effect of the channel is relatively reduced, the number of carriers is less affected, the first region and the second region of the third transistor are easier to conduct, the threshold voltage is slightly negative, the electron mobility (Mob) and the on-state current (Ion) are improved, as can be seen from table 1, the electron mobility (Mob) is increased to 4.31 from the original 0.11, and the on-state current (Ion) average value is increased by two orders of magnitude.

In some exemplary embodiments, the first region 33-1 of the third active layer and the second region of the third active layer may be symmetrical with respect to the channel region 33-3 of the third active layer.

In some exemplary embodiments, the semiconductor layer pattern in the display substrate may include the compensation line 38, and the compensation line 38 may be a straight line extending in the second direction Y. The compensation line 38 is located at one side of the channel region 33-3 of the third active layer 33 in the second direction Y. A first end of the compensation line 38 may be connected to the channel region 33-3 of the third active layer 33, a second end of the compensation line 38 extends in the second direction Y, and a second end of the compensation line 38 is connected to a second end of the first region 33-1 of the third active layer. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, may reduce an on-resistance of the third transistor, and may improve a problem of threshold voltage dispersion of the third transistor.

In some exemplary embodiments, the front projection of the compensation line 38 on the substrate does not overlap with the front projection of the fourth electrode plate 14 on the substrate, and the front projection of the compensation line 38 on the substrate does not overlap with the front projection of the second electrode plate 12 on the substrate, so that adverse effects on the compensation line caused by the step difference formed by the edges of the fourth electrode plate and the second electrode plate can be avoided, breakage of the compensation line at the step formed by the edges of the fourth electrode plate and the second electrode plate can be avoided, and stability of the performance of the pixel driving circuit can be improved.

In some exemplary embodiments, the semiconductor layer pattern in the display substrate may further include a first connection bridge 38-1. The first connection bridge 38-1 may have a rectangular shape extending in the first direction X, a first end of the first connection bridge 38-1 may be connected with a second end of the compensation line 38, a second end of the first connection bridge 38-1 may extend in an opposite direction of the first direction X, and a second end of the first connection bridge 38-1 may be connected with a second end of the first region 33-1 of the third active layer.

In some exemplary embodiments, the semiconductor layer pattern in the display substrate may further include a second connection bridge 38-2. The second connection bridge 38-2 may be located between the first connection bridge 38-1 and the channel region 33-3 of the third active layer 33, and the second connection bridge 38-2 may be located between the first region 33-1 of the third active layer and the compensation line 38. The second connection bridge 38-2 may have a rectangular shape, a first end of the second connection bridge 38-2 may be connected with the compensation line 38, a second end of the second connection bridge 38-2 may extend in a direction opposite to the first direction X, and a second end of the second connection bridge 38-2 may be connected with the first region 33-1 of the third active layer.

In some possible exemplary embodiments, the semiconductor layer pattern in the display substrate may further include a plurality of second connection bridges 38-2. The plurality of second connection bridges 38-2 may be disposed at intervals along the second direction Y, and as an example, the plurality of second connection bridges 38-2 may be disposed at equal intervals along the second direction Y. In the embodiment of the disclosure, by providing a plurality of second connection bridges, the reliability of the connection between the compensation line and the first region of the third active layer may be improved.

In some possible exemplary embodiments, the semiconductor layer pattern in the display substrate may include at least the third active layer 33 of the third transistor T3, the fourth active layer 34 of the fourth transistor T4, and the fifth active layer 35 of the fifth transistor T5. The third active layer 33 and the fifth active layer 35 may be an integral structure connected to each other. In the first direction X, the fourth active layer 34 may be located at one side of the third active layer 33 and the fifth active layer 35 in the opposite direction of the first direction X. The fifth active layer 35 may be located at one side of the third active layer 33 in the second direction Y.

In some exemplary embodiments, the semiconductor layer may employ an oxide, i.e., the third transistor T3 to the sixth transistor T6 are oxide transistors, which have advantages of high electron mobility, low operating voltage, low leakage characteristics, and the like. The oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium gallium zinc oxide material (IGZO), and indium gallium aluminum nitride (InGaAlN).

(14) And forming a third conductive layer pattern. Forming the third conductive layer pattern may include: a third insulating film and a third conductive film are sequentially deposited on the substrate on which the foregoing patterns are formed, and the third conductive film is patterned by a patterning process to form a third insulating layer covering the semiconductor layer pattern, and a third conductive layer pattern disposed on the third insulating layer, as shown in fig. 9A and 9B, fig. 9B is a schematic view of the third conductive layer in fig. 9A. In an exemplary embodiment, the third conductive layer may be referred to as a third GATE metal (GATE 3) layer.

In some exemplary embodiments, the third conductive layer pattern in the display substrate may include at least: a third top gate electrode 43, a fourth top gate electrode 44, a sixth top gate electrode 46, and a light emitting signal line 48.

In some exemplary embodiments, the shape of the third top gate electrode 43 may be rectangular extending along the first direction X, an orthographic projection of the third top gate electrode 43 on the substrate may at least partially overlap with an orthographic projection of the third active layer 33 on the substrate, and the third top gate electrode 43 may serve as a top gate electrode of the third transistor T3.

In some exemplary embodiments, the shape of the fourth top gate electrode 44 may be rectangular, the orthographic projection of the fourth top gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer 34 on the substrate, and the fourth top gate electrode 44 may serve as a top gate electrode of the fourth transistor T4. The orthographic projection of the fourth top gate electrode 44 onto the substrate at least partially overlaps with the orthographic projection of the fourth bottom gate electrode 24 onto the substrate, the fourth top gate electrode 44 and the fourth bottom gate electrode 24 forming a fourth transistor T4 of top gate bottom gate structure.

In some exemplary embodiments, a fourth top gate connection block 44-1 may be disposed on the fourth top gate electrode 44. The fourth top gate connection block 44-1 may have a block shape, for example, a rectangular block shape, a hexagonal block shape, or the like, the fourth top gate connection block 44-1 may be disposed at a side of the fourth top gate electrode 44 remote from the fifth transistor T5, and the fourth top gate connection block 44-1 is connected to the fourth top gate electrode 44. The fourth top gate connection block 44-1 is configured to be connected to a third scanning signal line formed later.

In some exemplary embodiments, the shape of the sixth top gate electrode 46 may be rectangular, and the orthographic projection of the sixth top gate electrode 46 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer 36 on the substrate, and the sixth top gate electrode 46 may serve as the top gate electrode of the sixth transistor T6. The orthographic projection of the sixth top gate electrode 46 onto the substrate at least partially overlaps with the orthographic projection of the sixth bottom gate electrode 26 onto the substrate, the sixth top gate electrode 46 and the sixth bottom gate electrode 26 forming a sixth transistor T6 of top gate bottom gate structure.

In some exemplary embodiments, a sixth top gate connection block 46-1 may be disposed on the sixth top gate electrode 46. The sixth top gate connection block 46-1 may have a block shape, for example, a rectangular block shape, a hexagonal block shape, or the like, the sixth top gate connection block 46-1 may be disposed at a side of the sixth top gate electrode 46 near the third transistor T3, and the sixth top gate connection block 46-1 is connected to the sixth top gate electrode 46. The sixth top gate connection block 46-1 is configured to be connected to a fourth scanning signal line formed later.

In some exemplary embodiments, the light emitting signal line 48 may have a shape of a straight line or a folded line extending along the first direction X, may be disposed at one side of the fourth electrode 14 in the second direction Y, and the light emitting signal line 48 may at least partially overlap the fifth active layer 35, and the overlapping region may serve as a top gate electrode of the fifth transistor T5.

In some exemplary embodiments, the light emitting signal line 48 may be a straight line of non-uniform width, and the width of a position where the light emitting signal line 48 overlaps the fifth active layer 35 may be greater than that of other positions. The front projection of the light emitting signal line 48 on the substrate may at least partially overlap with the front projection of the shielding line 27 on the substrate, the light emitting signal line 48 and the shielding line 27 may be connected to the same signal source, the shielding line 27 may be made to serve as a bottom gate electrode of the fifth transistor T5, the light emitting signal line 48 may be made to serve as a top gate electrode of the fifth transistor T5, and the fifth transistor T5 of the top gate bottom gate structure is formed.

In some exemplary embodiments, after the third conductive layer pattern is formed, the semiconductor layer may be subjected to a conductive treatment using the third conductive layer as a mask, the semiconductor layer of the region masked by the third conductive layer forms channel regions of the third to sixth transistors T3 to T6, and the semiconductor layer of the region not masked by the third conductive layer is conductive.

(15) And forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: and depositing a fourth insulating film on the substrate with the patterns, and patterning the fourth insulating film by a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of through holes are formed on the fourth insulating layer, as shown in fig. 10.

In some example embodiments, the plurality of vias in the display substrate may include at least: the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth vias V1, V2, V3, V4, V5, V6, V7, V8, V9, and V10.

In some exemplary embodiments, the front projection of the first via V1 on the substrate may be within the range of the front projection of the first region 35-1 of the fifth active layer on the substrate, and both the third insulating layer and the fourth insulating layer within the first via V1 are etched away and expose the surface of the first region 35-1 of the fifth active layer. The first via V1 is configured such that a subsequently formed power connection line may be connected with the first region 35-1 of the fifth active layer through the via.

In some exemplary embodiments, the orthographic projection of the second via V2 on the substrate may be within the orthographic projection of the first region 34-1 of the fourth active layer on the substrate, and both the third insulating layer and the fourth insulating layer within the second via V2 are etched away and expose the surface of the first region 34-1 of the fourth active layer. The second via hole V2 is configured such that a subsequently formed first connection electrode may be connected with the first region 34-1 of the fourth active layer through the via hole.

In some exemplary embodiments, the orthographic projection of the third via V3 on the substrate may be within the orthographic projection of the fourth top gate connection block 44-1 on the substrate, the fourth insulating layer within the third via V3 being etched away and exposing the surface of the fourth top gate connection block 44-1. The third via hole V3 is configured such that a third scan signal line formed later may be connected with the fourth top gate connection block 44-1 through the via hole.

In some exemplary embodiments, the front projection of the fourth via V4 on the substrate may be within the range of the front projection of the fourth bottom gate connection block 24-1 on the substrate, and the second, third, and fourth insulating layers within the fourth via V4 are etched away and expose the surface of the fourth bottom gate connection block 24-1. The fourth via hole V4 is configured such that a third scanning signal line formed later may be connected with the fourth bottom gate connection block 24-1 through the via hole.

In some exemplary embodiments, the front projection of the fifth via V5 on the substrate may be within the range of the front projection of the second region 36-2 of the sixth active layer (also the second region 34-2 of the fourth active layer) on the substrate, and both the third insulating layer and the fourth insulating layer within the fifth via V5 are etched away and expose the surface of the second region 36-2 of the sixth active layer (also the second region 34-2 of the fourth active layer). The fifth via V5 is configured such that a subsequently formed second connection electrode may be connected with the second region 36-2 of the sixth active layer (also the second region 34-2 of the fourth active layer) through the via.

In some exemplary embodiments, the orthographic projection of the sixth via V6 on the substrate may be within the orthographic projection of the fourth electrode plate 14 on the substrate, and the second insulating layer, the third insulating layer, and the fourth insulating layer within the sixth via V6 are etched away and expose the surface of the fourth electrode plate 14. The sixth via hole V6 is configured such that a subsequently formed second connection electrode can be connected with the fourth electrode plate 14 through the via hole.

In some exemplary embodiments, the orthographic projection of the seventh via V7 on the substrate may be within the range of the orthographic projection of the sixth bottom gate electrode 26 on the substrate, and the second, third and fourth insulating layers within the seventh via V7 are etched away and expose the surface of the sixth bottom gate electrode 26. The seventh via hole V7 is configured such that a fourth scan signal line formed later may be connected to the sixth bottom gate electrode 26 through the via hole.

In some exemplary embodiments, the orthographic projection of the eighth via V8 on the substrate may be within the orthographic projection of the sixth top gate connection block 46-1 on the substrate, the fourth insulating layer within the eighth via V8 being etched away and exposing the surface of the sixth top gate connection block 46-1. The eighth via hole V8 is configured such that a fourth scan signal line formed later may be connected with the sixth top gate connection block 46-1 through the via hole.

In some exemplary embodiments, the orthographic projection of the ninth via V9 on the substrate may be within the range of the orthographic projection of the first region 36-1 of the sixth active layer on the substrate, and both the third insulating layer and the fourth insulating layer within the ninth via V9 are etched away and expose the surface of the first region 36-1 of the sixth active layer. The ninth via hole V9 is configured such that a third connection electrode formed later may be connected with the first region 36-1 of the sixth active layer through the via hole.

In some exemplary embodiments, the orthographic projection of the tenth via V10 on the substrate may be within the range of the orthographic projection of the third top gate electrode 43 on the substrate, the fourth insulating layer within the tenth via V10 being etched away and exposing the surface of the third top gate electrode 43. The tenth via hole V10 is configured such that a third connection electrode formed later may be connected with the third top gate electrode 43 through the via hole.

(16) And forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: on the substrate with the patterns, a fourth conductive film is deposited, and a patterning process is used to pattern the fourth conductive film to form a fourth conductive layer disposed on the fourth insulating layer, as shown in fig. 11A and 11B, and fig. 11B is a schematic plan view of the fourth conductive layer in fig. 11A. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source drain metal (SD 1) layer.

In some exemplary embodiments, the fourth conductive layer may include at least: a power connection line 50, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a third scan signal line 54, and a fourth scan signal line 55.

In some exemplary embodiments, the power connection line 50 may be located at one side of the light emitting signal line 48 in the second direction Y. The power connection line 50 may have a linear shape or a folded shape extending along the first direction X. The front projection of the power connection line 50 on the substrate may at least partially overlap with the front projection of the first region of the fifth active layer on the substrate, the front projection of the power connection line 50 on the substrate may include the front projection of the first via V1 on the substrate, and the power connection line 50 may be connected to the first region of the fifth active layer through the first via V1.

In some exemplary embodiments, the first connection electrode 51 may be located between the power connection line 50 and the fourth top gate connection block 44-1. The first connection electrode 51 may have a rectangular shape. The front projection of the first connection electrode 51 on the substrate may overlap with the front projection of the light emitting signal line 48 on the substrate. The front projection of the first connection electrode 51 on the substrate may partially overlap with the front projection of the first region of the fourth active layer on the substrate, the front projection of the first connection electrode 51 on the substrate may include the front projection of the second via V2 on the substrate, and the first connection electrode 51 may be connected with the first region of the fourth active layer through the second via V2.

In some exemplary embodiments, the third scan signal line 54 may be located at one side of the first connection electrode 51 opposite to the second direction Y. The orthographic projection of the third scanning signal line 54 on the substrate at least partially overlaps with the orthographic projections of the fourth top gate connection block 44-1 and the fourth bottom gate connection block 24-1 on the substrate, and the third scanning signal line 54 is connected to the fourth top gate connection block 44-1 through the third via hole V3 on the one hand and the fourth bottom gate connection block 24-1 through the fourth via hole V4 on the other hand. Since the fourth top gate connection block 44-1 is connected to the fourth top gate electrode 44 and the fourth bottom gate connection block 24-1 is connected to the fourth bottom gate electrode 24, connection of the third scan signal line 54 to the bottom gate electrode of the fourth transistor T4 and the top gate electrode of the fourth transistor T4 is achieved at the same time, and the third scan signal line 54 can control on or off of the fourth transistor T4.

In some exemplary embodiments, the third scan signal line 54 may include a first connection block 54-1, a second connection block 54-2, and a body portion 54-3 connected. The body portion 54-3 may be linear extending along the first direction X, a first end of the first connection block 54-1 may be connected to the body portion 54-3, a second end of the first connection block 54-1 may extend along the second direction Y, an orthographic projection of the first connection block 54-1 on the substrate may include an orthographic projection of the third via V3 on the substrate, and the first connection block 54-1 may be connected to the fourth top gate connection block 44-1 through the third via V3. A first end of the second connection block 54-2 may be connected to the body portion 54-3, a second end of the second connection block 54-2 may extend in a direction opposite to the second direction Y, an orthographic projection of the second connection block 54-2 on the substrate may include an orthographic projection of the fourth via V4 on the substrate, and the second connection block 54-2 may be connected to the fourth bottom gate connection block 24-1 through the fourth via V4.

In some exemplary embodiments, the second connection electrode 52 may have a rectangular shape, and the second connection electrode 52 may be located at one side of the third scan signal line 54 opposite to the second direction Y. The orthographic projection of the second connection electrode 52 on the substrate may include an orthographic projection of the fifth via V5 on the substrate, the orthographic projection of the second connection electrode 52 on the substrate may include an orthographic projection of the sixth via V6 on the substrate, the second connection electrode 52 may be connected with the second region of the sixth active layer through the fifth via V5, and the second connection electrode 52 may be connected with the fourth electrode plate through the sixth via V6.

In some exemplary embodiments, the fourth scan signal line 55 may have a shape of a straight line or a folded line extending along the first direction X. The fourth scan signal line 55 may be located at one side of the second connection electrode 52 in the opposite direction of the second direction Y. The front projection of the fourth scanning signal line 55 on the substrate at least partially overlaps with the front projections of the sixth top gate connection block 46-1 and the sixth bottom gate electrode 26 on the substrate, and the fourth scanning signal line 55 is connected to the sixth bottom gate electrode 26 through the seventh via hole V7 on the one hand and the sixth top gate connection block 46-1 through the eighth via hole V8 on the other hand. Since the sixth top gate connection block 46-1 is connected to the sixth top gate electrode 46, connection of the fourth scan signal line 55 to the bottom gate electrode of the sixth transistor T6 and the top gate electrode of the sixth transistor T6 is achieved at the same time, and the fourth scan signal line 55 can control on or off of the sixth transistor T6.

In some exemplary embodiments, the third connection electrode 53 may have a rectangular shape, and the third connection electrode 53 may be located at one side of the fourth scan signal line 55 in the opposite direction to the second direction Y. The orthographic projection of the third connection electrode 53 on the substrate may include an orthographic projection of the ninth via V9 on the substrate, the orthographic projection of the third connection electrode 53 on the substrate may include an orthographic projection of the tenth via V10 on the substrate, the third connection electrode 53 may be connected to the first region of the sixth active layer through the ninth via V9, and the third connection electrode 53 may be connected to the third top gate electrode through the tenth via V10.

Fig. 12 is a schematic view of a partial planar structure of a display substrate according to another embodiment of the disclosure. In a plane perpendicular to the display substrate, the display substrate may include a base and first, second, semiconductor, third, fourth, and fifth conductive layers sequentially located at one side of the base. The compensation line 38 may be located in the fifth conductive layer and the orthographic projection of the compensation line 38 on the substrate may include the orthographic projection of the first region 33-1 of the third active layer on the substrate. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, may reduce an on-resistance of the third transistor, and may improve a problem of threshold voltage dispersion of the third transistor.

The preparation process of the display substrate may include the steps of:

(21) The first conductive layer pattern and the second conductive layer pattern are sequentially formed on the substrate, and reference may be made to the foregoing embodiments, and detailed descriptions thereof will not be repeated here.

(22) A semiconductor layer pattern is formed. Forming the semiconductor layer pattern may include: a second insulating film and a semiconductor film are sequentially deposited on the substrate on which the foregoing patterns are formed, and the semiconductor film is patterned by a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in fig. 13A and 13B, fig. 13B being a schematic plan view of the semiconductor layer in fig. 13A.

In some example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. The orthographic projection of the third active layer 33 on the substrate may at least partially overlap with the orthographic projection of the third electrode plate 13 on the substrate, and the overlapping region may serve as a channel region of the third transistor T3. The orthographic projection of the fourth active layer 34 on the substrate may at least partially overlap with the orthographic projection of the fourth bottom gate electrode 24 on the substrate, and the overlapping region serves as a channel region of the fourth transistor T4. The front projection of the fifth active layer 35 on the substrate may at least partially overlap with the front projection of the shielding line 27 on the substrate, the overlapping region serving as a channel region of the fifth transistor T5. The orthographic projection of the sixth active layer 36 on the substrate may at least partially overlap with the orthographic projection of the sixth bottom gate electrode 26 on the substrate, the overlapping region serving as a channel region of the sixth transistor T6.

In some exemplary embodiments, the channel region 33-3 of the third active layer may have a rectangular shape, and corners of the rectangular shape may be provided with chamfers or grooves. The channel region 33-3 of the third active layer has a first width W1 in the first direction X. The first region 33-1 of the third active layer is located at one side of the channel region 33-3 of the third active layer in the second direction Y, a first end of the first region 33-1 of the third active layer is connected to the channel region 33-3 of the third active layer, and a second end of the first region 33-1 of the third active layer extends in the second direction Y. The first region 33-1 of the third active layer has a second width W2 in the first direction X. The second width W2 is smaller than the first width W1.

(23) The third conductive layer pattern may be formed by referring to the previous embodiments, and will not be described in detail herein.

(24) And forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: on the substrate on which the foregoing pattern is formed, a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer covering the third conductive layer, and a plurality of vias are disposed on the fourth insulating layer, as shown in fig. 14.

In some example embodiments, the plurality of vias in the display substrate may include at least: the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth vias V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, and V12. The first through tenth vias V1 through V10 may refer to the foregoing embodiments, and will not be described herein in detail.

In some exemplary embodiments, the front projection of the eleventh via V11 on the substrate may be within the range of the front projection of the first region 33-1 of the third active layer on the substrate, and both the third insulating layer and the fourth insulating layer within the eleventh via V11 are etched away and expose the surface of the first region 33-1 of the third active layer. The eleventh via hole V11 is configured such that a subsequently formed first bridge electrode may be connected with the first end of the first region 33-1 of the third active layer through the via hole.

In some exemplary embodiments, the orthographic projection of the twelfth via V12 on the substrate may be within the range of the orthographic projection of the first region 33-1 of the third active layer on the substrate, and both the third insulating layer and the fourth insulating layer within the twelfth via V12 are etched away and expose the surface of the first region 33-1 of the third active layer. The twelfth via V12 is configured such that a second bridge electrode formed later can be connected to the second end of the first region 33-1 of the third active layer through the via.

(25) And forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: on the substrate with the patterns, a fourth conductive film is deposited, and a patterning process is used to pattern the fourth conductive film to form a fourth conductive layer disposed on the fourth insulating layer, as shown in fig. 15A and 15B, and fig. 15B is a schematic plan view of the fourth conductive layer in fig. 15A. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source drain metal (SD 1) layer.

In some exemplary embodiments, the fourth conductive layer may include at least: the power connection line 50, the first connection electrode 51, the second connection electrode 52, the third connection electrode 53, the third scan signal line 54, the fourth scan signal line 55, the first bridge electrode 56, and the second bridge electrode 57. The power connection line 50, the first connection electrode 51, the second connection electrode 52, the third connection electrode 53, the third scan signal line 54 and the fourth scan signal line 55 may refer to the foregoing embodiments, and will not be described in detail herein.

In some exemplary embodiments, the first bridge electrode 56 may have a rectangular shape, and the first bridge electrode 56 may be positioned between the third connection electrode 53 and the fourth scan signal line 55. The orthographic projection of the first bridge electrode 56 on the substrate may include an orthographic projection of the eleventh via V11 on the substrate, and the first bridge electrode 56 may be connected to the first end of the first region of the third active layer through the eleventh via V11.

In some exemplary embodiments, the second bridge electrode 57 may have a rectangular shape, and the second bridge electrode 57 may be positioned between the power connection line 50 and the third scan signal line 54. The orthographic projection of the second bridge electrode 57 on the substrate may include an orthographic projection of the twelfth via V12 on the substrate, and the second bridge electrode 57 may be connected to the second end of the first region of the third active layer through the twelfth via V12.

(26) A fifth insulating layer pattern is formed. Forming the fifth insulating layer pattern may include: and depositing a fifth insulating film on the substrate with the patterns, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer covering the fourth conductive layer, wherein a plurality of through holes are formed on the fifth insulating layer, as shown in fig. 16.

In some example embodiments, the plurality of vias in the display substrate may include at least: twenty-first via V21, twenty-second via V22, twenty-third via V23, and twenty-fourth via V24.

In some exemplary embodiments, the front projection of the twenty-first via V21 on the substrate may be within the range of the front projection of the first bridge electrode 56 on the substrate, the fifth insulating layer within the twenty-first via V21 is etched away, and the surface of the first bridge electrode 56 is exposed. The twenty-first via V21 is configured such that a compensation line to be formed later can be connected with the first bridge electrode 56 through the via.

In some exemplary embodiments, the front projection of the twenty-second via V22 on the substrate may be within the range of the front projection of the second bridge electrode 57 on the substrate, the fifth insulating layer within the twenty-second via V22 being etched away and exposing the surface of the second bridge electrode 57. The twenty-second via V22 is configured such that a compensation line to be formed later can be connected with the second bridge electrode 57 through the via.

In some exemplary embodiments, the front projection of the twenty-third via V23 on the substrate may be within the range of the front projection of the power connection line 50 on the substrate, the fifth insulating layer within the twenty-third via V23 being etched away and exposing the surface of the power connection line 50. The twenty-third via hole V23 is configured such that a subsequently formed first power line may be connected with the power connection line 50 through the via hole.

In some exemplary embodiments, the front projection of the twenty-fourth via V24 on the substrate may be within the range of the front projection of the first connection electrode 51 on the substrate, and the fifth insulating layer within the twenty-fourth via V24 is etched away and exposes the surface of the first connection electrode 51. The twenty-fourth via hole V24 is configured such that a data signal line formed later may be connected to the first connection electrode 51 through the via hole.

(27) And forming a fifth conductive layer pattern. Forming the fifth conductive layer pattern may include: on the substrate with the patterns, a fifth conductive film is deposited, and a patterning process is used to pattern the fifth conductive film to form a fifth conductive layer disposed on the fifth insulating layer, as shown in fig. 17A and 17B, and fig. 17B is a schematic plan view of the fifth conductive layer in fig. 17A. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source drain metal (SD 2) layer.

In some exemplary embodiments, the fourth conductive layer may include at least: a data signal line 61, a first power line 62 and a compensation line 38. The first power line 62 may be located between the data signal line 61 and the compensation line 38. The data signal line 61, the first power line 62, and the compensation line 38 may have a linear shape extending in the second direction Y.

In some exemplary embodiments, the front projection of the data signal line 61 on the substrate overlaps with the front projection of the first connection electrode 51 on the substrate, and the front projection of the data signal line 61 on the substrate may include the front projection of the twenty-fourth via V24 on the substrate, and the data signal line 61 may be connected to the first connection electrode 51 through the twenty-fourth via V24, and the connection of the first connection electrode 51 to the first region of the fourth active layer is achieved.

In some exemplary embodiments, the front projection of the first power line 62 on the substrate overlaps with the front projection of the power connection line 50 on the substrate, and the front projection of the first power line 62 on the substrate may include the front projection of the twenty-third via V23 on the substrate, and the first power line 62 may be connected with the power connection line 50 through the twenty-third via V23, so that a mesh structure for transmitting the first power signal may be formed, which may not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and the display quality.

In some exemplary embodiments, the orthographic projection of the compensation line 38 on the substrate may include orthographic projections of the twenty-first via V21 and the twenty-second via V22 on the substrate, the compensation line 38 may be connected to the first bridge electrode 56 through the twenty-first via V21, and the compensation line 38 may be connected to the second bridge electrode 57 through the twenty-second via V22. The front projection of the compensation line 38 on the substrate overlaps with the front projection of the first region 33-1 of the third active layer on the substrate, and the front projection of the compensation line 38 on the substrate includes, illustratively, the front projection of the first region 33-1 of the third active layer on the substrate. The compensation line 38 and the first region 33-1 of the third active layer may form a parallel path, may reduce an on-resistance of the third transistor, and may improve a problem of threshold voltage dispersion of the third transistor.

The preparation process of the embodiment of the disclosure can be well compatible with the existing preparation process, and has the advantages of simple process implementation, easy implementation, high production efficiency, low production cost and high yield.

In some exemplary embodiments, the first, second, third, fourth, and fifth conductive layers may be a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, or the like. The materials of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The material of the fifth insulating layer may be one or more of epoxy resin, phenolic resin, urea resin, melamine formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin. The active layer may be made of amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene or polythiophene, etc., i.e., the present disclosure is applicable to transistors manufactured based on Oxide (Oxide) technology, silicon technology or organic technology. The foregoing structure and the preparation process thereof according to the embodiments of the present disclosure are merely exemplary, and in the exemplary embodiment, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs, which is not limited herein.

The embodiment of the disclosure also provides a display device, which includes the display substrate according to any one of the foregoing embodiments. The display device may be: the embodiments of the present disclosure are not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. It should be noted that the above-described examples or implementations are merely exemplary and not limiting. Accordingly, the present disclosure is not limited to what has been particularly shown and described herein. Various modifications, substitutions, or omissions may be made in the form and details of the implementations without departing from the scope of the disclosure.

Claims

1. A display substrate comprising a base and at least one pixel drive circuit on one side of the base, the at least one pixel drive circuit comprising at least one transistor, the at least one transistor comprising an active layer comprising a channel region and first and second regions on opposite sides of the channel region; the first region has a first end and a second end which are oppositely arranged, the first end of the first region is connected with the channel region, and the second end extends along a second direction;

2. The display substrate of claim 1, wherein an absolute value of a difference between the first width and the second width is greater than 10% of the first width.

3. The display substrate according to claim 1, further comprising at least one capacitor, wherein the at least one capacitor is closer to the base than the compensation line, and the capacitor is located at one side of the extension direction of the compensation line, the capacitor comprises two polar plates arranged oppositely, and the orthographic projection of the compensation line on the base and the orthographic projection of the two polar plates on the base are not overlapped.

4. A display substrate according to claim 3, wherein the compensation line is arranged in the same layer as the active layer.

5. The display substrate of claim 4, further comprising a first connection bridge having a first end and a second end disposed opposite along the first direction, the first end of the first connection bridge being connected to the second end of the compensation line, the second end of the first connection bridge being connected to the second end of the first region of the active layer.

6. The display substrate of claim 5, further comprising at least one second connection bridge between the first connection bridge and the channel region, and between the first region and the compensation line; the second connecting bridge extends along the first direction and comprises a first end and a second end which are oppositely arranged; the first end of the second connecting bridge is connected with the compensation line, and the second end of the second connecting bridge is connected with the first region.

7. The display substrate of claim 6, wherein the first connection bridge, the at least one second connection bridge, and the compensation line are an integral structure connected to each other.

8. The display substrate of claim 1, wherein the compensation line is located on a side of the active layer away from the base.

9. The display substrate of claim 8, further comprising a semiconductor layer, a first source drain metal layer, and a second source drain metal layer in this order on one side of the base in a plane perpendicular to the display substrate;

10. The display substrate of claim 9, wherein the display substrate further comprises a first bridge electrode and a second bridge electrode; the front projection of the first bridging electrode at the substrate at least partially overlaps the front projection of the first end of the first region at the substrate, and the front projection of the second bridging electrode at the substrate at least partially overlaps the front projection of the second end of the first region at the substrate; the orthographic projection of the compensation line on the substrate is overlapped with the orthographic projection of the first bridging electrode and the second bridging electrode on the substrate;

11. The display substrate of claim 10, wherein the first bridge electrode and the second bridge electrode are both located in the first source drain metal layer, and the compensation line is located in the second source drain metal layer.

12. The display substrate of claim 9, wherein there is at least a partial overlap of the orthographic projection of the compensation line at the base with the orthographic projection of the first region at the base.

13. The display substrate of claim 12, wherein an orthographic projection of the compensation line at the base is located within an orthographic projection of the first region at the base.

14. The display substrate according to any one of claims 1 to 13, wherein the at least one transistor is a driving transistor; the at least one pixel driving circuit further includes a light emission control transistor connected to the second end of the first region.

15. A display device comprising a display substrate according to any one of claims 1 to 14.