CN114242755A

CN114242755A - Display substrate and display device

Info

Publication number: CN114242755A
Application number: CN202111405398.3A
Authority: CN
Inventors: 袁粲; 李永谦; 张大成; 袁志东; 吴刘
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-11-24
Filing date: 2021-11-24
Publication date: 2022-03-25

Abstract

The embodiment of the disclosure provides a display substrate and a display device. The display substrate includes: the LED display panel comprises a substrate, a driving circuit layer arranged on the substrate, a color film layer arranged on one side, far away from the substrate, of the driving circuit layer and a light emitting structure layer arranged on one side, far away from the substrate, of the color film layer; wherein the driving circuit layer includes: the color filter comprises a light shielding layer positioned in the sub-pixels and a metal oxide layer arranged on one side, far away from the substrate, of the light shielding layer, wherein the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the metal oxide layer on the substrate is larger than the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the light shielding layer on the substrate.

Description

Display substrate and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and particularly relates to a display substrate and a display device.

Background

An Organic Light-Emitting Diode (OLED) display device is an active Light-Emitting display device, and has the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and very high response speed. With the continuous development of display technology, OLED technology is increasingly applied to transparent displays. Transparent display is an important personalized display field of display technology, and is an image display in a transparent state, so that a viewer can see not only images in a display device but also scenes behind the display device. However, some transparent display products suffer from sub-pixel light leakage.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including: the LED display panel comprises a substrate, a driving circuit layer arranged on the substrate, a color film layer arranged on one side, far away from the substrate, of the driving circuit layer and a light emitting structure layer arranged on one side, far away from the substrate, of the color film layer; wherein the driving circuit layer includes: the color filter comprises a light shielding layer positioned in the sub-pixels and a metal oxide layer arranged on one side, far away from the substrate, of the light shielding layer, wherein the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the metal oxide layer on the substrate is larger than the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the light shielding layer on the substrate.

In a second aspect, an embodiment of the present disclosure provides a display device, including: the display substrate in the above embodiments.

According to the display substrate and the display device provided by the embodiment of the disclosure, by adopting the design that the orthographic projection of the color film layer on the substrate and the orthographic projection of the shading layer on the substrate are overlapped, white light generated by the organic light emitting layer of the sub-pixel leaks out from the edge of the color film layer through the diffuse reflection or refraction of the cathode and other film layers and is emitted to the shading layer, so that the white light is shaded by the shading layer. Therefore, the problem of light leakage of the sub-pixels can be avoided, the problem of color unevenness caused by the light leakage can be avoided, and the display quality can be improved.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not limit the disclosure. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but are merely intended to illustrate the present disclosure.

FIG. 1 is a schematic view of a display substrate;

FIG. 2 is a schematic diagram of a display device;

FIG. 3 is a diagram of a pixel structure in a display substrate;

FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

fig. 5 is a schematic plan view of a display substrate in an exemplary embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional view taken along the direction A-A' of the display substrate shown in FIG. 5;

FIG. 7 is a schematic diagram of an equivalent circuit of the pixel driving circuit in the four sub-pixels shown in FIG. 5;

fig. 8 is a schematic structural diagram of a first conductive layer in an exemplary embodiment of the present disclosure;

fig. 9A is a schematic structural view after a second conductive layer is formed in an exemplary embodiment of the present disclosure;

FIG. 9B is a schematic diagram of the second conductive layer shown in FIG. 9A;

FIG. 10A is a schematic diagram of a structure after a metal oxide layer is formed in an exemplary embodiment of the disclosure;

FIG. 10B is a schematic diagram of the structure of the metal oxide layer in FIG. 10A;

fig. 11A is a schematic structural view after a third conductive layer is formed in an exemplary embodiment of the present disclosure;

FIG. 11B is a structural diagram of the third conductive layer in FIG. 11A;

fig. 12 is a schematic structural view after a third insulating layer is formed in an exemplary embodiment of the present disclosure;

fig. 13A is a schematic structural view after a fourth conductive layer is formed in an exemplary embodiment of the present disclosure;

FIG. 13B is a schematic diagram of the fourth conductive layer in FIG. 13A;

fig. 14 is a schematic structural view after a fourth insulating layer is formed in an exemplary embodiment of the present disclosure;

fig. 15A is a schematic structural diagram after a red color film unit is formed in an exemplary embodiment of the disclosure;

fig. 15B is a schematic structural diagram of the red color film unit in fig. 15A;

fig. 15C is a schematic structural diagram after a green color film unit is formed in an exemplary embodiment of the disclosure;

FIG. 15D is a schematic view of the structure of the green color film cell of FIG. 15C;

fig. 15E is a schematic structural diagram after a blue color film unit is formed in an exemplary embodiment of the disclosure;

fig. 15F is a schematic structural diagram of the blue color film unit in fig. 15E;

fig. 16 is a schematic structural view after a fifth insulating layer is formed in an exemplary embodiment of the present disclosure;

fig. 17A is a schematic structural view after a fifth conductive layer is formed in an exemplary embodiment of the present disclosure;

FIG. 17B is a schematic structural diagram of the fifth conductive layer shown in FIG. 17A;

fig. 18A is a schematic structural view after a pixel defining layer is formed in an exemplary embodiment of the present disclosure;

FIG. 18B is a schematic structural diagram of the pixel definition layer shown in FIG. 18A;

fig. 19 is a schematic view illustrating an overlapping area between a color film layer and a light-shielding layer in a display substrate in an exemplary embodiment of the present disclosure.

Detailed Description

Various embodiments are described herein, but the description is intended to be exemplary, rather than limiting and many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the exemplary embodiments, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

In describing representative embodiments, the specification may have presented a method or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps herein, the method or process should not be limited to the particular sequence of steps. Other orders of steps are possible, as will be appreciated by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present disclosure.

In the drawings, the size of the constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and shapes and sizes of components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In the exemplary embodiments of the present disclosure, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used for convenience in describing positional relationships of constituent elements with reference to the accompanying drawings, only for the purpose of facilitating description and simplifying description, and are not intended to indicate or imply that the referred device or element has a specific orientation, is configured and operated in a specific orientation, and thus, is not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In the exemplary embodiments of the present disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the exemplary embodiments of the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected constituent elements. The "element having some kind of electric function" may be, for example, an electrode, a wiring, a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor.

In exemplary embodiments of the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode (gate or control electrode), a drain electrode (drain electrode terminal, drain region, or drain), and a source electrode (source electrode terminal, source region, or source). The transistor has a channel region between a drain electrode and a source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In the exemplary embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate electrode (gate or control electrode), one of them is directly described as a first pole, and the other is a second pole, where the first pole may be a drain electrode and the second pole may be a source electrode, or the first pole may be a source electrode and the second pole may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

The transistors in the exemplary embodiments of the present disclosure may each be a Thin Film Transistor (TFT) or a Field Effect Transistor (FET) or other devices having the same characteristics. For example, the thin film transistor used in the embodiments of the present disclosure may include, but is not limited to, an Oxide transistor (Oxide TFT), a Low Temperature polysilicon thin film transistor (LTPS TFT), or the like. For example, the thin film transistor may be a thin film transistor of a bottom gate structure or a thin film transistor of a top gate structure as long as a switching function can be achieved. Here, the embodiment of the present disclosure is not limited to this.

In exemplary embodiments of the present disclosure, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In the exemplary embodiments of the present disclosure, the triangle, the rectangle, the trapezoid, the pentagon, the hexagon, etc. are not strict, and may be an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, an approximate hexagon, etc., there may be some small deformation caused by tolerance, there may be a chamfer, an arc side, and deformation, etc.

In exemplary embodiments of the present disclosure, "about" refers to a numerical value that is not narrowly limited, allowing for process and measurement error.

In exemplary embodiments of the present disclosure, the "integral structure" may refer to a structure in which two (or more) structures are formed through the same deposition process and patterned through the same patterning process to be connected to each other, and their materials may be the same or different.

In the present exemplary embodiment, the first direction DR1 may refer to an extending direction or a column direction of data signal lines or the like in the display area, the second direction DR2 may refer to an extending direction or a row direction of scan signal lines or the like in the display area, and the third direction DR3 may refer to a thickness direction of the display panel or a direction perpendicular to the plane of the display panel or the like. Wherein the first direction DR1 intersects the second direction DR2, and the first direction DR1 intersects the third direction DR 3. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other, and the first direction DR1 and the third direction DR3 may be perpendicular to each other. Here, the embodiment of the present disclosure is not limited to this.

In some white light evaporation bottom emission OLED display products, in order to obtain a larger aperture ratio, a transparent Pixel architecture is generally adopted, and a design distance between a Pixel Definition Layer (PDL) and a shielding Layer in a driving circuit Layer is often closer. The inventor of the present disclosure finds that: as shown in fig. 1, when displaying monochromatic RGB (red, green, blue), in the area circled by the dotted line in fig. 1, the white light generated by the organic light emitting layer of the sub-pixel will diffuse or refract through the cathode and other film layers and leak from the edge of the color film unit, so that the light leakage problem occurs in the RGB sub-pixel, thereby causing the RGB color non-uniformity problem, and further affecting the display image quality.

Fig. 2 is a schematic structural diagram of a display device. As shown in fig. 2, the display device may include: the liquid crystal display device includes a timing controller connected to a data signal driver and a scan signal driver, respectively, the data signal driver connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to a plurality of scan signal lines (S1 to Sm), respectively, and a pixel array. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line and a pixel driving circuit.

In one exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may supply a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver may sample a gray value with a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number.

Fig. 3 is a schematic plan view of a display substrate. As shown in fig. 3, the display substrate may include: a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P may include: the pixel driving circuit comprises a first sub-pixel P1 for emitting light of a first color, a second sub-pixel P2 for emitting light of a second color, a third sub-pixel P3 for emitting light of a third color and a fourth sub-pixel P4 for emitting light of a fourth color, wherein the four sub-pixels can respectively comprise a circuit unit and a light-emitting device, the circuit unit can comprise a scanning signal line, a data signal line and a pixel driving circuit, the pixel driving circuit is respectively connected with the scanning signal line and the data signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line and output corresponding current to the light-emitting device under the control of the scanning signal line. The light emitting device in each sub-pixel is respectively connected with the pixel driving circuit of the sub-pixel, and the light emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a Red (Red, R) subpixel emitting Red light, the second subpixel P2 may be a White (W) subpixel emitting White light, the third subpixel P3 may be a Green (G) subpixel emitting Green light, and the fourth subpixel P4 may be a Blue (Blue, B) subpixel emitting Blue light. Here, the embodiment of the present disclosure is not limited to this.

In an exemplary embodiment, the shape of the sub-pixels may be triangular, square, rectangular, diamond, trapezoidal, parallelogram, pentagon, hexagon or other polygon, etc. Here, the present disclosure does not limit this.

In one exemplary embodiment, the four sub-pixels may be arranged in a horizontal side-by-side manner to form a RWGB pixel arrangement. Alternatively, the four sub-pixels may be arranged in a Square (Square), Diamond (Diamond), or vertical parallel manner. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the pixel driving circuit may be a 3T1C (i.e., including three transistors and one capacitor unit), 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, taking the pixel driving circuit adopting the 3T1C structure as an example, fig. 4 is an equivalent circuit diagram of the pixel driving circuit. As shown in fig. 4, the pixel driving circuit may include: 3 transistors (a first transistor T1, a second transistor T2, and a third transistor T3), 1 storage capacitor C, and 6 signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a compensation signal line Se, a first power supply line VDD, and a second power supply line VSS). The first transistor T1 may be a switching transistor, the second transistor T2 may be a driving transistor, and the third transistor T3 may be a compensating transistor. The first plate of the storage capacitor C is coupled to the second pole of the second transistor T2, the second plate of the storage capacitor C is coupled to the gate electrode of the second transistor T2, and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2. The gate electrode of the first transistor T1 is coupled to the first scan signal line S1, the first pole of the first transistor T1 is coupled to the data signal line D, the second pole of the first transistor T1 is coupled to the gate electrode of the second transistor T2, and the first transistor T1 is configured to receive the data signal transmitted by the data signal line D under the control of the first scan signal line S1, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is coupled to the second pole of the first transistor T1, the first pole of the second transistor T2 is coupled to the first power line VDD, the second pole of the second transistor T2 is coupled to the first pole of the light emitting device, and the second transistor T2 is configured to generate a corresponding current at the second pole under the control of the data signal received by the gate electrode thereof. A gate electrode of the third transistor T3 is coupled to the second scan signal line S2, a first pole of the third transistor T3 is coupled to the compensation signal line Se, a second pole of the third transistor T3 is coupled to the second pole of the second transistor T2, and the third transistor T3 is configured to extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

In an exemplary embodiment, the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, the first electrode of the OLED being coupled to the second electrode of the second transistor T2, the second electrode of the OLED being coupled to the second power line VSS, the OLED being configured to emit light with a corresponding brightness in response to a current of the second electrode of the second transistor T2.

In an exemplary embodiment, the signal of the first power line VDD is a signal continuously supplying a high level, and the signal of the second power line VSS is a signal of a low level. The first to third transistors T1 to T3 may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved.

An exemplary embodiment of the present disclosure provides a display substrate, which may include: the LED display panel comprises a substrate, a driving circuit layer arranged on the substrate, a color film layer arranged on one side, far away from the substrate, of the driving circuit layer and a light emitting structure layer arranged on one side, far away from the substrate, of the color film layer; wherein the driving circuit layer includes: the color filter comprises a light shielding layer positioned in the sub-pixels and a metal oxide layer arranged on one side, far away from the substrate, of the light shielding layer, wherein the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the metal oxide layer on the substrate is larger than the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the light shielding layer on the substrate. Therefore, by adopting the design that the orthographic projection of the color film layer on the substrate and the orthographic projection of the light shielding layer on the substrate are overlapped, white light generated by the organic light emitting layer of the sub-pixel is leaked from the edge of the color film layer through the diffuse reflection or refraction of the cathode and other film layers, can shoot to the light shielding layer and is shielded by the light shielding layer, the problem of light leakage of the sub-pixel can be avoided, further, the problem of uneven color caused by the light leakage can be avoided, and the display quality can be improved. And, adopt transparent metal oxide layer as a polar plate of storage capacitor, so, because light can see through transparent metal oxide layer outgoing, can set up storage capacitor in the luminous area, can effectively increase pixel aperture opening rate.

The following describes a structure of a display substrate and a manufacturing process thereof provided in an exemplary embodiment of the present disclosure with reference to the drawings, taking four sub-pixels of the display substrate and taking a 3T1C structure as an example of a pixel driving circuit in each sub-pixel.

Fig. 5 is a schematic structural diagram of a display substrate in an exemplary embodiment of the disclosure, fig. 6 is a schematic cross-sectional diagram of the display substrate along a-a' direction in fig. 5, and fig. 7 is a schematic equivalent circuit diagram of a pixel driving circuit in four sub-pixels shown in fig. 5. Fig. 5 illustrates a structure of a driving circuit layer in four sub-pixels of a bottom emission display substrate and a part of a film layer in a light emitting structure layer, and fig. 6 illustrates a structure of one sub-pixel in a display substrate as an example.

In an exemplary embodiment, as shown in fig. 5 to 7, the plurality of sub-pixels may include, in a direction parallel to the display substrate: a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4 which are sequentially disposed along the second direction DR 2. Wherein each sub-pixel may include: the pixel driving circuit, the pixel driving circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C. In the following description, the sub-pixels each refer to a region where a pixel driving circuit is disposed.

In one exemplary embodiment, as shown in fig. 5 to 7, the display substrate may include, in a plane perpendicular to the display substrate: the light emitting diode comprises a substrate 101, a driving circuit layer 102 arranged on the substrate 101, a Color Film (CF) layer 401 arranged on one side, away from the substrate 101, of the driving circuit layer 102, and a light emitting structure layer 103 arranged on one side, away from the substrate 101, of the Color Film (CF) layer 401. The driving circuit layer 102 may include: the color filter comprises a light shielding layer 23 arranged in the sub-pixel and a metal oxide layer 501 arranged on one side of the light shielding layer 23 far away from the substrate 101, wherein the overlapping area of the orthographic projection of the color film layer (CF)401 on the substrate and the orthographic projection of the metal oxide layer 501 on the substrate is larger than that of the orthographic projection of the color film layer 401 on the substrate and the orthographic projection of the light shielding layer 23 in the sub-pixel on the substrate.

In an exemplary embodiment, the color film layer 401 is configured to filter light emitted by the light emitting device to generate light of different colors. For example, the color film layer 401 may include: the color filter comprises a red (R) color filter unit, a green (G) color filter unit and a blue (B) color filter unit. For example, one color film unit and the corresponding light emitting device and pixel driving circuit may be divided into one sub-pixel. For example, a red (R) color film unit, a green (G) color film unit, and a blue (B) color film unit correspond to the red sub-pixel, the green sub-pixel, and the blue sub-pixel, respectively. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, an orthographic projection of the red color film unit on the substrate and an orthographic projection of the light-shielding layer on the substrate have a first overlapping area, an orthographic projection of the blue color film unit on the substrate and an orthographic projection of the light-shielding layer on the substrate have a second overlapping area, an orthographic projection of the green color film unit on the substrate and an orthographic projection of the light-shielding layer on the substrate have a third overlapping area, and the first overlapping area is larger than the second overlapping area, or the first overlapping area is larger than the third overlapping area.

In an exemplary embodiment, a width of an overlapping region between an orthographic projection of the color film layer 401 on the substrate and an orthographic projection of the light shielding layer 23 on the substrate in the first direction DR1 may be about 5 microns to 350 microns. For example, the width of the overlap region in the first direction DR1 may be 275 microns. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 5 to 7, the display substrate may further include: a pixel driving circuit in the sub-pixel, the pixel driving circuit may include: a driving transistor (for example, the second transistor T2 may be a driving transistor), and an orthogonal projection of the color film layer 401 on the substrate 101 at least partially overlaps an orthogonal projection of a gate electrode (for example, the second gate electrode 43 may be a gate electrode of the driving transistor) of the driving transistor on the substrate 101.

In an exemplary embodiment, as shown in fig. 5 to 7, the display substrate may further include: a pixel driving circuit in the sub-pixel, the pixel driving circuit may include: the storage capacitor C, the driving circuit layer 102 may further include: the first conductive layer 502 is disposed on a side of the light shielding layer 23 close to the substrate, the first conductive layer 502 may include a first plate 11, and the metal oxide layer 501 may include a second plate 34, an orthogonal projection of the second plate 34 on the substrate 101 at least partially overlaps an orthogonal projection of the first plate 11 on the substrate 101 to form the storage capacitor C.

In one exemplary embodiment, as shown in fig. 5 to 7, the light emitting structure layer 103 may include: a pixel defining layer 102, wherein a pixel opening defining a light emitting region is disposed on the pixel defining layer 102, an orthogonal projection of the first electrode plate 11 on the substrate 101 at least partially overlaps an orthogonal projection of the pixel opening on the substrate 101, and an orthogonal projection of the second electrode plate 34 on the substrate 101 at least partially overlaps an orthogonal projection of the pixel opening on the substrate 101. Thus, the transparent metal oxide layer 501 is used as a plate of the storage capacitor C, so that the storage capacitor C can be disposed in the pixel opening, and the pixel opening ratio can be effectively increased.

In an exemplary embodiment, as shown in fig. 5 to 7, the first plate 11 and the second plate 34 of the storage capacitor C may be made of a transparent conductive material. Therefore, the light can be emitted through the transparent storage capacitor, so that the storage capacitor C can be arranged in the pixel opening, and the pixel opening rate can be effectively increased.

In an exemplary embodiment, as shown in fig. 5 to 7, an orthogonal projection of the light shielding layer 23 on the substrate 101 is spaced from an orthogonal projection of the second electrode plate 34 on the substrate 101, that is, the orthogonal projection of the light shielding layer 23 on the substrate 101 does not overlap with the orthogonal projection of the second electrode plate 34 on the substrate 101.

In an exemplary embodiment, as shown in fig. 5 to 7, the storage capacitor C may include: the first electrode plate 11 and the second electrode plate 34, the light shielding layer 23 has a light shielding opening, and the light shielding opening is configured to expose the surface of the first electrode plate 11.

In one exemplary embodiment, as shown in fig. 5 to 7, the pixel driving circuit may include: a first transistor T1 (not shown), a second transistor T2, and a third transistor T3 (not shown), wherein the second region of the active layer of the first transistor T1 is connected to the second electrode 34, the second region of the active layer of the second transistor T2 is connected to the first electrode 11 through the light-shielding opening formed by the light-shielding layer 23, and the second region of the active layer of the third transistor T3 is connected to the first electrode 11.

In an exemplary embodiment, an orthographic projection of the second region of the active layer of the first transistor T1 on the substrate at least partially overlaps with an orthographic projection of the light shielding layer on the substrate.

In an exemplary embodiment, the active layer and the second plate of the first transistor T1 may be a unitary structure connected to each other.

In one exemplary embodiment, as shown in fig. 5 to 7, an orthographic projection of the active layer (i.e., the second active layer 32) of the second transistor T2 on the substrate 101 is located within a range of an orthographic projection of the light shielding layer 23 on the substrate 101. Thus, the light shielding layer 23 can shield the channel region of the second transistor T2, so as to prevent light from affecting the channel and reduce leakage current, thereby preventing the influence of light on the transistor characteristics.

In an exemplary embodiment, an orthographic projection of the active layer of the third transistor T3 on the substrate is spaced apart from an orthographic projection of the light shielding layer on the substrate, i.e., there is no overlapping area between the active layer of the third transistor T3 and the light shielding layer, so that it is advantageous to design a channel width-to-length ratio of the third transistor T3 according to related requirements.

In an exemplary embodiment, the orthographic projection of the active layer of the third transistor T3 on the substrate is spaced apart from the orthographic projection of the second plate on the substrate, i.e., there is no overlapping area between the active layer of the third transistor T3 and the second plate, which facilitates designing the channel width-to-length ratio of the third transistor T3 according to the related requirements. .

In an exemplary embodiment, as shown in fig. 5 to 7, the driving circuit layer 102 may include, in a plane perpendicular to the display substrate: a first conductive layer 502, a second conductive layer 503, a metal oxide layer 501, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate 101, wherein the first electrode plate 11 is disposed on the first conductive layer 502, the light shielding layer 23 is disposed on the second conductive layer, the second electrode plate 34, an active layer (not shown) of the first transistor T1, an active layer (i.e., the second active layer 32) of the second transistor T2 and an active layer (not shown) of the third transistor T3 are disposed on the metal oxide layer 501, a gate electrode (not shown) of the first transistor T1, a gate electrode (i.e., the second gate electrode 43) of the second transistor T2 and a gate electrode (not shown) of the third transistor T3 are disposed on the third conductive layer, a first electrode of the first transistor T1, a second electrode of the first transistor T1, a first electrode of the second transistor T2, a second electrode of the second transistor T2 and a third electrode (not shown) are disposed on the third conductive layer, A first pole of the third transistor T3 and a second pole of the third transistor T3 are on the fourth conductive layer.

In an exemplary embodiment, as shown in fig. 5 to 7, the driving circuit layer may further include: the first scanning signal line S1, the second scanning signal line S2, the first power line VDD, the data signal line D, and the compensation signal line Se, the first scanning signal line S1 and the second scanning signal line S2 are located on the third conductive layer, and the first power line VDD, the data signal line D, and the compensation signal line Se are located on the fourth conductive layer.

In one exemplary embodiment, as shown in fig. 5 to 7, the first and second sub-pixels P1 and P2 are controlled by one first power line VDD, and the third and fourth sub-pixels P2 and P4 are controlled by the other first power line VDD; also, the first, second, third and fourth sub-pixels P1, P2, P3 and P4 are controlled by one compensation signal line.

In an exemplary embodiment, as shown in fig. 5 to 7, the at least one pixel unit may further include: one first scan signal line S1, one second scan signal line S2, two first power lines VDD, four data signal lines D, one compensation signal line Se, and four pixel driving circuits.

In an exemplary embodiment, as shown in fig. 5 to 7, the first and second scan signal lines S1 and S2 may extend along the second direction DR2 and be sequentially disposed along the first direction DR1, the second direction DR2 crossing the first direction DR 1.

In one exemplary embodiment, as shown in fig. 5 to 7, the first power line VDD, the data signal line D, and the compensation signal line Se may extend along the first direction DR1 and be disposed along the second direction DR2, respectively.

In one exemplary embodiment, as shown in fig. 5 to 7, four data signal lines D and one compensation signal line Se may be disposed between two first power lines VDD, two data signal lines D of the four data signal lines D are located between the compensation signal line Se and one first power line VDD, and the other two data signal lines D of the four data signal lines D are located between the compensation signal line Se and the other first power line VDD. Thus, four sub-pixels are formed between the two first power lines VDD by disposing four data signal lines D and one compensation signal line Se, and correspondingly, four sub-pixels are also formed between the two compensation signal lines Se by disposing two first power lines VDD and four data signal lines D.

In one exemplary embodiment, as shown in fig. 5 to 7, one first power line VDD, two data signal lines D, a compensation signal line Se, another two data signal lines D, and another first power line VDD may be sequentially disposed along the second direction DR 2. A first sub-pixel P1 is formed between one first power line VDD and one data signal line D adjacent in the second direction DR2, a second sub-pixel P2 is formed between the compensation signal line Se and one data signal line D adjacent in the opposite direction of the second direction DR2, a third sub-pixel P3 is formed between the compensation signal line Se and one data signal line D adjacent in the second direction DR2, and a fourth sub-pixel P4 is formed between the other first power line VDD and one data signal line D adjacent in the opposite direction of the second direction DR 2.

In one exemplary embodiment, as shown in fig. 5 to 7, the first scan signal line S1 is connected to the gate electrode of the first transistor T1 in each sub-pixel, the second scan signal line S2 is connected to the gate electrode of the third transistor T3 in each sub-pixel, the data signal line D is connected to the first electrode of the first transistor T1 in each sub-pixel, the compensation signal line Se is connected to the first electrode of the third transistor T3 in each sub-pixel, the first power line VDD is connected to the first electrode of the second transistor T2 in each sub-pixel, the second electrode of the first transistor T1 in each sub-pixel is connected to the gate electrode of the second transistor T2, the second electrode of the second transistor T2 in each sub-pixel is connected to the first electrode of the third transistor T3 and the anode of the light emitting device, the first electrode of each sub-pixel is connected to the second electrode of the second transistor T2 and the third electrode of the third transistor T3, the second plate in each sub-pixel is connected to the second pole of the first transistor T1 and the gate electrode of the second transistor T2, respectively.

In an exemplary embodiment, as shown in fig. 5 to 7, at least one pixel cell may include a plurality of connection lines including at least two power connection lines 21 extending along the second direction DR2 and two compensation connection lines 22 extending along the second direction DR2, and thus, a two-by-two structure of the first power line and a four-by-one structure of the compensation signal line may be formed. Therefore, the number of signal lines can be saved, the occupied space can be reduced, the structure is simple, the layout space can be fully utilized, the space utilization rate can be improved, and the improvement of the resolution ratio is facilitated.

In one exemplary embodiment, as shown in fig. 5 to 7, one power connection line 21 is disposed at the first and second sub-pixels P1 and P2, a first end of the power connection line 21 is connected to the first power line VDD in the first sub-pixel P1 through a via, and a second end of the power connection line 21 is connected to the second transistor T2 in the second sub-pixel P2 through a via. Another power connection line 21 is disposed at the third sub-pixel P3 and the fourth sub-pixel P4, a first end of the power connection line 21 is connected to the first power line VDD in the fourth sub-pixel P4 through a via, and a second end of the power connection line 21 is connected to the second transistor T2 in the third sub-pixel P3 through a via. Thus, one first power line VDD can supply power signals to two sub-pixels.

In one exemplary embodiment, as shown in fig. 5 to 7, one compensation connection line 22 is disposed at the first and second sub-pixels P1 and P2, and the first end of the compensation connection line 22 is connected to the compensation signal line Se through a via hole and the second end is connected to the third transistor T3 in the first sub-pixel P1 through a via hole. Another compensation connection line 22 is disposed at the third sub-pixel P3 and the fourth sub-pixel P4, and a first end of the compensation connection line 22 is connected to the compensation signal line Se through a via hole and a second end is connected to the third transistor T3 in the fourth sub-pixel P4 through a via hole. Thus, one compensation signal line Se can supply compensation signals to four sub-pixels.

In one exemplary embodiment, as shown in fig. 5 to 7, the light emitting structure layer 103 of each sub-pixel may include a light emitting device composed of a plurality of film layers, which may include: the organic light emitting diode comprises an anode 301, a pixel defining layer 302, an organic light emitting layer 303 and a cathode 304, wherein the anode 301 is connected with a pixel driving circuit, the organic light emitting layer 303 is connected with the anode 301, the cathode 304 is connected with the organic light emitting layer 303, and the organic light emitting layer 303 emits light rays with corresponding colors under the driving of the anode 301 and the cathode 304. In some possible implementations, the display substrate may include other film layers, which are not limited by this disclosure.

In one exemplary embodiment, the organic light emitting layer may include: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), an emission layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked. For example, the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all the subpixels may be common layers that are connected together. For example, the light-emitting layers of all sub-pixels may be a common layer connected together, or may be isolated from each other, and the light-emitting layers of adjacent sub-pixels may overlap by a small amount.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. For example, the substrate 101 may be a glass substrate. Here, the embodiment of the present disclosure does not limit this.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in this disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, etc., for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, etc., for an organic material. The deposition may be any one or more of sputtering, evaporation, and chemical vapor deposition, the coating may be any one or more of spraying, spin coating, and inkjet printing, and the etching may be any one or more of dry etching and wet etching, which is not limited in this disclosure. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "film" needs a patterning process during the whole fabrication process, it is called "film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the disclosure, the term "a and B are disposed on the same layer" means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the forward projection of B is located within the range of the forward projection of a" or "the forward projection of a includes the forward projection of B" means that the boundary of the forward projection of B falls within the boundary range of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

The following describes a process for manufacturing a display substrate, taking four sub-pixels (the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4) of the display substrate as an example.

In an exemplary embodiment, the manufacturing process of the driving circuit layer may include the steps of:

(1) a first conductive layer is formed.

In one exemplary embodiment, the forming of the first conductive layer may include: depositing a first conductive film on the substrate, and patterning the first conductive film through a patterning process to form a first conductive layer on the substrate.

In an exemplary embodiment, the first conductive layer may use a transparent conductive material, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). For example, the first conductive layer may be formed using ITO, and the first conductive layer may be referred to as a first transparent (ITO1) layer.

In one exemplary embodiment, as shown in fig. 8, the first conductive layer may include: formed at the first plate 11 of each sub-pixel. The first conductive layer may further include: a first auxiliary electrode 12 and a second auxiliary electrode 13.

In an exemplary embodiment, as shown in fig. 8, the first plate 11 in each sub-pixel may include: a body portion 11-0 and a first portion 11-1 and a second portion 11-2 located on both sides of the body portion 11-2. For example, the body portion 11-2 may extend along a first direction DR1 configured to form one transparent plate of the storage capacitor. For example, the first portion 11-1 may be disposed at a side of the body portion 11-0 opposite to the first direction DR1, and connected to the body portion 11-0, configured to be connected to the interlayer connection electrode 24 to be formed later. For example, the second portion 11-2 may be disposed at one side of the body portion 11-0 in the first direction DR1, and connected with the body portion 11-0, configured to be connected with the light blocking layer 23 formed later. For example, corners of at least one of the body portion 11-0, the first portion 11-1, and the second portion 11-2 may be chamfered. For example, the edge of at least one of the body portion 11-0, the first portion 11-1, and the second portion 11-2 may be a fold line.

In an exemplary embodiment, the first auxiliary electrode 12, which may be disposed in each sub-pixel, is configured to be connected to a power connection line 21, which is formed later, to reduce the resistance of the power connection line 21. For example, the shape of the first auxiliary electrode 12 may be rectangular, and corners of the rectangular shape may be chamfered.

In an exemplary embodiment, the second auxiliary electrode 13, which may be disposed in each sub-pixel, is configured to be connected to the compensation connection line 22, which is formed later, to reduce the resistance of the compensation connection line 22. For example, the shape of the second auxiliary electrode 13 may be rectangular. The corners of the rectangular shape may be chamfered and the edges of the rectangular shape may be broken lines.

(2) And forming a second conductive layer.

In one exemplary embodiment, the forming of the second conductive layer may include: and depositing a second conductive film on the substrate with the structure, patterning the second conductive film through a patterning process, and forming a second conductive layer on the substrate.

In one exemplary embodiment, the second conductive layer may be formed using a metal material. For example, the metallic material may include, but is not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-listed metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and the like. The second conductive layer may have a single-layer structure or a multi-layer composite structure such as Mo/Cu/Mo, etc.

In one exemplary embodiment, the second conductive layer may be referred to as a Shield (SHL) layer.

In one exemplary embodiment, as shown in fig. 9A and 9B, the second conductive layer may include: a power supply connection line 21, a compensation connection line 22, and a light shielding layer 23 and an interlayer connection electrode 24 formed at each sub-pixel.

In an exemplary embodiment, as shown in fig. 9A and 9B, the two power connection lines 21 may have a bar structure extending along the second direction DR2, and are positioned at one side of the first direction DR1 of the first plate 11 in sequence along the second direction DR 2. For example, one power connection line 21 may be provided across the first and second sub-pixels P1 and P2, configured to be connected to a first power supply line VDD formed in the first sub-pixel P1 to be formed later, and provide a power signal output from the first power supply line VDD to the second transistor T2 of the second sub-pixel P2. Another power connection line 21 may be provided across the third and fourth sub-pixels P3 and P3, configured to be connected to a first power line VDD formed in the fourth sub-pixel P3 to be formed later, and provide a power signal output from the first power line VDD to the second transistor T2 of the third sub-pixel P3.

In an exemplary embodiment, as shown in fig. 9A and 9B, the two compensation connecting lines 22 may be bar-shaped structures extending along the second direction DR2, and may be sequentially arranged along the second direction DR 2. The two compensation connection lines 22 are located on the opposite side of the first plate 11 from the first direction DR 1. For example, one compensation connection line 22 may be provided across the first and second sub-pixels P1 and P2, configured to be connected to a compensation signal line Se formed later, to supply a compensation signal output by the compensation signal line Se to the third transistor T3 of the first sub-pixel P1. Another compensation connection line 22 may be provided across the third and fourth sub-pixels P3 and P3, configured to be connected to a compensation signal line Se formed later, and provide a compensation signal output by the compensation signal line Se to the third transistor T3 of the fourth sub-pixel P4.

In an exemplary embodiment, as shown in fig. 9A and 9B, a light shielding layer 23 may be disposed in each sub-pixel, configured to shield the first transistor T1 and the second transistor T2 in the sub-pixel, preventing light leakage. For example, the four light shielding layers 23 may be sequentially disposed along the second direction DR 1.

In one exemplary embodiment, as shown in fig. 9A and 9B, each of the light shielding layers 23 may include: a first side 23-1, a second side 23-2, a third side 23-3 and a fourth side 23-4, the first side 23-1 and the third side 23-3 being disposed opposite each other, and the second side 23-2 and the fourth side 23-4 being disposed opposite each other. The body portions of the first and third sides 23-1 and 23-3 may extend in the second direction DR1, and the body portions of the second and fourth sides 23-2 and 23-4 may extend in the first direction DR 2. The first end of the first side 23-1 is connected to the first end of the second side 23-2, the second end of the second side 23-2 is connected to the first end of the third side 23-3, the second end of the third side 23-3 is connected to the second end of the fourth side 23-4, and the first end of the fourth side 23-4 is connected to the second end of the first side 23-1. The first direction DR2 intersects the second direction DR 1.

In one exemplary embodiment, as shown in FIGS. 9A and 9B, one or more of the first side 23-1, the second side 23-2, the third side 23-3, and the fourth side 23-4 may be in the shape of a broken line.

In an exemplary embodiment, an overlapping region exists between an orthographic projection of the light shielding layer 23 on the substrate and an orthographic projection of the color film layer 401 formed in the sub-pixel subsequently on the substrate. Thus, sub-pixel light leakage can be avoided. For example, the orthographic projection of first edge 23-1 on the substrate is within the overlap region. For example, the width of the overlap region in the first direction DR1 may be approximately 5 to 350 microns. For example, the width of the overlapping region in the first direction DR1 may be 275 microns. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 9A and 9B, an orthographic projection of each light shielding layer 23 on the substrate at least partially overlaps with an orthographic projection of the first plate 11 in the sub-pixel on the substrate. For example, the orthographic projection of the light shielding layer 23 on the substrate at least partially overlaps the orthographic projection of the second part 11-2 of the first electrode plate 11 in the sub-pixel on the substrate, and the light shielding layer 23 is connected with the second part 11-2 of the first electrode plate 11.

In an exemplary embodiment, as shown in fig. 9A and 9B, each light shielding layer 23 is opened with a light shielding opening 25, and the light shielding layer 23 in the light shielding opening 25 is removed to expose the surface of the second portion 11-2 of the first plate 11 in the sub-pixel. The light shielding opening 25 is configured to connect the second pole of the subsequently formed second transistor T2 with the second portion 11-2 of the first plate 11 through the light shielding opening 25 and the fourth via V4, wherein an orthographic projection of the subsequently formed fourth via V4 on the substrate at least partially overlaps with an orthographic projection of the light shielding opening 25 on the substrate to expose the second portion 11-2 of the first plate 11.

In an exemplary embodiment, an orthogonal projection of the light shielding layer 23 on the substrate and an orthogonal projection of the second electrode plate 34 formed in the sub-pixel subsequently on the substrate may be spaced apart, i.e. there is no overlapping area between the light shielding layer 23 and the second electrode plate 42. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 9A and 9B, the shapes of the light-shielding layers 23 of different sub-pixels may be different. Alternatively, the areas of the light-shielding layers 23 may be different for different sub-pixels.

In one exemplary embodiment, as shown in fig. 9A and 9B, an interlayer connection electrode 24 may be disposed in each sub-pixel, the interlayer connection electrode 24 being configured to be connected to a second pole of the third transistor T3 formed later. The four interlayer connection electrodes 24 may be sequentially disposed along the second direction DR 1. For example, the interlayer connection electrode 24 may have a rectangular shape, and corners of the rectangular shape may be chamfered.

In an exemplary embodiment, as shown in fig. 9A and 9B, an orthogonal projection of the interlayer connection electrode 24 on the substrate at least partially overlaps an orthogonal projection of the first plate 11 in the sub-pixel on the substrate. For example, an orthogonal projection of the interlayer connection electrode 24 on the substrate at least partially overlaps an orthogonal projection of the first portion 11-1 of the first plate 11 in the sub-pixel on the substrate, and the interlayer connection electrode 24 is connected to the first portion 11-1.

(3) A metal oxide layer is formed.

In one exemplary embodiment, the forming of the metal oxide layer may include: and sequentially depositing a first insulating film and a semiconductor film on the substrate with the structure, patterning the semiconductor film by a patterning process, and forming a first insulating layer covering the second conductive layer and a metal oxide layer arranged on the first insulating layer. In one exemplary embodiment, the first insulating layer may be referred to as a Buffer (Buffer) layer, and the metal oxide layer may be referred to as an Active (ACT) layer.

In one exemplary embodiment, as shown in fig. 10A and 10B, the metal oxide layer may include: a first active layer 31, a second active layer 32, a third active layer 33, and a second plate 34 formed at each sub-pixel.

In one exemplary embodiment, as shown in fig. 10A and 10B, the first active layer 31 serves as an active layer of the first transistor T1, the second active layer 32 serves as an active layer of the second transistor T2, and the third active layer 33 serves as an active layer of the third transistor T3. The first, second, and third

active layers

31, 32, and 33 each include a channel region and first and second regions located at both sides of the channel region.

In an exemplary embodiment, as shown in fig. 10A and 10B, the first active layer 31 may have an "L" shape, and the first active layer 31 may be positioned at one side of the second electrode 34 in the first direction DR 1. The first region 31-1 of the first active layer 31 is located on the side of the channel region far from the second plate 34, the second region 31-2 of the first active layer 31 is located on the side of the channel region near the second plate 34, and an orthographic projection of the second region 31-2 of the first active layer 31 on the substrate at least partially overlaps with an orthographic projection of the light shielding layer 23 on the substrate.

In one exemplary embodiment, as shown in fig. 10A and 10B, the second region 31-2 of the first active layer 31 may be connected with the second plate 34. For example, the first active layer 31 and the second plate 34 may be an integral structure connected to each other. Therefore, compared with the respective arrangement, the arrangement of the pixels can be more compact on the premise of meeting the design rule, and the improvement of the resolution of the display substrate is facilitated.

In one exemplary embodiment, as shown in fig. 10A and 10B, the second region 31-2 of the first active layer 31 in the first and third sub-pixels P1 and P3 has a polygonal line shape extending along the first direction D2, and the polygonal line shape protrudes toward an adjacent sub-pixel. The broken line shape in the first sub-pixel P1 protrudes toward the second sub-pixel P2, and the broken line shape in the third sub-pixel P31 protrudes toward the fourth sub-pixel P4. Since the second region 31-2 of the first active layer 31 is connected to the second gate electrode through the second pole of the first transistor T1 formed later, the interconnection among the second pole of the first transistor T1, the second gate electrode, and the second plate of the storage capacitor is realized, and thus the connection structure of the first transistor T1 and the storage capacitor in the first subpixel P1 and the third subpixel P3 is a corner structure protruding toward the adjacent subpixel. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 10A and 10B, an orthographic projection of the second region 31-2 of the first active layer 31 on the substrate at least partially overlaps with an orthographic projection of the light-shielding layer 23 in the sub-pixel on the substrate.

In an exemplary embodiment, as shown in fig. 10A and 10B, the second active layer 32 may be located on one side of the second plate 34 in the first direction DR1, and an orthographic projection of the second active layer 32 on the substrate is spaced apart from an orthographic projection of the second plate 34 on the substrate, i.e., there is no overlapping area between the second active layer 32 and the second plate 42, so that it is advantageous to design a channel width-to-length ratio of the second transistor according to related requirements.

In one exemplary embodiment, as shown in fig. 10A and 10B, the second active layer 32 may have an "I" shape.

In an exemplary embodiment, as shown in fig. 10A and 10B, the first region 32-1 of the second active layer 32 is located on a side of the channel region away from the second plate 34, an overlapping region exists between an orthographic projection of a portion of the first region 32-1 of the second active layer 32 close to the channel region on the substrate and an orthographic projection of the light shielding layer 23 on the substrate, and an overlapping region exists between an orthographic projection of a portion of the first region 32-1 of the second active layer 32 away from the channel region on the substrate and an orthographic projection of the second portion 11-2 of the first plate 11 on the substrate.

In an exemplary embodiment, as shown in fig. 10A and 10B, the second region 32-2 of the second active layer 32 is located on a side of the channel region close to the second plate 34 and within the light shielding opening 25, and there is an overlapping region between an orthographic projection of the second region 32-2 of the second active layer 32 on the substrate and an orthographic projection of the light shielding layer 23 on the substrate.

In an exemplary embodiment, as shown in fig. 10A and 10B, an orthographic projection of the second active layer 32 on the substrate is located within a range of an orthographic projection of the light-shielding layer 23 on the substrate in the sub-pixel. In this way, the light shielding layer 23 can shield the channel region of the second active layer 32, thereby preventing light from affecting the channel and reducing leakage current, and further preventing light from affecting the characteristics of the transistor.

In an exemplary embodiment, as shown in fig. 10A and 10B, the third active layer 33 may be located on one side of the second plate 34 opposite to the first direction DR1, and an orthogonal projection of the third active layer 33 on the substrate is spaced apart from an orthogonal projection of the second plate 34 on the substrate, i.e., there is no overlapping area between the third active layer 33 and the second plate 42, which is beneficial to design the channel width-to-length ratio of the third transistor according to related requirements.

The first region 33-1 of the third active layer 33 is located on the side of the channel region away from the second plate 34, and there is an overlapping region between the orthographic projection of the first region 33-1 of the third active layer 33 on the substrate and the orthographic projection of the offset connecting line 22 on the substrate. The second region 33-2 of the third active layer 33 is located on the side of the channel region close to the second plate 34, and there is an overlapping region between the orthographic projection of the second region 33-2 of the third active layer 33 on the substrate and the orthographic projection of the interlayer connection electrode 24 on the substrate. Here, the embodiment of the present disclosure does not limit this.

In one exemplary embodiment, as shown in fig. 10A and 10B, the third active layer 33 may have an "I" shape.

In an exemplary embodiment, as shown in fig. 10A and 10B, there is an overlapping region between the orthographic projection of the second plate 34 on the substrate in each sub-pixel and the orthographic projection of the first plate 11 on the substrate in the sub-pixel, the second plate 34 is configured to form the other plate of the storage capacitor C, and the first plate 11 and the second plate 34 form the storage capacitor C. For example, the first plate and the second plate may be transparent conductive layers, forming a transparent storage capacitor C. Therefore, the light can be emitted through the transparent storage capacitor, so that the transparent storage capacitor C can be arranged in the pixel opening, and the pixel opening rate can be effectively increased.

In an exemplary embodiment, the second pole plate 34 may be rectangular in shape. For example, the corners of the rectangular shape may be chamfered. For example, the rectangular shaped edge may be a fold line. The embodiments of the present disclosure do not limit this.

In one exemplary embodiment, the metal oxide layer may be made of a metal oxide material. For example, metal oxide materials may include, but are not limited to: oxides containing indium and tin, oxides containing tungsten and indium and zinc, oxides containing titanium and indium and tin, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, and the like. For example, Indium Gallium Zinc Oxide (IGZO) may be used as the metal oxide layer. For example, the metal oxide layer may be a single layer, a double layer, or a multilayer, etc. Here, the embodiment of the present disclosure does not limit this.

(4) And forming a third conductive layer.

In one exemplary embodiment, the forming of the third conductive layer may include: and sequentially depositing a second insulating film and a third conductive film on the substrate with the structure, and patterning the third conductive film through a patterning process to form a second insulating layer covering the metal oxide layer and a third conductive layer arranged on the second insulating layer. For example, the second insulating layer may be referred to as a Gate Insulating (GI) layer. For example, the third conductive layer may be referred to as a Gate metal (GT) layer.

In one exemplary embodiment, the third conductive layer may be formed using a metal material. For example, the metallic material may include, but is not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-listed metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and the like. For example, the third conductive layer may have a single-layer structure or a multi-layer composite structure such as Mo/Cu/Mo, etc.

In one exemplary embodiment, as shown in fig. 11A and 11B, the third conductive layer may include a first scan signal line S1, a first gate electrode 41, a second scan signal line S2, a third gate electrode 42, a second gate electrode 43, an auxiliary power line 44, an auxiliary data line 45, and an auxiliary compensation line 46.

In an exemplary embodiment, as shown in fig. 11A and 11B, the first scan signal line S1 may be a stripe structure extending along the second direction DR2, located at one side of the second pole plate 34 in the first direction DR 1. The first scan signal line S1 may be spanned among the first to fourth sub-pixels P1 to P4.

In an exemplary embodiment, the first scanning signal line S1 may be disposed with an equal width, the width being a size of the first scanning signal line S1 in the first direction DR 1.

In an exemplary embodiment, as shown in fig. 11A and 11B, a plurality of through holes may be disposed on the first scanning signal line S1, an orthogonal projection of the plurality of through holes on the substrate and an orthogonal projection of the first power supply line VDD, the data signal line D, and the compensation signal line Se formed later on the substrate have an overlapping region, and the plurality of through holes are configured to reduce parasitic capacitances between the first scanning signal line S1 and the first power supply line VDD, the data signal line D, and the compensation signal line Se.

In an exemplary embodiment, the first scanning signal line S1 may be disposed mirror-symmetrically with respect to a vertical axis (e.g., the auxiliary compensation line 46 or the compensation signal line Se).

In one exemplary embodiment, as shown in fig. 11A and 11B, a first gate electrode 41 may be provided in each sub-pixel as a gate electrode of the first transistor T1. In each sub-pixel, there is an overlapping region between the orthographic projection of the first gate electrode 41 on the substrate and the orthographic projection of the first active layer 31 on the substrate. For example, the first gate electrode 41 may have a rectangular shape.

In one exemplary embodiment, as shown in fig. 11A and 11B, the first gate electrode 41 may be positioned at a side of the first scan signal line S1 close to the second scan signal line S2 and connected to the first scan signal line S1. For example, the first scan signal line S1 and the first gate electrode 41 may be an integral structure connected to each other. For example, four first gate electrodes 41 may be sequentially disposed along the second direction DR 2.

In an exemplary embodiment, as shown in fig. 11A and 11B, the second scan signal line S2 may be a stripe structure extending along the second direction DR2 at a side of the second pole plate 34 opposite to the first direction DR 1. The second scan signal line S2 may be spanned among the first to fourth sub-pixels P1 to P4.

In an exemplary embodiment, as shown in fig. 11A and 11B, the second scan signal lines S2 may be disposed with unequal widths, the width being a dimension of the second scan signal lines S2 in the first direction DR 1. For example, the second scan signal line S2 may include a region overlapping the third active layer 33 and a region not overlapping the third active layer 33, wherein a width of the second scan signal line S2 of the region overlapping the third active layer 33 may be smaller than a width of the second scan signal line S2 of the region not overlapping the third active layer 33. For example, in a region not overlapping with the third active layer 33, a plurality of vias may be disposed on the second scanning signal line S2, and an orthographic projection of the plurality of vias on the substrate and an orthographic projection of the first power supply line VDD, the data signal line D, and the compensation signal line Se formed later on the substrate have an overlapping region, the plurality of vias being configured to reduce parasitic capacitance between the second scanning signal line S2 and the first power supply line VDD, the data signal line D, and the compensation signal line Se.

In an exemplary embodiment, as shown in fig. 11A and 11B, an overlapping region exists between the orthographic projection of the second scan signal line S2 on the substrate and the orthographic projection of the third active layer 33 in each sub-pixel on the substrate, and a portion of the second scan signal line S2 corresponding to the overlapping region may serve as the third gate electrode 42.

In one exemplary embodiment, as shown in fig. 11A and 11B, the third gate electrode 42 may be disposed in each sub-pixel as a gate electrode of the third transistor T3.

In an exemplary embodiment, the second scan signal line S2 and the first scan signal line S1 may be disposed in parallel.

In an exemplary embodiment, the second scan signal line S2 may be disposed mirror-symmetrically with respect to a vertical axis (e.g., the auxiliary compensation line 46).

In one exemplary embodiment, as shown in fig. 11A and 11B, the second gate electrode 43 may be disposed within each sub-pixel as a gate electrode of the second transistor T2. In each sub-pixel, an overlapping region exists between the orthographic projection of the second gate electrode 43 on the substrate and the orthographic projection of the second active layer 32 on the substrate, and an overlapping region exists between the orthographic projection of the second gate electrode 43 on the substrate and the orthographic projection of the second region 31-2 of the first active layer 31 on the substrate.

In one exemplary embodiment, as shown in fig. 11A and 11B, the second gate electrodes 43 in the first and fourth sub-pixels P1 and P4 may be mirror-symmetrically disposed with respect to a vertical axis (e.g., the auxiliary compensation line 46), and the second gate electrodes 43 in the second and third sub-pixels P2 and P3 may be mirror-symmetrically disposed with respect to a vertical axis (e.g., the auxiliary compensation line 46).

In an exemplary embodiment, as shown in fig. 11A and 11B, the two auxiliary power lines 44 may have a bar structure extending along the first direction DR 1. Wherein, an auxiliary power line 44 may be formed in the first sub-pixel P1 at a side of the second plate 34 of the first sub-pixel P1 opposite to the second direction DR 2. Another auxiliary power line 44 may be formed in the fourth sub-pixel P4 at one side of the second plate 34 of the fourth sub-pixel P4 in the second direction DR 2. For example, the two auxiliary power lines 44 may be arranged mirror-symmetrically with respect to a vertical axis (e.g., the auxiliary compensation line 46). For example, the auxiliary power line 44 is configured to be connected to the first power line VDD formed later, forming a double-layered routing, ensuring reliability of power signal transmission, and reducing resistance of the first power line VDD.

In one exemplary embodiment, as shown in fig. 11A and 11B, the auxiliary data lines 45 are bar-shaped structures extending along the first direction DR 1. An auxiliary data line 45 is formed within each sub-pixel. In the first and third sub-pixels P1 and P3, the auxiliary data line 45 is positioned at one side of the second direction DR2 of the second plate 34. In the second and fourth sub-pixels P2 and P4, the auxiliary data line 45 is positioned at a side of the second plate 34 opposite to the second direction DR 2. The auxiliary data line 45 is configured to be connected to a subsequently formed data signal line, forming a double-layered wiring, which can ensure reliability of data signal transmission and reduce resistance of the data signal line.

In an exemplary embodiment, as shown in fig. 11A and 11B, the auxiliary compensation line 46 may be a stripe structure extending along the first direction DR 1. The auxiliary compensation line 46 may be formed between the second subpixel P2 and the third subpixel P3. The auxiliary compensation line 46 is configured to be connected with a compensation signal line formed later, and a double-layer routing is formed, so that the reliability of transmission of the compensation signal can be ensured, and the resistance of the compensation signal line can be reduced.

In an exemplary embodiment, the main body portions of the auxiliary power line 44, the auxiliary data line 45, and the auxiliary compensation line 46 may be disposed in parallel.

In one exemplary embodiment, the auxiliary power line 44 within the first and fourth sub-pixels P1 and P4 may be disposed mirror-symmetrically with respect to a vertical axis (e.g., the auxiliary compensation line 46).

In an exemplary embodiment, the process may further include a conductimerization process. The conductive treatment is a treatment of plasma using the third conductive layer as a mask after the third conductive layer pattern is formed, and a region of the metal oxide layer which is masked by the first gate electrode, the second gate electrode, and the third gate electrode serves as a channel region of the transistor, a region of the metal oxide layer which is not masked by the third conductive layer is treated as a conductive region, and the second plate 34 which is conductive and a source/drain region which is conductive (i.e., a first region which is conductive and a second region which is conductive) are formed.

(5) A third insulating layer is formed.

In one exemplary embodiment, the forming of the third insulating layer may include: and depositing a third insulating film on the substrate with the structure, and patterning the third insulating film by adopting a patterning process to form a third insulating layer covering the third conductive layer. In one exemplary embodiment, the third insulating layer may be referred to as an interlayer dielectric (ILD) layer.

In an exemplary embodiment, as shown in fig. 12, a plurality of vias are disposed on the third insulating layer, and the plurality of vias may include: the first via hole V1, the second via hole V2, the third via hole V3, the fourth via hole V4, the fifth via hole V5, the sixth via hole V6, the seventh via hole V7, the eighth via hole V8, the ninth via hole V9, the tenth via hole V10 and the eleventh via hole V11.

In an exemplary embodiment, as shown in fig. 12, a first via V1 may be disposed at each sub-pixel. For each sub-pixel, the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the first region 31-1 of the first active layer 31 on the substrate, and the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region 31-1 of the first active layer 31. In an exemplary embodiment, the first via hole V1 is configured to allow the first pole of the subsequently formed first transistor T1 to be simultaneously connected with the subsequently formed data signal line D and the first region 31-1 of the first active layer 31 through the via hole.

In an exemplary embodiment, as shown in fig. 12, a second via V2 may be disposed at each sub-pixel. The orthographic projection of the second via hole V2 in each sub-pixel on the substrate is within the range of the orthographic projection of the second region 31-2 of the first active layer 31 in the present sub-pixel on the substrate, and the orthographic projection of the second via hole V2 on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 43 on the substrate. In one exemplary embodiment, the third insulating layer and the second insulating layer within the second via hole V2 are etched away while exposing the surface of the second region 31-2 of the first active layer 31 and the surface of the second gate electrode 43. In one exemplary embodiment, the second via hole V2 is a transit via composed of two half holes, one half hole formed on the second region 31-2 of the first active layer 31 and the other half hole formed on the second gate electrode 43, such that the transit via composed of two half holes simultaneously exposes the surface of the second region 31-2 of the first active layer 31 and the surface of the second gate electrode 43. In an exemplary embodiment, the second via V2 is configured to connect the second pole of the subsequently formed first transistor T1 with the second gate electrode 43 and the second region 31-2 of the first active layer 31 simultaneously through the via.

In an exemplary embodiment, as shown in fig. 12, a third via V3 may be disposed at each sub-pixel, an orthographic projection of the third via V3 on the substrate is within an orthographic projection of the first region 32-1 of the second active layer 32 on the substrate, and the third insulating layer and the second insulating layer within the third via V3 are etched away to expose a surface of the first region 32-1 of the second active layer 32. In an exemplary embodiment, the third via hole V3 is configured to connect a subsequently formed first power line or fifth connection electrode with the second active layer 32 through the via hole.

In one exemplary embodiment, as shown in fig. 12, a fourth via V4 may be disposed in each sub-pixel, and an orthogonal projection of the fourth via V4 on the substrate at least partially overlaps an orthogonal projection of the second region 32-2 of the second active layer 32 on the substrate, at least partially overlaps an orthogonal projection of the second portion 11-2 of the first plate 11 on the substrate, and at least partially overlaps an orthogonal projection of the light shielding opening 25 on the substrate. In an exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer within the fourth via hole V4 are etched away while exposing the surface of the second region 32-2 of the second active layer 32 and the surface of the second portion 11-2 of the first plate 11. In an exemplary embodiment, the fourth via V4 is configured to allow the second pole of the subsequently formed second transistor T2 to simultaneously connect with the second portion 11-2 of the first plate 11 and the second active layer 32 through the via.

In an exemplary embodiment, as shown in fig. 12, a fifth via V5 may be disposed at each sub-pixel. For each sub-pixel, an orthographic projection of the fifth via V5 on the substrate at least partially overlaps with an orthographic projection of the first region 33-1 of the third active layer 33 on the substrate, and an orthographic projection of the fifth via V5 on the substrate at least partially overlaps with an orthographic projection of the compensation link line 22 on the substrate. In one exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer within the fifth via hole V5 are etched away while exposing the surface of the first region 33-1 of the third active layer 33 and the surface of the offset connection line 22. In an exemplary embodiment, the fifth via hole V5 is configured to allow the first pole of the subsequently formed third transistor T3 to simultaneously connect with the compensation connection line 22 and the first region 33-1 of the third active layer 33 through the via hole.

In an exemplary embodiment, as shown in fig. 12, a sixth via V6 may be disposed at each sub-pixel. For each sub-pixel, an orthogonal projection of the sixth via V6 on the substrate at least partially overlaps an orthogonal projection of the second region 33-2 of the third active layer 33 on the substrate, and an orthogonal projection of the sixth via V6 on the substrate at least partially overlaps an orthogonal projection of the interlayer connection electrode 24 on the substrate. In one exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer within the sixth via hole V6 are etched away while exposing the surface of the second region 33-2 of the third active layer 33 and the surface of the interlayer connection electrode 24. In an exemplary embodiment, the sixth via V6 is configured to simultaneously connect the second pole of the subsequently formed third transistor T3 with the interlayer connection electrode 24 and the third active layer 33 through the via.

In one exemplary embodiment, as shown in fig. 12, a seventh via V7 may be disposed at the first subpixel P1 and the fourth subpixel P4. The orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the first end of the power connecting line 21 on the substrate. In an exemplary embodiment, the third insulating layer, the second insulating layer and the first insulating layer within the seventh via hole V7 are etched away, exposing the surface of the first end of the power connection line 21. In an exemplary embodiment, the seventh via V7 is configured to allow a subsequently formed first power line to be connected to the first end of the power connection line 21 through the via.

In one exemplary embodiment, as shown in fig. 12, the eighth via hole V8 may be disposed at the second subpixel P2 and the third subpixel P3. The orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the second end of the power connecting line 21 on the substrate. In an exemplary embodiment, the third insulating layer, the second insulating layer and the first insulating layer within the eighth via hole V8 are etched away, exposing the surface of the second end of the power connection line 21. In an exemplary embodiment, the eighth via V8 is configured to connect the first pole of the subsequently formed second transistor T2 with the second end of the power connection line 21 through the via.

In an exemplary embodiment, as shown in fig. 12, a ninth via V9 may be disposed in the first and fourth sub-pixels P1 and P4, an orthogonal projection of the ninth via V9 on the substrate is within an orthogonal projection of the auxiliary power line 44 on the substrate, and the third insulating layer in the ninth via V9 is etched away, exposing a surface of the auxiliary power line 44. In an exemplary embodiment, the ninth via V9 is configured to allow a subsequently formed first power line to be connected to the auxiliary power line 44 through the via. In an exemplary embodiment, the ninth via V9 may include a plurality, and the plurality of ninth vias V9 may be sequentially arranged along the first direction DR1 to increase the connection reliability of the first power line with the auxiliary power line 44.

In an exemplary embodiment, as shown in fig. 12, a tenth via V10 may be disposed at each sub-pixel, an orthogonal projection of the tenth via V10 on the substrate is within a range of an orthogonal projection of the auxiliary data line 45 on the substrate, and the third insulating layer in the tenth via V10 is etched away to expose a surface of the auxiliary data line 45. In an exemplary embodiment, the tenth via V10 is configured to connect a subsequently formed data signal line with the auxiliary data line 45 through the via. In an exemplary embodiment, the tenth via V10 may include a plurality, for example, a plurality of tenth vias V10 may be sequentially arranged along the first direction DR1 to increase the connection reliability of the data signal line and the auxiliary data line 45.

In an exemplary embodiment, as shown in fig. 12, an eleventh via V11 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, an orthogonal projection of the eleventh via V11 on the substrate is within an orthogonal projection of the auxiliary compensation line 46 on the substrate, and the third insulating layer within the eleventh via V11 is etched away to expose a surface of the auxiliary compensation line 46. In an exemplary embodiment, the eleventh via V11 is configured to allow a subsequently formed compensation signal line to be connected to the auxiliary compensation line 46 through the via. In an exemplary embodiment, the eleventh via V11 may include a plurality, for example, a plurality of eleventh vias V11 may be sequentially arranged along the first direction DR1 to increase the connection reliability of the compensation signal line and the auxiliary compensation line 46.

(6) And forming a fourth conductive layer.

In one exemplary embodiment, the forming of the fourth conductive layer may include: and depositing a fourth conductive film on the substrate with the structure, and patterning the fourth conductive film by adopting a patterning process to form a fourth conductive layer arranged on the third insulating layer.

In one exemplary embodiment, the fourth conductive layer may be formed using a metal material. For example, the metallic material may include, but is not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-listed metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and the like. For example, the fourth conductive layer may have a single-layer structure or a multi-layer composite structure such as Mo/Cu/Mo, etc.

In one exemplary embodiment, the fourth conductive layer may be referred to as a source drain metal (SD) layer.

In one exemplary embodiment, as shown in fig. 13A and 13B, the fourth conductive layer may include: a data signal line D, a compensation signal line Se, a first power supply line VDD, a first connection electrode 54, a second connection electrode 55, a third connection electrode 56, a fourth connection electrode 57, and a fifth connection electrode 58.

In an exemplary embodiment, as shown in fig. 13A and 13B, a data signal line D may be disposed at each sub-pixel. The body portion of the data signal line D extends along the first direction DR 1. On one hand, the data signal line D is connected to the first region 31-1 of the first active layer 31 through the first via hole V1 to implement writing of the data signal into the first transistor T1, and on the other hand, the data signal line D is connected to the auxiliary data line 45 through the tenth via holes V10, such that the data signal line D and the auxiliary data line 45 form a dual-layer trace. As such, the exemplary embodiment of the present disclosure realizes writing of data signals to the first transistors T1 of the four subpixels, respectively, by providing the data signal line D extending in the first direction DR1 in each subpixel, the data signal line D being connected to the first transistor T1 of the present subpixel through a via hole.

In one exemplary embodiment, as shown in fig. 13A and 13B, the compensation signal line Se may be disposed between the second sub-pixel P2 and the third sub-pixel P3. The body portion of the compensation signal line Se extends along the first direction DR 1. The compensation signal line Se is connected to the auxiliary compensation line 46 through a plurality of eleventh vias V11, such that the compensation signal line Se and the auxiliary compensation line 46 form a dual-layer trace.

In one exemplary embodiment, as shown in fig. 13A and 13B, the compensation signal line Se is provided with a first projecting portion 51 and a second projecting portion 52. For example, a first end of the first protrusion 51 is connected to the compensation signal line Se, and a second end of the first protrusion 51 extends to the second subpixel P2 along an opposite direction of the second direction DR2 and is simultaneously connected to the first region 33-1 of the third active layer 33 and the compensation connection line 22 through the fifth via hole V5 in the second subpixel P2, so that, on the one hand, the first protrusion 51 may serve as a first pole of the third transistor T3 in the second subpixel P2, and write the compensation signal output from the compensation signal line Se into the third transistor T3 of the second subpixel P2, and on the other hand, the first protrusion 51 may transmit the compensation signal output from the compensation signal line Se to the compensation connection line 22 in the first subpixel P1 and the second subpixel P2, so that the compensation connection line 22 transmits the compensation signal to the third transistor T3 of the first subpixel P1. For example, the first end of the second protrusion 52 is connected to the compensation signal line Se, the second end of the second protrusion 52 extends to the third subpixel P3 along the second direction DR2, and simultaneously connected to the first region 33-1 of the third active layer 33 and the compensating connection line 22 through the fifth via hole V5 in the third sub-pixel P3, in this manner, the second protrusion portion 52 can serve as the first pole of the third transistor T3 in the pixel driving circuit of the third sub-pixel P3 to write the compensation signal outputted from the compensation signal line Se into the third transistor T3 of the third sub-pixel P3, on the one hand, the second protrusion portion 52 can transmit the compensation signal outputted from the compensation signal line Se to the compensation connection line 22 connected across the third sub-pixel P3 and the fourth sub-pixel P4, so that the compensation connection line 22 transmits the compensation signal to the third transistor T3 of the fourth sub-pixel P4.

As such, the present exemplary embodiment realizes the third transistor T3 writing the compensation signals to the four sub-pixels, respectively, by providing one compensation signal line Se whose body portion extends along the first direction DR1 and two compensation connection lines 22 extending along the second direction DR 2. Here, in the second and third sub-pixels P2 and P3, the compensation signal line Se is directly connected to the third transistor T3 through vias, respectively. In the first and fourth sub-pixels P1 and P4, the compensation signal line Se is connected to the third transistor T3 through the compensation connection line 22, respectively. The compensation signal is provided to the four sub-pixels by arranging the compensation signal line Se, RC delay of the compensation signal before writing in the transistor can be basically the same, and display uniformity is guaranteed.

In one exemplary embodiment, as shown in fig. 13A and 13B, the first power line VDD may be disposed at the first and fourth sub-pixels P1 and P4, respectively. A body portion of the first power line VDD extends along the first direction DR 1. On one hand, the first power line VDD may be provided with a third protrusion 53, a first end of the third protrusion 53 is connected to the first power line VDD, and a second end of the third protrusion 53 is connected to the first region 32-1 of the second active layer 32 through a third via hole V3 in the present sub-pixel, so that the third protrusion 53 may serve as a first pole of the second transistor T2, and thus, the power signals output from the first power line VDD may be transmitted to the second transistors T2 of the first sub-pixel P1 and the fourth sub-pixel P4, respectively. On the other hand, the first power line VDD is connected to the first end of the power connection line 21 through the seventh via V7, and the second end of the power connection line 21 is connected to the fifth connection electrode 58 through the eighth via V8, and the fifth connection electrode 58 is connected to the first region 32-1 of the second active layer 32 through the third via V3 in the present sub-pixel, and thus, the power connection line 21 may be allowed to transmit power signals to the second transistors T2 of the second and third sub-pixels P2 and P3, respectively. In yet another aspect, the first power line VDD is connected to the auxiliary power line 44 through a plurality of ninth vias V9, such that the first power line VDD and the auxiliary power line 44 form a double-layered routing.

As such, the present exemplary embodiment realizes the writing of the power signal to the second transistors T2 of the four sub-pixels, respectively, by providing two first power lines VDD extending along the first direction DR1 and two power connection lines 21 extending along the second direction DR 2. Here, the first power line VDD is directly connected to the second transistor T2 through a via hole in the first and fourth sub-pixels P1 and P4. In the second and third sub-pixels P2 and P3, the first power line VDD is connected to the second transistor T2 through the fifth connection electrode 58, respectively.

In one exemplary embodiment, a power signal is supplied to the first and second sub-pixels P1 and P2 through one first power line VDD provided in the first sub-pixel P1, and a power signal is supplied to the third and fourth sub-pixels P3 and P4 through another first power line VDD provided in the first sub-pixel P4.

In an exemplary embodiment, the first power line VDD, the data signal line D, and the compensation signal line Se may be straight lines or polygonal lines of equal width, or straight lines or polygonal lines of unequal width. The first power line VDD, the data signal line D and the compensation signal line Se adopt straight lines or broken lines with variable widths, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance.

In an exemplary embodiment, as shown in fig. 13A and 13B, the first connection electrode 54 may be disposed at each of the sub-pixels, respectively, and may serve as the second pole of the first transistor T1. In an exemplary embodiment, the first connection electrode 54 in each sub-pixel is simultaneously connected to the second region 31-2 of the first active layer 31 and the second gate electrode 43 through the second via V2, and thus, since the second region 31-2 of the first active layer 31 is connected to the second electrode 34, the first connection electrode 54 makes the second pole of the first transistor T1, the second gate electrode 43, and the second electrode 34 have the same potential, i.e., the potential of the first node N1. For example, the first connection electrode 54 may have a rectangular shape.

In an exemplary embodiment, as shown in fig. 13A and 13B, the second connection electrode 55 is disposed at each sub-pixel, respectively, and may serve as a second pole of the second transistor T2. In an exemplary embodiment, the second connection electrode 55 in each sub-pixel is simultaneously connected to the second region 32-2 of the second active layer 32 and the second portion 11-2 of the first plate 11 through the fourth via V4 such that the second connection electrode 55 makes the second pole of the second transistor T2 and the first plate 11 have the same potential. For example, the second connection electrode 55 may have a rectangular shape.

In an exemplary embodiment, as shown in fig. 13A and 13B, the third connection electrode 56 is disposed at each sub-pixel, respectively, and may serve as the second pole of the third transistor T3. In an exemplary embodiment, the third connection electrode 56 in each sub-pixel is simultaneously connected to the second region 33-2 of the third active layer 33 and the interlayer connection electrode 24 through the sixth via V6, and thus, the third connection electrode 56 makes the second pole of the third transistor T3 and the first plate 11 have the same potential since the interlayer connection electrode 24 is connected to the first portion 11-1 of the first plate 11. For example, the third connection electrode 56 may have a rectangular shape.

Here, since the second connection electrode 55 makes the first plate 11 have the same potential as the second pole of the second transistor T2 and the third connection electrode 56 makes the first plate 11 have the same potential as the second pole of the third transistor T3, the second pole of the second transistor T2, the second pole of the third transistor T3 and the first plate 11 have the same potential, that is, the potential of the second node N2.

In one exemplary embodiment, as shown in fig. 13A and 13B, the fourth connection electrode 57 serves as a first pole of the third transistor T3. In an exemplary embodiment, one fourth connection electrode 57 may be disposed at the first sub-pixel P1 as a first pole of the third transistor T3 in the first sub-pixel P1, and the other fourth connection electrode 57 may be disposed at the fourth sub-pixel P4 as a first pole of the third transistor T3 in the fourth sub-pixel P4. In one exemplary embodiment, the fourth connection electrode 57 in the first sub-pixel P1 is simultaneously connected to the first region 33-1 of the third active layer 33 and the compensation connection line 22 through the fifth via hole V5 in the first sub-pixel P1, and since the compensation connection line 22 is connected to the compensation signal line Se, the fourth connection electrode 57 in the first sub-pixel P1 may write the compensation signal output from the compensation signal line Se to the third transistor T3 in the first sub-pixel P1. In an exemplary embodiment, the fourth connection electrode 57 in the fourth sub-pixel P4 is simultaneously connected to the first region 33-1 of the third active layer 33 and the compensation connection line 22 through the fifth via hole V5 in the fourth sub-pixel P4, and since the compensation connection line 22 is connected to the compensation signal line Se, the fourth connection electrode 57 in the fourth sub-pixel P4 may write a compensation signal to the third transistor T3 of the fourth sub-pixel P4. For example, the fourth connection electrode 57 may have a rectangular shape.

In one exemplary embodiment, as shown in fig. 13A and 13B, the fifth connection electrode 58 may serve as the first pole of the second transistor T2. In one exemplary embodiment, one fifth connection electrode 58 may be disposed at the second sub-pixel P2 as the first pole of the second transistor T2 in the second sub-pixel P2, and the other fifth connection electrode 58 may be disposed at the third sub-pixel P3 as the first pole of the second transistor T2 in the third sub-pixel P3. In one exemplary embodiment, a first end of the fifth connection electrode 58 is connected to the power connection line 21 through the eighth via V8 in the second sub-pixel P2, and a second end of the fifth connection electrode 58 is connected to the first region 32-1 of the second active layer 32 through the third via V3 of the sub-pixel. In this manner, since the power connection line 21 is connected to the first power line VDD, the fifth connection electrode 58 may write the power signal to the second transistor T2 of the second and third sub-pixels P2 and P3. For example, the fifth connection electrode 58 may have a strip shape extending along the first direction DR 1.

(7) And forming a fourth insulating layer.

In one exemplary embodiment, the forming of the fourth insulating layer may include: and coating a fourth insulating film on the substrate with the structure, and patterning the fourth insulating film by adopting a patterning process to form a fourth insulating layer covering the fourth conductive layer. In one exemplary embodiment, the fourth insulating layer may be referred to as a Passivation (PVX) layer.

In an exemplary embodiment, as shown in fig. 14, a plurality of vias are opened on the fourth insulating layer, and the plurality of vias may include: a twenty-first via V21 in each subpixel.

In an exemplary embodiment, as shown in fig. 14, a twenty-first via V21 may be disposed in each sub-pixel, an orthographic projection of the twenty-first via V21 on the substrate is within an orthographic projection of the second connection electrode 55 on the substrate, and the fourth insulation layer in the twenty-first via V21 is removed to expose a surface of the second connection electrode 55. In an exemplary embodiment, the twenty-first via V21 is configured to connect a subsequently formed anode with the second connection electrode 55 through the via and the thirty-first via V31.

In one exemplary embodiment, the first, second, third, and fourth insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer.

Thus, the driving circuit layer is prepared and completed on the substrate.

In an exemplary embodiment, after the driving circuit layer is manufactured, a Color Filter (CF) layer is manufactured on the driving circuit layer, and the manufacturing process of the Color Filter (CF) layer may include the following steps:

(9) forming a color film layer.

In one exemplary embodiment, forming the color film layer 401 may include: as shown in fig. 15A and 15B, on the substrate on which the foregoing structure is formed, a red filter film is coated, and a red color film unit 401R is formed by a photolithography process; as shown in fig. 15C and 15D, a green color filter film is coated, and a green color filter unit 401G is formed through a photolithography process; as shown in fig. 15E and 15F, a blue color filter film is coated, and a blue color filter unit 401B is formed by a photolithography process. Here, the coating sequence of the color film unit is merely an example, and the color film layer may be formed in a different manner from the listed sequence.

In an exemplary embodiment, as shown in fig. 15A to 15F, the red color film unit 401R may be disposed at the first sub-pixel P1, the green color film unit 401G may be disposed at the third sub-pixel P3, and the blue color film unit 401B may be disposed at the fourth sub-pixel P4. Here, the embodiment of the present disclosure is not limited to this.

In an exemplary embodiment, as shown in fig. 15A to 15F, an orthographic projection of the red color film unit 401R on the substrate and an orthographic projection of the light-shielding layer 23 on the substrate have a first overlapping area, an orthographic projection of the blue color film unit 401B on the substrate and an orthographic projection of the corresponding light-shielding layer 23 on the substrate have a second overlapping area, an orthographic projection of the green color film unit 401G on the substrate and an orthographic projection of the light-shielding layer 23 on the substrate have a third overlapping area, and the first overlapping area is larger than the second overlapping area or the third overlapping area.

In an exemplary embodiment, as shown in fig. 15A to 15B, that the orthographic projection of the color film layer 401 on the substrate at least partially overlaps with the orthographic projection of the gate electrode (e.g., the second gate electrode 43) of the driving transistor on the substrate may mean that the orthographic projection of the red color film unit 401R on the substrate at least partially overlaps with the orthographic projection of the gate electrode (e.g., the second gate electrode 43) of the driving transistor on the substrate. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, as shown in fig. 15A to 15F, the second subpixel P2 is a white subpixel, and no color film unit is disposed in the white subpixel.

In an exemplary embodiment, the material of the color film unit may be a negative photoresist. Such as a negative color photoresist (which may be referred to simply as a color photoresist).

In an exemplary embodiment, the material of the red filter film, the green filter film and the blue filter film may employ a negative photoresist. Therefore, the characteristic of large process deviation (CD) in negative photoresist exposure can be utilized, and the fact that the orthographic projection of the color film unit on the substrate and the orthographic projection of the shading layer on the substrate are at least partially overlapped can be achieved on the basis that a Mask (Mask) is not added. Therefore, the light leakage of the sub-pixels can be avoided, the problem of color unevenness caused by the light leakage can be prevented, and the quality of a display picture can be improved. Moreover, because a Mask (Mask) is not added, the method can be well compatible with the current preparation process, the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.

(10) Forming a fifth insulating layer.

In one exemplary embodiment, the forming of the fifth insulating layer may include: and depositing a fifth insulating film on the substrate with the structure, and patterning the fifth insulating film by adopting a patterning process to form a fifth insulating layer covering the color film unit. In one exemplary embodiment, the fifth insulating layer may be referred to as a flat (PLN) layer or a Resin (Resin) layer.

In an exemplary embodiment, as shown in fig. 16, a plurality of vias are opened on the fifth insulating layer, and the plurality of vias may include: and a thirty-first via V31 in each subpixel. In an exemplary embodiment, an orthographic projection of the thirty-first via V31 on the substrate is within an orthographic projection of the second connection electrode 55 on the substrate, and an orthographic projection of the twenty-first via V21 on the substrate is within an orthographic projection of the thirty-first via V31 on the substrate, the fifth insulating layer and the fourth insulating layer within the thirty-first via V31 are removed to expose a surface of the second connection electrode 55. In an exemplary embodiment, the thirty-first via V31 is configured to connect a subsequently formed anode with the second connection electrode 55 through the via and the twenty-first via V21.

In an exemplary embodiment, the fifth insulating layer may employ an organic material, for example, Resin (Resin), etc. May be a single layer, multiple layers or composite layers.

And preparing a color film layer on the drive circuit layer.

In an exemplary embodiment, after the driving circuit layer and the color film layer are prepared, the light emitting structure layer is prepared on the color film layer, and the preparation process of the light emitting structure layer may include the steps of:

(11) and forming a fifth conductive layer.

In one exemplary embodiment, the forming of the fifth conductive layer may include: and depositing a fifth conductive film on the substrate with the structure, and patterning the fifth conductive film by adopting a patterning process to form a fifth conductive layer arranged on the flat layer.

In an exemplary embodiment, the fifth conductive layer may use a transparent conductive material, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). May be a single layer, multiple layers or composite layers. For example, in the case where the fifth conductive layer is formed using ITO, the fifth conductive layer may be referred to as a second transparent (ITO2) layer.

In one exemplary embodiment, as shown in fig. 17A and 17B, the fifth conductive layer may include: the anode electrode 301 is positioned in each sub-pixel, and the anode electrode 301 in each sub-pixel is connected to the second connection electrode 55 through the twenty-first via hole V21. For example, one side of the anode 301 in the first direction DR1 in each sub-pixel is provided with a protrusion connected to the second connection electrode 55 through the twenty-first via hole V21 and the thirty-first via hole V31. In this manner, since the second connection electrode 55 serves as the second pole of the second transistor T2, the connection of the anode 301 and the second transistor T2 can be achieved.

In one exemplary embodiment, as shown in fig. 17A and 17B, the fifth conductive layer may include: a first anode 301R located in the first sub-pixel P1, a second anode 301W located in the second sub-pixel P2, a third anode 301G located in the third sub-pixel P3, and a fourth anode 301B located in the fourth sub-pixel P4.

In one exemplary embodiment, as shown in fig. 17A and 17B, the first, second, third and

fourth anodes

301R, 301W, 301G and 301B may have a bar shape extending along the first direction DR 1.

In an exemplary embodiment, the orthographic projection of the anode in each sub-pixel on the substrate may include the orthographic projection of the storage capacitor C in the sub-pixel on the substrate.

(12) A pixel definition layer is formed.

In one exemplary embodiment, forming the pixel defining layer may include: as shown in fig. 18A and 18B, a pixel defining film is coated on the substrate on which the foregoing structure is formed, and the pixel defining film is patterned using a patterning process to form a pixel defining layer 302. Among them, the pixel definition layer 302 may include at least: a pixel opening in each sub-pixel.

In an exemplary embodiment, as shown in fig. 18A and 18B, the pixel defining layer 302 may include: a first pixel opening 302R in the first sub-pixel P1 exposing the first anode 301R, a second pixel opening 302W in the second sub-pixel P2 exposing the second anode 301W, a third pixel opening 302G in the third sub-pixel P3 exposing the third anode 301G, and a fourth pixel opening 302B in the fourth sub-pixel P4 exposing the fourth anode 301B. Here, the embodiment of the present disclosure does not limit this.

In one exemplary embodiment, the shape and area of the pixel opening of different sub-pixels may be different. The four sub-pixels are designed to have different aperture opening ratios, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, the service lives of the four sub-pixel light-emitting devices are optimized to the greatest extent, and the service lives of products are guaranteed.

In an exemplary embodiment, as shown in fig. 18A and 18B, the pixel defining layer 302 may further include: the partition groove 302A, the partition groove 302A may have a bar shape extending along the first direction DR1, may be disposed between adjacent sub-pixels, and the partition groove 302A is configured to reduce light leakage between the adjacent sub-pixels.

In an exemplary embodiment, the pixel defining layer may be made of Polyimide (PI), acryl, or polyethylene terephthalate (PET), etc. May be a single layer, multiple layers or composite layers. Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, after the preparing the pixel defining layer, the preparing process of the display substrate may further include: and forming an organic light emitting layer connected with the anode through the pixel opening, and forming a cathode on the organic light emitting layer, wherein the cathode is connected with the organic light emitting layer.

In one exemplary embodiment, the organic light emitting layer may be formed by using an evaporation or inkjet printing process. For example, the organic light emitting layer may be formed by evaporation using a Fine Metal Mask (FMM), an Open Mask (Open Mask), or the like.

And finally, preparing the light emitting structure layer on the color film structure layer.

In one exemplary embodiment, the display substrate may further include: and an encapsulation layer disposed on a side of the light emitting structure layer 103 away from the substrate 101. For example, the encapsulation layer may include: the packaging structure comprises a first packaging layer, a second packaging layer and a third packaging layer which are stacked. For example, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be disposed between the first encapsulation layer and the third encapsulation layer, so that it is ensured that external moisture cannot enter the light emitting structure layer 103.

In an exemplary embodiment, after the preparing the light emitting structure layer, the preparing process of the display substrate may further include: and forming an encapsulation layer.

In an exemplary embodiment, as shown in fig. 5 to 18B, a display substrate provided by an exemplary embodiment of the present disclosure may include:

a substrate 101;

a first conductive layer 502 disposed on the substrate 101, the first conductive layer 502 may include: a first pole plate 11;

a second conductive layer 503 disposed on the first conductive layer 502, the second conductive layer 503 may include: a light-shielding layer 23;

a first insulating layer 201 covering the second conductive layer 503;

a metal oxide layer 501 disposed on the first insulating layer 201, the metal oxide layer may include: a second plate 34 and three transistor active layers, wherein the second plate 34 and the first plate 11 form a transparent storage capacitor;

a second insulating layer 202 covering the metal oxide layer;

a third conductive layer disposed on the second insulating layer 202, the third conductive layer may include: the first scanning signal line 41, the second scanning signal line 42, and the gate electrodes of three transistors:

a third insulating layer 203 covering the third conductive layer, the third insulating layer 203 being provided with a plurality of via holes;

a fourth conductive layer disposed on the third insulating layer 203, the fourth conductive layer may include: a first power supply line VDD, a data signal line D, a compensation signal line Se, and first and second poles of three transistors;

a fourth insulating layer 204 covering the fourth conductive layer, the fourth insulating layer 204 being provided with a plurality of via holes;

a color film unit 401 disposed on the fourth insulating layer 204;

a fifth insulating layer 205 covering the color film unit 401, wherein the fifth insulating layer 205 is provided with a plurality of via holes;

a fifth conductive layer disposed on the fifth insulating layer 205, the fifth conductive layer may include an anode 301;

a pixel defining layer 302 covering the fifth conductive layer, wherein the pixel defining layer 302 is provided with a pixel opening exposing the anode 301;

an organic light emitting layer 303 disposed on the pixel defining layer 302, the organic light emitting layer 303 being connected to the anode electrode 301 through the pixel opening;

and a cathode 304 disposed on the organic light emitting layer 303.

As can be seen from the above, in the display substrate provided in the exemplary embodiment of the disclosure, as shown in fig. 6 and 19, by adopting a design in which the orthographic projection of the color film layer 401 on the substrate 101 overlaps with the orthographic projection of the light shielding layer 23 on the substrate 101, in the area circled by the dotted line in fig. 19, the white light (for example, the light ray indicated by the dotted line with an arrow in fig. 6) generated by the organic light emitting layer 303 of the sub-pixel leaks from the edge of the color film layer 401 by diffuse reflection or refraction of the cathode 304 and other film layers, and is emitted to the light shielding layer 23, so as to be shielded by the light shielding layer 23. Therefore, the problem of light leakage of the sub-pixels can be avoided, the problem of color unevenness caused by the light leakage can be avoided, and the display quality can be improved. The first electrode 11 of the storage capacitor C and the second electrode 34 of the storage capacitor C are formed by the transparent first conductive layer 502 and the transparent metal oxide layer 501, so that light can penetrate through the transparent storage capacitor C, and therefore the storage capacitor C can be disposed in a pixel opening formed in the pixel defining layer 302, the pixel opening ratio can be increased, and the display quality can be improved.

The structure of the display substrate and the process of manufacturing the same listed above are merely exemplary illustrations, and those skilled in the art can modify the corresponding structure and add or reduce the patterning process according to the actual situation. For example, one pixel unit may include three sub-pixels. For example, the pixel driving circuit may have a structure of 5T1C or 7T 1C. Here, the embodiment of the present disclosure does not limit this.

The exemplary embodiments of the present disclosure also provide a method for manufacturing a display substrate, where the display substrate may be the display substrate in one or more exemplary embodiments described above, and the method for manufacturing may include:

step 1: forming a driving circuit layer on the substrate, the driving structure layer including: the light shading layer is positioned in the sub-pixel, and the metal oxide layer is arranged on one side, far away from the substrate, of the light shading layer;

step 2: forming a color film layer on one side of the driving circuit layer, which is far away from the substrate, wherein the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the metal oxide layer on the substrate is larger than that of the orthographic projection of the color film layer on the substrate and the orthographic projection of the shading layer on the substrate;

and step 3: and forming a light emitting structure layer on one side of the color film layer far away from the substrate.

In an exemplary embodiment, step 2 may include: coating a layer of negative photoresist on one side of the drive circuit layer, which is far away from the substrate, to form a light filtering film; and processing the light filtering film through a photoetching process to form a color film layer.

As can be seen from the above, in the manufacturing method provided in the exemplary embodiment of the disclosure, the orthographic projection of the color film unit on the substrate in the manufactured display substrate is overlapped with the orthographic projection of the light shielding layer on the substrate, so that the white light generated by the organic light emitting layer of the sub-pixel leaks from the edge of the color film unit through the diffuse reflection or refraction of the cathode and other film layers, and is emitted to the light shielding layer, so that the white light is shielded by the light shielding layer. Therefore, the problem of light leakage of the sub-pixels can be avoided, the problem of color unevenness caused by the light leakage can be avoided, and the display quality can be improved.

The above description of the embodiment of the manufacturing method is similar to the above description of the embodiment of the display substrate, and has similar advantageous effects to the embodiment of the display substrate. For technical details not disclosed in the embodiments of the preparation method of the present disclosure, those skilled in the art should refer to the description in the embodiments of the display substrate of the present disclosure for understanding, and therefore, the description is omitted here for brevity.

Exemplary embodiments of the present disclosure also provide a display device. The display device may include: the display substrate in one or more of the above exemplary embodiments.

In one exemplary embodiment, the display substrate may include, but is not limited to: an OLED display substrate, a Quantum-dot Light Emitting Diode (QLED) display substrate, a Micro Light-Emitting Diode (Micro LED) display substrate, or a submillimeter Light-Emitting Diode (Mini LED). Here, the embodiment of the present disclosure does not limit this.

In an exemplary embodiment, the display device may include, but is not limited to: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, and the like. Here, the embodiment of the present disclosure does not limit the type of the display device. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

The above description of the embodiments of the display device, similar to the above description of the embodiments of the display substrate, has similar advantageous effects as the embodiments of the display substrate. For technical details not disclosed in the embodiments of the display device of the present disclosure, those skilled in the art should refer to the description of the embodiments of the display substrate of the present disclosure for understanding, and therefore, the description thereof is omitted here for brevity.

Although the embodiments disclosed in the present disclosure are described above, the above description is only for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. It will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made in the form and details without departing from the spirit and scope of the disclosure, but that the scope of the disclosure is to be determined solely by the appended claims.

Claims

1. A display substrate, comprising: the LED display panel comprises a substrate, a driving circuit layer arranged on the substrate, a color film layer arranged on one side, far away from the substrate, of the driving circuit layer and a light emitting structure layer arranged on one side, far away from the substrate, of the color film layer; wherein the driving circuit layer includes: the color filter comprises a light shielding layer positioned in the sub-pixels and a metal oxide layer arranged on one side, far away from the substrate, of the light shielding layer, wherein the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the metal oxide layer on the substrate is larger than the overlapping area of the orthographic projection of the color film layer on the substrate and the orthographic projection of the light shielding layer on the substrate.

2. The display substrate of claim 1, wherein the color film layer comprises: the orthographic projection of the red color film unit on the substrate and the orthographic projection of the shading layer on the substrate have a first overlapping area, the orthographic projection of the blue color film unit on the substrate and the orthographic projection of the shading layer on the substrate have a second overlapping area, the orthographic projection of the green color film unit on the substrate and the orthographic projection of the shading layer on the substrate have a third overlapping area, and the first overlapping area is larger than the second overlapping area or the third overlapping area.

3. The display substrate of claim 1, further comprising: a pixel driving circuit in a sub-pixel, the pixel driving circuit comprising: and the orthographic projection of the color film layer on the substrate is at least partially overlapped with the orthographic projection of the gate electrode of the driving transistor on the substrate.

4. The display substrate of claim 1, further comprising: a pixel driving circuit in a sub-pixel, the pixel driving circuit comprising: a storage capacitor, the driving circuit layer further comprising: the first conducting layer is arranged on one side, close to the substrate, of the shading layer and comprises a first polar plate, the metal oxide layer comprises a second polar plate, and the orthographic projection of the second polar plate on the substrate is at least partially overlapped with the orthographic projection of the first polar plate on the substrate to form the storage capacitor.

5. The display substrate according to claim 4, wherein the light emitting structure layer comprises: the pixel definition layer is provided with a pixel opening for defining a light emitting area, the orthographic projection of the first polar plate on the substrate is at least partially overlapped with the orthographic projection of the pixel opening on the substrate, and the orthographic projection of the second polar plate on the substrate is at least partially overlapped with the orthographic projection of the pixel opening on the substrate.

6. The display substrate of claim 4, wherein an orthographic projection of the light shielding layer on the substrate is spaced from an orthographic projection of the second electrode plate on the substrate.

7. The display substrate of claim 4, wherein the light-shielding layer defines a light-shielding opening configured to expose a surface of the first electrode plate.

8. The display substrate of claim 7, wherein the pixel driving circuit further comprises: the second region of the active layer of the first transistor is connected with the second polar plate through the light shielding opening, the second region of the active layer of the third transistor is connected with the first polar plate, and the second transistor is a driving transistor.

9. The display substrate according to claim 8, wherein an orthographic projection of the active layer of the second transistor on the base is within a range of an orthographic projection of the light-shielding layer on the base.

10. The display substrate of claim 8, wherein an orthographic projection of the second region of the active layer of the first transistor on the substrate at least partially overlaps with an orthographic projection of the light shielding layer on the substrate.

11. The display substrate of claim 8, wherein the active layer of the first transistor and the second plate are connected to each other in a unitary structure.

12. The display substrate according to claim 8, wherein an orthographic projection of the active layer of the third transistor on the substrate is spaced from an orthographic projection of the light shielding layer on the substrate, and wherein an orthographic projection of the active layer of the third transistor on the substrate is spaced from an orthographic projection of the second electrode on the substrate.

13. The display substrate of claim 4, wherein the first and second plates are made of a transparent conductive material.

14. The display substrate according to claim 1, wherein the light-shielding layer comprises: the light shielding layer comprises a first edge, a second edge, a third edge and a fourth edge, wherein the first edge and the third edge are oppositely arranged and extend along a second direction, the second edge and the fourth edge are oppositely arranged and extend along a first direction, the first end of the first edge is connected with the first end of the second edge, the second end of the first edge is connected with the first end of the fourth edge, the second end of the second edge is connected with the first end of the third edge, the second end of the third edge is connected with the second end of the fourth edge, the orthographic projection of the first edge on the substrate is located within the range of an overlapping area between the orthographic projection of the color film layer on the substrate and the orthographic projection of the light shielding layer on the substrate, and the first direction is crossed with the second direction.

15. The display substrate of claim 14, wherein one or more of the first edge, the second edge, the third edge, and the fourth edge are in the shape of a broken line.

16. The display substrate of claim 1, wherein a width of an overlapping region between an orthographic projection of the color film layer on the substrate and an orthographic projection of the light shielding layer on the substrate in the first direction is 5 to 350 micrometers.

17. The display substrate of claim 1, further comprising: a pixel driving circuit in a sub-pixel, the pixel driving circuit comprising: a first transistor, a second transistor, a third transistor, and a storage capacitor;

in a direction perpendicular to the display substrate, the driving circuit layer includes: a first conductive layer, a second conductive layer, the metal oxide layer, a third conductive layer and a fourth conductive layer sequentially arranged on the substrate, the first electrode plate of the storage capacitor is positioned on the first conductive layer, the shading layer is positioned on the second conductive layer, the second plate of the storage capacitor, the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are located on the metal oxide layer, a gate electrode of the first transistor, a gate electrode of the second transistor, and a gate electrode of the third transistor are located on the third conductive layer, a first pole of the first transistor, a second pole of the first transistor, a first pole of the second transistor, a second pole of the second transistor, a first pole of the third transistor, and a second pole of the third transistor are located on the fourth conductive layer.

18. The display substrate of claim 17, wherein the driving circuit layer further comprises: the first scanning signal line and the second scanning signal line are located on the third conducting layer, and the first power line, the data signal line and the compensation signal line are located on the fourth conducting layer.

19. The display substrate of claim 1, wherein the driving circuit layer further comprises: a first power line and a compensation signal line extending in a first direction, the display substrate further including: the display panel comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel which are arranged along a second direction in sequence and have different colors, wherein the second sub-pixel is a white sub-pixel, the first sub-pixel and the second sub-pixel are controlled by one first power line, and the third sub-pixel and the fourth sub-pixel are controlled by the other first power line; and, the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel are controlled by one compensation signal line.

20. A display device, comprising: the display substrate of any one of claims 1 to 19.