CN117936543A

CN117936543A - Electronic device

Info

Publication number: CN117936543A
Application number: CN202211254412.9A
Authority: CN
Inventors: 詹宜频; 郭霭翎
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2022-10-13
Filing date: 2022-10-13
Publication date: 2024-04-26
Also published as: TW202416480A

Abstract

The present disclosure provides an electronic device, comprising: a substrate having an active region and a non-active region adjacent to the active region; the first conducting wire layer is arranged in the non-active area; the second wire layer is arranged on the first wire layer; the first insulating layer is arranged on the second wire layer; and an alignment layer disposed on the first insulating layer, wherein in a cross-sectional view of the electronic device, the first conductive line layer has a first edge, the second conductive line layer has a second edge, the first edge and the second edge are horizontally spaced apart by a first distance, and the first insulating layer has a first sidewall portion covering the first edge and the second edge and forming a stepped structure.

Description

Electronic device

Technical Field

The present disclosure relates to an electronic device, and more particularly, to an electronic device with a fan-out region having metal conductive layers arranged in a staggered and stacked manner.

Background

In recent years, the frames of mobile phone products gradually shrink toward the trend of narrowing the surrounding frames, so that the distance between the active area and the bonding pad (bonding pad) is compressed, and the risk of the alignment layer flowing to the bonding area increases. If the alignment layer flows to the bonding region, an alignment layer is disposed between the conductive particles and the bonding pad, and the signal is abnormal due to the larger resistance of the alignment layer.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided an electronic apparatus including: a substrate having an active region and a non-active region adjacent to the active region; the first conducting wire layer is arranged in the non-active area; the second wire layer is arranged on the first wire layer; the first insulating layer is arranged on the second wire layer; and an alignment layer disposed on the first insulating layer, wherein in a cross-sectional view of the electronic device, the first conductive line layer has a first edge, the second conductive line layer has a second edge, the first edge and the second edge are horizontally spaced apart by a first distance, and the first insulating layer has a first sidewall portion covering the first edge and the second edge and forming a stepped structure.

Drawings

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. It should be noted that the various features are not drawn to scale and are merely illustrative. Indeed, the dimensions of the components may be exaggerated or reduced to clearly illustrate the technical features of the embodiments of the present disclosure.

FIG. 1 is a top view of an electronic device according to an embodiment of the present disclosure;

FIG. 2 is a top view of a partial area of an electronic device according to an embodiment of the present disclosure;

FIG. 3 is a top view of a partial area of an electronic device according to an embodiment of the present disclosure;

FIG. 4 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure;

FIG. 5 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure;

FIG. 6 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure; and

Fig. 7 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure.

[ Symbolic description ]

10,100 Electronic device

10A partial region of an electronic device

10B partial region of an electronic device

11 Substrate

11A upper surface of the substrate

12 Active layer

14 Non-active layer

16 Circuit protection area

18 Fan-out section

20-Joining zone

22 Frame glue

24 Integrated circuit

26 Anisotropic conductive adhesive

28 Finger engagement structure

30 Virtual thin film transistor

32 Electrostatic discharge protection device

34 Conductive line layer

36 First conductor layer

36' First portion of first conductor layer

36' (Second portion of first conductive line layer)

36A upper surface of the first conductive line layer

36B lower surface of the first conductive line layer

36E1 first edge/edge of upper surface of first conductor layer

36E3 edge of the lower surface of the third/first conductor layer

38 Second conductor layer

38': First portion of second conductor layer

38'

38B lower surface of the second conductive line layer

38E2 second edge/edge of the lower surface of the second conductor layer

38E4 edge of the fourth edge/edge of the lower surface of the second conductor layer

40 First insulating layer

40A platform portion of the first insulating layer

40S1 first sidewall portion of the first insulating layer

40S1a bottom of the first side wall portion

40S1b step portion of the first side wall portion

40S2 second sidewall portion of the first insulating layer

40S2a bottom of the second side wall portion

40S2b step portion of the second side wall portion

42 Alignment layer

44 Second insulating layer

46 First step-like structure

48 Second stepped structure

50 Ball shape

C (c 1) connecting the edge of the upper surface of the first conductive line layer with the edge of the lower surface of the second conductive line layer

C2 connecting the edge of the lower surface of the first wire layer with the edge of the lower surface of the second wire layer

D1 first distance

D2 second distance

H horizontal direction

L1 thickness of alignment layer on bottom of first sidewall portion

Thickness of alignment layer on step portion of first sidewall portion

Thickness of alignment layer on mesa

Thickness of the second insulating layer t1

Width of first conducting wire layer

Width of the second conductive line layer

Beta is the included angle between the connection of the edge of the upper surface of the first wire layer and the edge of the lower surface of the second wire layer and the upper surface of the first wire layer

Gamma is the included angle between the edge of the lower surface of the first conducting wire layer and the edge of the lower surface of the second conducting wire layer and the upper surface of the substrate

Detailed Description

The following disclosure provides many different embodiments for implementing different features of the disclosure. The following disclosure describes specific examples of various components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the embodiments of the present disclosure describe a first feature formed on or over a second feature, it may include embodiments in which the first feature is in direct contact with the second feature, or may include embodiments in which additional features are formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact.

It is to be understood that additional operational steps may be performed before, during, or after the methods, and that in other embodiments of the methods, some of the operational steps may be replaced or omitted.

Further, spatially relative terms, such as "below" …, "" below, "" lower, "" above "…," "upper," "higher," and the like, may be used herein to facilitate description of the relationship of one component(s) or feature(s) to another component(s) or feature(s) in the drawings, including different orientations of the device in use or operation, and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 45 degrees or other orientations), the spatially relative descriptors used herein interpreted in terms of the turned orientation. In some embodiments of the disclosure, terms such as "connected," "interconnected," and the like, with respect to joining, connecting, and the like, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, unless otherwise specified, with other structures being disposed between the two structures. And the term coupled, connected, may also include situations where both structures are movable, or where both structures are fixed.

In the specification, the terms "about", "approximately", "substantially" and "substantially" generally refer to a range where a characteristic value is within plus or minus 10%, or within plus or minus 5%, or within plus or minus 3%, or within plus or minus 2%, or within plus or minus 1%, or within plus or minus 0.5% of a given value.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one component, region, layer or section from another component, region, layer or section. Thus, a first component, region, layer or section discussed below could be termed a second component, region, layer or section without departing from the techniques of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be appreciated that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The electronic device of the present disclosure may include a display apparatus, a backlight device, an antenna device, a sensing device, or a stitching device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous type display device or a self-luminous type display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat energy or ultrasonic waves, but is not limited thereto. The electronic components may include passive components and active components such as capacitors, resistors, inductors, diodes, transistors, and the like. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include an organic light emitting diode or an inorganic light emitting diode. The light emitting diode may be, for example, but not limited to, an Organic LIGHT EMITTING Diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED. The splicing device can be, for example, a display splicing device or an antenna splicing device, but is not limited to this. It should be noted that the electronic device may be any combination of the foregoing, but is not limited thereto.

Referring to fig. 1-3, an electronic device 10 is provided according to an embodiment of the disclosure. Fig. 1 is a top view of an electronic device 10. Fig. 2 is a top view (enlarged view) of a partial area 10a of the electronic device 10. Fig. 3 is a top view (enlarged view) of a partial region 10b of the electronic device 10.

As shown in fig. 1, the electronic device 10 includes an active region 12 and a non-active region 14, and the non-active region 14 is adjacent to the active region 12. The active region 12 is a region for displaying images. Inactive region 14 includes a circuit protection region 16, a fan-out (fanout) region 18, and a bonding (bonding) region 20. The circuit protection region 16 is a region where circuit protection devices are disposed. The fanout area 18 is the area where the wires fan out. The bonding region 20 is a region to be bonded to, for example, an external circuit board or an integrated circuit. The circuit protection region 16 is disposed between the active region 12 and the fan-out region 18. The fan-out region 18 is disposed between the active region 12 and the bonding region 20. The frame 22 surrounds the active region 12, and a portion of the frame 22 is disposed in the fan-out region 18. An alignment layer (not shown) covers the active region 12, is located under the frame glue 22, and has a boundary located in the fan-out region 18. The detailed structure of the partial region 10a of the electronic device 10 is further described below with reference to fig. 2. The partial region 10a of the electronic device 10 includes a portion of the active region 12, the circuit protection region 16, the fan-out region 18, and the bonding region 20.

As shown in fig. 2, in a partial region 10a of the electronic device 10, a portion of the sealant 22 is disposed in the fan-out region 18. Notably, the bonding region 20 includes an integrated circuit 24, anisotropic conductive adhesive (anisotropic conductive film, ACF) 26, and finger-like bonding structures 28 that are bonded to, for example, a flexible circuit board (FPC). The detailed structure of the partial region 10b of the electronic device 10 is further described below with reference to fig. 3. The partial region 10b of the electronic device 10 includes a portion of the active region 12, the circuit protection region 16, and the fan-out region 18, wherein the active region 12 includes a Thin Film Transistor (TFT) 31.

As shown in fig. 3, in a partial region 10b of the electronic device 10, the circuit protection region 16 includes a dummy thin film transistor (dummy TFT) 30 and an electrostatic discharge (electrostatic discharge, ESD) protection device 32. The dummy TFT 30 and/or the ESD (electrostatic discharge, ESD) protection device 32 can reduce the possibility of damage to the electronic device due to static electricity. In addition, the fan-out region 18 presents a fan-out of a plurality of wires 34, which plurality of wires 34 may include a plurality of wire layers. In some embodiments, the dummy thin film transistor 30 is disposed adjacent to the thin film transistor 31, and a length A1 of the thin film transistor 31 in a direction Y is greater than a length A1' of the dummy thin film transistor 30 in the direction Y. In addition, the first connection portion connects two adjacent thin film transistors 31, the second connection portion connects two adjacent dummy thin film transistors 30, and a length A2 of the first connection portion in a direction Y is smaller than a length A2' of the second connection portion in the direction Y.

Referring to fig. 4, an electronic device 10 is provided according to an embodiment of the present disclosure. Fig. 4 is a schematic cross-sectional view of the electronic device 10.

As shown in fig. 4, the electronic device 10 includes a substrate 11, a first conductive line layer 36, a second conductive line layer 38, a first insulating layer 40, and an alignment layer (ALIGNMENT LAYER) 42. The substrate 11 has an active region (not shown) and a non-active region 14, and the non-active region 14 is adjacent to the active region. In some embodiments, the substrate 11 may comprise a rigid substrate, such as a glass substrate, but the disclosure is not limited thereto, and other suitable rigid substrate materials are suitable for the disclosure. In some embodiments, the substrate 11 may comprise a flexible substrate, such as a Polyimide (PI) substrate, but the disclosure is not limited thereto, and other suitable flexible substrate materials are also suitable for the disclosure.

In fig. 4, the first conductive line layer 36 is disposed on the substrate 11 and is located in the inactive region 14 of the substrate 11. The second conductive line layer 38 is disposed on the first conductive line layer 36. In some embodiments, the first and second wire layers 36 and 38 may include molybdenum, aluminum, copper, titanium, or combinations thereof, for example, molybdenum/aluminum/molybdenum, titanium/aluminum/titanium, or titanium/aluminum/molybdenum, although the disclosure is not limited thereto, and other suitable metallic conductive materials are suitable for the disclosure. In some embodiments, the width w1 of the first wire layer 36 is not equal to the width w2 of the second wire layer 38, e.g., the width w1 of the first wire layer 36 is greater than the width w2 of the second wire layer 38. In some embodiments, the width (w 1, w 2) of the wire layers (36, 38) may be the width of the bottom of the wire layers. It is noted that the first conductive line layer 36 has a first edge 36e1, the second conductive line layer 38 has a second edge 38e2, the second edge 38e2 is adjacent to the first edge 36e1, and the first edge 36e1 of the first conductive line layer 36 and the second edge 38e2 of the second conductive line layer 38 are separated by a first distance d1 in the horizontal direction h, more specifically, the first distance d1 is the distance between the bottom edges of the two conductive line layers. In some embodiments, the first edge 36e1 of the first wire layer 36 is spaced apart from the second edge 38e2 of the second wire layer 38 by a first distance d1 of approximately 0.3 microns to 1.5 microns.

It should be noted that the second conductive line layer 38 is not limited to the same process or the same material, i.e., the second conductive line layer 38 is located above the first conductive line layer 36 or the second conductive line layer 38 is formed after the first conductive line layer 36.

In fig. 4, a first insulating layer 40 is disposed on the second wire layer 38. The second insulating layer 44 is disposed between the first conductive line layer 36 and the second conductive line layer 38. In some embodiments, the first insulating layer 40 and the second insulating layer 44 may include an organic insulating material or an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but the disclosure is not limited thereto, and other suitable organic or inorganic insulating materials are suitable for the disclosure. In some embodiments, the first insulating layer 40 includes a mesa portion 40a, a first sidewall portion 40s1, and a second sidewall portion 40s2, and the mesa portion 40a connects the first sidewall portion 40s1 and the second sidewall portion 40s2, respectively. It is noted that the first sidewall 40s1 of the first insulating layer 40 covers the first edge 36e1 of the first conductive line layer 36 and the second edge 38e2 of the second conductive line layer 38, and forms a stepped structure.

In some embodiments, since the width w1 of the first conductive line layer 36 is not equal to the width w2 of the second conductive line layer 38 (e.g., the width w1 of the first conductive line layer 36 is greater than the width w2 of the second conductive line layer 38), the first sidewall 40s1 of the first insulating layer 40 is formed in a stepped shape, which can increase the resistance to the flow of the alignment layer 42 in the structure. However, when the difference between the width w1 of the first conductive line layer 36 and the width w2 of the second conductive line layer 38 is too small (e.g., the first distance d1 is less than about 0.3 μm), the first sidewall portion 40s1 of the first insulating layer 40 cannot generate a stepped structure, which is difficult to provide sufficient resistance or/and surface area for the alignment layer 42 to adhere to, and reduces the risk of the alignment layer 42 flowing to the bonding area. However, when the difference between the width w1 of the first conductive line layer 36 and the width w2 of the second conductive line layer 38 is too large (for example, the first distance d1 is greater than about 1.5 μm), one of the two cases can be further distinguished, and if the width w1 of the first conductive line layer 36 is fixed at this time, the width w2 of the second conductive line layer 38 will be small, which will greatly increase the impedance of the second conductive line layer 38. Secondly, if the width w2 of the second conductive line layer 38 is fixed at this time, the width w1 of the first conductive line layer 36 is very large, so that the gap penetrated by the UV light (the gap between the plurality of conductive lines 34) is too small, the penetration of the UV light is reduced, the curing effect of the frame glue is further affected by the irradiation of the UV light.

In some embodiments, the width w1 of the first wire layer 36 is about 2.59 microns, the width w2 of the second wire layer 38 is about 2.00 microns, and the first distance d1 is about 0.61 microns. In some embodiments, the width w1 of the first wire layer 36 is about 3.13 microns, the width w2 of the second wire layer 38 is about 2.08 microns, and the first distance d1 is about 0.89 microns. In some embodiments, the width w1 of the first wire layer 36 is about 2.87 microns, the width w2 of the second wire layer 38 is about 2.15 microns, and the first distance d1 is about 0.57 microns. In some embodiments, the width w1 of the first wire layer 36 is about 2.74 microns, the width w2 of the second wire layer 38 is about 2.14 microns, and the first distance d1 is about 0.74 microns. In some embodiments, the width w1 of the first wire layer 36 is about 3.29 microns, the width w2 of the second wire layer 38 is about 3.00 microns, and the first distance d1 is about 0.48 microns.

In fig. 4, an alignment layer 42 is disposed on the first insulating layer 40. In some embodiments, the alignment layer 42 may include Polyimide (PI), but the disclosure is not limited thereto, and other suitable alignment materials are also suitable for guiding the alignment direction of the liquid crystal molecules.

In fig. 4, the electronic device 10 includes a second insulating layer 44 disposed between the first conductive line layer 36 and the second conductive line layer 38. In some embodiments, the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 is about 0.3 to 1.1. In some embodiments, since the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 is between a suitable value (e.g., about 0.3 to 1.1), the first insulating layer 40 forms a stepped structure, providing enough surface area for the alignment layer 42 to adhere to the surface of the first insulating layer 40. However, when the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 is too large (e.g., greater than about 1.1), the first insulating layer 40 will not be able to create a stepped structure, it is difficult to provide sufficient resistance or/and it is difficult to provide sufficient surface area for the alignment layer 42 to adhere. When the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 is too small (e.g., less than about 0.3), it can be further divided into two cases, one of which is that if the thickness t1 of the second insulating layer 44 is too thin, the parasitic capacitance between the first conductive line layer 36 and the second conductive line layer 38 will become larger, and the resistance-capacitance load (RC loading) of the trace will be indirectly increased. If the first distance d1 is too large, the width w2 of the second conductive layer 38 will be small, which will cause the impedance of the second conductive layer 38 to be greatly increased, or the width w1 of the first conductive layer 36 will be large, which will reduce the curing effect of the sealant due to UV light irradiation.

In some embodiments, the angle between the line c of the edge 36e1 of the upper surface 36a of the first conductive line layer 36 and the edge 38e2 of the lower surface 38b of the second conductive line layer 38 and the upper surface 36a of the first conductive line layer 36 is defined as β. In some embodiments, the included angle β is between about 10 degrees and 50 degrees. In some embodiments, the included angle β is between about 10 degrees and about 50 degrees, such that the first insulating layer 40 forms a stepped structure, providing sufficient surface area for the alignment layer 42 to adhere to the surface of the first insulating layer 40. However, when the included angle β is too large (e.g., greater than 50 degrees), it will be difficult for the first insulating layer 40 to create a stepped structure, and it will be difficult to provide sufficient surface area for the alignment layer 42 to adhere. When the included angle β is too small (e.g., less than 10 degrees), it can be further divided into two cases, one of which is that if the thickness t1 of the second insulating layer 44 is too thin, the parasitic capacitance between the first conductive line layer 36 and the second conductive line layer 38 will become large, and the resistance-capacitance load (RC loading) of the trace will be indirectly increased. If the first distance d1 is too large, the width w2 of the second conductive layer 38 will be small, which will cause the impedance of the second conductive layer 38 to be greatly increased, or the width w1 of the first conductive layer 36 will be large, which will reduce the curing effect of the sealant due to UV light irradiation.

Referring to fig. 5, an electronic device 10 is provided according to an embodiment of the present disclosure. Fig. 5 is a schematic cross-sectional view of the electronic device 10.

As shown in fig. 5, the electronic device 10 includes a substrate 11, a first conductive line layer 36, a second conductive line layer 38, a first insulating layer 40, and an alignment layer (ALIGNMENT LAYER) 42. The substrate 11 has an active region (not shown) and a non-active region 14, and the non-active region 14 is adjacent to the active region. In some embodiments, the first conductive line layer 36 is disposed on the substrate 11 and is located in the inactive region 14 of the substrate 11. The second conductive line layer 38 is disposed on the first conductive line layer 36. In some embodiments, the first and second wire layers 36 and 38 may include molybdenum, aluminum, copper, titanium, or combinations thereof, for example, molybdenum/aluminum/molybdenum, titanium/aluminum/titanium, or titanium/aluminum/molybdenum, although the disclosure is not limited thereto, and other suitable metallic conductive materials are suitable for the disclosure. In some embodiments, first wire layer 36 includes a first portion 36 'and a second portion 36", second wire layer 38 includes a first portion 38' and a second portion 38", wherein first portion 36 'of first wire layer 36 overlaps first portion 38' of second wire layer 38, second portion 36 "of first wire layer 36 does not overlap second wire layer 38, and second portion 38" of second wire layer 38 does not overlap first wire layer 36, i.e., a portion of first wire layer 36 does not overlap second wire layer 38, and a portion of second wire layer 38 does not overlap first wire layer 36. In some embodiments, the width w1 of the first wire layer 36 is equal to the width w2 of the second wire layer 38. In some embodiments, the width w1 of the first conductive line layer 36 is not equal to the width w2 of the second conductive line layer 38, for example, the width w1 of the first conductive line layer 36 is greater than the width w2 of the second conductive line layer 38, or the width w1 of the first conductive line layer 36 is less than the width w2 of the second conductive line layer 38. It is noted that the first conductive line layer 36 has a first edge 36e1, the second conductive line layer 38 has a second edge 38e2, the second edge 38e2 is adjacent to the first edge 36e1, and the first edge 36e1 of the first conductive line layer 36 is separated from the second edge 38e2 of the second conductive line layer 38 by a first distance d1 in the horizontal direction h. The first conductive line layer 36 has a third edge 36e3, the second conductive line layer 38 has a fourth edge 38e4 with respect to the first edge 36e1, the fourth edge 38e4 is adjacent to the third edge 36e3, and the third edge 36e3 of the first conductive line layer 36 is spaced apart from the fourth edge 38e4 of the second conductive line layer 38 in the horizontal direction h by a second distance d2. In some embodiments, the first edge 36e1 of the first wire layer 36 is spaced apart from the second edge 38e2 of the second wire layer 38 by a first distance d1 of approximately 0.3 microns to 1.5 microns. In some embodiments, the third edge 36e3 of the first wire layer 36 is spaced apart from the fourth edge 38e4 of the second wire layer 38 by a second distance d2 of approximately 0.3 microns to 1.5 microns.

In fig. 5, a first insulating layer 40 is disposed on the second wire layer 38. The second insulating layer 44 is disposed between the first conductive line layer 36 and the second conductive line layer 38. In some embodiments, the first insulating layer 40 and the second insulating layer 44 may include an organic insulating material or an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but the disclosure is not limited thereto, and other suitable organic or inorganic insulating materials are suitable for the disclosure. In some embodiments, the first insulating layer 40 includes a mesa portion 40a, a first sidewall portion 40s1, and a second sidewall portion 40s2, and the mesa portion 40a connects the first sidewall portion 40s1 and the second sidewall portion 40s2, respectively. It is noted that the first sidewall portion 40s1 of the first insulating layer 40 covers the first edge 36e1 of the first conductive line layer 36 and the second edge 38e2 of the second conductive line layer 38, and forms the first step-like structure 46. The second sidewall portion 40s2 of the first insulating layer 40 covers the fourth edge 38e4 of the second wire layer 38, and forms a second stepped structure 48.

In some embodiments, since a portion of the first conductive line layer 36 is not overlapped with the second conductive line layer 38 and a portion of the second conductive line layer 38 is not overlapped with the first conductive line layer 36, the first sidewall portion 40s1 and the second sidewall portion 40s2 of the first insulating layer 40 are formed in a stepped shape, so that the resistance to the flow of the alignment layer 42 in the structure can be further improved. However, when the width of the non-overlapping region of the first wire layer 36 and the second wire layer 38 is too small (e.g., the first distance d1 or the second distance d2 is less than about 0.3 μm), it is difficult for the first sidewall portion 40s1 or the second sidewall portion 40s2 of the first insulating layer 40 to generate a stepped structure, and it is difficult to provide sufficient resistance and surface area for the alignment layer 42 to adhere. However, when the width of the non-overlapped area of the first conductive line layer 36 and the second conductive line layer 38 is too large (for example, the first distance d1 or the second distance d2 is greater than about 1.5 μm), it can be further divided into two cases, one of which is that if the width w1 of the first conductive line layer 36 is fixed at this time, the width w2 of the second conductive line layer 38 is small, which will greatly increase the impedance of the second conductive line layer 38. Secondly, if the width w2 of the second conductive layer 38 is fixed at this time, the width w1 of the first conductive layer 36 will be very large, resulting in too high density of the conductive layers in the fan-out area, so that the opening for curing the sealant is too small, and the UV light is blocked, thereby affecting the curing effect of the sealant.

In some embodiments, the width w1 of the first wire layer 36 is about 2.63 microns, the width w2 of the second wire layer 38 is about 2.02 microns, the first distance d1 is about 1.15 microns, and the second distance d2 is about 0.53 microns. In some embodiments, the width w1 of the first wire layer 36 is about 2.93 microns, the width w2 of the second wire layer 38 is about 2.12 microns, the first distance d1 is about 1.24 microns, and the second distance d2 is about 0.41 microns. In some embodiments, the width w1 of the first wire layer 36 is about 2.04 microns, the width w2 of the second wire layer 38 is about 2.11 microns, the first distance d1 is about 0.47 microns, and the second distance d2 is about 0.53 microns. In some embodiments, the width w1 of the first wire layer 36 is about 2.30 microns, the width w2 of the second wire layer 38 is about 2.52 microns, the first distance d1 is about 0.39 microns, and the second distance d2 is about 0.62 microns. In some embodiments, the width w1 of the first wire layer 36 is about 2.09 microns, the width w2 of the second wire layer 38 is about 2.33 microns, the first distance d1 is about 0.43 microns, and the second distance d2 is about 0.67 microns.

In fig. 5, the electronic device 10 further includes a second insulating layer 44 disposed between the first conductive line layer 36 and the second conductive line layer 38. In some embodiments, the second insulating layer 44 may include an organic insulating material or an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but the disclosure is not limited thereto, and other suitable organic or inorganic insulating materials are suitable for the disclosure.

In some embodiments, the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 is about 0.3 to 1.1. The ratio of the thickness t1 of the second insulating layer 44 to the second distance d2 is about 0.3 to 1.1. In some embodiments, since the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 and the second distance d2 is between a suitable value (e.g., about 0.3 to 1.1), the first insulating layer 40 forms a stepped structure, providing enough surface area for the alignment layer 42 to adhere to the surface of the first insulating layer 40. However, when the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 or the second distance d2 is too large (e.g., greater than about 1.1), the first insulating layer 40 will not produce a stepped structure, it is difficult to provide sufficient resistance or/and it is difficult to provide sufficient surface area for the alignment layer 42 to adhere. When the ratio of the thickness t1 of the second insulating layer 44 to the first distance d1 or the second distance d2 is too small (e.g., less than about 0.3), it can be further divided into two cases, one of which is that if the thickness t1 of the second insulating layer 44 is too small, the parasitic capacitance between the first conductive line layer 36 and the second conductive line layer 38 will become larger, and the resistance-capacitance load (RC loading) of the trace will be indirectly increased. If the first distance d1 or the second distance d2 is too large, the width w2 of the second conductive layer 38 will be small, which will cause the impedance of the second conductive layer 38 to be greatly increased, or the width w1 of the first conductive layer 36 will be large, which reduces the curing effect of the sealant due to UV light irradiation, thereby affecting the curing effect of the sealant.

In some embodiments, the angle between the line c1 of the edge 36e1 of the upper surface 36a of the first conductive line layer 36 and the edge 38e2 of the lower surface 38b of the second conductive line layer 38 and the upper surface 36a of the first conductive line layer 36 is defined as β. In some embodiments, the angle between the line c2 of the edge 36e3 of the lower surface 36b of the first conductive line layer 36 and the edge 38e4 of the lower surface 38b of the second conductive line layer 38 and the upper surface 11a of the substrate 11 is defined as γ. In some embodiments, angle β is approximately 10 to 50 degrees and angle γ is approximately 10 to 50 degrees. In some embodiments, the first insulating layer 40 is formed in a stepped configuration due to the included angle β or γ ranging from 10 degrees to 50 degrees, providing sufficient surface area for the alignment layer 42 to adhere to the surface of the first insulating layer 40. However, when the included angle β or γ is too large (e.g., greater than 50 degrees), it will be difficult for the first insulating layer 40 to produce a stepped structure, and it will be difficult to provide sufficient surface area for the alignment layer 42 to adhere. When the included angle β or γ is too small (e.g., less than 10 degrees), it can be further divided into two cases, one of which is that if the thickness t1 of the second insulating layer 44 is too thin, the parasitic capacitance between the first conductive line layer 36 and the second conductive line layer 38 will become large, and the resistance-capacitance load (RC loading) of the trace will be indirectly increased. If the first distance d1 or the second distance d2 is too large, the width w2 of the second conductive layer 38 will be small, which will cause the impedance of the second conductive layer 38 to be greatly increased, or the width w1 of the first conductive layer 36 will be large, which reduces the curing effect of the sealant due to UV light irradiation, thereby affecting the curing effect of the sealant.

Referring to fig. 6, an electronic device 100 is provided according to an embodiment of the disclosure. Fig. 6 is a schematic cross-sectional view of the electronic device 100.

As shown in fig. 6, in the electronic device 100, similar to the parts disclosed in fig. 4, a detailed description is omitted herein. The electronic device 100 includes a frame glue 22 disposed on the electronic device 10 shown in fig. 4. In some embodiments, the frame gel 22 includes a plurality of balls 50. In some embodiments, the material of the ball 50 may include silicon dioxide, but the disclosure is not limited thereto, and other materials suitable as a sealant filler are also suitable for the disclosure. In fig. 6, the first sidewall 40s1 of the first insulating layer 40 includes a bottom 40s1a and a step 40s1b, and the alignment layer 42 is stopped on the step 40s1 b. In some embodiments, regarding the thickness difference of the alignment layer 42 everywhere, for example, the thickness L1 of the alignment layer 42 on the bottom 40s1a of the first sidewall 40s1 of the first insulating layer 40 is greater than the thickness L2 thereof on the step 40s1 b.

Referring to fig. 7, an electronic device 100 is provided according to an embodiment of the disclosure. Fig. 7 is a schematic cross-sectional view of the electronic device 100.

As shown in fig. 7, in the electronic device 100, similar to the parts disclosed in fig. 5, a detailed description is omitted herein. The electronic device 100 includes a frame glue 22 disposed on the electronic device 10 shown in fig. 5. In some embodiments, the frame gel 22 includes a plurality of balls 50. In some embodiments, the material of the ball 50 may include silicon dioxide, but the disclosure is not limited thereto, and other materials suitable as a sealant filler are also suitable for the disclosure. In fig. 7, the second sidewall 40s2 of the first insulating layer 40 includes a bottom 40s2a and a step 40s2b, and the alignment layer 42 is stopped on the mesa 40a of the first insulating layer 40. In some embodiments, regarding the thickness difference of the alignment layer 42 everywhere, for example, the thickness L1 of the alignment layer 42 on the bottom 40s2a of the second sidewall portion 40s2 of the first insulating layer 40 is greater than the thickness L2 thereof on the step portion 40s2b, and the thickness L2 of the alignment layer 42 on the step portion 40s2b is greater than the thickness L3 thereof on the mesa portion 40 a.

Since the alignment layer material (for example, polyimide (PI)) still has fluidity after coating, in order to reduce the influence of the alignment layer material on the electrical transmission of the bonding area, the present disclosure provides a single-sided or double-sided stepped topography by using the arrangement mode of misplacement and stacking of the upper and lower metal wire layers located in the fan-out area in the electronic device, so as to increase the flow resistance of the alignment layer material in the structure, and increase the attachable surface area of the alignment layer material during flowing, so as to reduce the flowing distance of the alignment layer material towards the direction of the bonding area, and block the alignment layer material in the fan-out area.

According to the structural design of the metal wire layer in the fan-out area, the alignment layer material is blocked in the fan-out area, so that the alignment layer material is reduced from flowing to the bonding pad in the bonding area, and good electrical transmission is maintained.

The components of some of the embodiments described above so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the conception and specific embodiment disclosed as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the present disclosure is defined by the appended claims. In addition, while the disclosure has been disclosed in the context of several embodiments, it is not intended to limit the disclosure.

Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single embodiment of the disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussion of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in view of the description herein, that the disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the disclosure.

Claims

1. An electronic device, comprising:

A substrate having an active region and a non-active region, the non-active region being adjacent to the active region;

the first conducting wire layer is arranged in the non-active area;

The second wire layer is arranged on the first wire layer;

The first insulating layer is arranged on the second wire layer; and

An alignment layer disposed on the first insulating layer,

In a cross-sectional view of the electronic device, the first conductive line layer has a first edge, the second conductive line layer has a second edge, the first edge and the second edge are horizontally spaced apart by a first distance, and the first insulating layer has a first sidewall portion covering the first edge and the second edge and forming a stepped structure.

2. The electronic device of claim 1, wherein the first distance is between 0.3 microns and 1.5 microns.

3. The electronic device of claim 1, wherein the non-active region comprises a fan-out region and a bonding region, the fan-out region is disposed between the active region and the bonding region, and a boundary of the alignment layer is located in the fan-out region.

4. The electronic device of claim 1, wherein the width of the first conductive line layer is greater than the width of the second conductive line layer in the cross-sectional view of the electronic device.

5. The electronic device of claim 1, wherein the first conductive line layer has a third edge, the second conductive line layer has a fourth edge opposite the first edge, adjacent to the third edge, and the third edge is spaced apart from the fourth edge by a second distance in the horizontal direction.

6. The electronic device of claim 5, wherein the second distance is between 0.3 microns and 1.5 microns.

7. The electronic device of claim 5, wherein a portion of the first conductive line layer does not overlap the second conductive line layer, and a portion of the second conductive line layer does not overlap the first conductive line layer.

8. The electronic device of claim 1, further comprising a second insulating layer disposed between the first conductive line layer and the second conductive line layer, wherein a first ratio of a thickness of the second insulating layer to the first distance is between 0.3 and 1.1.

9. The electronic device of claim 8, wherein the first conductive line layer has a third edge, the second conductive line layer has a fourth edge opposite the first edge, adjacent to the third edge, the third edge and the fourth edge are separated by a second distance in the horizontal direction, and a second ratio of a thickness of the second insulating layer to the second distance is between 0.3 and 1.1.