CN117935879A - Memristor reading method and computer readable medium - Google Patents
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Abstract
A memristor reading method and a computer readable medium can avoid the reduction of reading speed and margin, reduce the time consumption of the whole circuit to complete training, improve the circuit stability and reduce the circuit design cost. The memristor reading method is used for reading data stored in a resistance change register during on-chip training, and the resistance change register comprises: a memristor having one end connected to the bit line; and a selection transistor having a drain connected to the other end of the memristor and a source connected to a source line, the memristor reading method comprising: a step of fixing the bit line to a high level; a step of selecting the resistance change register to be read by setting the source line to a low level; and reading the reverse current on the bit line to realize reverse reading, wherein the magnitude of the reverse current represents the data stored in the resistance change register.
Description
Technical Field
The present invention relates to memristor reading methods, and more particularly, to memristor reading methods usable for on-chip training in the field of memory technology, and computer readable media storing programs that result in execution of the memristor reading methods.
Background
With the advent of the big data age, process nodes have been shrinking, and memory device duty cycles have been increasing. For volatile memories, in order to keep the stored data from being lost, it is still necessary to provide the memory with a power signal in the event of a power failure, which results in an additional large cell leakage power consumption. For this reason, a scheme of storing data using RRAM instead of a conventional volatile memory has been proposed.
RRAM (RESISTIVE RANDOM ACCESS MEMORY, memristor) is a novel nonvolatile memory based on the working principle of memristor, is a two-terminal device, and has the working mechanism that the low-high resistance state is shown by utilizing the formation and fracture of conductive filaments. Different operation modes of the memristor can be realized by adding different voltages at two ends of the memristor. Common operations are write operations and read operations.
When the memristor is subjected to writing operation, the memristor can be converted between different states by applying voltages with different polarities on two polar plates of the memristor. The resistance change layer is called a RESET operation or an erase operation (RESET) from a low resistance state to a high resistance state, and is called a SET operation or a program operation (SET) from a high resistance state to a low resistance state. Typically, as-fabricated RRAM devices have few defects, their initial state exhibits a high resistance state (HRS, HIGH RESISTANCE STATE). A high voltage operation is required to activate the RRAM before the RRAM is programmed normally, this operation is called a Forming operation (Forming). When the memristor is subjected to read operation, when the voltage difference between the upper polar plate and the lower polar plate of the memristor is a positive value, the storage value of the storage unit can be judged to be in a high-resistance state or a low-resistance state at the moment according to the read current.
The memristor has the advantages of simple structure, compatibility with the existing CMOS technology, high microminiaturization, multi-value storage, easiness in 3D integration and the like. As a non-volatile memory, memristors can still hold data after power failure, and thus have small cell leakage power consumption.
In addition, in the context of existing in-memory computation, since there is a non-ideal hardware configuration, in order to obtain the full value of the neural network taking the non-ideal circuit into account, to improve the robustness to the non-ideal hardware, it is necessary to perform on-chip training on the hardware using the neural network accelerator composed of memristors. In order to further improve the throughput rate of on-chip training and improve the energy efficiency area efficiency on hardware, the data stored in the memristor is read in a bidirectional reading mode comprising forward reading and reverse reading.
Disclosure of Invention
The invention aims to solve the technical problems
Taking a 1T1R resistive switching register as an example, a problem that exists in the reverse reading will be discussed. Fig. 4 is a schematic diagram showing a voltage operation of a prior art resistance change register at the time of reverse reading. As shown in fig. 4, the 1T1R resistance variable register includes a memristor RRAM2 and a MOS transistor Q2, which is gated by a high level voltage V WL = VDD on the word line WL. According to the conventional reverse reading method, for the selected resistive random access register, a low level voltage V BL =0v is required to be applied to the bit line BL, and a high level voltage V SL＝VREAD is required to be applied to the source line SL. At this time, the difference between the voltages applied to the bit line BL and the source line SL is larger than the threshold voltage of the MOS transistor Q3, so that a current determined by the state of the RRAM3 is generated on the bit line BL. If RRAM3 is in a high resistance state, corresponding to 0, then the current on bit line BL is low, corresponding to 0. Conversely, if RRAM3 is in a low resistance state, i.e., corresponds to 1, then the current on bit line BL is high, i.e., the result corresponds to 1.
However, with the conventional reverse reading method, when the level is raised on the source line SL, since no other components are blocked between the source line SL and the MOS transistor Q3, the source of the MOS transistor Q3 is directly connected to the high level. The voltage difference between the source and the drain of the MOS transistor Q3 is not more than VG-V th at maximum, wherein VG represents the gate voltage and V th represents the threshold voltage of the MOS transistor, which is influenced by the inherent characteristics of the MOS transistor. Therefore, if the source is directly connected with the high level, the switching threshold of the MOS transistor Q3 is changed, and thus the reading speed and margin of the whole resistance change register are affected.
Fig. 5 is a schematic diagram for comparing the margin and speed of the prior art resistive random access memory read method in forward and reverse reading. As shown in fig. 5, for the conventional reverse read method in the prior art, the reverse read speed is about 33% of the forward read speed, and the reverse read margin is about 80% of the forward read margin, so that the time required for the whole circuit to complete on-chip training is increased, and the stability of the circuit is reduced. In addition, the design difficulty of a circuit for processing the read data is increased, and the design cost is increased.
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a memristor reading method and a computer readable medium, which can avoid a decrease in reading speed and margin, reduce the time required for the whole circuit to complete training, improve circuit stability, and reduce circuit design cost.
Technical proposal for solving the technical problems
In order to solve the above problems, a memristor reading method according to a first aspect of the present invention is used for reading data stored in a resistance change register during on-chip training, the resistance change register including: a memristor having one end connected to the bit line; and a selection transistor having a drain connected to the other end of the memristor and a source connected to a source line, the memristor reading method comprising: a step of fixing the bit line to a high level; a step of selecting the resistance change register to be read by setting the source line to a low level; and reading the reverse current on the bit line to realize reverse reading, wherein the magnitude of the reverse current represents the data stored in the resistance change register.
Optionally, the plurality of the resistive registers form an array, bit lines of the resistive registers of each row of the array are collected on a bit line bus of the row, source lines of the resistive registers of each column are collected on a source line bus of the column, and the step of fixing the bit lines to a high level includes: the step of fixing the bit line bus of each row to a high level, the step of selecting the resistance change register to be read by setting the source line to a low level includes: a step of sequentially inputting levels corresponding to elements in a first vector to the source line bus lines of the columns, the first vector being composed of 0 representing selection and 1 representing non-selection, the step of reading the reverse current on the bit line to realize reverse reading comprising: and reading the total reverse current on the bit line bus of each row to realize reverse reading, wherein the total reverse current of each row represents the sum of the products of the first vector and the data stored in the resistance change register of the row.
Optionally, the input terminal of the bit line bus of each row is connected to a register via an input driver, and the input terminal of the source line bus of each column is connected to the register via the input driver, the step of fixing the bit line bus of each row to a high level includes: transmitting a high level from the register to an input terminal of the bit line bus of each row via the input driver, the step of sequentially inputting a level corresponding to each element in a first vector to the source line bus of each column comprising: the first vector is sent from the register via the input driver to the input of the source line bus of each column.
Optionally, the output end of the bit line bus of each row is connected to a shift adder via an analog-to-digital converter, and the step of reading the total reverse current on the bit line bus of each row to achieve reverse reading includes: transmitting a digital signal corresponding to the total reverse current from an output of the bit line bus of each row to the shift adder via the analog-to-digital converter; and calculating, by the shift adder, a convolution of the first vector of 1 bit and multi-bit data stored in a plurality of the resistance change registers based on the digital signal.
Optionally, the memristor reading method further includes: a step of fixing the source line to a low level; a step of selecting the resistance change register to be read by setting the bit line to a high level; and reading the forward current on the source line to realize forward reading, wherein the magnitude of the forward current represents the data stored in the resistance change register.
Optionally, the plurality of the resistive registers form an array, bit lines of the resistive registers of each row of the array are collected on a bit line bus of the row, source lines of the resistive registers of each column are collected on a source line bus of the column, and the step of fixing the source lines to be low level includes: the step of fixing the source line bus of each column to a low level, the step of selecting the resistance change register to be read by setting the bit line to a high level includes: a step of sequentially inputting levels corresponding to elements in a second vector to the bit line bus lines of each row, the second vector being composed of 1 representing selection and 0 representing non-selection, the step of reading the forward current on the source line to achieve forward reading comprising: and reading the total forward current on the source line bus of each column to realize forward reading, wherein the magnitude of the total forward current of each column represents the sum of the products of the second vector and the data stored in the resistance change register of the column.
Optionally, the input terminal of the source line bus of each column is connected to a register via an input driver, and the input terminal of the bit line bus of each row is connected to the register via the input driver, the step of fixing the source line bus of each column to a low level includes: transmitting a low level from the register to an input terminal of the source line bus of each column via the input driver, the step of sequentially inputting a level corresponding to each element in a second vector to the bit line bus of each row comprising: the second vector is sent from the register via the input driver to the input of the bit line bus of each row.
Optionally, the output end of the source line bus of each column is connected to a shift adder via an analog-to-digital converter, and the step of reading the total forward current on the source line bus of each column to achieve forward reading includes: transmitting a digital signal corresponding to the total forward current from an output of the source line bus of each column to the shift adder via the analog-to-digital converter; and calculating, by the shift adder, a convolution of the second vector of 1 bit with multi-bit data stored in a plurality of the resistance change registers based on the digital signal.
Optionally, the gate of the selection transistor is connected to a word line, and the memristor reading method further includes: and a step of gating the resistance change register by setting the word line to a high level.
Optionally, a plurality of the variable resistance registers form an array, word lines of the variable resistance registers of each row of the array are collected on a word line bus of the row, and the step of gating the variable resistance registers by setting the word lines to a high level includes: and a step of sequentially inputting levels corresponding to elements in a third vector to the word line bus lines of the rows, the third vector being composed of 1's indicating gating and 0's indicating non-gating.
Optionally, the input terminals of the word line buses of each row are connected to a register via an input driver, and the step of sequentially inputting the levels corresponding to each element in the third vector to the word line buses of each row includes: the third vector is sent from the register via the input driver to the input of the word line bus of each row.
In addition, in order to solve the above-described problems, a computer-readable medium according to a second aspect of the present invention stores a program for executing the memristor reading method according to the first aspect of the present invention.
Effects of the invention
According to the memristor reading method and the computer readable medium, the reduction of the reading speed and margin can be avoided, the time consumption for the whole circuit to complete training is reduced, the circuit stability is improved, and the circuit design cost is reduced.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the embodiments of the application. In the drawings:
Fig. 1A is a schematic diagram of a voltage operation of the resistive random access register according to embodiment 1 of the present invention in forward reading.
Fig. 1B is a schematic diagram of the voltage operation of the resistive random access register according to embodiment 1 of the present invention in the reverse reading.
Fig. 2A is a parameter table showing an arrangement mode of the memristor reading method according to embodiment 1 of the present invention in forward reading.
Fig. 2B is a parameter table showing a setting method of the memristor reading method according to embodiment 1 of the present invention in reverse reading.
Fig. 3 is a block diagram showing a configuration of a resistive register array system according to embodiment 2 of the present invention.
Fig. 4 is a schematic diagram showing a voltage operation of a prior art resistance change register at the time of reverse reading.
Fig. 5 is a schematic diagram for comparing the margin and speed of the prior art resistive random access memory read method in forward and reverse reading.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the detailed description described herein is merely for illustrating and explaining the embodiments of the present application, and is not intended to limit the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that, the technical solutions of the embodiments of the present application may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the embodiments, and when the technical solutions are contradictory or cannot be implemented, it should be considered that the combination of the technical solutions does not exist, and is not within the scope of protection required by the present application.
Embodiment 1
Fig. 1A is a schematic diagram of a voltage operation of the resistive random access register according to embodiment 1 in forward direction, fig. 1B is a schematic diagram of a voltage operation of the resistive random access register according to embodiment 1 in reverse direction, fig. 2A is a parameter table showing an installation mode of the memristor reading method according to embodiment 1 in forward direction, and fig. 2B is a parameter table showing an installation mode of the memristor reading method according to embodiment 1 in reverse direction.
In the present embodiment, a 1T1R resistance variable register is provided as an example of the resistance variable register, and the resistance variable register can be used for on-chip training. As shown in fig. 1A and 1B, the resistance variable register of 1T1R includes a memristor RRAM1 and a selection transistor Q1.
The memristor RRAM1 may employ a general memristor element, and weight data of, for example, 1bit may be stored therein in advance by a write operation, that is, the resistance value of the memristor RRAM1 may be changed to a low resistance state or a high resistance state corresponding to the weight data in advance by the write operation. As shown in fig. 1A and 1B, one end of the memristor RRAM1 is connected to a bit line BL of a resistance change register, and the other end thereof is connected to a gate of a selection transistor Q1 described later. When the resistive random access register of 1T1R is prepared through a flow sheet preparation process, after the selection transistor Q1 is finished, the memristor RRAM1 grows on the drain electrode of the selection transistor Q1 through a back-end process, so that the connection of the memristor RRAM1 and the selection transistor Q1 is finished.
The selection Transistor Q1 may be an N-type MOS Transistor (MOSFET: metal Oxide Semiconductor FIELD EFFECT transistors). As shown in fig. 1A and 1B, the drain of the selection transistor Q1 is connected to the other end of the memristor RRAM1, the source is connected to the source line SL of the resistance change register, and the gate is connected to the word line WL of the resistance change register.
The hardware configuration of the resistive random access register according to the present embodiment is as described above. When on-chip training is performed, in order to improve the data throughput rate and improve the energy efficiency area efficiency on hardware, a bidirectional reading mode is required. Next, a forward reading method and a reverse reading method in the bidirectional reading process according to the present embodiment will be described with reference to fig. 1A, 1B, 2A, and 2B, respectively.
As shown in fig. 1A and 2A, in the forward reading, first, the word line WL is set to a high level, for example, to a high level voltage VDD, thereby gating the resistance change register. Specifically, since the gate of the selection transistor Q1 is connected to the word line WL, when the high-level voltage VDD is inputted to the word line WL, the gate voltage of the selection transistor Q1 is higher than the threshold voltage, the MOS transistor is turned on, and the drain and the source thereof start to be turned on, so that a path between the bit line BL and the source line SL is established.
Next, the source line SL is fixed to a low level, for example, to a low level voltage 0, to complete the read preparation. Specifically, as shown in fig. 2A, in the forward reading, the voltage V SL on the source line SL is fixed to 0.
Then, by setting the bit line BL to a high level, the resistance change register is selected as the resistance change register to be read. Specifically, as shown in fig. 1A and 2A, when the voltage V BL of the bit line BL is set to the high-level voltage V READ, a voltage difference V READ-0＝VREAD is applied between the source of the selection transistor Q1 and the end of the memristor RRAM1 connected to the bit line BL, and therefore, the forward current I SL flows from the bit line BL to the source line SL via the memristor RRAM1 and the selection transistor Q1. At this time, the resistance change register is selected as a cell to be read.
Then, the forward current I SL on the source line SL is read to achieve forward reading. Specifically, since the magnitude of the forward current I SL read at this time is just the magnitude of the resistance value corresponding to the data stored in the resistance change register, that is, the weight data, as shown in fig. 2A, the read result can be obtained by reading the forward current I SL flowing from the source line SL.
On the other hand, if the bit line BL is set to a low level, the resistance change register is not selected as the resistance change register to be read, that is, the unselected cell. Specifically, as shown in fig. 1A and 2A, when the voltage V BL of the bit line BL is set to the low-level voltage 0, the voltage difference between the end of the memristor RRAM1 connected to the bit line BL and the source of the selection transistor Q1 is 0-0=0, and therefore, no current flows from the bit line BL to the source line SL, i.e., I SL =0. At this time, the resistance change register becomes an unselected cell.
As described above, in the forward read, the specific resistance change register is selected by the high level of the bit line BL by applying the low level 0 on the source line SL, and the stored data is acquired by reading the forward current I SL on the source line SL, in other words, the horizontal (BL) input and the vertical (SL) output in the forward read. Because the memristor RRAM1 is arranged between the high level of the bit line BL and the selection transistor Q1 and the source line SL is at a low level, the high level can be prevented from being directly added to the source of the selection transistor Q1, and the reduction of the reading speed and the margin of the whole resistance variable register caused by the influence of the threshold voltage V th on the selection transistor Q1 can be avoided. Therefore, the time consumption for completing on-chip training can be reduced, and the circuit stability is improved.
In contrast, as shown in fig. 1B and 2B, in the reverse read, first, the word line WL is set to a high level, for example, to a high level voltage VDD, as in the forward read, thereby gating the resistance change register.
Then, unlike in the forward read, the bit line BL is fixed to a high level, for example, to a high level voltage V READ, to complete the read preparation. Specifically, as shown in fig. 2B, the voltage V BL on the bit line WL is fixed to V READ at the time of the reverse read.
Then, by setting the source line SL to a low level, the resistance change register is selected as the resistance change register to be read. Specifically, as shown in fig. 1B and 2B, when the voltage V SL of the source line SL is set to the low-level voltage 0, a voltage difference V READ-0＝VREAD is applied between the source of the selection transistor Q1 and the end of the memristor RRAM1 connected to the bit line BL, and thus, a reverse current I BL flows from the bit line BL to the source line SL via the memristor RRAM1 and the selection transistor Q1. At this time, the resistance change register is selected as a cell to be read.
Thereafter, the reverse current I BL on the bit line BL is read to achieve reverse reading. Specifically, since the magnitude of the reverse current I BL read at this time is characterized by the magnitude of the resistance value corresponding to the data stored in the resistance change register, that is, the weight data, as shown in fig. 2B, the read result can be obtained by reading the reverse current I BL flowing into the bit line BL.
On the other hand, if the source line SL is set to the high level, the resistance change register is not selected as the resistance change register to be read, that is, the unselected cell. Specifically, as shown in fig. 1B and 2B, when the voltage V SL of the source line SL is set to the high-level voltage V READ, the voltage difference between the end of the memristor RRAM1 connected to the bit line BL and the source of the selection transistor Q1 is V READ-VREAD =0, and therefore, no current flows from the bit line BL to the source line SL, i.e., I BL =0. At this time, the resistance change register becomes an unselected cell.
As described above, at the time of the reverse read, the specific resistance change register is selected by the low level of the source line SL by applying the high level V READ on the bit line BL, and the stored data is acquired by reading the reverse current I BL on the bit line BL, in other words, the vertical (SL) input-lateral (BL) output at the time of the reverse read. As in the case of forward reading, since the memristor RRAM1 is spaced between the high level of the bit line BL and the selection transistor Q1 and the source line SL is low, the high level can be prevented from being directly applied to the source of the selection transistor Q1, and the reduction of the read speed and margin of the entire resistance change register due to the influence of the threshold voltage V th on the selection transistor Q1 can be prevented. Therefore, the time consumption for completing on-chip training can be reduced, and the circuit stability is improved.
Embodiment 2
In embodiment 1, a memristor reading method of one 1T1R resistance variable register is described, and in embodiment 2, a memristor reading method of a resistance variable register array system including a plurality of resistance variable registers is further described.
Fig. 3 is a block diagram showing the configuration of a resistance variable register array system according to embodiment 2.
The resistance change register array system of the present embodiment includes a resistance change register array. As shown in fig. 3, the resistive-switching register array is formed of a plurality of the resistive-switching registers of 1T1R as described above, and is formed as an m×n array. In the resistive register array, 1bit weight data is stored in the memristor RRAM in each resistive register in a high-low resistance state, so that the weight data stored in the resistive register array is formed into a matrix of m×n weight data. Word lines of the resistance change registers of each row of the resistance change register array are respectively gathered on word line buses WL1, WL2, … … and WLm of the row, bit lines of the resistance change registers of each row are respectively gathered on bit line buses BL1, BL2, … … and BLm of the row, and source lines of the resistance change registers of each column are respectively gathered on source line buses SL1, SL2, … … and SLn of the column.
The input terminals of the word line buses WL1, WL2, … …, WLm and the input terminals of the bit line buses BL1, BL2, … …, BLm of each row, and the input terminals of the source line buses SL1, SL2, … …, SLn of each column are connected to registers via input drivers, respectively. Specifically, the input terminals (left end in the figure) of the bit line buses BL1, BL2, … …, BLm of the respective rows are connected to the BL registers, for example, via FF (feed-forward) input drivers. The input terminals (left end in the figure) of the word line buses WL1, WL2, … …, WLm of the respective rows are connected to the WL register, for example, via an input driver. The input terminals (upper ends in the figure) of the source line buses SL1, SL2, … …, and SLn of the respective columns are connected to the SL register via, for example, BP (backward propagation: back propagation) input drivers. In this embodiment, when it is necessary to perform a read operation on the weight data stored in the resistive switching register array, BL, SL, and WL array data transferred from the on-chip or external are stored in the registers, and these array data are input into the resistive switching register array in a high-low level manner by driving of the input driver, thereby completing the read function.
The output terminals (lower end in the figure) of the source line buses SL1, SL2, … …, SLn of the respective columns are connected to the shift adder 3 via an analog-to-digital converter ADC 1. The output ends (right end in the figure) of the bit line buses BL1, BL2, … …, BLm of the respective rows are connected to the shift adder 4 via an analog-to-digital converter ADC 2. As shown in fig. 3, in the present embodiment, the shift adders 3 and 4 are constituted by a shift register shift and a full adder array Adder. The forward current/reverse current signal output by the resistive register array is converted into a digital signal by analog-to-digital conversion of the analog-to-digital converters ADC1 and ADC2, and is input to the shift registers 3 and 4. The shift registers 3 and 4 calculate the convolution of the 1-bit vector input from the input driver and the multi-bit weight data of the plurality of resistive registers stored in the resistive register array based on the input digital signal, thereby completing the parallel in-memory calculation, completing the multiplication of the vector and the matrix, and realizing the integration of memory calculation.
In addition, the resistive switching register array system of the present embodiment further includes a CIM (computing in memory: in-memory computation) controller for overall control of in-memory computation of the resistive switching register array system.
Next, a method of performing memristor reading by using the resistive register array system according to the present embodiment will be described based on the configuration of fig. 3.
In the forward reading, first, the levels corresponding to the elements in the third vector are sequentially input to the word line buses WL1, WL2, … …, WLm of the respective rows. Specifically, the third vector is sent from the WL register to the input terminals of the word line buses WL1, WL2, … …, WLm of each row via the input driver. In the present embodiment, the "third vector" is, for example, a vector composed of 0 and 1 and containing m elements. Where 1 denotes a resistance change register of a corresponding row in the gate resistance change register array, i.e., a word line bus of the corresponding row is raised to make a corresponding selection transistor conductive. A 0 indicates that the resistance change register of the corresponding row in the resistance change register array is not gated, i.e., a low level is applied to the word line bus of the corresponding row to make the corresponding selection transistor non-conductive.
Next, the source bus lines SL1, SL2, … …, SLn of each column are fixed to a low level. Specifically, a low level is sent from the SL register to the input terminals of the source line buses SL1, SL2, … …, SLn of each column via the BP input driver.
Then, the levels corresponding to the elements in the second vector are sequentially input to the bit line buses BL1, BL2, … …, BLm of the respective rows. Specifically, the second vector is sent from the BL register to the input terminals of the bit line buses BL1, BL2, … …, BLm of each row via the FF input driver. In the present embodiment, the "second vector" is, for example, a vector composed of 0 and 1 and containing m elements. Where 1 denotes a resistive switching register of a corresponding row in the resistive switching register array, i.e. a high level is applied to the bit line bus of the corresponding row. A 0 indicates that the resistance change register of the corresponding row in the resistance change register array is not selected, i.e., a low level is added to the bit line bus of the corresponding row.
Thereafter, the total forward current I SL1、ISL2、……、ISLn on the source line buses SL1, SL2, … …, SLn of each column is read to achieve forward reading. Specifically, a digital signal corresponding to the total forward current I SL1、ISL2、……、ISLn is transmitted from the output terminals of the source line buses SL1, SL2, … …, SLn of each column to the shift adder 3 via the analog-to-digital converter ADC1, and then the convolution of the 1-bit second vector and the multi-bit weight data stored in the plurality of resistance change registers is calculated by the shift adder 3 based on the digital signal for subsequent arithmetic processing. The magnitude of the total forward current I SL1、ISL2、……、ISLn of each column represents the sum of the products of the second vector and the weight data of the resistive random access register stored in the column.
In contrast, in the reverse read, first, the levels corresponding to the elements in the third vector are sequentially input to the word line buses WL1, WL2, … …, WLm of the respective rows. Specifically, the third vector is sent from the WL register to the input terminals of the word line buses WL1, WL2, … …, WLm of each row via the input driver. In the present embodiment, the "third vector" is, for example, a vector composed of 0 and 1 and containing m elements. Where 1 denotes a resistance change register of a corresponding row in the gate resistance change register array, i.e., a word line bus of the corresponding row is raised to make a corresponding selection transistor conductive. A0 indicates that the resistance change register of the corresponding row in the resistance change register array is not gated, i.e., a low level is applied to the word line bus of the corresponding row to make the corresponding selection transistor non-conductive.
Next, the bit line buses BL1, BL2, … …, BLm of each row are fixed to a high level. Specifically, a high level is sent from the BL register to the input terminals of the bit line buses BL1, BL2, … …, BLm of the respective rows via the FF input driver.
Then, the levels corresponding to the elements in the first vector are sequentially input to the source line buses SL1, SL2, … …, SLn of the respective columns. Specifically, the first vector is transmitted from the SL register to the input terminals of the source line buses SL1, SL2, … …, SLn of each column via the BP input driver. In the present embodiment, the "first vector" is, for example, a vector composed of 0 and 1 and containing n elements. Where 0 represents the selection of the resistive switching register of the corresponding column in the resistive switching register array, i.e. the low level is applied to the source line bus of the corresponding column. 1 indicates that the resistance change register of the corresponding column in the resistance change register array is not selected, i.e., a level is raised to the bit line bus of the corresponding column.
Thereafter, the total reverse current I BL1、IBL2、……、IBLm on the bit line buses BL1, BL2, … …, BLm of each row is read to effect a reverse read. Specifically, a digital signal corresponding to the total reverse current I BL1、IBL2、……、IBLm is transmitted from the bit line bus BL1, BL2, … …, BLm output terminals of each row via the analog-to-digital converter ADC2 to the shift adder 4, and then, the convolution of the 1-bit first vector and the multi-bit weight data stored in the plurality of resistance change registers is calculated by the shift adder 4 based on the digital signal for subsequent arithmetic processing. The magnitude of the total forward current I BL1、IBL2、……、IBLm of each row represents the sum of the products of the first vector and the weight data of the resistive random access register stored in the row.
As described above, forward reads may correspond to forward propagation process calculations and reverse reads may correspond to reverse propagation process calculations. In particular, in the reverse read process, since the bit line bus of each row is fixed to a high level, and the levels corresponding to the elements in the first vector are sequentially input to the source line bus of each column, the first vector is composed of 0 indicating selection and 1 indicating non-selection, and therefore, when the element in the first vector is 0, the resistance change register to be read is selected by setting the source line to a low level. Thus, even in the reverse reading, the high level is not directly applied to the source of the selection transistor in the resistance change register, and the reduction of the reading speed and margin of the entire resistance change register due to the influence of the threshold voltage V th on the selection transistor can be avoided. Therefore, the time consumption for completing on-chip training can be reduced, the circuit stability is improved, and the quantization range of the current output to the analog-to-digital converter in forward reading and reverse reading can be kept consistent, so that the design difficulty of the back-end processing circuit such as the analog-to-digital converter and the like can be reduced, and the cost of circuit design is reduced.
The memristor reading method according to the present invention is described above. The memristor reading method can be directly realized on a hardware chip in an in-memory computing mode, can also be realized through software, or can be realized through the combination of the software and the hardware. Further, a program for executing the memristor reading method of the present invention may also be stored in various computer-readable media and loaded into, for example, a CPU or the like to be executed as needed. The computer readable medium is not particularly limited, and for example, an optical disk such as an HDD, a CD-ROM, or a CD-R, MO, MD, DVD, an IC card, a floppy disk, a semiconductor memory such as a mask ROM, EPROM, EEPROM, or a flash ROM may be used.
It should be noted that all aspects of the embodiments disclosed herein are merely examples and are not intended to be limiting. The scope of the present invention is indicated by the claims rather than the above-described embodiments, and all modifications and variations that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
Industrial applicability
As described above, the memristor reading method according to the present invention, and the computer readable medium storing the program that results in execution of the memristor reading method, are useful for the bidirectional reading process in on-chip training.
Claims (12)
1. A memristor reading method for reading data stored in a resistance change register during on-chip training, the resistance change register comprising: a memristor having one end connected to the bit line; and a selection transistor having a drain connected to the other end of the memristor and a source connected to a source line, the memristor reading method comprising:
A step of fixing the bit line to a high level;
A step of selecting the resistance change register to be read by setting the source line to a low level; and
And reading the reverse current on the bit line to realize reverse reading, wherein the magnitude of the reverse current represents the data stored in the resistance change register.
2. The memristor reading method of claim 1,
The plurality of the resistance change registers form an array, bit lines of the resistance change registers of each row of the array are converged on a bit line bus of the row, source lines of the resistance change registers of each column are converged on a source line bus of the column,
The step of fixing the bit line to a high level includes: a step of fixing the bit line bus of each row to a high level,
The step of selecting the resistance change register to be read by setting the source line to a low level includes: a step of sequentially inputting levels corresponding to elements in a first vector to the source line bus lines of the columns, the first vector being composed of 0 representing selection and 1 representing non-selection,
The step of reading the reverse current on the bit line to achieve reverse reading includes: and reading the total reverse current on the bit line bus of each row to realize reverse reading, wherein the total reverse current of each row represents the sum of the products of the first vector and the data stored in the resistance change register of the row.
3. The memristor reading method of claim 2,
The inputs of the bit line buses of each row are connected to a register via an input driver, and the inputs of the source line buses of each column are connected to the register via the input driver,
The step of fixing the bit line bus of each row to a high level includes: a high is sent from the register via the input driver to the input of the bit line bus of each row,
The step of sequentially inputting the levels corresponding to the elements in the first vector to the source line bus of each column includes: the first vector is sent from the register via the input driver to the input of the source line bus of each column.
4. The memristor reading method of claim 2,
The outputs of the bit line buses of each row are connected via analog-to-digital converters to a shift adder,
The step of reading the total reverse current on the bit line bus of each row to achieve reverse reading includes:
transmitting a digital signal corresponding to the total reverse current from an output of the bit line bus of each row to the shift adder via the analog-to-digital converter; and
A convolution of the first vector of 1 bit and multi-bit data stored in a plurality of the resistance change registers is calculated by the shift adder based on the digital signal.
5. The memristor reading method of any one of claims 1 to 4, further comprising:
a step of fixing the source line to a low level;
A step of selecting the resistance change register to be read by setting the bit line to a high level; and
And reading the forward current on the source line to realize forward reading, wherein the magnitude of the forward current characterizes the data stored in the resistance change register.
6. The memristor reading method of claim 5,
The plurality of the resistance change registers form an array, bit lines of the resistance change registers of each row of the array are converged on a bit line bus of the row, source lines of the resistance change registers of each column are converged on a source line bus of the column,
The step of fixing the source line to a low level includes: a step of fixing the source line bus of each column to a low level,
The step of selecting the resistance change register to be read by setting the bit line to a high level includes: a step of sequentially inputting levels corresponding to elements in a second vector to the bit line bus lines of the rows, the second vector being composed of 1 representing selection and 0 representing non-selection,
The step of reading the forward current on the source line to achieve forward reading includes: and reading the total forward current on the source line bus of each column to realize forward reading, wherein the magnitude of the total forward current of each column represents the sum of the products of the second vector and the data stored in the resistance change register of the column.
7. The memristor reading method of claim 6,
The input of the source line bus of each column is connected to a register via an input driver, and the input of the bit line bus of each row is connected to the register via the input driver,
The step of fixing the source line bus of each column to a low level includes: a low level is sent from the register via the input driver to the input of the source line bus of each column,
The step of sequentially inputting the levels corresponding to the elements in the second vector to the bit line buses of the rows includes: the second vector is sent from the register via the input driver to the input of the bit line bus of each row.
8. The memristor reading method of claim 6,
The outputs of the source line buses of each column are connected via analog-to-digital converters to a shift adder,
The step of reading the total forward current on the source line bus of each column to achieve forward reading includes:
Transmitting a digital signal corresponding to the total forward current from an output of the source line bus of each column to the shift adder via the analog-to-digital converter; and
A convolution of the second vector of 1 bit with multi-bit data stored in a plurality of the resistance change registers is calculated by the shift adder based on the digital signal.
9. The memristor reading method of any one of claims 1 to 4,
The gate of the select transistor is connected to a word line,
The memristor reading method further comprises the following steps:
And a step of gating the resistance change register by setting the word line to a high level.
10. The memristor reading method of claim 9,
A plurality of the resistance change registers form an array, word lines of the resistance change registers of each row of the array are gathered on a word line bus of the row,
The step of gating the resistance change register by setting the word line to a high level includes: and a step of sequentially inputting levels corresponding to elements in a third vector to the word line bus lines of the rows, the third vector being composed of 1's indicating gating and 0's indicating non-gating.
11. The memristor reading method of claim 10,
The inputs of the word line buses of each row are connected to registers via input drivers,
The step of sequentially inputting the levels corresponding to the elements in the third vector to the word line bus lines of the rows includes: the third vector is sent from the register via the input driver to the input of the word line bus of each row.
12. A computer readable medium storing a program for executing the memristor reading method according to any one of claims 1 to 11.
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