CN117933153A - I3C bus verification system - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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Abstract
The invention discloses an I3C bus verification system. In order to verify an I3C bus, the I3C bus verification system comprises a first I3C intellectual property verification module, a second I3C intellectual property verification module and a design module to be tested; the first I3C intellectual property verification module comprises a first I3C bus module; the second I3C intellectual property verification module comprises a second I3C bus module; the design module to be tested is a slave of the first I3C bus module; the design to be tested module is the host of the second I3C bus module. The invention solves the technical problem of how to efficiently verify the I3C bus system, and improves the chip verification reliability and verification efficiency. The invention is suitable for the field of chip verification.
Description
Technical Field
The invention relates to the field of chip verification, in particular to an I3C bus verification system.
Background
Compared with an Inter-INTEGRATED CIRCUIT (I2C) bus, the Improved Inter-INTEGRATED CIRCUIT (I3C) bus is a faster, more efficient, low-power-consumption and multifunctional bus protocol, and besides supporting faster speed, the I3C bus compensates for the disadvantage that the I2C bus cannot actively inform the host of information.
The I3C bus supports in-band interrupts of the device, and the slave actively initiates interrupt events to interact with the host through a serial data line (SERIAL DATA LINE, SDA), and meanwhile, functions such as dynamic address configuration, universal command codes (Common Command Codes, CCC) and the like are added.
Supporting more functionality means increased I3C device verification difficulty and time, and for more complex bus designs, errors tend to occur more easily, and any errors tend to be fatal to the chip. Therefore, for I3C devices, there is a need for more reliable, faster, more efficient, and more versatile chip verification methods.
To meet chip verification requirements, some electronic design automation (Electron Design Automation, EDA) manufacturers have introduced efficient and reliable intellectual property core verification (Verification Intellectual Property, VIP) modules. The verification personnel can directly multiplex the intellectual property verification module when building the verification environment, and the intellectual property verification module can provide excitation and time sequence check of standard protocols, so that the verification time cost can be greatly reduced.
The current I2C intellectual property verification module is quite common in application, and the application in a verification system is very mature, and in contrast, the I3C intellectual property verification module is less in application. For the equipment to be verified based on the I3C bus, the application of the I3C intellectual property verification module is certainly a time-saving and efficient technical path.
The current prior art has presented I3C master and slave device authentication systems and communication methods, and I3C bus universal authentication methods (Universal Verification Methodology, UVM). In this scenario, only a few of the verification systems given by the prior art can be reused, however, the prior art lacks a verification method for an I3C device with a hub function and an "internal interrupt" function, and lacks an applicable intellectual property verification module, so that the verification time is longer, the labor cost is higher, and the reliability of the verification result is worse.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
An I3C bus verification system, the I3C bus verification system comprising a first I3C intellectual property core verification module and a second I3C intellectual property core verification module, and a design module to be tested; the first I3C intellectual property verification module comprises a first I3C bus module; the second I3C intellectual property verification module comprises a second I3C bus module; the design module to be tested is a slave of the first I3C bus module; the design to be tested module is a host of a second I3C bus module.
Further, the design to be tested module is a hub.
Further, the first I3C intellectual property verification module further includes a first I3C configuration module, where the first I3C configuration module is configured to perform parameter configuration on a master machine belonging to the first I3C bus module and a slave machine of the first I3C bus module; the second I3C intellectual property verification module further comprises a second I3C configuration module, and the second I3C configuration module is used for carrying out parameter configuration on a host computer belonging to the second I3C bus module and a slave computer of the second I3C bus module.
Further, a first host in a first I3C intellectual property verification module initiates a request incentive; the request stimulus is a read or write operation conforming to the I2C protocol format, or the request stimulus is a read or write operation conforming to the I3C protocol format.
Further, the request excitation initiated by the first host in the first I3C intellectual property verification module is the configuration operation of the design module to be tested, and whether the function of the design module to be tested is normal is verified by verifying whether the configuration is effective; or/and, the request excitation initiated by the first host in the first I3C intellectual property verification module is a read operation of the design module to be tested, and whether the read function of the design module to be tested is normal or not is verified according to the read data.
Further, the request incentive initiated by the first host in the first I3C intellectual property verification module is a read operation or a write operation to the first slave in the second I3C intellectual property verification module, and the read operation has corresponding read data, and the write operation has corresponding write data; the design module to be tested receives the request excitation initiated by the first host in the first I3C intellectual property verification module through the first I3C bus module, analyzes the request excitation and then forwards and outputs the request excitation to the second I3C bus module; the first slave in the second I3C intellectual property verification module initiates response excitation; the design module to be tested receives the response excitation initiated by the first slave in the second I3C intellectual property verification module through the second I3C bus module, analyzes the response excitation and then forwards and outputs the response excitation to the first I3C bus module; comparing whether read data received by the design module to be tested from the second I3C bus module is consistent with the read data sent by the design module to be tested to the first I3C bus module, or comparing whether write data received by the design module to be tested from the first I3C bus module is consistent with write data sent by the design module to be tested to the second I3C bus module, so as to verify whether the analysis and forwarding functions of the design module to be tested are normal.
Further, a first host in the first I3C intellectual property verification module sends configuration operation excitation through the first I3C bus module, wherein the configuration operation excitation is used for configuring the design module to be tested, so that the design module to be tested requests interrupt data when the first I3C bus module is idle; the interrupt data includes a device address; when a design module to be tested requests interruption, a first host in a first I3C intellectual property verification module initiates read operation excitation or write operation excitation; when a first host in a first I3C intellectual property verification module sends a device address of a slave in the first I3C intellectual property verification module to a first I3C bus module, a design module to be tested sends a device address of the design module to be tested to the first I3C bus module; and the first I3C bus module executes interrupt arbitration on the equipment address of the slave in the first I3C intellectual property verification module and the equipment address of the design module to be tested.
Further, configuring a first slave in the first I3C intellectual property verification module and a second slave in the first I3C intellectual property verification module, and enabling the first slave in the first I3C intellectual property verification module and the second slave in the first I3C intellectual property verification module to send interrupt stimulus to the first I3C bus module; the first slave in the first I3C intellectual property verification module and the second slave in the first I3C intellectual property verification module respectively send the self device address to the first I3C bus module to participate in interrupt competition.
Configuring a first slave in a second I3C intellectual property verification module and a second slave in the second I3C intellectual property verification module, enabling the first slave in the second I3C intellectual property verification module and the second slave in the second I3C intellectual property verification module to send interrupt incentives to the second I3C bus module, and enabling the design module to be tested to forward the interrupt incentives in the second I3C bus module to the first I3C bus module to participate in interrupt competition.
Further, the I3C bus verification system further comprises an interrupt verification module; the interrupt verification module detects whether the design module to be tested can continuously send the equipment address after successful interrupt competition of the first I3C bus module and stop sending interrupt data after failure in interrupt competition of the first I3C bus module so as to verify whether the interrupt competition function of the design module to be tested is normal; the interrupt verification module detects whether interrupt excitation initiated by a first slave in a second I3C intellectual property verification module and a second slave in the second I3C intellectual property verification module on a second I3C bus module can be correctly arbitrated by the interrupt of the design module to be tested and can be correctly forwarded to the first I3C bus module so as to verify whether the forwarding interrupt function of the design module to be tested is normal or not and whether the interrupt arbitration function of the design module to be tested is normal or not.
The technical scheme of the invention has one or more of the following beneficial technical effects:
(1) The prior art provides an authentication system and a communication method of an I3C master-slave device, but the authenticated device comprises a host and a slave on an I3C bus, which are two different devices hung on the same bus, the authenticated device does not have a hub function, and the system cannot perform authentication of a forwarding function. The invention relates to a design module to be tested, which has a hub function, relates to two I3C buses, is used as a slave on a first I3C bus and is used as a host on a second I3C bus, and the verification system provided by the invention can verify the special DUT module function.
(2) The prior art provides an I3C host and slave verification system and a communication method, but has no application of an intellectual property core verification module, and a verifier needs to independently write incentives, so that not only is the host required to write the incentives initiated, but also the corresponding slave response incentives are written. Further to this, since the hub forwarding function involves switching back and forth of SDA input/output directions of two I3C buses, the difficulty of stimulus programming is greatly increased, and timing inspection is also lacking. The verification system provided by the invention is applied to two sets of I3C intellectual property core verification, can reduce the time cost of writing and excitation of verification personnel, can perform I2C and I3C time sequence inspection, and improves the reliability of verification results.
(3) The prior art lacks a verification method of the interrupt and arbitration functions of an I3C bus, devices on the I3C bus support an in-band interrupt function, a slave can actively initiate an interrupt to a host, and the host performs interrupt arbitration. The invention provides an interrupt arbitration verification method, which also comprises two I3C buses, wherein a design module to be tested can initiate the interrupt and the host and the slave on the two I3C buses to perform bus competition and arbitration, and can verify the interrupt and arbitration functions of the I3C buses.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a topology diagram of an I3C bus validation system in accordance with an embodiment of the present invention;
FIG. 2 is a flow chart of a request interrupt arbitration function verification in an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
FIG. 1 illustrates an exemplary topology of an I3C bus validation system in one embodiment of the invention. In an I3C bus validation system of the present invention, a first I3C bus module, a second I3C bus module, and a design under test module (Design Under Test, DUT) are included.
Specifically, the design module to be tested of the present invention may be a hub, such as a fifth generation serial presence detect (SERIAL PRESENCE DETECT, SPD 5) hub. The specific details of the present invention will be described below using a hub as an example, and these embodiments are also considered as embodiments based on the design module to be tested. Those skilled in the art will recognize that other products having similar functionality may be used in the present invention and that these embodiments are intended to be encompassed by the present invention.
In the invention, the hub can forward data. Further, when the hub forwards data, parsing, transparent transmission or forwarding after changing some data according to requirements can be included.
The verification target which can be realized by the invention comprises one or more of the following functions:
(1) The basic functions of the authentication hub include the authentication of the parsing and forwarding functions, or the host and slave functions.
(2) The hub may be verified for functionality in both the I2C and I3C data formats, including timing checking the stimuli of the I3C and I2C data formats sent on the two I3C bus modules.
(3) An interrupt race function of the hub in the first I3C bus module is verified.
(4) The interrupt arbitration function of the hub in the second I3C bus module is verified.
In the present invention, arbitration refers to a process or step of determining to win a bus participant (such as a slave). According to the rule of arbitration, each slave machine can judge whether the current bit wins arbitration or not.
First, two sets of I3C intellectual property core verification modules are instantiated in a verification environment: a first I3C intellectual property verification module and a second I3C intellectual property verification module. Illustratively, the first I3C intellectual property verification module comprises a first I3C bus module, a first host in the first I3C intellectual property verification module, a first slave in the first I3C intellectual property verification module, a second slave in the first I3C intellectual property verification module, and a design module to be tested, wherein the first host in the first I3C intellectual property verification module is the host of the first I3C bus module; the first slave in the first I3C intellectual property verification module and the second slave in the first I3C intellectual property verification module are slaves of the first I3C bus module.
Alternatively, the number of slaves in the first I3C intellectual property verification module may be other numbers, such as 1, 3; the number of hosts in the first I3C intellectual property core block may also be other numbers, such as 2, 3, etc. The present invention is not limited thereto at all, and is not limited thereto.
Illustratively, the second I3C intellectual property verification module includes a second I3C bus module, a first slave in the second I3C intellectual property verification module, a second slave in the second I3C intellectual property verification module. Alternatively, the number of slaves included in the second I3C intellectual property verification module may be other numbers.
The design module to be tested, such as a hub, serves as a host in the second I3C intellectual property verification module. In another aspect, the hub of the present invention is also a slave to the first I3C intellectual property core verification module.
In addition, the first I3C intellectual property verification module further comprises a first I3C configuration module, not shown, and the second I3C intellectual property verification module further comprises a second I3C configuration module, not shown. The two I3C configuration modules function to configure parameters, and to control behavior or response, of the master and slave (including hubs) on the first I3C bus module, the second I3C bus module.
In the invention, the hub serving as the design module to be tested is connected with the first I3C bus module and also connected with the second I3C bus module. Specifically, a Host serial clock line (Host Serial Clock Line, HSCL) and a Host serial data line (Host SERIAL DATA LINE, HSDA) of the hub are connected to the first I3C bus module, and a Local serial clock line (Local Serial Clock Line, LSCL) and a Local serial data line (Local SERIAL DATA LINE, LSDA) of the hub are connected to the second I3C bus module.
Taking fig. 1 as an example, for a first I3C bus module, a host belonging to the first I3C bus module is a first host in a first I3C intellectual property verification module, and a slave is a first slave in the first I3C intellectual property verification module, a second slave in the first I3C intellectual property verification module, and a design module to be tested; for the second I3C bus module, the host computer belonging to the second I3C bus module is the design module to be tested, and the slave computers are the first slave computers in the second I3C intellectual property verification module and the second slave computers in the second I3C intellectual property verification module. The host or the slave is corresponding to the equipment mounted on the I3C bus module. The slave devices all have their own device addresses, including the design module to be tested.
In the example topology of the above verification system defined in the present invention, the design module to be tested functions as a master and a slave in two different I3C bus systems, respectively, thereby being the basis for verification that can implement the hub parsing and forwarding functions.
To verify the functionality of the hub, a first host in a first I3C intellectual property verification module in the I3C bus verification system initiates a request stimulus that is a read operation or a write operation according to an I2C protocol format or an I3C protocol format, wherein the I3C protocol includes its own CCC command.
Typically, data is included if the request stimulus belongs to a write operation stimulus; if the request stimulus belongs to the read operation stimulus, no data is included. In response to the stimulus, data is read only in response to the read operation stimulus; in response to a write operation stimulus, then is an acknowledge.
Alternatively, the request stimulus may be a configuration operation or a read operation stimulus to the hub, or a configuration operation or a read operation stimulus to the device mounted on the second I3C bus module.
In addition, the first I3C configuration module and the second I3C configuration module can configure the data packet which is stimulated to be in an I3C protocol format or an I2C protocol format, and the same use case can simultaneously support to send the stimulating signals in the I3C protocol format and the I2C protocol format.
The following specific verification methods disclosed herein may be selected by one or more of ordinary skill in the art:
The request stimulus initiated by the first host in the first I3C intellectual property verification module comprises a write operation and a read operation. The request incentive may be for the first slave or the second slave in the second I3C intellectual property verification module or for the hub. The specific means of distinguishing the object devices may be distinguished by, for example, the device address of the slave or hub.
If the request incentive initiated by the first host in the first I3C intellectual property verification module is for a slave in the second I3C intellectual property verification module, such as the first slave or the second slave, the hub forwards the request incentive to the second I3C bus module.
If the request excitation initiated by the first host in the first I3C intellectual property verification module is a write operation or a read operation to the device (such as the first slave) mounted on the second I3C bus module, the first slave in the second I3C intellectual property verification module initiates a response excitation, and the hub receives the request excitation initiated by the first host in the first I3C intellectual property verification module through the first I3C bus module, analyzes and then forwards the request excitation and outputs the request excitation to the second I3C bus module.
At the same time, the hub receives the response stimulus initiated by the first slave in the second I3C intellectual property verification module through the second I3C bus module, analyzes and forwards the response stimulus, and outputs the response stimulus to the first I3C bus module.
The process completes the interactive communication between the hub and the two I3C bus modules, compares the write data or the read data interacted by the first I3C bus module with the write data or the read data interacted by the second I3C bus module, so as to verify whether the analysis and forwarding functions of the hub are normal. The specific details are as follows:
Illustratively, if a first host in a first I3C intellectual property verification module accesses a first slave in a second I3C intellectual property verification module in a read operation, a request stimulus initiated by the first host in the first I3C intellectual property verification module is a read operation, and the hub receives the request stimulus and forwards the request stimulus to the first slave in the second I3C intellectual property verification module. After the first slave in the second I3C intellectual property verification module receives the request stimulus, the first slave sends read data to the hub, and the hub forwards the received read data to the first master in the first I3C intellectual property verification module.
Preferably, in the verification link, it is checked whether the whole communication process and handshake functions of the hosts and the slaves at two ends of the hub are normal, and whether the read data received by the hub from the second I3C bus module and the read data sent by the hub to the first I3C bus module are consistent is compared to verify whether the analysis and forwarding functions of the hub are normal.
For example, if a first host in a first I3C intellectual property verification module accesses a first slave in a second I3C intellectual property verification module with a write operation, a request stimulus initiated by the first host in the first I3C intellectual property verification module is the write operation, and after receiving the request stimulus, the hub forwards the request stimulus to the first slave in the second I3C intellectual property verification module through the second I3C bus module. After receiving the response of the first slave in the second I3C intellectual property verification module, the first host in the first I3C intellectual property verification module sends write data, and the hub forwards the write data to the second I3C bus module after receiving the write data.
Preferably, in the verification link, whether the analysis and forwarding function of the hub is normal is verified by comparing whether the write data received by the hub from the first I3C bus module and the write data sent by the hub to the second I3C bus module are consistent.
If the first host initiated request incentive in the first I3C intellectual property verification module is for a hub, then a configuration operation or a read operation is performed on the hub. The configuration operation is one type of write operation.
Optionally, if the request initiated by the first host in the first I3C intellectual property verification module is an incentive for the type of configuration operation of the hub, and verifies whether the hub functions normally, such as a write function, by verifying whether the configuration is valid.
Optionally, if the request stimulus initiated by the first host in the first I3C intellectual property verification module is a read operation stimulus to the hub, it may be verified whether the read function of the hub is normal according to the read data.
FIG. 2 is a flow chart of a request interrupt arbitration function verification in an embodiment of the present invention. Also taking as an example the exemplary topology diagram based on the I3C bus validation system shown in fig. 1, the I3C bus validation system further includes an interrupt validation module for validating the interrupt arbitration function of the hub. The invention discloses a specific verification method which comprises the following steps:
And configuring the address of a first slave in the first I3C intellectual property verification module as a first equipment address and the address of a second slave in the first I3C intellectual property verification module as a second equipment address through the first I3C configuration module. And configuring the address of the first slave in the second I3C intellectual property verification module as a third equipment address and the address of the second slave in the second I3C intellectual property verification module as a fourth equipment address through the second I3C configuration module.
Further, in one embodiment, the functions of these slaves to initiate interrupts are enabled by an enable signal. The configuration for these slave device addresses may be configured according to the verification requirements of the actual arbitration function and the device address of the hub.
A configuration operation stimulus is sent by a first host in the first I3C intellectual property verification module through the first I3C bus module for configuring the hub to request interrupt data including the device address when the first I3C bus module is idle.
When the hub requests interruption, a first host in the first I3C intellectual property verification module initiates a read operation stimulus or a write operation stimulus, and at the moment, when the first host in the first I3C intellectual property verification module sends a device address of a slave in the first I3C intellectual property verification module to the first I3C bus module, the hub sends a device address of the hub to the first I3C bus module, and the first I3C bus module executes interruption arbitration on the two device addresses.
Meanwhile, a first slave in the first I3C intellectual property verification module and a second slave in the first I3C intellectual property verification module are configured to send interrupt excitation to the first I3C bus module, and the two slaves send own device addresses to the first I3C bus module to participate in interrupt competition.
In addition, a first slave in the second I3C intellectual property verification module and a second slave in the second I3C intellectual property verification module are configured to send interrupt excitation to the second I3C bus module, and the hub forwards the interrupt excitation of the second I3C bus module to the first I3C bus module to participate in interrupt competition.
Typically, if a local device, such as a slave, is to send an interrupt, an interrupt stimulus needs to be constructed, the local device sends an interrupt request, and the hub identifies the interrupt request sent by the local device. In other words, the slave may send an interrupt request to the master. The interrupt stimulus is in the present invention to let the slave issue an interrupt request.
In the example of the present invention, interrupt contention involved in the second I3C bus module involves: the first slave in the second I3C intellectual property verification module and the second slave in the second I3C intellectual property verification module send out interrupt excitation; and the design module to be tested participates in competition of the second I3C bus module with the slave of the second I3C bus module when the design module to be tested transmits data to the second I3C bus module.
Further, interrupt contention involved in the first I3C bus module involves: a first slave in the first I3C intellectual property verification module and a second slave in the first I3C intellectual property verification module send interrupt incentives and device addresses; and the design module to be tested forwards the interrupt stimulus to the first I3C bus module from the second I3C bus module.
In the invention, in the first I3C bus module, the design module to be tested participates in interrupt competition and verifies whether the interrupt function is correct. In the second I3C bus module, the design module to be tested executes interrupt arbitration and participates in interrupt competition of the second I3C bus module.
In the invention, the interrupt verification module detects whether the hub can continue to send interrupt data after successful interrupt arbitration and releases the bus to stop sending interrupt data after failure in interrupt arbitration so as to verify the interrupt arbitration function of the hub.
For example, one arbitration method is to compare the magnitude of the values of the device addresses, letting the device with the smaller value of the device address win arbitration. The present invention is not limited thereto at all, and is not limited thereto.
Meanwhile, the interrupt verification module detects whether interrupt arbitration can be correctly completed by the first slave in the second I3C intellectual property verification module on the second I3C bus module and the interrupt excitation initiated by the second slave in the second I3C intellectual property verification module, and can be correctly forwarded to the first I3C bus module so as to verify whether the function of forwarding the interrupt excitation by the design module to be tested is normal or not.
The slave request interrupt can be divided into two cases: the first is that the slave machine initiates an interrupt request through steps of actively pulling up a serial data line after waiting for the I3C bus module to be idle for a certain time; the second is that the slave recognizes that other devices (the master or other slaves) mounted on the I3C bus module initiate an interrupt request, and the slaves send their own device addresses to participate in the contention. For the first case, no additional stimulus is required, the interrupt is sent after waiting a certain time, while for the second case an additional read or write stimulus is sent.
Further still, the first I3C intellectual property core block and the second I3C intellectual property core block can perform timing check on the data of the two I3C bus blocks and print the related information in the process.
Numerous specific details are set forth in the above description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An I3C bus validation system, characterized by:
The I3C bus verification system comprises a first I3C intellectual property verification module, a second I3C intellectual property verification module and a design module to be tested;
the first I3C intellectual property verification module comprises a first I3C bus module;
the second I3C intellectual property verification module comprises a second I3C bus module;
the design module to be tested is a slave of the first I3C bus module;
the design to be tested module is a host of a second I3C bus module.
2. The I3C bus validation system of claim 1, wherein:
the design to be tested module is a hub.
3. The I3C bus validation system of claim 2, wherein:
The first I3C intellectual property verification module further comprises a first I3C configuration module, wherein the first I3C configuration module is used for carrying out parameter configuration on a host computer belonging to the first I3C bus module and a slave computer of the first I3C bus module;
the second I3C intellectual property verification module further comprises a second I3C configuration module, and the second I3C configuration module is used for carrying out parameter configuration on a host computer belonging to the second I3C bus module and a slave computer of the second I3C bus module.
4. An I3C bus validation system according to claim 2 or 3, wherein:
A first host in a first I3C intellectual property verification module initiates a request incentive;
the request stimulus is a read or write operation conforming to the I2C protocol format, or the request stimulus is a read or write operation conforming to the I3C protocol format.
5. The I3C bus validation system of claim 4, wherein:
The request excitation initiated by a first host in the first I3C intellectual property verification module is configuration operation of the design module to be tested, and whether the function of the design module to be tested is normal is verified by verifying whether the configuration is effective; or/and the combination of the two,
The request excitation initiated by the first host in the first I3C intellectual property verification module is a read operation of the design module to be tested, and whether the read function of the design module to be tested is normal or not is verified according to the read data.
6. The I3C bus validation system of claim 4, wherein:
the request stimulus initiated by the first host in the first I3C intellectual property verification module is a read operation or a write operation to the first slave in the second I3C intellectual property verification module, and the read operation has corresponding read data, and the write operation has corresponding write data;
the design module to be tested receives the request excitation initiated by the first host in the first I3C intellectual property verification module through the first I3C bus module, analyzes the request excitation and then forwards and outputs the request excitation to the second I3C bus module;
the first slave in the second I3C intellectual property verification module initiates response excitation;
The design module to be tested receives the response excitation initiated by the first slave in the second I3C intellectual property verification module through the second I3C bus module, analyzes the response excitation and then forwards and outputs the response excitation to the first I3C bus module;
Comparing whether read data received by the design module to be tested from the second I3C bus module is consistent with the read data sent by the design module to be tested to the first I3C bus module, or comparing whether write data received by the design module to be tested from the first I3C bus module is consistent with write data sent by the design module to be tested to the second I3C bus module, so as to verify whether the analysis and forwarding functions of the design module to be tested are normal.
7. The I3C bus validation system of claim 4, wherein:
a first host in the first I3C intellectual property verification module sends configuration operation excitation through the first I3C bus module, and the configuration operation excitation is used for configuring the design module to be tested, so that the design module to be tested requests interrupt data when the first I3C bus module is idle; the interrupt data includes a device address;
When a design module to be tested requests interruption, a first host in a first I3C intellectual property verification module initiates read operation excitation or write operation excitation;
When a first host in a first I3C intellectual property verification module sends a device address of a slave in the first I3C intellectual property verification module to a first I3C bus module, a design module to be tested sends a device address of the design module to be tested to the first I3C bus module;
and the first I3C bus module executes interrupt arbitration on the equipment address of the slave in the first I3C intellectual property verification module and the equipment address of the design module to be tested.
8. The I3C bus validation system of claim 7, wherein:
Configuring a first slave in the first I3C intellectual property verification module and a second slave in the first I3C intellectual property verification module, and enabling the first slave in the first I3C intellectual property verification module and the second slave in the first I3C intellectual property verification module to send interrupt stimulus to the first I3C bus module;
The first slave in the first I3C intellectual property verification module and the second slave in the first I3C intellectual property verification module respectively send the self device address to the first I3C bus module to participate in interrupt competition.
9. The I3C bus validation system of claim 8, wherein:
Configuring a first slave in a second I3C intellectual property verification module and a second slave in the second I3C intellectual property verification module, enabling the first slave in the second I3C intellectual property verification module and the second slave in the second I3C intellectual property verification module to send interrupt incentives to the second I3C bus module, and enabling the design module to be tested to forward the interrupt incentives in the second I3C bus module to the first I3C bus module to participate in interrupt competition.
10. The I3C bus validation system of claim 9, wherein:
The I3C bus verification system further comprises an interrupt verification module;
The interrupt verification module detects whether the design module to be tested can continuously send the equipment address after successful interrupt competition of the first I3C bus module and stop sending interrupt data after failure in interrupt competition of the first I3C bus module so as to verify whether the interrupt competition function of the design module to be tested is normal;
The interrupt verification module detects whether interrupt excitation initiated by a first slave in a second I3C intellectual property verification module and a second slave in the second I3C intellectual property verification module on a second I3C bus module can be correctly arbitrated by the interrupt of the design module to be tested and can be correctly forwarded to the first I3C bus module so as to verify whether the forwarding interrupt function of the design module to be tested is normal or not and whether the interrupt arbitration function of the design module to be tested is normal or not.
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