CN117916881A - Semiconductor module, semiconductor chip, and method for manufacturing semiconductor module - Google Patents
Semiconductor module, semiconductor chip, and method for manufacturing semiconductor module Download PDFInfo
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Abstract
A semiconductor chip (1 a) is provided with a processor (10 a), a coil (70 a) which performs wireless communication with other semiconductor chips (1 b), a positive electrode power supply terminal (62 a) and a negative electrode power supply terminal (61 a), wherein the positive electrode power supply region (52) in the material provided with a positive electrode power supply region (52) and a negative electrode power supply region (51) is connected with or abutted against the positive electrode power supply terminal (62 a), the negative electrode power supply region (51) is connected with or abutted against the negative electrode power supply terminal (61 a), and the area of at least one of the positive electrode power supply region (52) and the negative electrode power supply region (51) is larger than the area of the end part of at least one of the positive electrode power supply terminal (62 a) and the negative electrode power supply terminal (61 a).
Description
Technical Field
The present invention relates to a semiconductor module, a semiconductor chip, and a method for manufacturing the semiconductor module.
Background
Conventionally, in a semiconductor chip module in which a plurality of semiconductor chips are integrated into one package, wired signal transmission by wire bonding, a silicon interposer, or the like has been performed for signal transmission between the integrated plurality of semiconductor chips. The semiconductor chip module for performing such wired signal transmission requires several thousands of communication lines to be connected between the semiconductor chip and the substrate, and also requires that the semiconductor chip be bonded to a predetermined position on the substrate with high accuracy, which is difficult to manufacture. Patent document 1 proposes the following technique for solving the above problems: the wireless communication using the coil is utilized instead of the wired communication lines, thereby reducing the number of communication lines between the semiconductor chip and the substrate.
However, even when signal transmission between a plurality of semiconductor chips is performed by wireless communication without using a communication line, in order for the plurality of semiconductor chips to function, it is necessary to connect the substrate and the semiconductor chips by a wired power line to supply electric power to each semiconductor chip. Therefore, there is a problem that the semiconductor chip is required to be bonded to a predetermined position on the substrate to which power can be supplied, and the semiconductor chip is required to be bonded to a predetermined position on the substrate with high accuracy as in the conventional art, and the manufacturing is not easy.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open No. 2021-87044
Disclosure of Invention
Problems to be solved by the invention
However, the information processing apparatus described in patent document 1 does not consider a method of mounting a power supply line to a semiconductor chip, which can be more easily manufactured.
The present invention has been made in view of such a background, and an object thereof is to provide a semiconductor module, a semiconductor chip, and a method for manufacturing a semiconductor module, which can be manufactured more easily.
Means for solving the problems
The present invention relates to a semiconductor chip including a processor, a coil for performing wireless communication with another semiconductor chip, a positive electrode power supply terminal, and a negative electrode power supply terminal, wherein the positive electrode power supply region and the negative electrode power supply region are joined to or in contact with the positive electrode power supply terminal, and the negative electrode power supply region and the negative electrode power supply terminal are joined to or in contact with each other, and at least one of the positive electrode power supply region and the negative electrode power supply region has an area larger than an area of an end portion of at least one of the positive electrode power supply terminal and the negative electrode power supply terminal.
Effects of the invention
According to the present invention, a semiconductor chip and a semiconductor chip module can be manufactured more easily.
Drawings
Fig. 1 is a diagram showing an example of a hardware configuration of a semiconductor chip according to an embodiment of the present invention.
Fig. 2 is a configuration diagram of an embodiment of the present invention, in which a coil 70 is applied as an example of the installation of the sensor unit S30 and the communication unit 40.
Fig. 3 is a block diagram showing a functional configuration of a semiconductor chip according to an embodiment of the present invention.
Fig. 4 is a block diagram showing a functional configuration of the semiconductor chip 103 according to an embodiment of the present invention.
Fig. 5 is a control flow chart illustrating a process flow according to an embodiment of the present invention.
Fig. 6 is a diagram showing a mounting example 1 in which a semiconductor chip according to an embodiment of the present invention is mounted on a substrate.
Fig. 7 is a diagram showing a mounting example 2 in which a semiconductor chip according to an embodiment of the present invention is mounted on a material.
Fig. 8 is a diagram showing a mounting example 3 in which a semiconductor chip according to an embodiment of the present invention is mounted on a material.
Fig. 9 is a diagram showing a mounting example 4 in which a semiconductor chip according to an embodiment of the present invention is mounted on a material.
Fig. 10 is a diagram showing one example of the structure of the semiconductor chip in mounting example 4 of the present invention.
Fig. 11 is a diagram showing another example of the structure of the semiconductor chip in the mounting example 4 of the present invention.
Fig. 12 is a configuration diagram of a semiconductor chip when a multi-level voltage is supplied to the semiconductor chip according to an embodiment of the present invention (mounting example 5).
Fig. 13 is a diagram showing a first mounting example (mounting example 5) when a semiconductor chip of one embodiment of the present invention is supplied with a voltage of a plurality of levels.
Fig. 14 is a diagram showing a mounting example 6 in which a semiconductor chip according to an embodiment of the present invention is mounted on a substrate.
Fig. 15 is a diagram showing a mounting example 7 in which a semiconductor chip according to an embodiment of the present invention is mounted on a substrate.
Fig. 16 is a diagram showing a mounting example 8 in which a semiconductor chip according to an embodiment of the present invention is mounted on a substrate.
Fig. 17 is a diagram showing a mounting example 9 in which a semiconductor chip according to an embodiment of the present invention is mounted on a substrate.
Fig. 18 is a diagram showing a mounting example 10 in which a semiconductor chip according to an embodiment of the present invention is mounted on a substrate.
Fig. 19 is a diagram showing a mounting example 11 in which a semiconductor chip according to an embodiment of the present invention is mounted on a substrate.
Fig. 20 is a flowchart showing a process for manufacturing a semiconductor chip module according to an embodiment of the present invention.
Fig. 21 is a diagram showing a mounting example 12 in which a semiconductor chip according to an embodiment of the present invention is mounted on a material.
Fig. 22 is a diagram showing a mounting example 13 in which a semiconductor chip according to an embodiment of the present invention is mounted on a material.
Fig. 23 is a diagram showing a mounting example 14 in which a semiconductor chip according to an embodiment of the present invention is mounted on a material.
Fig. 24 is a diagram showing a mounting example 15 of a semiconductor chip mounting material according to an embodiment of the present invention.
Fig. 25 is a diagram showing a mounting example 16 in which a semiconductor chip according to an embodiment of the present invention is mounted on a material.
Fig. 26 is a diagram (mounting example 17) illustrating a method of manufacturing a semiconductor module by a continuous conveyance method according to an embodiment of the present invention.
Fig. 27 is a diagram showing a configuration example when the communication chip 14 is employed.
Fig. 28 is a diagram illustrating a semiconductor module including the semiconductor chip 1a shown in the first embodiment and the semiconductor chip 1b according to the mounting example 17.
Fig. 29 is a diagram (installation example 18) showing an overall configuration example of an information processing apparatus according to an embodiment of the present invention.
Fig. 30 is a diagram showing an example of the hardware configuration of an information processing apparatus according to an embodiment of the present invention.
Fig. 31 is a block diagram showing a functional configuration of a semiconductor chip according to an embodiment of the present invention.
Fig. 32 is a control flowchart showing an operation of the information processing apparatus according to the embodiment of the present invention.
Fig. 33 is a diagram showing an example of a wireless signal communicated between semiconductor chips and a voltage value of a coil according to an embodiment of the present invention.
Fig. 34 is a diagram showing one example of information stored in the communication history storage section of the present invention.
Fig. 35 is a diagram showing one example of information stored in the measured value storage section of the present invention.
Fig. 36 is a diagram showing one example of information stored in the state quantity storage section of the present invention.
Fig. 37 is a diagram showing another example of the hardware configuration of the information processing apparatus according to the embodiment of the present invention.
Detailed Description
< Summary of the invention >
The following describes the embodiments of the present invention. The present invention has the following structure, for example.
[ Item 1]
A semiconductor chip comprising a processor, a coil for performing wireless communication with another semiconductor chip, a positive power supply terminal, and a negative power supply terminal, characterized in that,
The positive electrode power supply region and the negative electrode power supply region are joined to or abutted against the positive electrode power supply terminal, and the negative electrode power supply region and the negative electrode power supply terminal are joined to or abutted against each other,
At least one of the positive power supply region and the negative power supply region has an area larger than an area of an end of at least one of the positive power supply terminal and the negative power supply terminal.
[ Item 2]
The semiconductor chip according to item 1, wherein,
The positive power supply terminal and the negative power supply terminal are arranged on a first surface of one side of the semiconductor chip,
A positive electrode region and a negative electrode region of a release electrode are provided on a second surface of the semiconductor chip opposite to the first surface.
[ Item 3]
The semiconductor chip according to item 1, wherein,
The terminals of the semiconductor chip are composed of only the positive power supply terminal and the negative power supply terminal.
[ Item 4]
The semiconductor chip according to item 1, wherein,
Communication with other semiconductor chips is not performed via the positive power supply terminal and the negative power supply terminal, but is performed by wireless communication via the coil.
[ Item 5]
The semiconductor chip according to item 1, wherein,
The processor is disposed inside the coil.
[ Item 6]
The semiconductor module according to item 1, wherein,
The method further comprises: a positive electrode conductive portion that electrically connects the positive electrode power supply terminal and the positive electrode region; and a negative electrode conductive portion electrically connecting the negative electrode power supply terminal with the negative electrode region.
[ Item 7]
The semiconductor module according to item 5, wherein,
The first positive electrode power supply terminal and the first negative electrode power supply terminal are provided on a first surface on the material side, and a first positive electrode region where a positive electrode is exposed and a first negative electrode region where a negative electrode is exposed are provided on a second surface on the opposite side from the first surface.
[ Item 8]
The semiconductor module according to item 5, wherein,
The distance between the positive power supply region and the negative power supply region provided on the material is shorter than the distance between the positive power supply terminal and the negative power supply terminal.
[ Item 9]
The semiconductor module according to item 5, wherein,
The semiconductor chip includes the first positive electrode power supply terminal, the first negative electrode power supply terminal, a first positive electrode region where a positive electrode is exposed, and a first negative electrode region where a negative electrode is exposed, on a second surface opposite to the material.
[ Item 10]
The semiconductor module according to item 5, wherein,
The material is provided with: a first material having a positive power supply region connected to the positive power supply terminal of the semiconductor chip; and a second material having a negative power supply region connected to the negative power supply terminal of the semiconductor chip,
The first material and the second material are configured to clamp the plurality of semiconductor chips.
[ Item 11]
The semiconductor module according to item 5, wherein,
The material is provided with: and a power supply element that stores or generates power and supplies power via at least one of the positive power supply region and the negative power supply region.
[ Item 12]
The semiconductor module according to item 5, wherein,
The semiconductor chip includes: and an external communication unit that performs wireless communication with an external device external to the semiconductor module via the coil.
[ Item 13]
The semiconductor module according to item 5, wherein,
The semiconductor chip includes: and a power supply element that stores or generates power and supplies power via at least one of the positive power supply terminal and the negative power supply element.
[ Item 14]
A semiconductor module is characterized by comprising: the semiconductor chip of item 1; and
A sensor wired to the semiconductor chip,
The semiconductor chip communicates with the sensor through the wire.
[ Item 15]
A semiconductor module is characterized by comprising: a first semiconductor chip and a second semiconductor chip, which are the semiconductor chips of item 1;
and is provided with: a sensor wired to the first semiconductor chip,
The processor provided in the first semiconductor chip processes the signal received from the sensor, transmits the processed data to the coil of the second semiconductor chip through the coil by inductive coupling,
The processor provided in the second semiconductor chip performs processing based on the data received from the coil of the second semiconductor chip.
[ Item 16]
The semiconductor module according to item 15, wherein,
The positive power supply terminal of the first semiconductor chip and the positive power supply terminal of the second semiconductor chip are joined or abutted with the same positive power supply region,
The negative power supply terminal of the first semiconductor chip and the negative power supply terminal of the second semiconductor chip are joined or abutted with the same negative power supply region.
[ Item 17]
The semiconductor module according to item 15, wherein,
The width of the positive electrode power supply region and the negative electrode power supply region in the direction in which the first semiconductor chip and the second semiconductor chip are arranged is twice or more the width of the semiconductor chip.
[ Item 18]
The semiconductor module according to item 1, characterized by comprising a third semiconductor chip having:
A processor;
A coil for performing wireless communication; and
A positive power supply terminal and a negative power supply terminal that obtain driving power of the processor from outside the semiconductor chip,
The positive power terminal of the third semiconductor chip is connected with or abutted against the same positive power supply area,
The negative power supply terminal of the third semiconductor chip performs wireless communication by inductive coupling between the coil of the third semiconductor chip and the coil of the second semiconductor chip, which are joined or abutted to the same negative power supply region.
[ Project 19]
A semiconductor chip provided with a processor and a coil, characterized by comprising:
a communication unit that communicates with another semiconductor chip using the coil;
a measurement unit that acquires a measurement value corresponding to a state of the information processing apparatus using the coil; and
And a power receiving unit that obtains power consumed by the semiconductor chip using the coil.
[ Item 20]
The semiconductor chip of item 19, wherein,
The power receiving unit acquires electric power of a specific frequency band generated in the coil by an electromagnetic field generated by an external power supply device,
The communication section transmits an unmodulated wireless signal to the coil of another semiconductor chip in proximity to the semiconductor chip via a near field electromagnetic field.
[ Item 21]
The semiconductor chip according to item 19, comprising:
A calculation logic storage unit that stores calculation logic for calculating a state quantity indicating the state; and
And a calculation unit that calculates the state quantity from the measurement value according to the calculation logic.
[ Item 22]
The semiconductor chip of item 19, wherein,
The coil sends power to a coil outside the semiconductor chip.
[ Project 23]
The semiconductor chip of item 19, wherein,
The semiconductor device includes a positive power supply terminal and a negative power supply terminal, and obtains driving power of the processor from outside the semiconductor chip.
[ Item 24]
An information processing apparatus, comprising: the semiconductor chip of item 19; and
A power supply device which transmits power of a specific frequency band to the coil via an electromagnetic field,
The communication section transmits an unmodulated wireless signal to the coil of another semiconductor chip in proximity to the semiconductor chip via a near field electromagnetic field.
[ Project 25]
A semiconductor module is characterized by comprising: the semiconductor chip of item 19; and
A sensor wired to the semiconductor chip,
The semiconductor chip communicates with the sensor through the wire.
[ Item 26]
A semiconductor module is characterized by comprising: a first semiconductor chip and a second semiconductor chip, which are the semiconductor chips of item 19,
And is provided with: a sensor wired to the first semiconductor chip,
The processor provided in the first semiconductor chip processes the signal received from the sensor, transmits the processed data to the coil of the second semiconductor chip through the coil by inductive coupling,
The processor provided in the second semiconductor chip performs processing based on the data received from the coil of the second semiconductor chip.
[ Project 27]
A material to be bonded to or abutted against a semiconductor chip having a processor, a coil for performing wireless communication with another semiconductor chip, a positive electrode power supply terminal and a negative electrode power supply terminal, characterized in that,
Comprises a positive electrode power supply region and a negative electrode power supply region,
The positive power supply area is connected with or abutted against the positive power terminal,
The negative power supply region is engaged or abutted with the negative power terminal,
At least one of the positive power supply region and the negative power supply region has an area larger than an area of an end of at least one of the positive power supply terminal and the negative power supply terminal.
< Hardware >
Fig. 1 is a diagram showing an example of a hardware configuration of a semiconductor chip according to an embodiment of the present invention. The semiconductor chip 1 includes a processor 10, a sensor unit S30, and a communication unit 40, and the processor 10 includes a memory 20. The sensor S30 measures a measurement value corresponding to the environment in which the semiconductor chip is provided. The processor 10 receives the measured value measured by the sensor S30 and records the measured value in the memory 20, and gives the measured value to the calculation logic to calculate the environmental value. The environment value is a value indicating the state of the environment in which the semiconductor chip is provided. The processor 10 records the calculated environment value to the memory 20. The semiconductor chip 1 further has a power supply line D60 for supplying power from the external power supply D50 to the processor 10, the sensing section S30, and the communication section 40.
Fig. 2 shows an example of a hardware configuration in which the coil 70 is used as an example of the mounting of the sensor section S30 and the communication section 40. In the example shown in fig. 2, an example is shown in which semiconductor chips are used in pairs, the semiconductor chips being provided with: a processor (10 a,10 b); a memory (20 a,20 b) disposed within the processor; transceiver circuitry (80 a,80 b) communicatively coupled to the processor; a coil (70 a,70 b) connected to the transceiver circuit; a first power supply terminal (61 a, 61 b) on the negative electrode side for supplying power to the processor and the transceiver circuit; and second power supply terminals (62 a, 62 b) on the positive electrode side.
Two semiconductor chips (1 a,1 b) disposed adjacently shown in fig. 2 are provided with coils (70 a,70 b) and transmitting/receiving circuits (80 a,80 b) for generating signals flowing to the coils, respectively, so that signals can be transmitted/received to/from the coils 70 of the other semiconductor chips adjacent to each other by inductive coupling.
The semiconductor chip (1 b) further includes an external communication unit capable of transmitting and receiving signals to and from the external device 90 by wireless communication such as inductive coupling via the coil (70 b). As one example, an environmental value request signal described below can be received and the latest environmental value detected by the semiconductor module, history of environmental values, can be transmitted. Among them, the semiconductor chip (1 b) has a function of communicating with an external device external to the semiconductor module through an external communication section, and therefore, it is desirable to have the same or larger communication range than the semiconductor chip (1 a) communicating with an adjacent semiconductor chip. Therefore, the coil (70 b) mounted on the semiconductor chip (1 b) may be configured to have a larger number of turns than the coil (70 a) of the semiconductor chip (1 a), and the transmitting/receiving circuit (80 b) mounted on the semiconductor chip (1 b) may be configured to have a larger voltage or current output to the coil than the transmitting/receiving circuit (80 a) of the semiconductor chip (1 a).
In addition, since the relative distance and the relative angle between the coils (70 a,70 b) of the two semiconductor chips are changed, the coupling strength of the inductive coupling is changed, and the voltage value or the amplitude value of the voltage generated in the coils is changed. In the present embodiment, the transceiver circuit detects a voltage value or an amplitude value of a voltage generated in the coil, and the processor 10 acquires the detected voltage value or amplitude value of the voltage as a measured value, and can calculate an environmental change in which a relative distance and a relative angle between the semiconductor chips are changed as an environmental value. The memory 20 records the calculated environmental value.
The semiconductor chip of the present embodiment stores calculation logic for each of a plurality of environmental value types, and can calculate environmental values of a plurality of types from the same measurement value. The semiconductor chip can calculate environmental values of different types from the measured values (voltages measured by the coils 70) of the same sensor by using calculation logic corresponding to the specified type. Further, by inseparably mounting the processor, the sensing section, and the communication section shown in fig. 1 on the semiconductor chip, the semiconductor chip in the present embodiment can be constituted by a CPU. The diameter of the semiconductor chip at this time can be made, for example, about 0.3mm, and the semiconductor chip can be miniaturized. In addition, the size is not limited to this. For example, the processor, the sensing section, and the communication section may be inseparably mounted on a semiconductor chip (on a single chip). Among them, a semiconductor chip is defined as a small piece of silicon (silicon wafer or wafer) on which an electronic circuit is mounted. Or may be defined as a package in which a silicon wafer is packaged, as the case may be.
Software
Fig. 3 is a block diagram showing a functional configuration of a semiconductor chip. As shown in fig. 3, the semiconductor chip is configured to include an acquisition section 111, a calculation section 112, a transmission section 113, a reception section 114, a logic storage section 131, an environment value storage section 132, and a condition storage section 133.
The logic storage 131 stores calculation logic. The logic storage unit 131 of the present embodiment stores the calculation logic for each type of environment value. The logic storage unit 131 stores calculation logic in association with the type of the environment value. As described above, the calculation logic includes an algorithm that calculates the environmental value based on the measured value. The measured value is a voltage value generated in the coil or an amplitude value of the voltage detected by the transmitting/receiving circuit, and in the present embodiment, the measured value may be, for example, a voltage value generated in the coil. The environmental value is a value related to the environment in which the sensor chip is placed, and may be, for example, temperature, vibration, pressure, electromagnetic wave, volume, humidity, or the like. For example, when the positional relationship between two sensor chips is changed, the voltage generated in the coil or the amplitude of the voltage is changed. Furthermore, it is known that the change in the positions of two sensor chips is caused by: temperature, pressure, humidity, etc. around the sensor chip; vibrations such as sound, electromagnetic waves, etc. applied from outside the sensor chip; and vibration of an object in which the sensor chip is embedded, arranged, or attached, the temperature, vibration, pressure, electromagnetic wave, volume, humidity, and the like can be calculated by processing the voltage or the change in voltage of the coil due to the change in the relative positional relationship of the sensor chip by appropriate calculation logic.
The environment value storage 132 stores an environment value. The environment value storage unit 132 of the present embodiment stores the history of the environment values by category. The environment value storage unit 132 includes information such as the type of the environment value, and the time point (time stamp) at which the calculation is performed, but is not limited thereto. The time stamp may also be the point in time when the measured value was measured.
The condition storage unit 133 stores information for determining which type of environment value is calculated. The condition storage unit 133 of the present embodiment stores the type of the environmental value that can be calculated when the condition is satisfied in association with the condition related to the phenomenon that can be obtained by the semiconductor chip. A plurality of pairs of conditions and types of environment values may be registered. The condition storage unit 133 may store the type of the environmental value calculated without the condition. In addition, the condition storage unit 133 may store one or more types of computable environment values without setting the condition.
The acquisition unit 111 acquires a measurement value measured by a sensor unit (coil) included in the semiconductor chip. The acquisition unit 111 of the present embodiment can acquire the value of the voltage generated in the coil 30 as the measured value.
The calculation unit 112 calculates an environment value. The calculating unit 112 can calculate the environmental value from the measured value according to the calculation logic corresponding to the set type. The calculation unit 112 can, for example, specify the type corresponding to the condition satisfied among the conditions stored in the condition storage unit 133, read the calculation logic corresponding to the specified type from the logic storage unit 131, and assign the measured value acquired by the acquisition unit 111 to the read calculation logic to calculate the environment value.
Furthermore, the calculation section 112 can also calculate, from the measured values acquired from the coils 30, environmental values of a first kind in accordance with a first calculation logic, and environmental values of a second kind in accordance with a second calculation logic different from the first calculation logic. For example, the calculation unit 112 can calculate the humidity and the temperature by giving the measured value to calculation logic corresponding to the temperature and also giving calculation logic corresponding to the humidity.
The calculation unit 112 can calculate the corresponding environment value according to the measurement logic that meets the condition. The calculation unit 112 can determine whether or not, for example, time information obtainable from a clock (not shown), a measured value obtained from the coil 70, or the like satisfies the condition stored in the condition storage unit 133, and when the satisfied condition exists, it identifies the type corresponding to the satisfied condition, reads the calculation logic corresponding to the identified type from the logic storage unit 131, and calculates the environment value using the read calculation logic.
The receiving section 114 receives a signal from outside the semiconductor chip. For example, identification information of the semiconductor chip (1 b) and information of an environmental value measured by the semiconductor chip (1 b) can be received from the adjacent semiconductor chip (1 b). Further, an environment value request signal requesting output of the environment value stored in the environment value storage unit can be received.
Fig. 4 is a block diagram showing a functional configuration of the semiconductor chip 1b which communicates with the outside. The semiconductor chip 1b includes an external communication unit 120 and an external request storage unit 134 in addition to the functional units of the semiconductor chip 1 shown in fig. 3. The external communication unit 120 further includes an external transmitting unit 121 and an external receiving unit 122.
The external receiving unit 122 receives a signal such as an environment value request signal from the external device 90. Further, the external transmitting section 121 transmits a signal related to the environmental value detected by the semiconductor module to the external device 90. The external communication unit 120 including the external transmission unit 121 and the external reception unit 122 may be configured to share hardware such as a transmission/reception circuit with the coils configuring the transmission unit 113 and the reception unit 114.
The external request storage unit 134 stores the environment value request signal received from the external device 90 by the external receiving unit 122. The stored environment value request signal is transmitted to the adjacent semiconductor chip 1 via the transmitting section 113.
Action
Fig. 5 is a control flow chart illustrating a process flow according to an embodiment of the present invention.
In the semiconductor chip, the acquisition unit 111 acquires a measurement value (in this embodiment, the voltage of the coil 70) measured by the sensor (S141). Thereafter, the calculation unit 112 identifies the type of the environmental value corresponding to the condition that has been satisfied among the conditions stored in the condition storage unit 133, the logic storage unit 131 identifies the calculation logic corresponding to the identified type (S142), the measurement value is given to the identified calculation logic to calculate the environmental value (S143), and the calculated environmental value is registered in the environmental value storage unit 132 in association with the type of the environmental value and the time stamp (S144).
When the transmission unit 113 receives the environment value request signal from the external device (yes in S145), it transmits the environment value registered in the environment value storage unit 132 to the external device (S146). The transmitting unit 113 may transmit the latest environment value or may transmit a part or all of the environment value history.
A specific example of mounting the semiconductor chip 1 on the substrate 100 will be described below. In order to mount a plurality of semiconductor chips 1 on the substrate 100 and to make each semiconductor chip 1 function, it is necessary to perform necessary communication between the semiconductor chips 1 and to supply electric power to each semiconductor chip 1. In each mounting example described later, a specific example of a mounting structure that realizes communication and power supply in the plurality of semiconductor chips 1 will be described. Wherein the communication does not include a power supply (e.g., wireless power supply).
Mounting example 1
Fig. 6 is a diagram showing a first mounting example in which the semiconductor chip 1 of the present embodiment is mounted on the substrate 100. Fig. 6a shows a side view and fig. 6b shows a plan view. As shown in fig. 6, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side of the substrate 100. The plurality of semiconductor chips (1 a, 1 b) are arranged on one side of the substrate 100, and the power supply terminal (61) on the negative electrode side of the semiconductor chip is joined to the power supply region (51) on the negative electrode side, and the power supply terminal (62) on the positive electrode side of the semiconductor chip is joined to the power supply region (52) on the positive electrode side.
The semiconductor chip 1 can receive power supply from the substrate 100 via the power supply terminals (61, 62) of the negative and positive electrodes, and can perform wireless communication with other semiconductor chips 1 via the communication section constituted by the coil 70 and the like, so that wiring connected between the substrate 100 and the semiconductor chip 1 does not need other wiring than the power supply line, and conventional wiring of about several thousands can be greatly reduced. Therefore, the connection work between the substrate 100 and the semiconductor chip 1 can be simplified, and in addition, a deformable material can be used as the substrate 100.
In the example shown in fig. 6, two negative-side power supply terminals (61) and two positive-side power supply terminals (62) are provided on each semiconductor chip 1, and therefore, even when one of the two negative-side power supply terminals 61a of the semiconductor chip 1a is not in contact with the negative-side power supply region (51) due to, for example, defects in the bonding operation at the time of manufacture or deformation of the flexible substrate 100, the semiconductor chip can obtain electric power via the other negative-side power supply terminal 61 a. However, there are not necessarily two power supply terminals, but three or more power supply terminals may be provided, or only one power supply terminal may be provided.
The power supply regions 51 and 52 provided on the substrate 100 are regions where the positive electrode or the negative electrode is exposed, and the power supply terminals in contact with the power supply regions 51 and 52 can obtain power supply via the power supply regions 51 and 52. The negative-side power supply region (51) and the positive-side power supply region (52) can be realized by, for example, a conductive film or a conductive plate provided on the surface of the substrate 100. Alternatively, when the substrate 100 has a laminate structure of a conductor and a non-conductor, the substrate may be realized by the conductor layer. As shown in the plan view of fig. 6b, the power supply region (51) on the negative electrode side and the power supply region (52) on the positive electrode side are provided at positions adjacent to each other with a certain distance (400) therebetween so as not to be in contact with each other. Wherein at least one of the positive electrode power supply region 52 and the negative electrode power supply region 51 is formed to have an area larger than an area of an end portion of at least one of the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61. With this configuration, in the manufacturing process of the semiconductor module, that is, in the process of connecting the substrate 100 and the semiconductor chip 1, the connection of the power supply regions 51 and 52 and the power supply terminals 61 and 62 can be more easily performed even if the positioning accuracy is poor. Further, it is preferable that a distance (400) between the positive power supply region 52 and the negative power supply region 51 provided in the substrate 100 is smaller than a distance (200) between the positive power supply terminal 62 and the negative power supply terminal 61 of the semiconductor chip (1 a, 1 b). With this configuration, the degree of freedom in the arrangement position of the semiconductor chip 1 is improved in the up-down direction of fig. 6.
The length (500) of the short side of each power supply region 51, 52 is larger than the width of the power supply terminal (61, 62). With this configuration, in the step of connecting the substrate 100 and the semiconductor chip 1, even if the positioning accuracy in the short side direction of the power supply regions 51, 52 is poor, the connection of the power supply regions 51, 52 and the power supply terminals 61, 62 can be smoothly performed. For example, as shown in fig. 6b, even when the orientation of the semiconductor chip 1a is rotated by about 10 degrees relative to the substrate or the other semiconductor chip 1b, the semiconductor chip 1 is connected to the substrate 100 by a power line, and wireless communication with the semiconductor chip 1b is not affected, so that difficulty in positioning the semiconductor chip 1 during manufacturing can be reduced, and manufacturing cost can be reduced. In particular, when a semiconductor module is manufactured by connecting a semiconductor chip 1 having a side length of 1mm or less and 0.5mm or less to a substrate 100, a high positioning accuracy is required to align the power supply regions 51 and 52 with the power supply terminals 61 and 62, and therefore, generally, the manufacturing cost is very high. In this case, as in the present invention, by making the area of at least one of the positive electrode power supply region 52 and the negative electrode power supply region 51 larger than the area of at least one end portion of the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61, a semiconductor module can be manufactured even if the positioning accuracy is low. The present invention can be applied to all semiconductor modules regardless of the size of the semiconductor module, but the present invention is particularly effective when applied to a small semiconductor chip having a side length of 1mm or less than 0.5mm and a semiconductor module using the same.
When a semiconductor chip having a length of one side of 1mm is used, for example, the width of the end portions of the positive electrode and negative electrode power supply terminals may be set to about 0.1mm to 0.3mm, the distance (200) between the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61 may be set to about 0.3 to 0.7mm, the distance (400) between the positive electrode power supply region 52 and the negative electrode power supply region 51 may be set to about 0.1 to 0.6mm, the width (500) in the longitudinal directions of the positive electrode power supply region 52 and the negative electrode power supply region 51 may be set to 0.2mm or more, and the width (300) in the transverse directions of the positive electrode power supply region 52 and the negative electrode power supply region 51 (the directions in which a plurality of chips are arranged) may be set to 2.1mm or more.
As the intervals of the plurality of pins (terminals) of the general semiconductor chip 1, a full pitch of 1/10 inch (2.54 mm), a half pitch of 1/20 inch (1.27 mm), a 1/4 pitch of 1/40 inch (0.635 mm) and even 1/8 pitch of 1/80 inch (0.3175 mm) are known, and it is expected that practical use will be made. Therefore, the distance (200) between the current positive power supply terminal and the negative power supply terminal needs to be 0.3mm or more, and if the widths of the positive power supply terminal 62 and the negative power supply terminal 61 are included, the length of one side of the semiconductor chip 1 needs to be 0.5mm or more. On the other hand, when the distance (400) between the positive electrode power supply region 52 and the negative electrode power supply region 51 is too short, the risk of short-circuiting increases, and therefore, it is necessary to make the distance (400) between the regions 0.1mm or more at the minimum. In the semiconductor module manufacturing process, it is preferable to allow a deviation of about 0.1mm as the positioning accuracy of the semiconductor chip 1. Therefore, the distance (400) between the positive electrode power supply region 52 and the negative electrode power supply region 51 is preferably set to a value of 0.1mm or more and less than the distance (200) between the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61. The specific dimensions described above are only one example of a mounting to which the present invention is applied, and the present invention is not limited to these specific dimensions.
Mounting example 2
Fig. 7 is a diagram showing a mounting example 2 in which the semiconductor chip of the present embodiment is mounted on a material. Fig. 7a shows a side view and fig. 7b shows a plan view. As shown in fig. 7, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on the side of the substrate 100, which is the material 100 on which the semiconductor chip is mounted. The plurality of semiconductor chips (1 a, 1 b) are disposed on one side of the material 100, and the power supply terminal (61) on the negative electrode side of the semiconductor chip is joined to the power supply region (51) on the negative electrode side, and the power supply terminal (62) on the positive electrode side of the semiconductor chip is joined to the power supply region (52) on the positive electrode side.
Further, a power source element 101 capable of generating or storing electric power is mounted on the material 100, and the power source element 101 is capable of supplying electric power to each semiconductor chip via the power source supply regions (51, 52) of the negative and positive electrodes and the power source terminals (61, 62). The power source element 101 may be configured by a power generation element that generates power such as solar power generation and vibration power generation, or a power storage element including a primary battery and a secondary battery that store power such as a lithium ion battery and a lead battery. The semiconductor chips can communicate with each other wirelessly via a communication unit including the coil 70 and the like. Further, at least any one of the plurality of semiconductor chips is provided as the semiconductor chip 103 having an external communication function capable of wirelessly communicating with an external device, so that the semiconductor module including the semiconductor chip and the material can wirelessly communicate with the external device. With this configuration, the wiring connected between the material and the semiconductor chip does not need other wiring than the power supply line, and the number of wiring lines in the past can be significantly reduced by about several thousand. Therefore, the connection work between the material and the semiconductor chip can be simplified, and the semiconductor chip can be mounted on the deformable material.
In the example shown in fig. 7, two power supply terminals (61) on the negative electrode side and two power supply terminals (62) on the positive electrode side are provided on each semiconductor chip, and therefore, even in the case where one of the two power supply terminals 61a on the negative electrode side of the semiconductor chip 1a is not in contact with the power supply region (51) on the negative electrode side due to, for example, defects in the bonding work at the time of manufacture or deformation of a soft material, the semiconductor chip can obtain electric power via the other power supply terminal 61a on the negative electrode side. However, there are not necessarily two power supply terminals, but three or more power supply terminals may be provided, or only one power supply terminal may be provided.
The power supply region provided on the material is a region where the positive electrode or the negative electrode is exposed, and the power supply terminal in contact with the power supply region can obtain power supply via the power supply region. The negative-side power supply region (51) and the positive-side power supply region (52) can be realized by, for example, a conductive film or a conductive plate provided on the surface of the material. Or may be realized by the conductor layer when the material is made into a laminate structure of a conductor and a non-conductor. As shown in the plan view of fig. 7b, the power supply region (51) on the negative electrode side and the power supply region (52) on the positive electrode side are provided at positions adjacent to each other with a certain distance (400) therebetween so as not to be in contact with each other. Wherein at least one of the positive power supply region and the negative power supply region is formed to have an area larger than an area of an end portion of at least one of the positive power supply terminal and the negative power supply terminal. With this configuration, in the manufacturing process of the semiconductor module, that is, in the process of connecting the material and the semiconductor chip, the connection between the power supply region and the power supply terminal can be more easily performed even if the positioning accuracy is poor. Further, it is preferable that a distance (400) between the positive power supply region and the negative power supply region of the material is smaller than a distance (200) between the positive power supply terminal and the negative power supply terminal of the semiconductor chip (1 a, 1 b). With this configuration, the degree of freedom in the arrangement position of the semiconductor chip is improved in the up-down direction of fig. 7.
The length (500) of the short side of each power supply region is larger than the width of the power supply terminals (61, 62). With this configuration, in the step of connecting the material to the semiconductor chip, the connection between the power supply region and the power supply terminal can be smoothly performed even if the positioning accuracy in the short side direction of the power supply region is poor. For example, as shown in fig. 7b, even when the orientation of the semiconductor chip 1a is rotated by about 10 degrees relative to the material or the other semiconductor chip 103, the connection with the material via the power line does not affect the wireless communication with the semiconductor chip 1b, and therefore, the difficulty in positioning the semiconductor chip at the time of manufacturing can be reduced, and the manufacturing cost can be reduced. In particular, when a semiconductor module is manufactured by connecting a semiconductor chip having a side length of 1mm or less and 0.5mm or less to a material, a high positioning accuracy is required to align a power supply region with a power supply terminal, and therefore, generally, the manufacturing cost is very high. In this case, as in the present invention, the area of at least one of the positive electrode power supply region and the negative electrode power supply region is made larger than the area of at least one end portion of the positive electrode power supply terminal and the negative electrode power supply terminal, so that the semiconductor module can be manufactured even if the positioning accuracy is low. The present invention can be applied to all semiconductor modules regardless of the size of the semiconductor module, but the present invention is particularly effective when applied to a small semiconductor chip having a side length of 1mm or less than 0.5mm and a semiconductor module using the same.
When a semiconductor chip having a length of one side of 1mm is used, for example, the width of the end portions of the positive electrode and negative electrode power supply terminals may be set to about 0.1mm to 0.3mm, the distance (200) between the positive electrode power supply terminals and the negative electrode power supply terminals may be set to about 0.3 to 0.7mm, the distance (400) between the positive electrode power supply region and the negative electrode power supply region may be set to about 0.1 to 0.6mm, the width (500) in the longitudinal directions of the positive electrode power supply region and the negative electrode power supply region may be set to 0.2mm or more, and the width (300) in the transverse directions of the positive electrode power supply region and the negative electrode power supply region (the direction in which the plurality of chips are arranged) may be set to 2.1mm or more.
As the intervals of a plurality of pins (terminals) of a general semiconductor chip, a full pitch of 1/10 inch (2.54 mm), a half pitch of 1/20 inch (1.27 mm), a 1/4 pitch of 1/40 inch (0.635 mm) and even 1/8 pitch of 1/80 inch (0.3175 mm) are known, and it is expected that practical use will be made. Therefore, the distance (200) between the current positive power supply terminal and the negative power supply terminal needs to be 0.3mm or more, and if the width of the positive power supply terminal and the negative power supply terminal is included, the length of one side of the semiconductor chip needs to be 0.5mm or more. On the other hand, when the distance (400) between the positive electrode power supply region and the negative electrode power supply region is too short, the risk of short circuit increases, and therefore, it is necessary to make the distance (500) between the regions 0.1mm or more at the minimum. In the semiconductor module manufacturing process, it is preferable to allow a deviation of about 0.1mm as the positioning accuracy of the semiconductor chip. Therefore, the distance (400) between the positive power supply region and the negative power supply region is preferably set to a value of 0.1mm or more and less than the distance (200) between the positive power supply terminal and the negative power supply terminal. The specific dimensions described above are only one example of a mounting to which the present invention is applied, and the present invention is not limited to these specific dimensions.
Mounting example 3
Fig. 8 is a diagram showing a mounting example 3 in which the semiconductor chip of the present embodiment is mounted on a material. Fig. 8a shows a side view and fig. 8b shows a plan view. As shown in the plan view of fig. 8, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side of the material 100. The plurality of semiconductor chips (1 a, 103, 1c, 1 d) are disposed on one side of the material 100, and the power supply terminal (61) on the negative electrode side of the semiconductor chip is joined to the power supply region (51) on the negative electrode side, and the power supply terminal (62) on the positive electrode side of the semiconductor chip is joined to the power supply region (52) on the positive electrode side. In this case, unlike the mounting example 2 shown in fig. 7, on one side of the material 100, the power supply regions (51) on the negative side and the power supply regions (52) on the positive side are alternately provided at a plurality of positions, respectively. Therefore, by disposing the semiconductor chip at an arbitrary position on the boundary between the negative-electrode-side power supply region (51) and the positive-electrode-side power supply region (52), power can be obtained from the material, and the degree of freedom in disposing the semiconductor chip on the material can be improved.
Further, a power source element 101 capable of generating or storing electric power is mounted on the material 100, and the power source element 101 is capable of supplying electric power to each semiconductor chip via the power source supply regions (51, 52) of the negative and positive electrodes and the power source terminals (61, 62). The semiconductor chips can communicate with each other wirelessly via a communication unit including the coil 70 and the like. Further, at least any one of the plurality of semiconductor chips is provided as the semiconductor chip 103 having an external communication function capable of wirelessly communicating with an external device, so that the semiconductor module including the semiconductor chip and the material can wirelessly communicate with the external device. With this configuration, the wiring connected between the material and the semiconductor chip does not need other wiring than the power supply line, and the number of wiring lines in the past can be significantly reduced by about several thousand. Therefore, the connection work between the material and the semiconductor chip can be simplified, and the semiconductor chip can be mounted on the deformable material.
Mounting example 4
Fig. 9 is a diagram showing a mounting example 4 in which the semiconductor chip of the present embodiment is mounted on a material. Fig. 9a shows a side view and fig. 9b shows a plan view. Further, fig. 10 is a diagram showing a hardware configuration of the semiconductor chip in mounting example 4. As shown in the plan view of fig. 9, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side of the material 100. The plurality of semiconductor chips (102, 103) are disposed on one side of the material (100), and the power supply terminal (61) on the negative electrode side of the semiconductor chip is joined to the power supply region (51) on the negative electrode side, and the power supply terminal (62) on the positive electrode side of the semiconductor chip is joined to the power supply region (52) on the positive electrode side.
In the mounting example 4, the power supply element 101 is not mounted on the material side but mounted on the semiconductor chip 102, and the power supply element 101 supplies power to the processor and the transceiver circuit in the semiconductor chip 102, and supplies power to the material side via the power supply terminals (61, 62), and further supplies power to the other semiconductor chips 103 mounted on the material via the power supply regions (51, 52) provided on the material side. Further, the semiconductor chips are in wireless communication with each other via a communication section including the coil 70 or the like, and at least any one of the semiconductor chips is provided as a semiconductor chip 103 having an external communication function capable of performing wireless communication with an external device, so that the semiconductor module including the semiconductor chip and the material can perform wireless communication with the external device. With this configuration, the wiring connected between the material and the semiconductor chip does not need other wiring than the power supply line, and the number of wiring lines in the past can be significantly reduced by about several thousand. Therefore, the connection work between the material and the semiconductor chip can be simplified, and the semiconductor chip can be mounted on the deformable material.
Fig. 11 is a hardware configuration diagram showing other examples of the installation example 4. As shown in fig. 11, the semiconductor chip 102 including the power source element 101 does not necessarily need to have the same function as the semiconductor chip 1, but may be configured to include a structure necessary for supplying electric power to the material side, that is, the power source element 101 and the power source terminals (61, 62), without including a processor, a transceiver circuit, and a coil. In this case, the power supplied from the semiconductor chip 102 is supplied to the other semiconductor chip 1, 103 via the material-side power supply region (51, 52).
Mounting example 5
Fig. 12 and 13 illustrate an example of mounting of supplying voltages of multiple levels to the semiconductor chip 1. Fig. 12 shows a hardware configuration to which the coil 70 is applied as an example of the mounting of the sensing section S30 and the communication section 40, that is, a configuration example different from fig. 2. The difference from the example shown in fig. 2 is that the power supply terminals are constituted by three kinds of negative power supply terminals 61, first positive power supply terminals (low voltage) 62, and second positive power supply terminals (high voltage) 63. The first positive electrode power supply terminal 62 is connected to a power supply that supplies, for example, 3V voltage, and the second positive electrode power supply terminal 63 is connected to a power supply that supplies, for example, 5V voltage higher than the first positive electrode power supply terminal 62. The negative power supply terminal 61 is a common power supply terminal connected to both the processor and the transceiver circuit, the first positive power supply terminal 62 is connected to a functional unit (e.g., a processor) requiring a low voltage power supply, and the second positive power supply terminal 63 is connected to a functional unit (e.g., a transceiver circuit) requiring a higher voltage power supply.
Fig. 13 is a diagram showing a mounting example 5 in which the semiconductor chip 1 of the present embodiment is mounted on the substrate 100. As shown in the plan view of fig. 13, a negative-side power supply region (51), a positive-side first power supply region (52), and a positive-side second power supply region (53) are provided on one side of the substrate 100. The plurality of semiconductor chips (1 a, 1 b) are arranged on one side of the substrate 100, the power supply terminal (61) on the negative electrode side of the semiconductor chip is joined to the power supply region (51) on the negative electrode side, the first power supply terminal (62) on the positive electrode side of the semiconductor chip is joined to the first power supply region (52) on the positive electrode side, and the second power supply terminal (63) on the positive electrode side of the semiconductor chip is joined to the second power supply region (53) on the positive electrode side. The first power supply region (52) on the positive electrode side is connected to a power supply for supplying a voltage of 3V, for example, and the second power supply region (53) on the positive electrode side is connected to a power supply for supplying a voltage of 5V higher than the first power supply region (52), for example.
Even when the semiconductor chip 1 requires a plurality of voltages as in the mounting example shown in fig. 12 and 13, the power supply regions (51, 52, 53) corresponding to the respective voltages are provided on the substrate 100 as shown in fig. 13, whereby the difficulty in positioning the semiconductor chip at the time of manufacturing can be reduced and the manufacturing cost can be reduced.
Mounting example 6
Fig. 14 is a diagram showing a mounting example 6 in which the semiconductor chip of the present embodiment is mounted on the substrate 100. As shown in the plan view of fig. 14, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side of the substrate 100. The plurality of semiconductor chips (1 a, 1 b) are arranged on one side of the substrate 100, and the power supply terminal (61) on the negative electrode side of the semiconductor chip is joined to the power supply region (51) on the negative electrode side, and the power supply terminal (62) on the positive electrode side of the semiconductor chip is joined to the power supply region (52) on the positive electrode side. In this case, unlike the mounting example 1 shown in fig. 6, on one side of the substrate 100, the power supply regions (51) on the negative side and the power supply regions (52) on the positive side are alternately provided at a plurality of positions, respectively. Therefore, by disposing the semiconductor chip at an arbitrary position on the boundary between the negative-electrode-side power supply region (51) and the positive-electrode-side power supply region (52), power can be obtained from the substrate 100, and the degree of freedom in disposing the semiconductor chip 1 on the substrate 100 can be improved.
Mounting example 7
Fig. 15 is a diagram showing a mounting example 7 in which the semiconductor chip 1 of the present embodiment is mounted on the substrate 100. As shown in the plan view of fig. 15, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side of the substrate 100. The plurality of semiconductor chips (1 a, 1b, 1c, 1d, 1e, 1 f) are arranged on one side of the substrate 100, and the power supply terminal (61) on the negative electrode side of the semiconductor chip is joined to the power supply region (51) on the negative electrode side, and the power supply terminal (62) on the positive electrode side of the semiconductor chip is joined to the power supply region (52) on the positive electrode side. Unlike the mounting example 6 shown in fig. 14, the negative-side power supply region (51) and the positive-side power supply region (52) are adjacently disposed at positions on the substrate 100 such that they do not contact each other at a predetermined distance (400), one of which is located inside the other and the other of which surrounds the periphery of one of the regions. Therefore, by disposing the semiconductor chip 1 at an arbitrary position on the boundary between the negative-side power supply region (51) and the positive-side power supply region (52), power can be obtained from the substrate 100, and the degree of freedom in disposing the semiconductor chip 1 on the substrate 100 can be improved.
Mounting example 8
Fig. 16 is a diagram showing a mounting example 8 in which the semiconductor chip 1 of the present embodiment is mounted on the substrate 100. Fig. 16a shows a side view, fig. 16b shows a cross-sectional view A-A, and fig. 16c shows a plan view. As shown in fig. 16, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side (upper side) of the substrate 100. The semiconductor chip (1 e) is disposed on one side (upper side) of the substrate 100, and the power supply terminal (61 e) on the negative side of the semiconductor chip (1 e) is joined to the power supply region (51) on the negative side of the substrate, and the power supply terminal (62 e) on the positive side of the semiconductor chip (1 e) is joined to the power supply region (52) on the positive side of the substrate 100. Unlike the above-described mounting example, the semiconductor chip (1 e) in contact with the substrate 100 via the power supply region is provided with a negative electrode region (91) exposing the electrode on the negative electrode side and a positive electrode region (92) exposing the electrode on the positive electrode side on the chip upper side opposite to the chip lower side provided with the power supply terminals (61 e, 62 e). The negative electrode region (91) and the positive electrode region (92) are disposed adjacent to each other with a predetermined distance (400) therebetween so as not to contact each other. The negative electrode region (91) of the semiconductor chip (1 e) is electrically connected to a negative electrode power supply terminal (61 e) via a negative electrode conductive portion (65) provided in the semiconductor chip (1 e), and the positive electrode region (92) of the semiconductor chip (1 e) is electrically connected to a power supply terminal (62 e) via a positive electrode conductive portion (65) provided in the semiconductor chip (1 e) and to a power supply of the substrate.
Further, semiconductor chips (1 f, 1 g) are provided on the upper side of the semiconductor chip (1 e), and power supply terminals (61 f, 61 g) on the negative side of the semiconductor chips (1 f, 1 g) are bonded to a negative electrode region (91) of the semiconductor chip (1 e), and power supply terminals (62 f, 62 g) on the positive side of the semiconductor chips (1 f, 1 g) are bonded to a positive electrode region (92) of the semiconductor chip (1 e). In this way, even when the semiconductor chips are arranged in a plurality of layers on the substrate, the semiconductor chips (1 f, 1 g) which are not in direct contact with the substrate can obtain electric power from the substrate via the semiconductor chip (1 e) which is in direct contact with the substrate. Further, the semiconductor chips (1 e, 1f, 1 g) are adjacent to each other, and therefore can communicate with each other through the communication section 40 constituted by the coil 70 and the like. Therefore, the degree of freedom in the arrangement of the semiconductor chips when the information processing apparatus is manufactured from a plurality of semiconductor chips is increased without directly contacting a part of the semiconductor chips with the substrate.
Mounting example 9
Fig. 17 is a diagram showing a mounting example 9 in which the semiconductor chip 1 of the present embodiment is mounted on the substrate 100. Fig. 17a shows a side view and fig. 17B shows a B-B cross-sectional view. As shown in fig. 17, semiconductor chips (1 h, 1i, 1j, 1 k) are provided at positions sandwiched by a plurality of substrates (100 a,100 b) from both sides. The upper surface (surface on the semiconductor chip 1 side) of the lower substrate 100a is provided with a negative-electrode-side power supply region (51). On the other hand, a power supply region (52) on the positive electrode side is provided on the lower surface (surface on the semiconductor chip 1 side) of the upper substrate 100 b. The semiconductor chips (1 h, 1i, 1j, 1 k) disposed between the substrates 100a,100b have negative-side power supply terminals (61) on one side and positive-side power supply terminals (62) on the other side, respectively.
The semiconductor chips (1 h, 1i, 1j,1 k) are held between the two substrates (100 a,100 b) in a state in which the power supply terminal (61) on the negative electrode side is in contact with the power supply region (51) of the substrate (100 a) and the power supply terminal (62) on the positive electrode side is in contact with the power supply region (52) of the substrate (100 b), so that power can be supplied from the respective substrates (100 a,100 b). Further, the power supply region (51) on the negative electrode side and the power supply region (52) on the positive electrode side are provided on the substrate 100a and the substrate 100b, respectively, so that it is not necessary to provide two power supply regions of the positive electrode and the negative electrode on one substrate, and furthermore, it is not necessary to provide a space between the power supply regions (51, 52), so that the power supply regions (51, 52) can be provided on almost the entire surfaces of the substrates (100 a,100 b). Therefore, no matter where the semiconductor chip 1 is arranged on the substrate (100 a,100 b), the power supply terminals (61, 62) and the power supply regions (51, 52) are in contact, and therefore, the semiconductor chip 1 does not need to be arranged at a predetermined position with high precision during manufacturing.
Further, when the substrates (100 a,100 b) are made of a soft material, bending deformation of the substrates (100 a,100 b) may cause a contact position of the power supply regions (51, 52) of the substrates (100 a,100 b) with the power supply terminals (61, 62) of the semiconductor chip 1 to be shifted, but even in this case, since the power supply regions (51, 52) are formed larger on the surfaces of the substrates (100 a,100 b), the semiconductor chip 1 can continue to be in contact with the power supply regions (51, 52) and power supply can continue to be obtained.
Mounting example 10
Fig. 18 is a diagram showing a mounting example 10 in which the semiconductor chip 1 in the present embodiment is mounted on the substrate 100. In the above-described mounting example, the example in which the power supply terminals (61, 62) are provided on the first surface (one side) of the semiconductor chip 1 and are in contact with the substrate 100 on the first surface side has been described, but as shown in fig. 18, the power supply terminals (61, 62) may be configured to extend from the first surface to the second surface side of the semiconductor chip 1 through the side surface of the semiconductor chip 1 and be connected to the substrate 100 located on the second surface side of the semiconductor chip 1.
Mounting example 11
Fig. 19 is a diagram showing a mounting example 11 in which the semiconductor chip 1 of the present embodiment is mounted on the substrate 100. In the mounting example shown in fig. 16, the description has been made of an example in which the power supply terminals (61, 62) are provided on the first surface (one side) of the semiconductor chip (1 e) and the positive electrode region and the negative electrode region are provided on the second surface (the other side), but as shown in fig. 19, the power supply terminals (61, 62), the positive electrode power supply region (52), and the negative electrode power supply region (51) may be provided on the first surface (one side) of the semiconductor chip (1 e), and the power supply terminals (61, 62) may extend from the first surface to the second surface side of the semiconductor chip 1 through the side surfaces of the semiconductor chip 1 and be connected to the substrate 100 and other semiconductor chips on the second surface side of the semiconductor chip 1.
Manufacturing method
Fig. 20 is a flowchart showing a process for manufacturing the semiconductor chip module according to the present embodiment. As a manufacturing process of the semiconductor chip module, first, power supply regions (51, 52) exposing electrodes are formed on a substrate 100 (step 201). In this step (step), the power supply regions (51, 52) formed on the surface of the substrate 100 may be formed by, for example, applying a conductive paint, or may be formed by attaching a conductive adhesive sheet to the substrate 100. Or may be produced by attaching a film material having conductivity such as a metal film to the surface of the material.
As a next step, the semiconductor chip 1 is arranged on the power supply regions (51, 52) (step 202). In this step (step), the semiconductor chip 1 is arranged at a position where the positive electrode power supply terminal (62) of the semiconductor chip 1 is in contact with the positive electrode power supply region (52) and the negative electrode power supply terminal (61) is in contact with the negative electrode power supply region (51). In step 201, when the power supply regions (51, 52) are formed by applying a conductive paint, the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61 are brought into contact with the paint before the paint dries or hardens, so that the power supply regions (51, 52) and the power supply terminals (61, 62) can be joined. Alternatively, in step 201, when an adhesive sheet having conductivity is attached to the substrate 100, the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61 are brought into contact with the adhesive sheet while the adhesive sheet is kept adhesive, whereby the power supply regions (51, 52) and the power supply terminals (61, 62) can be joined. In addition, since the area of at least one of the positive electrode power supply region 52 and the negative electrode power supply region 51 is larger than the area of the end portion of at least one of the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61, there is no need to increase the positioning accuracy of the arrangement of the semiconductor chip 1 in this step.
As a next step, a post-process of the power supply areas (51, 52) or the contact points is performed (step 203). In step 201, when the power supply regions (51, 52) are formed by applying a conductive paint, it is preferable that the paint be cured or dried so that the impurities are less likely to be bonded to each other in order to prevent the impurities from being bonded to the positive electrode power supply region (52) and the negative electrode power supply region (51) and causing a short circuit. Specifically, the paint is dried, heated, or irradiated with light such as ultraviolet rays by blowing air with a fan, thereby hardening or drying the paint. Or in step 201, even when the power supply region (51, 52) is generated by attaching an adhesive sheet having conductivity to the substrate, in order to suppress the problem that the impurity is bonded between the positive power supply region (52) and the negative power supply region (51) to form a short circuit, it is preferable that the adhesive force of the adhesive sheet is reduced to bring the impurity into a state of being difficult to bond. Specifically, the adhesive force of the adhesive sheet is reduced by blowing, heating, or irradiating light such as ultraviolet rays with a fan.
In the above-described mounting example, an example is shown in which the area of at least one of the positive electrode power supply region 52 and the negative electrode power supply region 51 is generated larger than the area of the end portion of at least one of the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61. With this configuration, in the step of connecting the substrate 100 and the semiconductor chip 1, even if the positioning accuracy in the longitudinal direction of each power supply region (51, 52) is poor, the power supply regions (51, 52) and the power supply terminals (61, 62) can be connected, as long as the adjacent semiconductor chips 1 are arranged within a distance range that enables mutual communication. In the above-described mounting example, it is further shown that the distance (400) between the positive electrode power supply region 52 and the negative electrode power supply region 51 provided in the substrate 100 is smaller than the distance (200) between the positive electrode power supply terminal 62 and the negative electrode power supply terminal 61 of the semiconductor chip (1 a, 1 b), and by this configuration, the degree of freedom in the arrangement position of the semiconductor chip 1 is improved.
In the above-described mounting example, the power supply regions (regions where the electrodes are exposed) are provided on the surfaces of the substrate 100 and the semiconductor chip 1, and the semiconductor chip module including the substrate 100 and the semiconductor chip 1 may be sealed (molded) with a resin after the semiconductor chip 1 is bonded in order to prevent the power supply regions (51, 52) of the negative electrode and the positive electrode from being temporarily or frequently short-circuited due to the contamination of foreign substances.
In each of the above-described mounting examples, the substrate 100 may be made of a hard material having low flexibility as in the case of a conventional semiconductor substrate, or may be made of a soft material having high flexibility as in the case of a flexible circuit board, cloth, or the like. In each mounting example, the example in which the plurality of semiconductor chips 1 are bonded to the common substrate 100 is shown, but the substrate 100 bonded to the plurality of semiconductor chips 1 is not necessarily a plate-shaped material, and all materials having the power supply regions (51, 52) on the surfaces thereof may be applied as the substrate 100.
Mounting example 12
Fig. 21 is a diagram showing a mounting example 12 in which the semiconductor chip of the present embodiment is mounted on a material. Fig. 21a shows a side view and fig. 21b shows a plan view. As shown in the plan view of fig. 21b, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side of the material 100, i.e., the substrate 100. The semiconductor chip 102 having the power source element and the semiconductor chip 1a are disposed on one side of the material 100, and the power source terminal 61 on the negative electrode side of the semiconductor chip is joined to the power source supply region 51 on the negative electrode side, and the power source terminal 62 on the positive electrode side of the semiconductor chip is joined to the power source supply region 52 on the positive electrode side. In the mounting example 12 shown in fig. 21, an external communication unit 104 that communicates with an external device is mounted on the material side, unlike the above-described mounting example. The external communication unit 104 mounted on the material includes a communication coil and a transmitting/receiving circuit, and can communicate with the coil 70a of the semiconductor chip 1a and can also wirelessly communicate with an external device outside the semiconductor module. With such a mounting structure, power can be supplied to all semiconductor chips in the semiconductor module, and signals can be transmitted and received between all semiconductor chips in the semiconductor module and an external device.
Mounting example 13
Fig. 22 is a diagram showing a mounting example 13 in which the semiconductor chip of the present embodiment is mounted on a substrate. Fig. 22a shows a side view and fig. 22B shows a B-B cross-sectional view. As shown in fig. 22, semiconductor chips (1 e, 105, 1g, 1 h) are provided at positions sandwiched by materials 110, 120 from both upper and lower sides. The upper surface (semiconductor chip side surface) of the lower material 110 is provided with a positive electrode side power supply region (52), and the lower material 110 is further provided with a power supply element 101. On the other hand, the lower surface (semiconductor chip side surface) of the upper material 120 is provided with a negative electrode side power supply region (51). The semiconductor chips (1 e, 105, 1g, 1 h) disposed between the materials 110, 120 have a negative-side power supply terminal (61) on the upper side and a positive-side power supply terminal (62) on the lower side. At least one of the semiconductor chips disposed between the materials 110 and 120 is configured to include a semiconductor chip 105 having an external communication function capable of communicating with an external device. With this mounting structure, power can be supplied to all semiconductor chips in the semiconductor module, and signals can be transmitted and received between all semiconductor chips in the semiconductor module and an external device.
The semiconductor chips (1 e, 105, 1g, 1 h) are sandwiched between the two pieces of materials (110, 120) in a state in which the negative-side power supply terminal (61) is in contact with the power supply region (51) of the material (120) and the positive-side power supply terminal (62) is in contact with the power supply region (52) of the material (110), so that power can be supplied from each material. Further, the power supply region (51) on the negative electrode side and the power supply region (52) on the positive electrode side are provided on the material 120 and the material 110, respectively, so that there is no need to provide two power supply regions of the positive electrode and the negative electrode on the surface of one sheet of material, and furthermore, there is no need to provide a space between the power supply regions, so that the power supply regions can be provided on almost the entire surface of the material. Therefore, the power supply terminal and the power supply region are in contact regardless of the position of the semiconductor chip on the material, and therefore, it is not necessary to precisely dispose the semiconductor chip on a predetermined position during manufacturing.
Further, when the materials 110, 120 are composed of a soft material, bending deformation of the material may cause a contact position of the power supply region of the material with the power supply terminal of the semiconductor chip to be shifted, but even in this case, since the power supply region is formed larger on the surface of the material, the semiconductor chip can continue to be in contact with the power supply region, and power supply can continue to be obtained.
Mounting example 14
Fig. 23 is a diagram showing a mounting example 14 in which the semiconductor chip of the present embodiment is mounted on a material. Fig. 23a shows a side view and fig. 23B shows a B-B cross-sectional view. As shown in fig. 23, semiconductor chips (105, 106, 1g, 1 h) are provided at positions sandwiched by materials 110, 120 from both upper and lower sides. The upper surface (semiconductor chip side surface) of the lower material 110 is provided with a positive electrode side power supply region (52). On the other hand, the lower surface (semiconductor chip side surface) of the upper material 120 is provided with a negative electrode side power supply region (51). The semiconductor chips (105, 106, 1g, 1 h) disposed between the materials 110, 120 have a negative-side power supply terminal (61) on the upper side and a positive-side power supply terminal (62) on the lower side. At least one of the semiconductor chips disposed between the material 110 and the material 120 is configured to include a semiconductor chip 105 having an external communication function capable of communicating with an external device, and a semiconductor chip 106 having a power source element. With this mounting structure, power of the power source element mounted on the semiconductor chip 106 is supplied to all the semiconductor chips via the material, and signals can be transmitted and received between all the semiconductor chips in the semiconductor module and an external device.
Mounting example 15
Fig. 24 is a diagram showing a mounting example 15 in which the semiconductor chip of the present embodiment is mounted on a material. Fig. 24a shows a side view and fig. 24B shows a B-B cross-sectional view. As shown in fig. 24, semiconductor chips (1 e, 106, 1g, 1 h) are provided at positions sandwiched by materials 110, 120 from both upper and lower sides. The upper surface (semiconductor chip side surface) of the lower material 110 is provided with a positive electrode side power supply region (52). On the other hand, the lower surface (semiconductor chip side surface) of the upper material 120 is provided with a negative electrode side power supply region (51). The semiconductor chips (1 e, 106, 1g, 1 h) disposed between the materials 110, 120 have a negative-side power supply terminal (61) on the upper side and a positive-side power supply terminal (62) on the lower side. Further, an external communication unit 104 for communicating with an external device is attached to the material 110. The external communication unit 104 mounted on the material 110 includes a communication coil and a transceiver circuit, and can communicate with the coil 70a of the semiconductor chip 1e and can also wirelessly communicate with an external device outside the semiconductor module. At least one of the semiconductor chips disposed between the materials 110 and 120 is configured to include the semiconductor chip 106 having a power source element. With this mounting structure, power of the power source element mounted on the semiconductor chip 106 is supplied to all the semiconductor chips via the material, and signals can be transmitted and received between all the semiconductor chips in the semiconductor module and an external device.
Mounting example 16
Fig. 25 is a diagram showing a mounting example 16 in which the semiconductor chip of the present embodiment is mounted on a material. Fig. 25a shows a side view and fig. 25b shows a plan view. As shown in the plan view of fig. 25b, a negative-side power supply region (51) and a positive-side power supply region (52) are provided on one side of the material 100. Further, a semiconductor chip 102 having a power source element and a semiconductor chip 107 having an external communication function are arranged on one side of the material 100, a power source terminal 61 on the negative side of the semiconductor chip 102, 107 is joined to a power source supply region 51 on the negative side, and a power source terminal 62 on the positive side of the semiconductor chip 102, 107 is joined to a power source supply region 52 on the positive side. In this connection, a mounting example 16 shown in fig. 25 is different from the mounting example 12 shown in fig. 21 in that a coil 71 realizing a communication antenna function for communicating with an external device and an external transceiver circuit connected to the coil 71 are mounted on a material 100 and a semiconductor chip 107, respectively. More specifically, the coil 71 is mounted on the material 100, the external transmission/reception circuit and the coil connection terminal K63 connected to the external transmission/reception circuit are mounted on the semiconductor chip 107, and the semiconductor chip 107 is disposed on the material 100 so that the coil connection terminal K63 is in contact with the coil 71. The semiconductor chip 107 has the coil 70 and the transceiver circuit 80 mounted on the semiconductor chip 1 for wireless communication with other adjacent semiconductor chips. Is electrically connected to the coil 71 via the coil connection terminal K63. With this mounting structure, power can be supplied to all semiconductor chips in the semiconductor module, and signals can be transmitted and received between all semiconductor chips in the semiconductor module and an external device.
Mounting example 17
An installation example 17 of the present invention is explained below. Fig. 26 is a diagram showing a configuration example of the semiconductor chip 1 according to the mounting example 17. In the mounting example 17, the semiconductor chip 1 includes, in addition to the power supply terminals 61 and 62, an input/output terminal N63 connected to the external sensor module 12. The semiconductor chip 1 and the sensor module 12 are in wired communication with each other through the wiring 13, and are in wireless communication with an external device 11 (other semiconductor chips 1 may be used) other than the sensor module 12 through the coil 70. The semiconductor chip 1 performs interaction of, for example, text information, numerical information, image information, voice information, control information, monitoring information by the wired communication and wireless communication.
The sensor module 12 includes a sensor unit 12A and a signal processing unit 12B. The sensor unit 12A is, for example, a temperature sensor, a humidity sensor, a distance sensor, an optical sensor, or a magnetic sensor. The sensor portion 12A corresponds to, for example, a sensor device 15 which will be described below with reference to fig. 28. The signal processing unit 12B includes, for example, an a/D conversion circuit (not shown) and a logic circuit (not shown). In the sensor module 12, the sensor unit 12A detects physical quantities such as temperature and humidity, and outputs the detected physical quantities to the signal processing unit 12B. In the signal processing section 12B, the a/D conversion circuit converts the physical quantity from an analog signal to a digital signal, and the logic circuit processes the digital signal, more specifically, so as to comply with a protocol of wired communication using the wiring 13. The wiring 13 between the sensor module 12 and the semiconductor chip 1 may be constituted by, for example, only one data signal line for serial communication, may be constituted by one clock signal line for transmitting a clock signal and one data signal line for bidirectional serial communication (I2C bus), or may be constituted by one clock signal line and two unidirectional (transmission and reception) data signal lines (SPI bus). In this case, there may be a number of input-output terminals N63 corresponding to the number of signal lines.
Thus, the output data from the sensor module 12 that outputs the digital signal by wire can be propagated to the outside by short-range wireless communication using inductive coupling.
Instead of the sensor module 12, various functional modules (e.g., a camera module, a display module, a microphone module, a speaker module, a clock module) may be employed, and the functional modules may be connected to the input-output terminal N63. In this case, the semiconductor chip 1 performs wired communication with the functional module, and performs wireless communication with the external device 11 other than the functional module via the coil 70.
In addition, the communication chip 14 may be employed instead of the sensor module 12. Fig. 27 is a diagram showing a configuration example when the communication chip 14 is employed. At this time, the semiconductor chip 1 can perform short-distance wireless communication with other semiconductor chips 1 based on inductive coupling via the coil 70, and can perform wired communication using the wiring 13 and wireless communication via the communication chip 14 with other devices 11 other than the semiconductor chip 1. The wired communication using the wiring 13 may be, for example, the I2c bus or the SPI bus, and the wireless communication with the other device 11 via the communication chip 14 may be performed in accordance with, for example, wiFi, bluetooth (registered trademark), LTE, LPWA, or the like, and the communication chip 14 may perform communication control in accordance with these protocols.
Furthermore, an analog sensor device 15 may also be used instead of the sensor module 12. Fig. 28 is a diagram illustrating a semiconductor module including the semiconductor chip 1a shown in the mounting example 1 and the semiconductor chip 1b according to the mounting example 17. In the mounting example 17, the semiconductor chip 1b performs a primary process, and the semiconductor chip 1a performs a secondary process. As shown in the figure, an analog signal from the analog sensor device 15 is transmitted to the semiconductor chip 1b by wired communication using the wiring 13, and the semiconductor chip 1b can perform one-time processing of the analog signal from the sensor device 15. The primary processing is the same as the processing of the signal processing unit 12B described with reference to fig. 26, and more precisely, for example, is the following processing: the physical quantity detected by the sensor device 15 is converted from an analog signal to a digital signal, and a signal suitable for wireless communication between the semiconductor chip 1a and the semiconductor chip 1b is generated from the digital signal. The semiconductor chip 1b can perform wireless communication based on inductive coupling via the coil 70b, and transmit the once processed data to the semiconductor chip 1a. In the semiconductor chip 1a, secondary processing can be performed using the data after the primary processing. The secondary process may be, for example, an aggregation process, a resolution process, or the like.
Mounting example 18
Overview of the System
Fig. 29 is a diagram showing a configuration example of an information processing apparatus of the installation example 18 of the present invention. The information processing apparatus of the mounting example 18 is configured to include a plurality of semiconductor chips (1 a,1 b). The semiconductor chip 1 is a device capable of measuring a measurement value that changes in accordance with the state of the semiconductor chip, such as the relationship with the relative position of the other semiconductor chip 1. The plurality of semiconductor chips 1 are arranged on the surface or inside of the installation object 4 on which the semiconductor chips are installed, and by measuring the relative position relationship with other semiconductor chips 1, the state of the installation object 4 (for example, the operation state, deformation, temperature, vibration, pressure, electromagnetic wave, volume, humidity, etc. of the installation object) can be estimated by calculation. The installation object 4 may be a device for relatively moving or deforming a plurality of objects such as a door and a motor, may be a civil engineering or construction material such as earth filling or concrete, or may be water or air.
The semiconductor chip 1 includes a processor 10 and a coil 30, and the processor 10 includes a memory 20. At least a portion of the memory 20 includes a nonvolatile memory device capable of storing programs and the like that are executed by the processor 10. The coil 30 can function as a communication antenna for communication with another semiconductor chip, and can transmit and receive signals to and from the coil 30 of another semiconductor chip 1 disposed adjacently by a near field communication method via a near field electromagnetic field, another communication method by inductive coupling, or another communication method. The coil 30 can also function as a measuring unit for detecting a voltage value, a voltage amplitude, or the like of a communication signal received from another semiconductor chip. Further, the coil 30 can also function as a power receiving portion for electric power supplied from the power supply device K40 outside the semiconductor chip.
The power supply device K40 generates an electromagnetic field by using, for example, a magnetic field induction system, a magnetic field resonance system, or the like, and generates a current of a predetermined frequency band in the coil 30 of the semiconductor chip.
< Hardware >
Fig. 30 shows an example of a hardware configuration in which the coil 30 is provided on the outer periphery of the processor and the electric circuit portion D100 in the semiconductor chip 1, and the electric circuit portion D100 including the transmission circuit 50, the voltage detection circuit 60, and the power acquisition circuit 70 is further provided as one example of realizing the semiconductor chip. In the example shown in fig. 30, an example in which the semiconductor chip 1a and the semiconductor chip 1b are used in pairs is shown, and the semiconductor chip 1 includes: a processor (10 a,10 b); a memory (20 a,20 b) disposed within the processor; coils (30 a,30 b) which are formed by wiring and the like arranged on the outer periphery of the semiconductor chip; a transmitting circuit (50 a,50 b) communicatively connected to the processor 10 and generating a voltage signal to be transmitted to the coils (30 a,30 b); voltage detection circuits (60 a,60 b) that detect voltages of the coils (30 a,30 b); and a power acquisition circuit (70 a,70 b) that acquires power flowing to the coils (30 a,30 b). Fig. 30 shows an example in which the coil is formed of a single wire, and the coil may be formed of a plurality of wires. In the example shown in fig. 30, the processor and the electric circuit portion D100 are provided inside the region where the coil 30 is formed, and the coil 30 is provided so as to surround the outside of the processor and the electric circuit portion D100, but the position of the coil is not limited to this, and as another example, one or both of the processor and the electric circuit portion D100 may be provided outside the coil instead of inside the region covered with the coil. Alternatively, as shown in fig. 37, when the semiconductor chip has a multi-layer structure, the coil 30 may be provided in a layer different from at least one of the processor 10 and the electric circuit unit D100. The semiconductor chip shown in fig. 37 may be formed of a single chip having an upper layer and a lower layer, or may be formed as a separate semiconductor chip in which the upper layer and the lower layer are electrically connected.
At least any one of the plurality of semiconductor chips 1 (the semiconductor chip 1a in fig. 30) is communicably connected to an external computer 80. The communication between the external computer 80 and the semiconductor chip 1 may be performed based on a communication request signal from either or both of the external computer 80 and the semiconductor chip 1, and may be wireless communication via the coil 30.
The external computer 80 is a computer that receives at least any one of communication history information, measurement value information, state quantity information, measurement logic information, and other semiconductor chip information stored in each storage section of the semiconductor chip 1a, and performs statistical processing or the like based on the received information on the plurality of semiconductor chips, for example.
The transmission circuit 50 is a circuit electrically connected to the coil 30, and generates a communication signal to the coil 30 according to a communication signal generation instruction generated by the processor. Specifically, the coil 30 is caused to generate a voltage signal constituting the communication signal.
The voltage detection circuit 60 is a circuit electrically connected to the coil 30, and detects a voltage value generated in the coil 30. Wireless communication signals from other semiconductor chips or an external computer 80 are received by the coil 30, which are generated in the coil 30 as voltage signals. The signal strength (voltage value or voltage amplitude) of the wireless signal varies according to the relative positional relationship with the other semiconductor chip or the external computer 80 to be communicated with. The processor can recognize the received wireless signal by detecting the voltage value generated in the coil 30 by the voltage detection circuit 60, and further, by performing calculation processing on the voltage value or the voltage amplitude generated in the coil 30 by using a predetermined calculation logic, it is possible to estimate the state quantity of the semiconductor chip including the relative position relationship between the semiconductor chip 1 itself and the other semiconductor chips 1, the state of the installation object 4 in which the semiconductor chip is installed (for example, the operation state, deformation, temperature, vibration, pressure, electromagnetic wave, volume, humidity, and the like of the installation object) by calculation.
The power acquisition circuit 60 is a circuit electrically connected to the coil 30, and acquires power from a current generated in the coil 30 due to an electromagnetic field generated by the power supply device K40 outside the semiconductor chip. The power acquired by the power acquisition circuit 60 is supplied to the processor 10, the memory 20, and the like, and is used as power necessary for driving each constituent element of the semiconductor chip.
As described above, the electric circuit unit D100 has the transmission circuit 50, the voltage detection circuit 60, and the power acquisition circuit 70, which are independent of each other, and can realize the functions of wireless signal transmission and reception, measurement value acquisition, and power acquisition via the common coil.
The semiconductor chip in the mounting example 18 can be constituted by a CPU by mounting the processor shown in fig. 30 on the semiconductor chip inseparably from the electric circuit portion. For example, the processor and the electric circuit portion may be inseparably mounted on a semiconductor chip (on a single chip). Among them, a semiconductor chip is defined as a small piece of silicon (silicon wafer or wafer) on which an electronic circuit is mounted. Or may be defined as a package in which a silicon wafer is packaged, as the case may be.
Software
Fig. 31 is a block diagram showing a functional configuration of the semiconductor chip 1. The semiconductor chip 1 includes a measurement unit K110, a communication unit T120, a power receiving unit 130, a state determining unit 140, a measurement logic recording unit 151, a communication history storage unit 152, a measurement value storage unit 153, a state quantity storage unit 154, and another semiconductor chip information storage unit 155. The measurement section K110 can be realized by: the processor records the voltage value of the coil 30 detected by the voltage detection circuit 60 to the memory. Further, the communication section T120 may be realized by: the processor generates a communication signal in the coil via the transmitting circuit 50, which is identified from the voltage value of the coil 30 detected by the voltage detecting circuit 60. Further, the power receiving section 130 may be realized by: the power acquisition circuit 70 acquires power from the current generated in the coil. Further, the state judgment section may be realized by: according to the pre-recorded calculation logic, the state quantity is calculated from the voltage value (measured value) of the coil 30 detected by the voltage detection circuit 60. The measurement logic recording unit 151, the communication history storage unit 152, the measurement value storage unit 153, the state quantity storage unit 154, and the other semiconductor chip information storage unit 155 may be implemented as a part of a storage area of the memory 20 provided in the semiconductor chip.
The calculation logic storage unit 151 stores calculation logic. The measurement logic storage 151 of the present mounting example stores calculation logic in association with the state quantity of the semiconductor chip or the kind of the state quantity of the setting object 4. The calculation logic includes an algorithm that calculates a state quantity based on the measured values.
The measurement unit K110 measures a measurement value that can be measured by the coil 30, and records the measurement value in the measurement value storage unit. The measured value is a value measured by the coil 30, and in this example, may be, for example, a voltage value generated in the coil. Fig. 33 shows a voltage value generated in the coil 30 by a transmission signal transmitted from a nearby semiconductor chip, and a reception signal generated from the voltage value. The voltage value or the amplitude of the voltage of the coil shown in fig. 33 varies according to the positional relationship between the two semiconductor chips. Therefore, the measurement unit K110 can acquire the voltage value of the coil or the amplitude of the voltage as the measurement value. The measurement value measured by the measurement unit K110 is recorded in the measurement value storage unit 153.
The state determining unit 140 calculates a state quantity from the voltage value (measured value) of the coil 30 detected by the voltage detecting circuit 60 according to a calculation logic recorded in advance. The state quantity is a value related to the state of the semiconductor chip or the state of the installation object 4, and may be, for example, a relative distance or a relative angle of a plurality of semiconductor chips, or a temperature, vibration, pressure, electromagnetic wave, volume, humidity, or the like of the installation object 4. For example, when the positional relationship between two semiconductor chips is changed, the voltage generated in the coil or the amplitude of the voltage is changed. Further, the change in the positional relationship of the two semiconductor chips changes according to the vibration such as the temperature, pressure, humidity, sound, electromagnetic wave, etc. of the installation object in which the semiconductor chips are embedded, arranged, and attached. The state determination unit 140 can estimate the various state amounts by processing the changes in the voltage or the voltage amplitude of the coil due to the changes in the relative position and the relative angle of the semiconductor chip in accordance with the calculation logic stored in the calculation logic storage unit. The estimated state quantity is recorded in the state quantity storage unit 154.
Fig. 33 shows a voltage value generated in the coil 30 by a transmission signal transmitted from a nearby semiconductor chip, and a reception signal generated from the voltage value. Since the voltage value or the voltage amplitude of the coil shown in fig. 33 changes according to the positional relationship between the two semiconductor chips, the various state amounts can be estimated from the voltage amplitude.
When transmitting a signal, the communication unit T120 generates a communication signal in the coil via the transmission circuit 50 by the processor, and transmits a wireless signal to another semiconductor chip or an external computer. Further, when receiving the signal, the processor recognizes the communication signal based on the voltage value of the coil 30 detected by the voltage detection circuit 60, and receives the wireless signal. Further, the communication history information transmitted or received by the communication section T120 is recorded in the communication history storage section 152. As shown in fig. 33, for example, the pulse signal of the reception signal increases due to the voltage increase on the positive side of the voltage value of the coil, and the pulse signal of the reception signal returns to zero due to the voltage decrease on the negative side of the voltage value of the coil, whereby the reception signal can be generated. Further, the other semiconductor chip information acquired as the reception signal by the communication section T120 is recorded in the other semiconductor chip information storage section 155.
The power receiving unit 130 obtains power used for the constituent elements in the semiconductor chip such as the processor by obtaining power from the current generated in the coil 30 by the power obtaining circuit 70. The power supply device K40 generates an electromagnetic field by using a magnetic field induction method, a magnetic field resonance method, or the like, and causes the coil 30 of the semiconductor chip to generate a current of a predetermined frequency band. Therefore, the power acquisition circuit 70 is configured to be able to acquire power from the current in the predetermined frequency band.
When at least one of the communication unit T120 and the measurement unit K110 uses a phenomenon in which a voltage is generated in the coil via an electromagnetic field, if power is to be supplied via a common coil by a power supply system using the electromagnetic field, it is difficult to realize three functions of communication, measurement, and power supply by the common coil due to interference of the electromagnetic field. However, when near field communication using a near field generated between the communication unit T120 and another semiconductor chip is used, a wireless signal is generated in a wide frequency band ranging from zero to gigahertz without modulation, and therefore if a magnetic field induction system or a magnetic field resonance system modulated to a predetermined frequency (for example, a frequency band of several tens megahertz) is used as a power supply system, an electromagnetic field in a frequency band used for power supply hardly affects an electromagnetic field of near field communication, and three functions of communication, measurement, and power supply can be realized using a common coil.
Action
Fig. 32 is a control flow chart illustrating the flow of processing of the information processing apparatus of the installation example 18 of the present invention.
An information processing apparatus including a plurality of semiconductor chips first obtains power from a power receiving unit 130 (S141). Then, the processor is started by the acquired power (S142). Then, the communication unit T120 transmits or receives a communication signal via the coil 30 (S143). Then, the communication information and the information of the communication history concerning the content of the communication signal are stored in the communication history storage section 152 (S144). Then, the voltage value or the amplitude of the voltage generated in the coil is measured by the measuring section (S145). Then, the measured value is recorded in the measured value storage 153 (S153). Then, the state judgment unit calculates the state quantity according to the calculation logic recorded in the calculation logic storage unit 151 (S147). Then, the calculated state quantity is stored in the state quantity storage unit 154 (S148). Then, it is judged whether or not there is a communication request from an external computer (S149), and if there is no communication request, the process is terminated. If there is a communication request from an external computer, information of each storage section (calculation logic storage section, communication history storage section, measurement value storage section, state quantity storage section, other semiconductor chip information storage section) recorded in the semiconductor chip is transmitted to the external computer (S150), and the process is terminated.
Fig. 34 is a diagram showing one example of information stored in the communication history storage section. The communication history storage unit 152 records the time when the communication information is acquired (the time elapsed since the start of measurement), the ID information of the semiconductor chip or the external computer that is the communication destination, and information related to the content of the communication signal. In the example shown in fig. 35, the communication signal with the semiconductor chip a as the measurement target is measured at 0.1 second intervals. Further, ID information of the semiconductor chip of the communication target or an external computer is contained in the communication signal.
Fig. 35 is a diagram showing one example of information stored in the measurement value storage section. The measurement value storage 153 stores the measurement time (time elapsed since the start of measurement), the identification information of the semiconductor chip to be measured, and the measured value (voltage value generated in the coil in the example shown in fig. 35) at which the measured value is measured. In the example shown in fig. 35, the communication signal with the semiconductor chip a as the measurement target is measured at 0.1 second intervals, and the voltage value generated in the coil is 3.00V at an elapsed time of 10.1 seconds, gradually decreases and becomes 1.27V at 11.3 seconds.
Fig. 36 is a diagram showing one example of information stored in the state quantity storage section. The state quantity storage 154 stores the measurement time (time elapsed since the start of measurement) at which the measurement value was measured, identification information of the semiconductor chips to be measured, the measurement value (voltage value generated in the coil in the example shown in fig. 36), and the state quantity (distance between the semiconductor chips in the example shown in fig. 36) calculated from the measurement value. In the example shown in fig. 36, the distance between the semiconductor chips estimated from the voltage value generated in the coil was 2.0mm at the elapsed time of 10.1 seconds, and the distance was gradually widened to be 4.2mm at 11.3 seconds.
Mounting example 1 to mounting example 18 modification examples
In the semiconductor chip of the above-described mounting example, the processor may also be provided inside the coil.
In the semiconductor module of the above-described mounting example, the positive electrode power supply terminal (62 a) of the first semiconductor chip (1 a) and the positive electrode power supply terminal (62 b) of the second semiconductor chip (1 b) may be joined to or abutted against the same positive electrode power supply region (52), and the negative electrode power supply terminal (61 a) of the first semiconductor chip (1 a) and the negative electrode power supply terminal (61 b) of the second semiconductor chip (1 b) may be joined to or abutted against the same negative electrode power supply region (51). This is shown for example in fig. 6a, 6b.
In the semiconductor module of the above-described mounting example, the width in the direction in which the first semiconductor chip (1 a) and the second semiconductor chip (1 b) are arranged in the positive electrode power supply region (52) and the negative electrode power supply region (51) may be two or more times the width of the semiconductor chips (1 a,1 b). This is shown for example in fig. 6a, 6 b.
The semiconductor module of the above-described mounting example is characterized by comprising a first semiconductor chip (1 a) and a second semiconductor chip (1 b), and a sensor (for example, a sensor portion 12A shown in fig. 26) connected to the first semiconductor chip (1 a) by wire, wherein a processor (for example, a processor 10a shown in fig. 2) provided in the first semiconductor chip (1 a) processes a signal received from the sensor (12A), and the processed data is transmitted to a coil (for example, a coil 70b shown in fig. 2) of the second semiconductor chip (1 b) through inductive coupling, and the processor (for example, a processor 10b shown in fig. 2) provided in the second semiconductor chip (1 b) performs processing based on data received from the coil (70 b) of the second semiconductor chip (1 b), and in addition, a third semiconductor chip (for example, semiconductor chips 1c, 1d, 1e, 1 f) having a communication processor, a coil for performing wireless communication, and a junction between the positive electrode terminal (62) and the negative electrode terminal (62) of the semiconductor chip (1 c) or the positive electrode (62) of the semiconductor chip (1) and the negative electrode (51) of the external power supply terminal (51) may be connected to each other, wireless communication is performed based on inductive coupling between the coils of the third semiconductor chip (1 c, 1d, 1e, 1 f) and the coils of the second semiconductor chip (1 b). This is shown for example in fig. 15.
A semiconductor chip (1 a) is provided with a processor and a coil, and is characterized by comprising: a communication unit (80 a) that communicates with another semiconductor chip (1 b) using the coil (70 a); a measuring unit (for example, a measuring unit K110 shown in FIG. 31) that acquires a measurement value corresponding to the state of the information processing device using the coil (70 a); and a power receiving unit (for example, a power receiving unit 130 shown in fig. 31) that obtains power consumed by the semiconductor chip (1 a) using the coil (70 a), wherein the coil (70 a) may transmit power to a coil outside the semiconductor chip (1 a) in the semiconductor chip that is the above-described mounting example of the semiconductor chip (1 a). This is shown, for example, in fig. 28.
From the viewpoint of combining with a structure in which power is received by a coil, a semiconductor chip (1 a) provided with a processor (10) and a coil (30) is characterized by comprising: a communication unit (for example, a communication unit 40 shown in fig. 1) that communicates with the other semiconductor chip (1 b) using the coil (30); a measuring unit (for example, a measuring unit K110 shown in fig. 31) that acquires a measurement value corresponding to the state of the information processing apparatus using the coil (30); and a power receiving unit (for example, a power receiving unit 130 shown in fig. 31) that obtains power consumed by the semiconductor chip (1 a) using the coil (30), wherein the semiconductor chip (1 a) may include a positive power supply terminal (for example, a positive power supply terminal 62 shown in fig. 6) and a negative power supply terminal (for example, a negative power supply terminal 61 shown in fig. 6) that obtain driving power of the processor (10) from outside the semiconductor chip (1 a). This is shown for example in fig. 29.
The two coils communicate with each other by magnetic field coupling. Communication based on magnetic field coupling is a transmission method using the principle of electromagnetic induction in information transmission. Further, communication based on inductive coupling, and communication based on magnetic field resonance or magnetic field resonance using a resonance phenomenon of a transmitting-receiving coil are also included in communication based on magnetic field coupling.
The present embodiment has been described above, but the above embodiment is merely illustrative for easy understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified and improved within a range not departing from the gist thereof, and the present invention includes, of course, equivalents thereof. The present embodiment may be used alone or in combination.
Industrial applicability
The semiconductor module, the semiconductor chip, and the method for manufacturing the semiconductor module according to the present invention can be used to manufacture the semiconductor module and the semiconductor chip more easily.
Symbol description
1A: semiconductor chip
1B: other semiconductor chips
10A: processor and method for controlling the same
51: Negative electrode power supply region
52: Positive electrode power supply area
61A: negative electrode power supply terminal
62A: positive electrode power supply terminal
70A: a coil.
Claims (27)
1. A semiconductor chip comprising a processor, a coil for performing wireless communication with another semiconductor chip, a positive power supply terminal, and a negative power supply terminal, characterized in that,
The positive electrode power supply region and the negative electrode power supply region are joined to or abutted against the positive electrode power supply terminal, and the negative electrode power supply region and the negative electrode power supply terminal are joined to or abutted against each other,
At least one of the positive power supply region and the negative power supply region has an area larger than an area of an end of at least one of the positive power supply terminal and the negative power supply terminal.
2. The semiconductor chip of claim 1, wherein the semiconductor chip comprises a plurality of semiconductor chips,
The positive power supply terminal and the negative power supply terminal are arranged on a first surface of one side of the semiconductor chip,
A positive electrode region and a negative electrode region of a release electrode are provided on a second surface of the semiconductor chip opposite to the first surface.
3. The semiconductor chip of claim 1, wherein the semiconductor chip comprises a plurality of semiconductor chips,
The terminals of the semiconductor chip are composed of only the positive power supply terminal and the negative power supply terminal.
4. The semiconductor chip of claim 1, wherein the semiconductor chip comprises a plurality of semiconductor chips,
Communication with other semiconductor chips is not performed via the positive power supply terminal and the negative power supply terminal, but is performed by wireless communication via the coil.
5. The semiconductor chip of claim 1, wherein the semiconductor chip comprises a plurality of semiconductor chips,
The processor is disposed inside the coil.
6. The semiconductor module according to claim 1, wherein,
The method further comprises: a positive electrode conductive portion that electrically connects the positive electrode power supply terminal and the positive electrode region; and a negative electrode conductive portion electrically connecting the negative electrode power supply terminal with the negative electrode region.
7. The semiconductor module according to claim 5, wherein,
The first positive electrode power supply terminal and the first negative electrode power supply terminal are provided on a first surface on the material side, and a first positive electrode region where a positive electrode is exposed and a first negative electrode region where a negative electrode is exposed are provided on a second surface on the opposite side from the first surface.
8. The semiconductor module according to claim 5, wherein,
The distance between the positive power supply region and the negative power supply region provided on the material is shorter than the distance between the positive power supply terminal and the negative power supply terminal.
9. The semiconductor module according to claim 5, wherein,
The semiconductor chip includes the first positive electrode power supply terminal, the first negative electrode power supply terminal, a first positive electrode region where a positive electrode is exposed, and a first negative electrode region where a negative electrode is exposed, on a second surface opposite to the material.
10. The semiconductor module according to claim 5, wherein,
The material is provided with: a first material having a positive power supply region connected to the positive power supply terminal of the semiconductor chip; and a second material having a negative power supply region connected to the negative power supply terminal of the semiconductor chip,
The first material and the second material are configured to clamp the plurality of semiconductor chips.
11. The semiconductor module according to claim 5, wherein,
The material is provided with: and a power supply element that stores or generates power and supplies power via at least one of the positive power supply region and the negative power supply region.
12. The semiconductor module according to claim 5, wherein,
The semiconductor chip includes: and an external communication unit that performs wireless communication with an external device external to the semiconductor module via the coil.
13. The semiconductor module according to claim 5, wherein,
The semiconductor chip includes: and a power supply element that stores or generates power and supplies power via at least one of the positive power supply terminal and the negative power supply element.
14. A semiconductor module is characterized by comprising: the semiconductor chip of claim 1; and
A sensor wired to the semiconductor chip,
The semiconductor chip communicates with the sensor through the wire.
15. A semiconductor module is characterized by comprising: a first semiconductor chip and a second semiconductor chip, which are the semiconductor chips of claim 1,
And is provided with: a sensor wired to the first semiconductor chip,
The processor provided in the first semiconductor chip processes the signal received from the sensor, transmits the processed data to the coil of the second semiconductor chip through the coil by inductive coupling,
The processor provided in the second semiconductor chip performs processing based on the data received from the coil of the second semiconductor chip.
16. The semiconductor module of claim 15, wherein,
The positive power supply terminal of the first semiconductor chip and the positive power supply terminal of the second semiconductor chip are joined or abutted with the same positive power supply region,
The negative power supply terminal of the first semiconductor chip and the negative power supply terminal of the second semiconductor chip are joined or abutted with the same negative power supply region.
17. The semiconductor module of claim 15, wherein,
The width of the positive electrode power supply region and the negative electrode power supply region in the direction in which the first semiconductor chip and the second semiconductor chip are arranged is twice or more the width of the semiconductor chip.
18. The semiconductor module according to claim 15, comprising a third semiconductor chip having:
A processor;
A coil for performing wireless communication; and
A positive power supply terminal and a negative power supply terminal that obtain driving power of the processor from outside the semiconductor chip,
The positive power terminal of the third semiconductor chip is connected with or abutted against the same positive power supply area,
The negative power supply terminal of the third semiconductor chip performs wireless communication by inductive coupling between the coil of the third semiconductor chip and the coil of the second semiconductor chip, which are joined or abutted to the same negative power supply region.
19. A semiconductor chip provided with a processor and a coil, characterized by comprising:
a communication unit that communicates with another semiconductor chip using the coil;
a measurement unit that acquires a measurement value corresponding to a state of the information processing apparatus using the coil; and
And a power receiving unit that obtains power consumed by the semiconductor chip using the coil.
20. The semiconductor chip of claim 19, wherein the semiconductor chip comprises a plurality of semiconductor chips,
The power receiving unit acquires electric power of a specific frequency band generated in the coil by an electromagnetic field generated by an external power supply device,
The communication section transmits an unmodulated wireless signal to the coil of another semiconductor chip in proximity to the semiconductor chip via a near field electromagnetic field.
21. The semiconductor chip according to claim 19, comprising:
A calculation logic storage unit that stores calculation logic for calculating a state quantity indicating the state; and
And a calculation unit that calculates the state quantity from the measurement value according to the calculation logic.
22. The semiconductor chip of claim 19, wherein the semiconductor chip comprises a plurality of semiconductor chips,
The coil sends power to a coil outside the semiconductor chip.
23. The semiconductor chip of claim 19, wherein the semiconductor chip comprises a plurality of semiconductor chips,
The semiconductor device includes a positive power supply terminal and a negative power supply terminal, and obtains driving power of the processor from outside the semiconductor chip.
24. An information processing apparatus, comprising: the semiconductor chip of claim 19; and
A power supply device which transmits power of a specific frequency band to the coil via an electromagnetic field,
The communication section transmits an unmodulated wireless signal to the coil of another semiconductor chip in proximity to the semiconductor chip via a near field electromagnetic field.
25. A semiconductor module is characterized by comprising: the semiconductor chip of claim 19; and
A sensor wired to the semiconductor chip,
The semiconductor chip communicates with the sensor through the wire.
26. A semiconductor module is characterized by comprising: a first semiconductor chip and a second semiconductor chip, which are the semiconductor chips of claim 19,
And is provided with: a sensor wired to the first semiconductor chip,
The processor provided in the first semiconductor chip processes the signal received from the sensor, transmits the processed data to the coil of the second semiconductor chip through the coil by inductive coupling,
The processor provided in the second semiconductor chip performs processing based on the data received from the coil of the second semiconductor chip.
27. A material to be bonded to or abutted against a semiconductor chip having a processor, a coil for performing wireless communication with another semiconductor chip, a positive electrode power supply terminal and a negative electrode power supply terminal, characterized in that,
Comprises a positive electrode power supply region and a negative electrode power supply region,
The positive power supply area is connected with or abutted against the positive power terminal,
The negative power supply region is engaged or abutted with the negative power terminal,
At least one of the positive power supply region and the negative power supply region has an area larger than an area of an end of at least one of the positive power supply terminal and the negative power supply terminal.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022-101726 | 2022-06-24 | ||
| JP2022-147441 | 2022-09-15 | ||
| JP2022-168739 | 2022-10-21 | ||
| JP2023063459 | 2023-04-10 | ||
| JP2023-063459 | 2023-04-10 | ||
| PCT/JP2023/023164 WO2023249086A1 (en) | 2022-06-24 | 2023-06-22 | Semiconductor module, semiconductor chip, and method for manufacturing semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117916881A true CN117916881A (en) | 2024-04-19 |
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ID=90695074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202380012547.0A Pending CN117916881A (en) | 2022-06-24 | 2023-06-22 | Semiconductor module, semiconductor chip, and method for manufacturing semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117916881A (en) |
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2023
- 2023-06-22 CN CN202380012547.0A patent/CN117916881A/en active Pending
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