CN117913025A - Semiconductor element, semiconductor package and method for manufacturing the same - Google Patents

Abstract

The invention discloses a semiconductor element, a semiconductor package and a manufacturing method thereof, wherein the method comprises the following steps: providing a wafer, comprising: an active surface, a back surface, a semiconductor device region and a scribe line region, wherein the scribe line region has a plurality of conductive pillars, and the plurality of conductive pillars do not penetrate to the back surface of the wafer; dicing the wafer using a tool to cut away a portion of the wafer and a portion of the plurality of conductive pillars in the dicing street region, wherein a width of the tool is less than a width of the dicing street region; grinding the back surface of the wafer to expose the plurality of conductive pillars; and separating the wafer into a plurality of semiconductor chips via the wafer portion cut in the scribe line region. The invention provides a semiconductor element with high integration, a semiconductor package and a manufacturing method thereof by arranging a silicon perforation in a cutting channel region and cutting by using a cutter with a narrower width than the cutting channel.

Description

Semiconductor element, semiconductor package and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device, a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor device, a semiconductor package and a method for manufacturing the same applied in three-dimensional stacked package.

Background

The current through silicon via (through silicon via, TSV) process is mainly applied to the stacked package of Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS), which can reduce the package size. The process is mainly divided into front end of line (FEOL), back end of line (BEOL) and packaging (OSAT), wherein the front end is responsible for etching through holes in a silicon wafer and copper plating to form through silicon vias, the back end is responsible for grinding and plating solder balls, and the packaging is responsible for testing and soldering tin packaging.

However, the integrated circuits (INTEGRATED CIRCUIT, IC) are now being designed in size to 3 nm and are ready to break through to 2 nm, which is a requirement for the application end. Thus, the area requirements for availability are also raised.

Therefore, there is a need for a highly integrated semiconductor device, a semiconductor package and a method of manufacturing the same, which solve the problems of the conventional art.

Disclosure of Invention

In view of the above, the present invention provides a semiconductor device, a semiconductor package and a method for manufacturing the same, and an object of the present invention is to provide a highly integrated semiconductor device, a semiconductor package and a method for manufacturing the same, which can save area and facilitate packaging, or increase transistor design and increase operation speed.

Still another object of the present invention is to provide a highly integrated semiconductor device, a semiconductor package and a method for manufacturing the same, which can increase the number of transistor designs and thus increase the operation speed.

To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: (a) providing a wafer, the wafer comprising: an active surface and a back surface, the back surface being disposed opposite the active surface; a semiconductor device region and a scribe line region, wherein the scribe line region has a plurality of conductive pillars, and the plurality of conductive pillars are electrically connected to the plurality of semiconductor devices in the semiconductor device region, and the plurality of conductive pillars do not penetrate through to the back surface of the wafer; (b) Cutting the wafer by using a cutter to cut away part of the wafer and part of the conductive posts in the cutting channel area, so that the side surfaces of the cut conductive posts are exposed, wherein the width of the cutter is smaller than that of the cutting channel area; (c) Grinding the back surface of the wafer to expose the plurality of conductive pillars; and (d) separating the wafer into a plurality of semiconductor chips via the portion of the wafer that is cut in the scribe line region.

In an embodiment of the present invention, the plurality of conductive pillars are integrally disposed in the scribe line region and not disposed in the semiconductor device region.

In an embodiment of the present invention, the step (a) further includes: laser drilling the wafer to remove a portion of the wafer material to form a plurality of through holes, wherein the plurality of through holes do not extend through to the back side of the wafer; and filling a conductive material into the plurality of through holes to form the plurality of conductive posts.

In an embodiment of the present invention, the semiconductor device region has a metal layer extending to the scribe line region, wherein when the wafer is laser drilled, the laser simultaneously removes a portion of the metal layer, such that the plurality of conductive pillars and the metal layer form an electrical connection when the conductive material fills the plurality of vias.

In an embodiment of the present invention, the step (a) further includes: a plurality of first conductive elements are disposed on the plurality of conductive posts.

In an embodiment of the present invention, after the step (a), the method further includes: a protective film is arranged on the wafer and coats the first conductive elements.

In an embodiment of the present invention, the step (c) further includes: a plurality of second conductive elements are disposed on the plurality of conductive pillars exposed from the back surface of the wafer via grinding.

In an embodiment of the present invention, the step (d) further includes: the protective film is removed so that the wafer is separated into the plurality of semiconductor chips via the wafer portion cut out in the dicing street region.

In one embodiment of the present invention, the width of the scribe line region is 40 micrometers to 60 micrometers and the width of the cutter is 20 micrometers to 40 micrometers.

The present invention also provides a wafer for use in the method of manufacturing a semiconductor device as described above, wherein the wafer comprises: an active surface and a back surface, the back surface being disposed opposite the active surface; the semiconductor device comprises a semiconductor element region and a dicing channel region, wherein the dicing channel region is provided with a plurality of conductive posts, and the conductive posts are electrically connected to the semiconductor element in the semiconductor element region, and the conductive posts do not penetrate through the back surface of the wafer.

The present invention is a semiconductor package, comprising:

a substrate, wherein the substrate is provided with a controller chip and at least one passive device, and the substrate is provided with a plurality of connection pads;

a first semiconductor chip manufactured by the manufacturing method of the semiconductor element as described above is stacked on the substrate, wherein the first semiconductor chip is electrically connected to the plurality of connection pads through the plurality of conductive pillars located at the side of the first semiconductor chip; and

A second semiconductor chip manufactured by the manufacturing method of the semiconductor element as described above is stacked on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the plurality of conductive pillars located on the side of the first semiconductor chip through the plurality of conductive pillars located on the side of the second semiconductor chip.

Under the requirement of integration, the design of 10 micron-sized through-silicon vias on a chip is very large for DRAMs, and is extremely space consuming if the number of input/output terminals (I/os) to be designed is large. The invention designs through silicon vias in the dicing streets, which reduces the chip size and saves space, and can be completed in the back end (i.e., the packaging factory). In the case of a dicing lane of 40 to 60 μm, the invention is to provide a through-silicon via structure having a diameter of, for example, about 10 μm at each end of the dicing lane, and the total pore diameter of the two ends is about 20 μm. In addition to the through-silicon vias, there is room for the dicing to remain 20 to 40 microns, and there is still enough room for dicing to proceed. The invention can save area by moving the position of the silicon perforation structure to the cutting channel, thereby being convenient for packaging, or can increase the design quantity of the transistor, thereby accelerating the operation speed of the electronic device. For example, taking 100I/Os as an example, the occupied area is about 0.1 square millimeter, and the design of the present invention can increase the number of transistors by 15,000,000 transistors or reduce the chip size for the process of Taiwan electric company of 5 nanometers.

In order to make the above and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:

Drawings

Fig. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the invention.

Fig. 2 to 10 are schematic structural views of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 11 is a schematic top view of a semiconductor chip manufactured by the method for manufacturing a semiconductor device according to the embodiment of the present invention.

Fig. 12 is a schematic diagram showing a front view of a semiconductor package according to a first embodiment of the present invention.

Fig. 13 is a schematic diagram showing a front view of a semiconductor package according to a second embodiment of the present invention.

Detailed Description

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. Furthermore, directional terms, such as upper, lower, top, bottom, front, rear, left, right, inner, outer, side, surrounding, center, horizontal, transverse, vertical, longitudinal, axial, radial, uppermost or lowermost, etc., as used herein are used with reference to the accompanying drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention.

As used herein, reference to a numerical range of a variable is intended to mean that the variable is equal to any value within the range. Thus, for a variable that is itself discontinuous, the variable is equal to any integer value within the range of values, including the endpoints of the range. Similarly, for a variable that is itself continuous, the variable is equal to any real value within the range of values, including the endpoints of the range. As an example, and not by way of limitation, if the variable itself is discontinuous, a variable described as having a value between 0 and 2 takes on a value of 0,1 or 2; if the variable itself is continuous, then a value of 0.0, 0.1, 0.01, 0.001 or any other real value that is 0 or more and 2 or less is taken.

Referring to fig. 1, fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention. The method (S100) for manufacturing the semiconductor element comprises the following steps: (S101) providing a wafer, the wafer comprising: an active surface and a back surface, the back surface being disposed opposite the active surface; a semiconductor device region and a scribe line region, wherein the scribe line region has a plurality of conductive pillars, and the plurality of conductive pillars are electrically connected to the plurality of semiconductor devices in the semiconductor device region, and the plurality of conductive pillars do not penetrate through to the back surface of the wafer; (S102) dicing the wafer using a cutter to cut away a portion of the wafer and a portion of the plurality of conductive pillars in the scribe line region such that sides of the diced plurality of conductive pillars are exposed, wherein a width of the cutter is less than a width of the scribe line region; (S103) grinding the back surface of the wafer to expose the plurality of conductive pillars; and (S104) separating the wafer into a plurality of semiconductor chips via the portion of the wafer cut in the scribe line region.

Referring to fig. 2 to 10, schematic structural diagrams of a method for manufacturing a semiconductor device according to an embodiment of the invention are shown. First, referring to fig. 2, a wafer 100 includes: an active surface 101, a back surface 102, a semiconductor device region 103 and a scribe line region 104. The back surface 102 is arranged opposite to the active surface 101. Optionally, the wafer is a silicon wafer. The wafer 100 includes a substrate 106 on which a plurality of semiconductor devices 105 are disposed, and the plurality of semiconductor devices 105 are connected to a metal layer 107 so as to communicate with the outside. An insulating layer 108 is covered on the semiconductor elements 105 and the metal layer 107 to protect the semiconductor elements 105 and the metal layer 107.

First, referring to fig. 3 and 4, the scribe line region 104 has a plurality of conductive pillars 110 disposed therein, and the plurality of conductive pillars 110 are electrically connected to the plurality of semiconductor devices 105 in the semiconductor device region 103, wherein the plurality of conductive pillars 110 do not penetrate to the back surface 102 of the wafer 100. It is noted that the plurality of conductive pillars 110 are integrally disposed in the scribe line region 104 and not disposed in the semiconductor device region 103. In addition, the method for forming the plurality of conductive pillars 110 may be to form a plurality of through holes 109 by performing laser drilling on the wafer 100 to remove a portion of the material of the wafer 100. It should be noted that the plurality of vias 109 do not extend through to the back side 102 of the wafer 100. Next, a conductive material is filled into the plurality of through holes 109 to form the plurality of conductive pillars 110. The plurality of conductive pillars 110 do not extend through to the back surface 102 of the wafer 100.

In this embodiment, the semiconductor device region 103 has a metal layer 107 extending to the scribe line region 104, wherein when the wafer 100 is laser drilled, the laser simultaneously removes a portion of the metal layer 107, such that the plurality of conductive pillars 110 form an electrical connection with the metal layer 107 when the conductive material fills the plurality of vias 109.

Next, as shown in fig. 5, a cutter 120 is used to cut the wafer 100 to remove a portion of the wafer 100 and a portion of the plurality of conductive pillars 110 in the scribe line region 104, so that the side surfaces of the plurality of conductive pillars 110 after cutting are exposed, wherein the width W1 of the cutter 120 is smaller than the width W2 of the scribe line region.

Optionally, as shown in fig. 6, the present embodiment further includes: disposing a plurality of first conductive elements 130 on the plurality of conductive pillars 110; and as shown in fig. 7, a protective film 140 is disposed on the wafer 100 and covers the first conductive elements 130. It should be noted that the step of disposing the plurality of first conductive elements 130 on the plurality of conductive posts 110 shown in fig. 6 may be performed before the step of fig. 5 or after the step of fig. 5.

Next, as shown in fig. 8, the back surface 102 of the wafer 100 is polished to expose the plurality of conductive pillars 110.

Optionally, as shown in fig. 9, a plurality of second conductive elements 150 are disposed on the plurality of conductive pillars 110 exposed from the back surface 102 of the wafer 100 via grinding.

Finally, as shown in fig. 10, the protective film 140 is removed, so that the wafer 100 is separated into a plurality of semiconductor chips 200 via the portion of the wafer 100 cut out in the scribe line region 104.

In one embodiment of the present invention, the width of the scribe line region is 40 to 60 microns and the width of the cutter is 20 to 40 microns.

As shown in fig. 11, fig. 11 shows a schematic top view of a semiconductor chip 200 manufactured by the method for manufacturing a semiconductor element according to the present invention. The semiconductor chip 200 includes: a semiconductor device region 203 and a scribe line residual region 204. The scribe line residual region 204 has a plurality of conductive pillars 210 disposed at the edge of the semiconductor chip 200. It should be noted that the plurality of conductive posts 210 may be formed in a non-complete cylindrical shape (e.g., a semi-cylindrical shape) by being cut.

It should be noted that, in general, under the requirement of integration, the design of 10 μm-diameter through-silicon vias on a chip is very large for DRAMs, and is even more space consuming if the number of I/os to be designed is large. The design of the invention is to design the aperture in the cutting path, so that the chip size can be reduced, the space can be saved, and the design can be completed in the rear section. In the case of a dicing lane of 40 to 60 μm, the invention is to provide a through-silicon via structure having a diameter of, for example, about 10 μm at each end of the dicing lane, and the total pore diameter of the two ends is about 20 μm. In addition to the through-silicon vias, there is room for the dicing to remain 20 to 40 microns, and there is still enough room for dicing to proceed. The invention can save area by moving the position of the silicon perforation structure to the cutting channel, thereby being convenient for packaging, or can increase the design quantity of the transistor, thereby accelerating the operation speed of the electronic device. For example, taking 100I/Os as an example, the occupied area is about 0.1 square millimeter, and the design of the present invention can increase the number of transistors by 15,000,000 transistors or reduce the chip size for the process of Taiwan electric company of 5 nanometers.

As described above, the present invention also provides a wafer 100 for use in the method of manufacturing a semiconductor device as described above. As shown in fig. 4, the wafer 100 includes: an active surface 101 and a back surface 102, the back surface 102 being disposed opposite the active surface 101; a semiconductor device region 103 and a scribe line region 104, the scribe line region 104 has a plurality of conductive pillars 110 disposed therein, and the plurality of conductive pillars 110 are electrically connected to the semiconductor devices 105 in the semiconductor device region 103, wherein the plurality of conductive pillars 110 do not penetrate to the back surface 102 of the wafer 100.

The present invention also provides a semiconductor package comprising: a substrate, wherein the substrate is provided with a controller chip and at least one passive device, and the substrate is provided with a plurality of connection pads; a first semiconductor chip manufactured by the manufacturing method of the semiconductor element as described above is stacked on the substrate, wherein the first semiconductor chip is electrically connected to the plurality of connection pads through the plurality of conductive pillars located at the side of the first semiconductor chip; and a second semiconductor chip manufactured by the manufacturing method of the semiconductor element as described above is stacked on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the plurality of conductive pillars located on the side of the first semiconductor chip through the plurality of conductive pillars located on the side of the second semiconductor chip.

Referring to fig. 12, fig. 12 is a schematic front view of a semiconductor package according to a first embodiment of the invention. A semiconductor package 30 comprising: a substrate 310, wherein the substrate 310 is provided with a controller chip 311 and at least one passive device 312, and the substrate 310 has a plurality of connection pads 313.

In one embodiment, the controller chip 311 is a Microcontroller (MCU). Alternatively, the passive devices 312 may be resistors or capacitors and are electrically connected to the controller chip 311.

Optionally, the controller chip 311 is a pad connected to the surface of the substrate 310 by flip-chip packaging. The passive devices 312 are connected to the traces on the surface of the substrate 310 by surface mount technology.

The substrate 310 has a first semiconductor chip 320 stacked thereon, and the first semiconductor chip 320 is manufactured by the manufacturing method of the semiconductor device as described above. The first semiconductor chip 320 is stacked on a surface of the substrate 310, wherein the first semiconductor chip 320 is electrically connected to the plurality of connection pads 313 through the plurality of first conductive pillars 321 located at the side of the first semiconductor chip 320. Optionally, the first semiconductor chip 320 conducts the plurality of first conductive pillars 321 of the first semiconductor chip 320 with the plurality of connection pads 313 through a plurality of first conductive bumps 322.

Alternatively, the first semiconductor chip 320 may be a flash memory chip. The first semiconductor chip 320 may be controlled by the controller chip 311.

It should be noted that the first semiconductor chip 320 has a similar structure as that of fig. 11, i.e., the plurality of first conductive pillars 321 are in a non-complete cylindrical shape (e.g., a semi-cylindrical shape) due to dicing.

The first semiconductor chip 320 has a second semiconductor chip 330 stacked thereon, and the second semiconductor chip 330 is manufactured by the manufacturing method of the semiconductor device as described above.

The second semiconductor chip 330 is stacked on a surface of the first semiconductor chip 320, wherein the second semiconductor chip 330 is electrically connected to the first semiconductor chip 320 through the plurality of second conductive pillars 331 located at the side of the second semiconductor chip 330.

Alternatively, the second semiconductor chip 330 conducts the plurality of second conductive pillars 331 of the second semiconductor chip 330 with the plurality of first conductive pillars 321 of the first semiconductor chip 320 through a plurality of second conductive bumps 332. The second semiconductor chip 330 may be controlled by the controller chip 311.

It should be noted that the second semiconductor chip 330 also has a similar structure as that of fig. 11, i.e., the plurality of second conductive pillars 331 are in a non-complete cylindrical shape (e.g., a semi-cylindrical shape) due to dicing.

In addition, in some embodiments of the present invention, a plurality of third conductive pillars 341, such as copper pillars (copper pillars), are disposed on the plurality of connection pads 313, and the first semiconductor chip 320 connects the plurality of first conductive pillars 321 of the first semiconductor chip 320 with the plurality of third conductive pillars 341 through the plurality of first conductive bumps 322.

It should be noted that the third conductive pillars 341 are different from the first conductive pillars 321 and the second conductive pillars 331, i.e., the third conductive pillars 341 are not cut and have a complete cylindrical shape.

Referring to fig. 13, fig. 13 is a schematic front view of a semiconductor package according to a second embodiment of the invention. The semiconductor package of the second embodiment of the present invention shown in fig. 13 is substantially the same as the semiconductor package of the first embodiment of the present invention shown in fig. 12, except that the substrate 310 and the first semiconductor chip 320 are electrically connected through the second substrate 450 and the third substrate 460. Hereinafter, a semiconductor package according to a second embodiment of the present invention will be described in detail with reference to fig. 13.

A semiconductor package 40 comprising: a first substrate 410, wherein the first substrate 410 is provided with a controller chip 411 and at least one passive device 412, and the first substrate 410 has a plurality of first connection pads 413.

In one embodiment, the controller chip 411 is a Microcontroller (MCU). Alternatively, the passive devices 412 may be resistors or capacitors and are electrically connected to the controller chip 411.

Optionally, the controller chip 411 is a pad connected to the surface of the first substrate 410 by flip-chip packaging. The passive devices 412 are connected to the wires on the surface of the first substrate 410 through surface assembly technology.

The first substrate 410 has a second substrate 450 stacked thereon. Optionally, the second substrate 450 is electrically connected to the first substrate 410 through a plurality of conductive elements (e.g., solder balls, conductive bumps, copper pillars, etc.).

The second substrate 450 has a hollowed-out area (for example, a top-down shape of a mouth) for disposing the controller chip 411 and the at least one passive device 412. Optionally, the second substrate 450 has a plurality of circuit layers therein.

A third substrate 460 is stacked on the second substrate 450. The third substrate 460 may have a plurality of circuit layers, and a plurality of second connection pads 463 are disposed on a surface of the third substrate 460. Optionally, the third substrate 460 is electrically connected to the second substrate 450 through a plurality of conductive elements (e.g., solder balls, conductive bumps, copper pillars, etc.).

Alternatively, the first substrate 410, the second substrate 450 and the third substrate 460 may be electrically connected to each other by eutectic bonding.

The third substrate 460 has a first semiconductor chip 420 stacked thereon, and the first semiconductor chip 420 is manufactured by the manufacturing method of the semiconductor device as described above. The first semiconductor chip 420 is stacked on a surface of the third substrate 460, wherein the first semiconductor chip 420 is electrically connected to the second connection pads 463 on the third substrate 460 through the first conductive pillars 421 located at the side of the first semiconductor chip 420.

Optionally, the first semiconductor chip 420 conducts the plurality of first conductive pillars 421 of the first semiconductor chip 420 with the plurality of second connection pads 463 through a plurality of first conductive elements 422 (e.g., solder balls, conductive bumps, copper pillars, etc.).

Alternatively, the first semiconductor chip 420 may be a flash memory chip. The first semiconductor chip 420 may be controlled by the controller chip 411.

It should be noted that the first semiconductor chip 420 has a similar structure as that of fig. 11, i.e., the plurality of first conductive pillars 421 have a non-complete cylindrical shape (e.g., a semi-cylindrical shape) after being cut.

A second semiconductor chip 430 is stacked on the first semiconductor chip 420, and the second semiconductor chip 430 is manufactured by the manufacturing method of the semiconductor device as described above.

The second semiconductor chip 430 is stacked on a surface of the first semiconductor chip 420, wherein the second semiconductor chip 430 is electrically connected to the first semiconductor chip 420 through the plurality of second conductive pillars 431 located at a side of the second semiconductor chip 430.

Alternatively, the second semiconductor chip 430 conducts the plurality of second conductive pillars 431 of the second semiconductor chip 430 with the plurality of first conductive pillars 421 of the first semiconductor chip 420 through a plurality of second conductive members 432 (e.g., solder balls, conductive bumps, copper pillars, etc.), so that the second semiconductor chip 430 can be controlled by the controller chip 411.

It should be noted that the second semiconductor chip 430 also has a similar structure as that of fig. 11, i.e., the plurality of second conductive pillars 431 have a non-complete cylindrical shape (e.g., a semi-cylindrical shape) due to dicing.

According to the semiconductor package of the embodiment of the invention, high integration can be achieved. The 10 micron aperture through silicon vias designed on chip are very large for DRAMs, and can be very space consuming if the number of I/os to be designed is large. The invention designs through silicon vias in the dicing streets, which reduces the chip size and saves space, and can be completed in the back end (i.e., the packaging factory). In the case of a dicing lane of 40 to 60 μm, the invention is to provide a through-silicon via structure having a diameter of, for example, about 10 μm at each end of the dicing lane, and the total pore diameter of the two ends is about 20 μm. In addition to the through-silicon vias, there is room for the dicing to remain 20 to 40 microns, and there is still enough room for dicing to proceed. The invention can save area by moving the position of the silicon perforation structure to the cutting channel, thereby being convenient for packaging, or can increase the design quantity of the transistor, thereby accelerating the operation speed of the electronic device. For example, taking 100I/Os as an example, the area occupied by the transistor is about 0.1 square millimeter, and the process of Taiwan of 5 nanometers is designed to increase the number of transistors by 15,000,000, or to reduce the chip size

Although the present invention has been described in terms of preferred embodiments, it is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the invention is capable of numerous modifications and variations within the spirit and scope of the invention as defined in the appended claims.

The foregoing has described in detail the semiconductor device, semiconductor package and method of manufacturing the same provided by the embodiments of the present application, and specific examples have been employed herein to illustrate the principles and embodiments of the present application, the above examples being provided only to assist in understanding the method of the present application and its core ideas; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) Providing a wafer, the wafer comprising: an active surface and a back surface, the back surface being disposed opposite the active surface; a semiconductor device region and a scribe line region, wherein the scribe line region has a plurality of conductive pillars, and the plurality of conductive pillars are electrically connected to the plurality of semiconductor devices in the semiconductor device region, and the plurality of conductive pillars do not penetrate through to the back surface of the wafer;

(b) Cutting the wafer by using a cutter to cut away part of the wafer and part of the conductive posts in the cutting channel area, so that the side surfaces of the cut conductive posts are exposed, wherein the width of the cutter is smaller than that of the cutting channel area;

(c) Grinding the back surface of the wafer to expose the plurality of conductive pillars; and

(D) The wafer is separated into a plurality of semiconductor chips via the portion of the wafer that is cut out in the scribe line region.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of conductive pillars are integrally provided in the scribe line region and not provided in the semiconductor device region.

3. The method of manufacturing a semiconductor device according to claim 1, wherein step (a) further comprises: laser drilling the wafer to remove a portion of the wafer material to form a plurality of through holes, wherein the plurality of through holes do not extend through to the back side of the wafer; and

A conductive material is filled into the plurality of vias to form the plurality of conductive pillars.

4. The method of claim 3, wherein the semiconductor device region has a metal layer extending to the scribe line region, wherein laser simultaneously removes portions of the metal layer when the wafer is laser drilled such that the plurality of conductive pillars form electrical connection with the metal layer when the conductive material is filled into the plurality of vias.

5. The method of manufacturing a semiconductor device according to claim 1, wherein step (a) further comprises: a plurality of first conductive elements are disposed on the plurality of conductive posts.

6. The method of manufacturing a semiconductor device according to claim 5, further comprising, after step (a): a protective film is arranged on the wafer and coats the first conductive elements.

7. The method of manufacturing a semiconductor device according to claim 6, wherein step (c) further comprises: a plurality of second conductive elements are disposed on the plurality of conductive pillars exposed from the back surface of the wafer via grinding.

8. The method of manufacturing a semiconductor device according to claim 7, wherein step (d) further comprises: the protective film is removed so that the wafer is separated into the plurality of semiconductor chips via the portion of the wafer cut out in the dicing street area.

9. The method of manufacturing a semiconductor device according to claim 1, wherein the dicing street region has a width of 40 μm to 60 μm and the cutter has a width of 20 μm to 40 μm.

10. A semiconductor package, the semiconductor package comprising:

a substrate, wherein the substrate is provided with a controller chip and at least one passive device, and the substrate is provided with a plurality of connection pads;

A first semiconductor chip manufactured by the manufacturing method of a semiconductor device according to any one of claims 1 to 9, stacked on the substrate, wherein the first semiconductor chip is electrically connected to the plurality of connection pads through the plurality of conductive pillars located at the side of the first semiconductor chip; and

A second semiconductor chip manufactured by the manufacturing method of a semiconductor element according to any one of claims 1 to 9 is stacked on the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the plurality of conductive pillars located on the side of the first semiconductor chip through the plurality of conductive pillars located on the side of the second semiconductor chip.