CN117913017A - Thin film semiconductor chip preparation method and thin film semiconductor chip preparation structure - Google Patents
Thin film semiconductor chip preparation method and thin film semiconductor chip preparation structure Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 138
- 239000010409 thin film Substances 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 139
- 229910052751 metal Inorganic materials 0.000 claims abstract description 75
- 239000002184 metal Substances 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 39
- 239000002131 composite material Substances 0.000 claims abstract description 35
- 230000008569 process Effects 0.000 claims abstract description 30
- 238000012545 processing Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims description 25
- 239000007788 liquid Substances 0.000 claims description 12
- 238000000227 grinding Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 239000007791 liquid phase Substances 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 119
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 19
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 19
- 239000010408 film Substances 0.000 description 18
- 239000000243 solution Substances 0.000 description 14
- 239000002346 layers by function Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 230000007797 corrosion Effects 0.000 description 8
- 238000005260 corrosion Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
- H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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Abstract
The application discloses a preparation method and a corresponding preparation structure of a thin film semiconductor chip. The method comprises the following steps: epitaxially growing a semiconductor chip epitaxial wafer on the first temporary substrate; preparing a composite metal substrate on a semiconductor chip epitaxial wafer; etching the sacrificial layer through a first etching solution, and stripping the semiconductor chip epitaxial wafer from the first temporary substrate; taking the composite metal substrate as a support, and carrying out subsequent chip processing on the semiconductor chip epitaxial wafer; and removing the second temporary substrate to obtain the thin film semiconductor chip. According to the preparation method and the corresponding preparation structure of the thin film semiconductor chip, the composite metal substrate is arranged, and comprises the thin film metal layer, the stop layer and the second temporary substrate, so that the composite metal substrate has enough thickness and supporting capacity in the chip processing process, and the requirement of chip thinning can be met by removing the second temporary substrate after the chip processing is finished; the process is simple and easy to implement.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a thin film semiconductor chip preparation technology.
Background
With the development of semiconductor technology, semiconductor chips with high power-weight ratio, thin film and flexibility are receiving more and more attention, and the semiconductor chips become the fields and the technical development directions of important research. Thin film semiconductor chips, such as thin film photodetector chips, LED chips, solar cell chips, etc., can be made in a micrometer or nanometer size, and because of their small thickness, the materials have weak mechanical strength and are liable to warp, it is generally necessary to process the chips on a hard substrate having a certain strength.
Therefore, in the process of manufacturing the semiconductor chip, the semiconductor chip epitaxial wafer is temporarily bonded on a hard supporting substrate, such as a silicon wafer and a sapphire wafer, and then the subsequent manufacturing process of the chip is performed, and the bonding layer and the hard substrate are removed after all the processing processes are completed. However, the temporary bonding method is adopted to connect the thin film chip on the supporting substrate, and then the chip is manufactured, so that the thin film chip belongs to the temporary bonding supporting substrate structure, and the limiting factors on the chip process are more, such as high temperature resistance, corrosion resistance and the like; in addition, the film chip can be secondarily damaged along with the temporary bonding and the temporary debonding in the process of temporary bonding, so that irreversible material defects of the film chip are caused, and quality parameters of the film chip are abnormal and yield is lost.
In the prior art, a metal substrate is also used as a film supporting substrate, but the thickness of the metal substrate is not easy to master, and the metal substrate is too thin to play a supporting role, so that the subsequent chip manufacturing is not facilitated; too thick and not meeting the requirement of chip thinning.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a process and a structure for manufacturing a thin film semiconductor chip, which can meet both the chip processing requirement and the requirement for thinning.
It is another object of the present application to avoid damage to the chip by using temporary bonding processes.
In one aspect, the present application provides a method for manufacturing a thin film semiconductor chip, including:
Epitaxially growing a semiconductor chip epitaxial wafer on a first temporary substrate, the semiconductor chip epitaxial wafer including a sacrificial layer adjoining the temporary substrate;
preparing a composite metal substrate on the opposite side of the semiconductor chip epitaxial wafer from the first temporary substrate, wherein the composite metal substrate comprises a thin film metal layer, a stop layer and a second temporary substrate in sequence from one side of the semiconductor chip epitaxial wafer;
etching the sacrificial layer through a first etching solution, and stripping the semiconductor chip epitaxial wafer from the first temporary substrate;
taking the composite metal substrate as a support, and carrying out subsequent chip processing on the side of the semiconductor chip epitaxial wafer opposite to the composite metal substrate; and
And removing the second temporary substrate and the cut-off layer to obtain the thin film semiconductor chip.
According to one embodiment of the present application, preparing a composite metal substrate on a side of a semiconductor chip epitaxial wafer opposite to a first temporary substrate includes:
And sequentially depositing a thin film metal layer, a stop layer and a temporary metal substrate layer on the semiconductor chip epitaxial wafer by adopting an evaporation process or a liquid phase deposition process.
According to one embodiment of the application, removing the second temporary substrate and the stop layer comprises:
And etching the stop layer by a second etching solution to peel the thin film semiconductor chip from the second temporary substrate.
According to one embodiment of the present application, the thin film semiconductor chip manufacturing method further includes: before etching the cut-off layer by the second etching liquid, the semiconductor chip is vertically divided up to the upper surface of the cut-off layer or the upper surface of the second temporary substrate.
According to one embodiment of the application, removing the second temporary substrate and the stop layer comprises:
The second temporary substrate is removed by grinding, after which the stop layer is etched by a second etching solution.
According to one embodiment of the application, the thin film metal layer has a thickness of 10-100um.
According to one embodiment of the application, the stop layer is a metal layer and the second temporary substrate is a metal substrate.
According to one embodiment of the present application, the thin film semiconductor chip is a light emitting diode device, a photovoltaic cell device, or a photodetector.
Another aspect of the present application provides a thin film semiconductor chip manufacturing structure, sequentially comprising:
A semiconductor chip epitaxial wafer on a first temporary substrate, wherein a sacrificial layer is arranged between the semiconductor chip epitaxial wafer and the temporary substrate, and the sacrificial layer is used for stripping the semiconductor chip and the first temporary substrate subsequently; and
And the composite metal substrate on the semiconductor chip epitaxial wafer sequentially comprises a thin film metal layer, a stop layer and a second temporary substrate from one side of the semiconductor chip epitaxial wafer, wherein the stop layer is used for stripping the semiconductor chip and the second temporary substrate.
According to one embodiment of the application, the thin film metal layer has a thickness of 10-100um.
According to the preparation method and the corresponding preparation structure of the thin film semiconductor chip, the composite metal substrate is arranged and comprises the thin film metal layer, the stop layer and the second temporary substrate, so that the composite metal substrate has enough thickness and supporting capacity in the chip processing process, and can meet the supporting requirement of chip processing; on the other hand, after the chip is processed, the requirement of chip thinning can be met by removing the second temporary substrate and the stop layer; therefore, the preparation method and the corresponding preparation structure of the thin film semiconductor chip can simultaneously meet the chip processing requirement and the thinning requirement, and the preparation method and the corresponding preparation structure of the thin film semiconductor chip are simple in process and easy to implement.
In addition, the preparation method and the corresponding preparation structure of the thin film semiconductor chip avoid secondary damage of the thin film chip caused by the fact that the semiconductor epitaxial wafer is connected with the support substrate by adopting a bonding process in the temporary bonding and debonding process, and improve the yield of the thin film semiconductor chip.
Drawings
Fig. 1 is a flowchart of a thin film semiconductor chip fabrication method according to one embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a thin film semiconductor chip fabrication structure after completion of step S2 of fig. 1;
Fig. 3 is a schematic cross-sectional view of a thin film semiconductor chip fabrication structure after completion of step S4 of fig. 1;
Fig. 4 is a schematic cross-sectional view of a thin film semiconductor chip fabrication structure after completion of step S5 of fig. 1;
Fig. 5 is a schematic view showing a manufacturing structure of a thin film semiconductor chip according to an exemplary embodiment of the present application;
Fig. 6 is a schematic structural view of the thin film semiconductor chip of fig. 5 after completion of fabrication.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following describes in detail the exemplary embodiments of the present application with reference to the accompanying drawings, in which the same or similar reference numerals are used for the same or similar functional components. Also, some components not directly related to the inventive concept may be omitted from illustration. The drawings and descriptions of specific embodiments are presented only to provide a better understanding of the application and the application is not limited to the embodiments illustrated in the drawings and described in the specification.
Technical or scientific terms used herein should be given the ordinary meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "comprising" or "includes" and the like in this specification is intended to be open-ended terms that do not exclude other elements, components, parts, or items than those explicitly listed. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed. "first," "second," etc. are used for the purpose of distinguishing between different elements and not necessarily for a specific order.
Referring to fig. 1 to 4, a method for manufacturing a thin film semiconductor chip according to an embodiment of the present application includes the steps of:
Step S1: epitaxially growing a semiconductor chip epitaxial wafer on the first temporary substrate 200, the semiconductor chip epitaxial wafer including a semiconductor functional layer 204 and a sacrificial layer 202 adjoining the first temporary substrate 200; wherein the sacrificial layer is subsequently used to strip the semiconductor chip and the first temporary substrate 200. The first temporary substrate 200 may be a GaAs substrate, a silicon substrate, or the like. The semiconductor chip may be a light emitting diode device, a photovoltaic cell device, a photodetector, or the like. Accordingly, the semiconductor functional layer 204 may include a light emitting diode functional layer, a photovoltaic cell functional layer, a photodetector functional layer, or the like. In some embodiments, the semiconductor chip epitaxial wafer may include a buffer layer, an ohmic contact layer, and the like as necessary, and the illustration thereof is omitted here.
Next, in step S2, a composite metal substrate is prepared on the semiconductor chip epitaxial wafer, the composite metal substrate including, in order, a thin film metal layer 102, a stopper layer 101, and a second temporary substrate 100; wherein the stop layer 101 is subsequently used for peeling off the semiconductor chip and the second temporary substrate 100. Here, the thickness of the thin film metal layer 102 may be 10-100um, the thickness of the blocking layer 101 may be 10-50um, and the thickness of the second temporary substrate 100 may be 150-450 um. The blocking layer 101 may be selected to be a metallic material or other materials, and the second temporary substrate 100 may be selected to be a metallic material. According to some embodiments of the application, preparing a composite metal substrate on a semiconductor chip epitaxial wafer includes: and sequentially depositing a thin film metal layer, a stop layer and a temporary metal substrate layer on the semiconductor chip epitaxial wafer by adopting an evaporation process or a liquid phase deposition process.
The thin film semiconductor chip preparation structure after completion of steps S1-S2 is shown in fig. 2.
Next, in step S3, the sacrificial layer 202 is etched and cleaned by the first etching solution, and the semiconductor chip epitaxial wafer is peeled from the first temporary substrate 200; here, the first etching liquid may be selected to have selective etching to the sacrificial layer 202 and the semiconductor chip epitaxial wafer, i.e., the first etching liquid may etch the sacrificial layer but not the semiconductor chip epitaxial wafer. Alternatively, other processes may be used to remove the sacrificial layer 202 and the first temporary substrate 200, resulting in a semiconductor chip epitaxial wafer comprising only the composite metal substrate.
Next, in step S4, the semiconductor chip preparation structure peeled from the first temporary substrate 200 is turned over, with the composite metal substrate as a support, and subsequent chip processing is performed on the opposite side of the semiconductor chip epitaxial wafer from the composite metal substrate, to prepare various desired structures on the semiconductor epitaxial wafer according to the specific semiconductor chip type. For example, an electrode 206, an antireflection film 205, and the like are prepared on the semiconductor functional layer 204, as shown in fig. 3.
Next, in step S5, the second temporary substrate 100 is removed, and a thin film semiconductor chip is obtained. Specifically, in some embodiments, removing the second temporary substrate 100 includes: the thin film semiconductor chip is peeled from the second temporary substrate 100 by etching the cleaning cutoff layer 101 with the second etching liquid. Here, the second etching liquid may be selected to have a selective etching to the cut-off layer 101 and the flexible metal layer 102, i.e., the second etching liquid may etch the cut-off layer 101 but not the flexible metal layer 102.
According to this embodiment, the semiconductor chip layer is divided vertically in advance until the upper surface of the stop layer 101 or the upper surface of the second temporary substrate 100, optionally, before the stop layer 101 is etched by the second etching liquid. For example, a boundary region between individual chips in the semiconductor chip layer may be etched using a photolithography process to separate a chip portion above the upper surface of the cutoff layer 101 or above the upper surface of the second temporary substrate 100 into individual chip units in advance. Thereafter, the cut-off layer 101 is etched and cleaned by the second etching liquid, and the thin film semiconductor chip is peeled off from the second temporary substrate 100. The etching solution can etch the stop layer in the whole range of the semiconductor chip layer, but not only from the side surface, thereby being beneficial to uniformly and efficiently etching the stop layer and ensuring the thickness of the semiconductor chip to be uniform; after the second etching solution etches the cut-off layer 101, the chips are formed as separate individual chips, and the chip separation work is not necessary.
In another embodiment, the second temporary substrate 100 and the stop layer 101 may be removed by a polish-bonded etch cleaning to obtain a thin film semiconductor chip, i.e., the second temporary substrate 100 is removed by polishing, and then the stop layer 101 is etched by a second etching liquid. The polishing process has the characteristic of uneven thickness of a polishing plane, the thickness fluctuates within a certain error range, the embodiment is firstly polished to the stop layer 101, the stop layer plane has the condition of uneven thickness, and then the thin stop layer is cleaned by adopting a solution, so that the thin semiconductor chip with consistent specification can be obtained. Compared with the process of directly grinding the flexible metal layer, the process of grinding and corrosion cleaning can avoid uneven thickness of the flexible substrate caused by directly grinding the flexible metal layer; compared with the scheme of independent corrosion cleaning, the method can avoid the work of independent corrosion cleaning of the subsequent treatment reactant. In addition, the second temporary substrate 100 and the stop layer 101 are removed by grinding and etching, and the semiconductor chip layer can be divided before or after the second temporary substrate 100 is removed, so that the process has more flexibility.
After step S5, the resulting thin film semiconductor chip structure is shown in fig. 4.
As described above, the composite metal substrate is provided and comprises the thin film metal layer, the stop layer and the second temporary substrate, so that the composite metal substrate has enough thickness and supporting capacity in the chip processing process, and can meet the supporting requirement of chip processing; on the other hand, after the chip processing is finished, the requirement of chip thinning can be met by removing the second temporary substrate. Therefore, the preparation method and the corresponding preparation structure of the thin film semiconductor chip can simultaneously meet the chip processing requirement and the thinning requirement.
In addition, the thin film semiconductor chip preparation method and the corresponding preparation structure adopt the processes of vapor deposition, liquid phase deposition, grinding, corrosive liquid cleaning and the like to prepare the thin film semiconductor chip, the process compatibility in the whole process of chip preparation is high, the process is simple, the implementation is easy, the secondary damage of the thin film chip caused by the fact that the bonding process is adopted to connect the semiconductor epitaxial wafer and the supporting substrate in the temporary bonding and debonding process of the thin film chip is avoided, and the yield of the thin film semiconductor chip is improved.
The process of manufacturing the thin film semiconductor chip of the present invention will be described below with reference to specific examples.
Referring to fig. 5-6, in one specific embodiment, the thin film semiconductor chip of the present invention is fabricated as follows:
Firstly, preparing a flip-chip semiconductor chip, which specifically comprises the following steps:
1. GaAs is used as a temporary substrate, and a GaAs buffer layer, a first sacrificial layer/corrosion barrier layer for stripping, an epitaxial functional layer 104 and an ohmic contact layer 103 are grown on the GaAs substrate by a metal organic vapor deposition (MOCVD) or Molecular Beam Epitaxy (MBE) method.
The GaAs substrate is an N-type conductive substrate. The stripping substrate sacrificial layer is made of AlAs or AlxGaAs materials with the thickness of 10-50 nm, and the component x of Al is 0.4< x less than or equal to 1. Alternatively, the etch stop layer may be GaInP. The ohmic contact layer 103 may be any one or any combination of two or more metal materials selected from Pd, au, ag, ni, ti, zn, al, cu, fe.
Further, the epitaxial functional layer may be selected from one of the following:
1.1 the epitaxial functional layer can be selected as an electro-optic conversion layer to form a light-emitting diode device structure, an N-type semiconductor, a multiple quantum well and a P-type semiconductor structure manufactured by a film type semiconductor manufacturing process are selected, high-concentration electrons and holes are respectively injected into the quantum well from an N-type semiconductor region and a P-type semiconductor region to be compounded, photons are generated, and electric-optical conversion is realized. Taking a red light emitting diode as an example, an N-AlInP layer, an AlGaInP multilayer quantum well and a P-AlInP layer can be selected as the epitaxial functional layer.
1.2 The epitaxy functional layer can be selected as a photoelectric conversion layer to form a photovoltaic cell device structure, and an N-type semiconductor structure and a P-type semiconductor structure manufactured by a thin film type semiconductor preparation process are selected, wherein the photovoltaic cell has the following working principle: (1) Electrons in the semiconductor absorb photons from an external light source (sun, laser, various fluorescence), the photons excite electrons to generate electron-hole pairs, and the unbalanced carriers have enough service life and do not recombine and disappear before separation; (2) The generated unbalanced carriers finish the separation of electron-hole pairs under the action of a built-in electric field, electrons are concentrated on one side of an N-type semiconductor, holes are concentrated on one side of a P-type semiconductor, and opposite charges are accumulated on two sides of a PN junction, so that photo-generated electromotive force is generated; (3) PN junctions are connected by leads to form current and supply power to a load through an external circuit, so that effective power output can be obtained.
Gallium arsenide is a direct transition type material, the gallium arsenide material can absorb sunlight with the wavelength ranging from 300 nm to 900nm, the thickness of the material ranging from 5 μm to 10 μm can absorb sunlight up to 95%, high photoelectric conversion efficiency can be achieved, and the single junction photovoltaic device of the photovoltaic device can select N-type GaAs/P-type GaAs. In order to further improve photoelectric conversion efficiency, a multi-junction photovoltaic cell is arranged, and semiconductor energy bands are regulated and controlled in a doping mode and the like, so that absorption of different wavebands is realized by different cells, and the light utilization rate is further improved; the typical multi-junction battery can be a GaInP/GaAs/InGaAs three-junction battery and has the characteristics of high conversion efficiency, excellent anti-radiation performance, stable performance and the like.
1.3 The epitaxial functional layer can be selected as an infrared detection layer formed by a photoelectric conversion layer. The basic principle of semiconductor detection is similar to that of a photovoltaic cell, and photons are detected to enter a PN junction to generate electron-hole pairs, and the electron-hole pairs drift under the action of an external electric field to output signals. In particular as a change in the number of corresponding carriers (i.e. electron-holes) of the detector. Taking infrared detection as an example, an InP/InGaAs material system can be selected as an infrared detector aiming at III-V materials, and the infrared detector has the characteristics of high detection rate, high uniformity, high stability and the like.
2. Growing a support substrate on the ohmic contact layer
The support substrate is a composite metal substrate, and the composite metal substrate at least comprises a flexible metal layer 102, a stop layer 101 and a temporary metal substrate layer 100. The metal substrate layer 100 mainly serves as a temporary support, and helps to realize the peeling of the epitaxial layer from the temporary GaAs substrate in the subsequent step and the growth of the subsequent structural layer. The stop layer 101 is finally removed by etching to separate the temporary metallic substrate layer 100 and the flexible metallic layer 102. The flexible metal layer 102 eventually serves as a part of the semiconductor chip, serves as a chip electrode and maintains flexibility of the entire chip, and its thickness may be set to 10-100um as needed.
Specifically, a composite metal substrate is prepared by adopting an evaporation mode; compared with bonding, the vapor plating process flow is simple, the same vapor plating equipment can be adopted, and the deposition of the multi-layer metal of the composite metal substrate can be carried out only by replacing the vapor plating source. Alternatively, the preparation of the composite metal substrate may also be performed by liquid phase deposition.
3. Stripping to remove temporary GaAs substrate
The first sacrificial layer can realize chemical stripping, and the realization principle is that a sacrificial layer is arranged between two films, and the high selectivity of the etching solution to the sacrificial layer and the two films is utilized, namely, the etching rate of the etching solution to the sacrificial layer is far higher than that of the two films, so that the etching of the etching solution to the two films can be ignored. And removing the sacrificial layer by using corrosive liquid to realize the separation of the two films. The stripping sacrificial layer is made of a material with a much higher corrosion rate than GaAs in an acidic or oxidizing solution, such as HF, and the gallium arsenide substrate is stripped and removed. Namely, immersing the AlAs sacrificial layer in HF solution to etch away the AlAs sacrificial layer so as to enable the gallium arsenide substrate to fall off, thus obtaining the epitaxial layer film with the composite metal substrate.
In other embodiments of the present invention, for the corrosion barrier layer, the gallium arsenide substrate is etched by using a mixed solution of phosphoric acid and hydrogen peroxide, the gallium arsenide is removed, and then the corrosion barrier layer GaInP is removed by using a mixed solution of nitric acid and hydrochloric acid, so as to realize the temporary GaAs substrate stripping, and obtain the epitaxial layer film with the composite metal substrate.
4. Preparing an electrode 106 on one surface of the epitaxial layer film, which is stripped from the gallium arsenide substrate
Specifically, the electrode 106 is prepared by photolithography, metal evaporation, photoresist removal.
5. Preparation of an antireflection film 105 around the electrode 106
Specifically, the antireflection film 105 can be manufactured by photolithography, evaporation of a TiO2/Al2O3 double antireflection film and photoresist removal.
The structure of the semiconductor chip obtained is shown in fig. 5.
6. Dicing epitaxial layers and portions of composite metal substrates
Covering the electrode 106 and the antireflection film 105 with photoresist; the method is that the effective area of the chip is covered with photoresist, the cutting area is free of photoresist, and the epitaxial layer and part of the composite metal substrate are etched along the cutting area in the direction vertical to the chip. Specifically, the epitaxial layer and the flexible metal layer can be selectively etched; optionally, the epitaxial layer, the flexible metal layer 102, the stop layer 101 may be selectively etched. Specifically, dry etching or wet etching may be selected.
7. The cut-off layer 101 and the temporary metal substrate layer 100 are removed to obtain a thinned semiconductor chip.
The temporary metal substrate 100 on the back of the chip is ground, specifically, optionally polished, thinned to a preset cut-off layer 101, and then the cut-off layer 101 is cleaned by wet chemical method using etching solution, so as to obtain super-filmed single chip particles, as shown in fig. 6.
The foregoing embodiments are merely illustrative of the principles and configurations of the present application, and are not intended to be limiting, it will be appreciated by those skilled in the art that any changes and modifications may be made without departing from the general inventive concept. The protection scope of the present application should be defined as the scope of the claims of the present application.
Claims (10)
1. A method for fabricating a thin film semiconductor chip, comprising:
Epitaxially growing a semiconductor chip epitaxial wafer on a first temporary substrate, the semiconductor chip epitaxial wafer including a sacrificial layer adjoining the temporary substrate;
preparing a composite metal substrate on the opposite side of the semiconductor chip epitaxial wafer from the first temporary substrate, wherein the composite metal substrate comprises a thin film metal layer, a stop layer and a second temporary substrate in sequence from one side of the semiconductor chip epitaxial wafer;
etching the sacrificial layer through a first etching solution, and stripping the semiconductor chip epitaxial wafer from the first temporary substrate;
taking the composite metal substrate as a support, and carrying out subsequent chip processing on the side of the semiconductor chip epitaxial wafer opposite to the composite metal substrate; and
And removing the second temporary substrate and the cut-off layer to obtain the thin film semiconductor chip.
2. The thin film semiconductor chip manufacturing method according to claim 1, wherein preparing the composite metal substrate on the opposite side of the semiconductor chip epitaxial wafer from the first temporary substrate comprises:
And sequentially depositing a thin film metal layer, a stop layer and a temporary metal substrate layer on the semiconductor chip epitaxial wafer by adopting an evaporation process or a liquid phase deposition process.
3. The thin film semiconductor chip manufacturing method according to claim 1, wherein removing the second temporary substrate and the stop layer comprises:
And etching the stop layer by a second etching solution to peel the thin film semiconductor chip from the second temporary substrate.
4. The thin film semiconductor chip manufacturing method according to claim 3, further comprising:
before etching the cut-off layer by the second etching liquid, the semiconductor chip layer is vertically divided up to the upper surface of the cut-off layer or the upper surface of the second temporary substrate.
5. The thin film semiconductor chip manufacturing method according to claim 1, wherein removing the second temporary substrate and the stop layer comprises:
The second temporary substrate is removed by grinding, after which the stop layer is etched by a second etching solution.
6. The method for manufacturing a thin film semiconductor chip as claimed in claim 1, wherein the thin film metal layer has a thickness of 10-100um.
7. The manufacturing method of the thin film semiconductor chip as claimed in claim 1, wherein the cut-off layer is a metal layer and the second temporary substrate is a metal substrate.
8. The method for manufacturing a thin-film semiconductor chip according to claim 1, wherein the thin-film semiconductor chip is a light-emitting diode device, a photovoltaic cell device, or a photodetector.
9.A thin film semiconductor chip manufacturing structure sequentially includes:
A semiconductor chip epitaxial wafer on a first temporary substrate, wherein a sacrificial layer is arranged between the semiconductor chip epitaxial wafer and the temporary substrate, and the sacrificial layer is subsequently used for stripping the semiconductor chip and the first temporary substrate; and
And the composite metal substrate on the semiconductor chip epitaxial wafer sequentially comprises a thin film metal layer, a stop layer and a second temporary substrate from one side of the semiconductor chip epitaxial wafer, wherein the stop layer is used for stripping the semiconductor chip and the second temporary substrate.
10. The thin film semiconductor chip fabrication structure of claim 9, wherein the thin film metal layer has a thickness of 10-100um.
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