CN117912511A - MRAM write operation temperature compensation circuit - Google Patents
MRAM write operation temperature compensation circuit Download PDFInfo
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- CN117912511A CN117912511A CN202211251316.9A CN202211251316A CN117912511A CN 117912511 A CN117912511 A CN 117912511A CN 202211251316 A CN202211251316 A CN 202211251316A CN 117912511 A CN117912511 A CN 117912511A
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Abstract
The invention provides an MRAM writing operation temperature compensation circuit, comprising: the temperature drift reference circuit with the adjustable linear slope generates a first reference voltage which linearly changes along with the temperature, and the slope of the first reference voltage which linearly changes along with the temperature is configurable; a bandgap reference circuit generating a constant second reference voltage; the data selector is provided with two input interfaces which are respectively and electrically connected with the linear slope adjustable temperature drift reference circuit and the band gap reference circuit; the temperature detection circuit is electrically connected with the enabling interface of the data selector, detects the ambient temperature and outputs an enabling signal to the data selector according to the detection result so as to control the data selector to select the first reference voltage and the second reference voltage. The MRAM write operation temperature compensation circuit provided by the invention can provide reference voltages with different temperature characteristics at different temperatures, so that the reference voltages more meet the requirements of corresponding temperatures, and the memory life is prolonged.
Description
Technical Field
The present invention relates to the field of magnetic memories, and in particular, to a MRAM write operation temperature compensation circuit.
Background
Information of the MRAM is stored in the magnetic material device MTJ, and read-write operation is performed on the memory cell through current. Ambient temperature variations can affect the memory cell, and the write voltage can vary with temperature during MTJ writing. In the prior art, the characteristic of the write voltage changing with temperature is usually set at the beginning of design, and the MTJ is written according to the characteristic curve after the preparation is completed. However, the characteristic curve of the set write voltage along with the temperature change usually has deviation from the voltage of actual demand, in a low temperature area, the write voltage value after temperature compensation in the existing design is higher than the actual demand, and the service life of the MTJ is influenced by the excessively high write voltage; in normal temperature and high temperature areas, due to process fluctuation, deviation exists between the slope of the write voltage curve of the MTJ after temperature compensation after the flow sheet and the design value, when the actual write voltage value is higher than the design value, the service life of the MTJ can be affected, and when the actual write voltage value is lower than the design value, the possibility of write failure exists.
Disclosure of Invention
The MRAM write operation temperature compensation circuit provided by the invention can provide reference voltages with different temperature characteristics at different temperatures, so that the reference voltages more meet the requirements of corresponding temperatures, and the memory life is prolonged.
The invention provides an MRAM writing operation temperature compensation circuit, comprising:
A linear slope adjustable temperature drift reference circuit for generating a first reference voltage that varies linearly with temperature, the slope of the first reference voltage that varies linearly with temperature being configurable;
A bandgap reference circuit for generating a constant second reference voltage;
the data selector is provided with two input interfaces which are respectively and electrically connected with the linear slope adjustable temperature drift reference circuit and the band gap reference circuit so as to select the first reference voltage and the second reference voltage;
The temperature detection circuit is electrically connected with the enabling interface of the data selector and is used for detecting the ambient temperature and outputting an enabling signal to the data selector according to the detection result so as to control the data selector to select the first reference voltage and the second reference voltage.
Optionally, the linear slope adjustable temperature drift reference circuit includes:
The first current mirror comprises a first PMOS tube and a second PMOS tube, and the grid electrodes of the first PMOS tube and the second PMOS tube are electrically connected; the first end of the first PMOS tube is connected with a voltage source, and the second end of the first PMOS tube is grounded through a first resistor; the first end of the second PMOS tube is connected with a voltage source, and the second end of the second PMOS tube is grounded through a second resistor;
The second current mirror comprises a third PMOS tube and a fourth PMOS tube, and the grid electrodes of the third PMOS tube and the fourth PMOS tube are electrically connected; the first end of the third PMOS tube is connected with a voltage source, and the second end of the third PMOS tube is electrically connected with the first end of the third resistor; the first end of the fourth PMOS tube is connected with a voltage source, and the second end of the fourth PMOS tube is grounded through a second resistor; the divided voltage of the second resistor is output outwards as a first reference voltage;
The output end of the first operational amplifier is electrically connected with the grid electrodes of the first PMOS tube and the second PMOS tube; the non-inverting input end of the first operational amplifier is electrically connected with the second end of the first MOS tube;
The first end of the first triode is electrically connected with a first current source, the first end of the first triode is also electrically connected with an inverting input end of the first operational amplifier, the second end of the first triode is grounded, and the base electrode of the first triode is grounded;
the first end of the second triode is electrically connected with the second end of the third resistor, the second end of the second triode is grounded, and the base electrode of the second triode is grounded;
The output end of the second operational amplifier is electrically connected with the grid electrodes of the third PMOS tube and the fourth PMOS tube; and the non-inverting input end of the second operational amplifier is electrically connected with a reference voltage source, and the inverting input end of the second operational amplifier is electrically connected with the second end of the third PMOS tube.
Optionally, the first transistor and the second transistor have the same process device type and physical dimensions.
Optionally, the first resistor, the second resistor and the third resistor have the same process device type.
Optionally, the first operational amplifier and the second operational amplifier have the same physical design structure.
Optionally, the ratio of the first current mirror to the second current mirror is determined according to the following formula:
Wherein VREF1 is a first reference voltage, R 1 is a first resistor, V BE is an inverted input terminal voltage of the first operational amplifier, m is a first current mirror ratio, VREF is a design reference voltage, R 2 is a second resistor, R 3 is a third resistor, and n is a second current mirror ratio.
Optionally, the temperature detection circuit includes:
a magnetic tunnel junction having an antiparallel state, a first end of the magnetic tunnel junction being electrically connected to a second current source, a second end of the magnetic tunnel junction being grounded;
And the positive input end of the comparator is electrically connected with the first end of the magnetic tunnel junction, the negative input end of the comparator is electrically connected with the output end of the band gap reference circuit, and the output end of the comparator is electrically connected with the enabling interface of the data selector.
Optionally, the second current source is an adjustable current source.
Optionally, the magnetic tunnel junction is selected according to the following formula:
tmr= (Rap-Rp)/Rp is 100%; wherein TMR is the tunnel magnetoresistance characteristic of the magnetic tunnel junction, rp is the parallel state resistance, and Rap is the antiparallel state resistance.
Optionally, the data selector includes:
The first end of the inverter is electrically connected with the temperature detection circuit and is used for inverting the enabling signal output by the temperature detection circuit;
The input end of the first transmission gate is electrically connected with the output end of the linear slope adjustable temperature drift reference circuit, and the output end of the first transmission gate is electrically connected with the reference voltage interface of the MRAM writing circuit; the first enabling interface of the first transmission gate receives an enabling signal before inversion, and the second enabling interface of the first transmission gate receives an enabling signal after inversion;
The input end of the second transmission gate is electrically connected with the output end of the band gap reference circuit, and the output end of the second transmission gate is used for being electrically connected with the reference voltage interface of the MRAM writing circuit; the first enabling interface of the second transmission gate receives the inverted enabling signal, and the second enabling interface of the first transmission gate receives the enabling signal before the inversion.
According to the technical scheme provided by the invention, the curve formed by the reference voltage and the temperature is divided into two parts according to the temperature drift characteristic of the MRAM, wherein one part is basically constant reference voltage, and the other part is the reference voltage presenting the negative temperature linear curve, so that the constant reference voltage and the reference voltage presenting the negative temperature linear curve are respectively provided by the two circuits in the technical scheme. In order to enable the two reference voltages to work in corresponding temperature ranges respectively, the technical scheme provided by the invention selects the two reference voltages through the data selector and enables the data selector through the temperature detection circuit. The technical scheme provided by the invention can output the reference voltage which is more in line with the writing operation of the MTJ at different temperatures, and is beneficial to prolonging the service life of the MTJ.
Drawings
FIG. 1 is a schematic diagram of an MRAM write operation temperature compensation circuit according to an embodiment of the invention;
FIG. 2 is a graph showing the variation of the write operation voltage of an MRAM according to another embodiment of the invention;
FIG. 3 is a schematic diagram of a temperature drift reference circuit with adjustable linear slope for an MRAM writing operation temperature compensation circuit according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a temperature sensing circuit of an MRAM write operation temperature compensation circuit according to another embodiment of the invention;
FIG. 5 is a graph showing TMR temperature characteristics of a magnetic tunnel junction in a temperature sensing circuit of an MRAM write operation temperature compensation circuit according to another embodiment of the invention;
FIG. 6 is a graph of resistance temperature of a magnetic tunnel junction in a temperature sensing circuit of an MRAM write operation temperature compensation circuit according to another embodiment of the invention;
FIG. 7 is a schematic diagram of a data selector for an MRAM write operation temperature compensation circuit according to another embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides an MRAM (magnetic random Access memory) write operation temperature compensation circuit, which is shown in FIG. 1, wherein an MRAM write operation power supply architecture is shown, a write operation reference voltage circuit is arranged on the left side in the figure, and a write operation power supply LDO (low dropout regulator) circuit is arranged on the right side in the figure. The write operation reference voltage circuit provides a reference voltage VREF required by a write operation power supply LDO, and outputs a required write operation power supply voltage through proportional amplification (RA is an adjustable resistor) of proportional resistors RA and RB in the LDO. The present embodiment provides a write operation reference voltage circuit on the left side, including:
A linear slope adjustable temperature drift reference circuit for generating a first reference voltage that varies linearly with temperature, the slope of the first reference voltage that varies linearly with temperature being configurable; a bandgap reference circuit for generating a constant second reference voltage;
the data selector is provided with two input interfaces which are respectively and electrically connected with the linear slope adjustable temperature drift reference circuit and the band gap reference circuit so as to select the first reference voltage and the second reference voltage;
The temperature detection circuit is electrically connected with the enabling interface of the data selector and is used for detecting the ambient temperature and outputting an enabling signal to the data selector according to the detection result so as to control the data selector to select the first reference voltage and the second reference voltage.
In some embodiments, as shown in FIG. 2, the actual array write voltage demand curve is a quadratic curve, VREF is a negative temperature linear curve when temperature > T1, VREF is approximately a fixed voltage when temperature < T1; thus, as shown in FIG. 1, in the design of the array write operation reference circuit, it is split into two parts, wherein the linear slope adjustable reference circuit outputs a negative temperature characteristic reference VREF1 that varies with temperature; a bandgap reference circuit (conventional circuit structure, not described in detail herein) outputting a reference VREF2 that approximates a zero temperature drift coefficient; the temperature detection circuit is used for detecting a temperature point T1, and further, the reference selection module MUX is used for selecting and outputting a write operation reference voltage meeting actual requirements.
In the technical scheme provided by the embodiment of the invention, the curve formed by the reference voltage and the temperature is divided into two parts according to the temperature drift characteristic of the MRAM, wherein one part is the basically constant reference voltage, and the other part is the reference voltage showing the negative temperature linear curve, so that the constant reference voltage and the reference voltage showing the negative temperature linear curve are respectively provided by the two circuits in the technical scheme of the invention. In order to enable the two reference voltages to work in corresponding temperature ranges respectively, the technical scheme provided by the invention selects the two reference voltages through the data selector and enables the data selector through the temperature detection circuit. The technical scheme provided by the invention can output the reference voltage which is more in line with the writing operation of the MTJ at different temperatures, and is beneficial to prolonging the service life of the MTJ.
As an alternative embodiment, as shown in fig. 3, the linear slope adjustable temperature drift reference circuit includes:
The first current mirror comprises a first PMOS tube and a second PMOS tube, and the grid electrodes of the first PMOS tube and the second PMOS tube are electrically connected; the first end of the first PMOS tube is connected with a voltage source, and the second end of the first PMOS tube is grounded through a first resistor; the first end of the second PMOS tube is connected with a voltage source, and the second end of the second PMOS tube is grounded through a second resistor;
The second current mirror comprises a third PMOS tube and a fourth PMOS tube, and the grid electrodes of the third PMOS tube and the fourth PMOS tube are electrically connected; the first end of the third PMOS tube is connected with a voltage source, and the second end of the third PMOS tube is electrically connected with the first end of the third resistor; the first end of the fourth PMOS tube is connected with a voltage source, and the second end of the fourth PMOS tube is grounded through a second resistor; the divided voltage of the second resistor is output outwards as a first reference voltage;
The output end of the first operational amplifier is electrically connected with the grid electrodes of the first PMOS tube and the second PMOS tube; the non-inverting input end of the first operational amplifier is electrically connected with the second end of the first MOS tube;
The first end of the first triode is electrically connected with a first current source, the first end of the first triode is also electrically connected with an inverting input end of the first operational amplifier, the second end of the first triode is grounded, and the base electrode of the first triode is grounded;
the first end of the second triode is electrically connected with the second end of the third resistor, the second end of the second triode is grounded, and the base electrode of the second triode is grounded;
The output end of the second operational amplifier is electrically connected with the grid electrodes of the third PMOS tube and the fourth PMOS tube; and the non-inverting input end of the second operational amplifier is electrically connected with a reference voltage source, and the inverting input end of the second operational amplifier is electrically connected with the second end of the third PMOS tube.
As a preferred embodiment, the ratio of the first current mirror to the second current mirror is determined according to the following formula:
Wherein VREF1 is a first reference voltage, R 1 is a first resistor, V BE is an inverted input terminal voltage of the first operational amplifier, m is a first current mirror ratio, VREF is a design reference voltage, R 2 is a second resistor, R 3 is a third resistor, and n is a second current mirror ratio.
In some embodiments, the first triode PNP1 and the second PNP2 are consistent (the base-emitter voltage difference VBE thereof is a negative temperature characteristic), the second PMOS transistor P2 and the first PMOS transistor P1 are proportional current mirrors, and the ratio of the number of the transistors is m:1, a fourth PMOS tube P4 and a third PMOS tube P3 are proportional current mirrors, and the tube number proportion is n:1, a step of; after the two ends of the input of the first operational amplifier AMP1 are balanced, the current of the first PMOS tube P1 isThe current of the second PMOS tube P2 is/>After the two input ends of the second operational amplifier AMP2 are balanced, the current of the third PMOS tube P3 is/>The current of the fourth PMOS tube P4 is/>Then, fitting the two currents can obtain the required linear slope temperature drift reference voltage VREF1, and the formula is as follows:
The reference voltage V0 is written corresponding to the temperature T0 point in fig. 2, and the value of the resistor R3 is adjusted; corresponding to the demand curves 3 and 4 of fig. 2, in which the slope deviation is caused by the process fluctuation, only the values of m and n need to be adjusted. VREF is a design reference voltage that varies with temperature and may be, for example, curve 2 in fig. 2.
As a preferred embodiment, the first transistor and the second transistor have the same process device type and physical dimensions. In some embodiments, when the first triode and the second triode have the same process device type and physical size, the current, the resistance, the voltage and other characteristics are consistent, and additional devices are not needed to adjust the current, the voltage, the resistance and other characteristics of the first triode and the second triode, so that the circuit structure is facilitated to be simplified.
As a preferred embodiment, the first resistor, the second resistor and the third resistor have the same process device type.
As a preferred embodiment, the first op-amp and the second op-amp have the same physical design.
As an alternative embodiment, as shown in fig. 4, the temperature detection circuit includes:
a magnetic tunnel junction having an antiparallel state, a first end of the magnetic tunnel junction being electrically connected to a second current source, a second end of the magnetic tunnel junction being grounded;
And the positive input end of the comparator is electrically connected with the first end of the magnetic tunnel junction, the negative input end of the comparator is electrically connected with the output end of the band gap reference circuit, and the output end of the comparator is electrically connected with the enabling interface of the data selector. As a preferred embodiment, the magnetic tunnel junction is selected according to the following formula: tmr= (Rap-Rp)/Rp is 100%; wherein TMR is the tunnel magnetoresistance characteristic of the magnetic tunnel junction, rp is the parallel state resistance, and Rap is the antiparallel state resistance.
In some embodiments, in the MRAM process, the TMR characteristic of the MTJ is temperature dependent, exhibiting a negative temperature characteristic, and the TMR characteristic of the MTJ in this embodiment is plotted against temperature as shown in fig. 5. The specific formula of TMR is as follows: tmr= (Rap-Rp)/Rp is 100%; where Rp is the parallel state resistance and Rap is the anti-parallel state resistance. Since the Rp resistance has a characteristic that does not vary with temperature, the temperature characteristic of the Rap resistance can be deduced from the formula as shown in fig. 6. The temperature detection circuit in this embodiment is designed by using the characteristic that the Rap resistance value changes with temperature, and specifically includes the following steps: the adjustable bias current I2 flows through the Rap resistor to generate voltage Vap which changes along with temperature, the voltage is compared with zero temperature drift reference voltage VREF2 (namely reference voltage V1 corresponding to temperature T1 in FIG. 2) generated by the band gap reference circuit, when Vap is more than or equal to VREF2, the output SEL is 1, and the working temperature point is lower than T1; when Vap < VREF2, the output SEL is "0", indicating that the operating temperature point is higher than T1.
As an alternative embodiment, the second current source is an adjustable current source. In some embodiments, because process fluctuation inevitably exists in the MTJ manufacturing process, in order to solve the problem of deviation between the resistance value of the MTJ resistor Rap and the actual value caused by the process fluctuation, the temperature drift voltage Vap meeting the actual requirement can be fitted by changing the magnitude of the adjustable bias current I2.
As an alternative embodiment, as shown in fig. 7, the data selector includes:
The first end of the inverter is electrically connected with the temperature detection circuit and is used for inverting the enabling signal output by the temperature detection circuit;
The input end of the first transmission gate is electrically connected with the output end of the linear slope adjustable temperature drift reference circuit, and the output end of the first transmission gate is electrically connected with the reference voltage interface of the MRAM writing circuit; the first enabling interface of the first transmission gate receives an enabling signal before inversion, and the second enabling interface of the first transmission gate receives an enabling signal after inversion;
The input end of the second transmission gate is electrically connected with the output end of the band gap reference circuit, and the output end of the second transmission gate is used for being electrically connected with the reference voltage interface of the MRAM writing circuit; the first enabling interface of the second transmission gate receives the inverted enabling signal, and the second enabling interface of the first transmission gate receives the enabling signal before the inversion.
In some embodiments, the reference selection module MUX selects and outputs the reference voltage VREF matching the temperature requirement using the aforementioned SEL signal, as shown in fig. 7, when SEL is "1", the transmission gate G1 is gated, indicating that the operating temperature point is lower than T1, and the write circuit references the reference voltage VREF1; when SEL is "0", the transfer gate G2 is gated, indicating that the operating temperature point is higher than T1, the write circuit references the reference selection VREF2.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. An MRAM write operation temperature compensation circuit, comprising:
A linear slope adjustable temperature drift reference circuit for generating a first reference voltage that varies linearly with temperature, the slope of the first reference voltage that varies linearly with temperature being configurable;
A bandgap reference circuit for generating a constant second reference voltage;
the data selector is provided with two input interfaces which are respectively and electrically connected with the linear slope adjustable temperature drift reference circuit and the band gap reference circuit so as to select the first reference voltage and the second reference voltage;
The temperature detection circuit is electrically connected with the enabling interface of the data selector and is used for detecting the ambient temperature and outputting an enabling signal to the data selector according to the detection result so as to control the data selector to select the first reference voltage and the second reference voltage.
2. The MRAM write operation temperature compensation circuit of claim 1, wherein the linear slope adjustable temperature drift reference circuit comprises:
The first current mirror comprises a first PMOS tube and a second PMOS tube, and the grid electrodes of the first PMOS tube and the second PMOS tube are electrically connected; the first end of the first PMOS tube is connected with a voltage source, and the second end of the first PMOS tube is grounded through a first resistor; the first end of the second PMOS tube is connected with a voltage source, and the second end of the second PMOS tube is grounded through a second resistor;
The second current mirror comprises a third PMOS tube and a fourth PMOS tube, and the grid electrodes of the third PMOS tube and the fourth PMOS tube are electrically connected; the first end of the third PMOS tube is connected with a voltage source, and the second end of the third PMOS tube is electrically connected with the first end of the third resistor; the first end of the fourth PMOS tube is connected with a voltage source, and the second end of the fourth PMOS tube is grounded through a second resistor; the divided voltage of the second resistor is output outwards as a first reference voltage;
The output end of the first operational amplifier is electrically connected with the grid electrodes of the first PMOS tube and the second PMOS tube; the non-inverting input end of the first operational amplifier is electrically connected with the second end of the first MOS tube;
The first end of the first triode is electrically connected with a first current source, the first end of the first triode is also electrically connected with an inverting input end of the first operational amplifier, the second end of the first triode is grounded, and the base electrode of the first triode is grounded;
the first end of the second triode is electrically connected with the second end of the third resistor, the second end of the second triode is grounded, and the base electrode of the second triode is grounded;
The output end of the second operational amplifier is electrically connected with the grid electrodes of the third PMOS tube and the fourth PMOS tube; and the non-inverting input end of the second operational amplifier is electrically connected with a reference voltage source, and the inverting input end of the second operational amplifier is electrically connected with the second end of the third PMOS tube.
3. The MRAM write operation temperature compensation circuit of claim 2, wherein the first transistor and the second transistor are of a same process device type and physical size.
4. The MRAM write operation temperature compensation circuit of claim 2, wherein the first resistor, the second resistor, and the third resistor are of a same process device type.
5. The MRAM write operation temperature compensation circuit of claim 2, wherein the first op-amp and the second op-amp have a same physical design structure.
6. The MRAM write operation temperature compensation circuit of claim 2, wherein a ratio of the first current mirror and the second current mirror is determined according to the following equation:
Wherein VREF1 is a first reference voltage, R 1 is a first resistor, V BE is an inverted input terminal voltage of the first operational amplifier, m is a first current mirror ratio, VREF is a design reference voltage, R 2 is a second resistor, R 3 is a third resistor, and n is a second current mirror ratio.
7. The MRAM write operation temperature compensation circuit of claim 1, wherein the temperature detection circuit comprises:
a magnetic tunnel junction having an antiparallel state, a first end of the magnetic tunnel junction being electrically connected to a second current source, a second end of the magnetic tunnel junction being grounded;
And the positive input end of the comparator is electrically connected with the first end of the magnetic tunnel junction, the negative input end of the comparator is electrically connected with the output end of the band gap reference circuit, and the output end of the comparator is electrically connected with the enabling interface of the data selector.
8. The MRAM write operation temperature compensation circuit of claim 7, wherein the second current source is an adjustable current source.
9. The MRAM write operation temperature compensation circuit of claim 7, wherein the magnetic tunnel junction is selected according to the following equation:
tmr= (Rap-Rp)/Rp is 100%; wherein TMR is the tunnel magnetoresistance characteristic of the magnetic tunnel junction, rp is the parallel state resistance, and Rap is the antiparallel state resistance.
10. The MRAM write operation temperature compensation circuit of claim 1, wherein the data selector comprises:
The first end of the inverter is electrically connected with the temperature detection circuit and is used for inverting the enabling signal output by the temperature detection circuit;
The input end of the first transmission gate is electrically connected with the output end of the linear slope adjustable temperature drift reference circuit, and the output end of the first transmission gate is electrically connected with the reference voltage interface of the MRAM writing circuit; the first enabling interface of the first transmission gate receives an enabling signal before inversion, and the second enabling interface of the first transmission gate receives an enabling signal after inversion;
The input end of the second transmission gate is electrically connected with the output end of the band gap reference circuit, and the output end of the second transmission gate is used for being electrically connected with the reference voltage interface of the MRAM writing circuit; the first enabling interface of the second transmission gate receives the inverted enabling signal, and the second enabling interface of the first transmission gate receives the enabling signal before the inversion.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211251316.9A CN117912511A (en) | 2022-10-12 | 2022-10-12 | MRAM write operation temperature compensation circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211251316.9A CN117912511A (en) | 2022-10-12 | 2022-10-12 | MRAM write operation temperature compensation circuit |
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| CN117912511A true CN117912511A (en) | 2024-04-19 |
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| CN202211251316.9A Pending CN117912511A (en) | 2022-10-12 | 2022-10-12 | MRAM write operation temperature compensation circuit |
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