CN117909127A

CN117909127A - Instruction interaction method, device and readable storage medium of on-chip random access memory

Info

Publication number: CN117909127A
Application number: CN202311843052.0A
Authority: CN
Inventors: 龚乐; 吴大畏; 李晓强
Original assignee: Deyi Microelectronics Co ltd
Current assignee: Deyi Microelectronics Co ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-04-19

Abstract

The application discloses an instruction interaction method, equipment and a readable storage medium of an on-chip random access memory, relating to the field of electronic data processing, wherein the method comprises the following steps: when the on-chip static random access memory receives a data operation instruction sent by the processor, determining whether the data operation instruction is related to a preset character or not; if yes, selecting a check area in the on-chip static random access memory based on the data operation instruction so as to execute error correction function expansion; and executing the data operation instruction to the on-chip static random access memory by the processor based on the checking area and the original data corresponding to the data operation instruction. The technical problem that the error correction technology in the related art needs to occupy extra storage resources to check byte data, so that the read-write speed of the byte data is reduced compared with that of the normal condition by times is solved, and the technical effect of dynamically executing error correction function expansion on a memory without error correction function and improving instruction processing efficiency is realized.

Description

Instruction interaction method, device and readable storage medium of on-chip random access memory

Technical Field

The present application relates to electronic data processing fields, and in particular, to a method, apparatus, and readable storage medium for instruction interaction for on-chip random access memory.

Background

An on-chip SRAM (Static Random Access Memory ) refers to a static random access memory embedded in an integrated circuit chip. In contrast to external SRAM, on-chip SRAM is a memory integrated on the chip itself. Because on-chip SRAM is on-chip, data transfer is faster, power consumption is lower, and accommodates higher operating frequencies, it is commonly used for on-chip data and instruction storage, such as buffers, registers, and cache memory in microprocessors, microcontrollers, and other integrated circuits.

In the related art, as the fabrication technology is advanced, the chip size is reduced, and the operating voltage of the chip is reduced accordingly. Lower operating voltages mean less voltage tolerance and therefore also relatively lower tolerance to voltage disturbances and supply noise. Voltage disturbances and supply noise can cause instability in the charge stored by the SRAM, which in turn can cause bit flipping. To solve this problem, an ECC (Error CHECKING AND correction), technique is introduced.

However, the ECC technique requires additional memory resources to verify the byte data, resulting in a reduced read/write speed of the byte data compared to the normal case.

Disclosure of Invention

The embodiment of the application solves the technical problem that the ECC technology in the related art needs to occupy extra storage resources to check byte data, so that the reading and writing speed of the byte data is reduced compared with that of the normal condition by a multiple level, and realizes the technical effects of dynamically executing the expansion of error correction function on a memory without the ECC function and improving the instruction processing efficiency by providing the instruction interaction method, the equipment and the readable storage medium of the on-chip random access memory.

The embodiment of the application provides an instruction interaction method of an on-chip random access memory, which comprises the following steps of:

When the on-chip static random access memory receives a data operation instruction sent by the processor, determining whether the data operation instruction is related to a preset character or not;

If the data operation instruction contains the preset character, selecting a check area in the on-chip static random access memory based on the data operation instruction so as to execute error correction function expansion;

And executing the data operation instruction to the on-chip static random access memory by the processor based on the checking area and the original data corresponding to the data operation instruction.

Optionally, before the step of determining whether the data operation instruction is associated with a preset character when the on-chip static random access memory receives the data operation instruction sent by the processor, the method includes:

The processor analyzes the received code to be executed and determines whether the code to be executed needs to start an error correction function or not;

when the error correction function needs to be started, acquiring the memory occupation condition of the on-chip static random access memory;

And if the memory occupation condition corresponds to that the load of the on-chip static random access memory is lower than an execution threshold, generating the data operation instruction based on the code to be executed and the preset character.

Optionally, if the data operation instruction includes the preset character, selecting a check area in the on-chip static random access memory based on the data operation instruction, so as to execute error correction function expansion, where the step includes:

if the data operation instruction contains the preset character, determining a storage occupation value of original data based on the data operation instruction;

determining the check area in the on-chip static random access memory based on a preset proportion and the storage occupation value;

and determining the check address corresponding to the check area.

Optionally, the step of executing, by the processor, the data operation instruction to the on-chip static random access memory based on the check area and the original data corresponding to the data operation instruction includes:

When the data operation instruction is a reading instruction, determining an original address corresponding to the original data in the on-chip static random access memory, and storing the original address into a first general register;

storing the check address corresponding to the check area into a second general register;

And executing the data operation instruction based on the first general register and the second general register, and storing an execution result to a destination register.

Optionally, the step of executing the data operation instruction based on the first general purpose register and the second general purpose register and storing an execution result to a destination register includes:

acquiring the original data in the on-chip static random access memory based on the original address in the first general register;

Based on the check address in the second general register, acquiring check data from the on-chip static random access memory;

And decoding operation is carried out on the original data based on the check data, and a decoding result is stored into the destination register.

When the data operation instruction is a writing instruction, determining an original address of the original data writing area in the on-chip static random access memory based on the storage occupation value of the original data;

Storing the original data into a first general register, and storing a check address corresponding to the check area into a second general register;

executing the data operation instruction based on the first general purpose register and the second general purpose register;

And storing the original address into a destination register.

Optionally, the step of executing the data operation instruction based on the first general purpose register and the second general purpose register includes:

encoding the original data in the first general register to determine check data;

Writing the check data into the check area in the on-chip static random access memory based on the check address in the second general register;

And writing the data to be written obtained after the original data are encoded into an original area in the on-chip static random access memory based on the original address.

Optionally, before the step of executing the data operation instruction based on the check area and the original data corresponding to the data operation instruction, the method includes:

And if the data operation instruction comprises the preset character and the on-chip static random access memory has an error correction function, determining a preset check area corresponding to the on-chip static random access memory as the check area.

In addition, the application also provides an instruction interaction device of the on-chip random access memory, which comprises a memory, a processor and an instruction interaction program of the on-chip random access memory, wherein the instruction interaction program of the on-chip random access memory is stored on the memory and can be run on the processor, and the processor realizes the steps of the instruction interaction method of the on-chip random access memory when executing the instruction interaction program of the on-chip random access memory.

In addition, the application also provides a computer readable storage medium, wherein the computer readable storage medium stores an instruction interaction program of the on-chip random access memory, and the instruction interaction program of the on-chip random access memory realizes the steps of the instruction interaction method of the on-chip random access memory when being executed by a processor.

One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

When the on-chip static random access memory is adopted to receive a data operation instruction sent by the processor, determining whether the data operation instruction is related to a preset character or not; if the data operation instruction contains the preset character, selecting a check area in the on-chip static random access memory based on the data operation instruction so as to execute error correction function expansion; and executing the data operation instruction to the on-chip static random access memory by the processor based on the checking area and the original data corresponding to the data operation instruction. Therefore, the technical problem that the ECC technology in the related technology needs to occupy extra storage resources to check byte data, so that the read-write speed of the byte data is reduced compared with that of the normal condition, and the technical effect of dynamically executing error correction function expansion for a memory without an ECC function and improving instruction processing efficiency is achieved.

Drawings

FIG. 1 is a flowchart of a method for instruction interaction of an on-chip RAM according to an embodiment of the present application;

FIG. 2 is a flowchart of steps S210-S230 in a second embodiment of the method for instruction interaction of an on-chip RAM of the present application;

FIG. 3 is a flowchart illustrating steps S310-S330 in a third embodiment of an instruction interaction method for an on-chip RAM according to the present application;

FIG. 4 is a flowchart of steps S510-S540 in a fifth embodiment of the method for instruction interaction of an on-chip RAM of the present application;

Fig. 5 is a schematic diagram of a hardware structure involved in an embodiment of an instruction interaction device of an on-chip random access memory according to the present application.

Detailed Description

In the related art, the ECC check is selected to be performed in a whole word of 32 bits in a part of the system on chip, i.e. two bits require 7-bit ECC codes, i.e. about 22% of the memory overhead is additionally increased. However, this means that the data must be read and written in 32 bits, and when only one byte of data is written, the 32 bits of data need to be read back first, the byte of data needs to be modified, and then the whole 32 bits of data need to be written back again after ECC check, which slows down the read and write speed of the byte of data by several times compared with the original one. Meanwhile, the ECC function occupies extra memory space, and for the on-chip SRAM with small memory space, simply adding ECC to all SRAMs brings great cost burden. The embodiment of the application adopts the main technical scheme that: and selecting a check area on the on-chip static random access memory according to the received data operation instruction, storing the check code, and executing the data operation instruction to the on-chip static random access memory according to the check area and the original data corresponding to the data operation instruction. Therefore, the expansion of the error correction function is dynamically executed for the memory without the ECC function, and the instruction processing efficiency is improved; meanwhile, the ECC expanding function is flexibly and rapidly deployed for the SRAM, and the technical effect of reducing the use cost of the SRAM in the integrated circuit is achieved.

In order to better understand the above technical solution, exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

Example 1

The embodiment of the application discloses an instruction interaction method of an on-chip random access memory, and referring to fig. 1, the instruction interaction method of the on-chip random access memory comprises the following steps:

step S110, when the on-chip static random access memory receives a data operation instruction sent by the processor, whether the data operation instruction is related to a preset character is determined.

In this embodiment, the on-chip static random access memory is an SRAM on the integrated circuit board. The processor is a central processor on an integrated circuit board. On an integrated circuit board, SRAM is typically used as a cache memory for a processor. The processor, when executing instructions, reads the instructions and data from main memory and then caches them in SRAM for quick access. Because SRAM has a faster access speed and low latency, it can provide faster data access speed, reducing the number of accesses to main memory by the processor, and thus improving the performance of the computer system. The relationship between SRAM and processor is also embodied in the communication protocol and bus connection between them. A standard bus protocol is typically used between the processor and SRAM to enable reading and writing of data. The wiring and connection design on the integrated circuit board ensures high-speed, reliable data transfer between the SRAM and the processor. The on-chip static random access memory is equivalent to SRAM or random access memory in this embodiment, i.e., can be abbreviated as SRAM or random access memory. The preset character is a character for indicating whether the instruction needs to start the error correction function, and when the data operation instruction is associated with the instruction, the preset character indicates that the error correction function needs to be started, otherwise, the error correction function does not need to be started. The error correction function in this embodiment is referred to as an ECC function.

In this embodiment, the data operation instruction is a read instruction and a write instruction that the processor sends to the random access memory. And the on-chip static random access memory responds correspondingly according to the received data operation instruction. The execution body of the embodiment is an instruction interaction system consisting of a processor and an on-chip random access memory.

As an alternative implementation manner, when the on-chip static random access memory receives a data operation instruction sent by the processor, whether the data operation instruction is associated with a preset character or not is determined, for example, whether the preset character is in an instruction head of the data operation instruction or not is detected.

As an example of this embodiment, the processor analyzes whether the code contains a relevant character for starting the error correction function according to the code to be executed sent by the upper software; if the error correction code is included, generating a data operation instruction containing a preset character for starting an error correction function based on data operation content corresponding to the code to be executed, and sending the data operation instruction to the on-chip static random access memory. That is, when the software program is developed, the software program can be developed in a targeted manner, and the adaptation is performed based on the need of starting and relation error correction functions, so as to ensure that the code to be executed received by the processor contains or does not contain relevant characters for starting the error correction functions.

Step S120, if the data operation instruction includes the preset character, selecting a check area in the on-chip sram based on the data operation instruction, so as to execute error correction function expansion.

In the present embodiment, the verification area is a storage area for storing verification data. When the on-chip random access memory has an ECC function, a preset check area is used as a check area corresponding to the execution of the data operation instruction.

As an optional implementation manner, if the data operation instruction includes the preset character and the on-chip static random access memory has an error correction function, a preset check area corresponding to the on-chip static random access memory is determined to be the check area.

As another optional implementation manner, if the data operation instruction includes the preset character and the on-chip static random access memory does not have an error correction function, determining the size and the area of the check area according to the storage occupation value of the original data corresponding to the data operation instruction. The size of the check area refers to the size of the storage space occupied by the check area.

Optionally, if the data operation instruction does not include the preset character, executing the data operation instruction based on a normal mode, wherein the normal mode does not start an error correction function. That is, when the data operation instruction does not include the preset character, the data reading or the data writing corresponding to the data operation instruction is performed using the conventional mode without the ECC function.

Step S130, based on the check area and the original data corresponding to the data operation instruction, the processor executes the data operation instruction to the on-chip static random access memory.

In this embodiment, after determining the check area, the on-chip random access memory executes the data operation instruction based on the physical address of the check area as the check address and the original data corresponding to the data operation instruction, where the original data is data that needs to be read or written.

As an alternative implementation manner, when the data operation instruction is a read instruction, the original data is stored in the on-chip random access memory, and the check data is also stored in the on-chip random access memory, so that the area where the check data is stored is used as a check area, and the processor decodes the target data based on the check data of the check area in the on-chip random access memory and the original data.

As another alternative implementation manner, when the data operation instruction is a write instruction, the original data is data that needs to be written into the on-chip random access memory, so that the processor determines the size of the check area according to the storage occupation value of the original data, and sends the corresponding data operation instruction to the on-chip random access memory, that is, the on-chip random access memory determines the corresponding check area according to the size of the check area included in the data operation instruction, and sends the check address of the check area to the processor. And the processor performs coding operation on the original data according to the determined check address and the original address of the original data, and stores the coded original data and the check data into the on-chip random access memory.

An instruction parsing module is implemented in the on-chip sram, and is configured to receive the data operation instruction sent by the processor, and determine whether the data operation instruction includes a preset character. If the preset character is included, the instruction analysis module selects a check area according to the instruction and executes error correction function expansion. Specifically, the instruction parsing module may determine a check area according to the check area address and size information contained in the instruction, and store ECC check bits in the check area. In addition, the instruction parsing module may also select a corresponding algorithm according to the encoding information contained in the instruction. When the processor executes the data operation instruction, corresponding operation is executed according to the check area and the original data. Specifically, when the processor executes the read instruction, the processor sends the read instruction to the instruction parsing module, and the instruction includes the ECC check bit address, the original data address, and the destination register address. The instruction analysis module selects a check area according to the instruction, acquires ECC check bits and original data from the check area, and performs algorithm decoding on the ECC check bits and the original data. And finally, the instruction analysis module stores the decoded data into a destination register for the processor to use. When the processor executes the writing instruction, the processor sends the writing instruction to the instruction analysis module, and the instruction comprises an ECC check bit address, original data and a destination address. The instruction analysis module selects a check area according to the instruction, performs ECC encoding on the original data, and stores ECC check bits into the check area. Finally, the instruction analysis module stores the encoded data into the area corresponding to the on-chip random access memory for later reading instructions.

In this way, ECC protection can be quickly deployed for critical data in the SRAM when needed, rather than adding ECC to all data, thereby reducing cost increases. At the same time, this approach also provides a flexible way to rapidly deploy ECC protection for SRAMs.

For example, two general registers respectively designated to store the check address and the original data address are required to be defined for a read instruction with ECC, and a destination register for storing the data to be read is required to be defined, when the instruction is executed, the processor respectively obtains 1 byte check data from the check address and 4 bytes of original data from the original data address, then carries out decoding operation of an ECC algorithm, if an ECC error with 2 bits is detected, an abnormal state is entered, otherwise, the data to be read obtained after decoding is directly stored in the destination register. The processor needs to define two general registers respectively designated to store the check address and the original data and one register for storing the destination address of the original data for the writing instruction with ECC, and when the instruction is executed, the processor stores the check address and the coded data to be written into the addresses designated by the two registers. The data to be read is data obtained by decoding the original data. The data to be written is the data stored in the random access memory after the original data is coded.

The technical scheme provided by the embodiment of the application at least has the following technical effects or advantages:

Based on the first embodiment, a second embodiment of the present application provides an instruction interaction method of an on-chip random access memory, referring to fig. 2, before step S110, including:

In step S210, the processor parses the received code to be executed, and determines whether the code to be executed needs to start an error correction function.

In this embodiment, the code to be executed is code that needs to be executed by the processor, and is code that is initiated to the processor when receiving an operation of a user and needs to be executed by the processor, where the software is run in the device where the processor is located.

As an alternative implementation, during the development of the software, the code to be executed initiated to the processor is normalized, and needs to include information whether to turn on the error correction function.

As an alternative embodiment, the processor parses whether the code to be executed contains a specific flag or indicator, and the processor may check whether the code to be executed contains a specific flag or indicator to indicate whether an error correction function is required. For example, a flag bit may be included in the instruction and when set, the processor will enable the error correction function. The processor may determine whether the error correction function needs to be enabled based on the type or content of the code to be executed. For example, for read and write operations on critical data, the processor may automatically enable error correction functions to ensure data integrity and reliability.

Step S220, when the error correction function needs to be started, obtaining the memory occupation condition of the on-chip static random access memory.

In this embodiment, the memory occupation condition refers to a ratio of a used value of a memory space of the on-chip static random access memory to a total value of the memory space.

In this embodiment, the memory occupation condition of the on-chip sram is determined, and one reason is to prevent the on-chip sram from having extra space for performing an error correction function under an extreme load condition, which results in using an error correction mode to further generate adverse effects such as data loss. Thus, as an alternative embodiment, when the processor determines that the error correction function is to be turned on, it is determined whether the error correction function needs to be turned on based on the actual memory usage of the on-chip sram. If the load is too large, corresponding prompt information is returned to the source equipment of the code to be executed so as to prompt that the current load is too large.

As an optional implementation manner, when the error correction function needs to be started, the memory occupation condition of the on-chip static random access memory is obtained, the memory usage condition of the on-chip static random access memory is queried, and the processor queries the memory usage condition of the on-chip static random access memory to determine the current memory load condition. This may include checking the proportion of current memory usage, available space, and whether the load is below an execution threshold. The memory usage is monitored, the error correction function is dynamically adjusted, and the processor dynamically monitors the memory usage and dynamically adjusts the error correction function as required. For example, when the memory load is low, the processor may enable more error correction functions to improve the reliability and integrity of the data. Conversely, when the memory load is higher, the processor may reduce the level of error correction functionality to reduce overhead and latency.

Step S230, if the memory occupancy corresponds to the load of the on-chip sram being lower than the execution threshold, generating the data operation instruction based on the code to be executed and the preset character.

In this embodiment, the execution threshold is a preset threshold of the load condition, that is, when the load is higher than the execution threshold, it indicates that there is no redundant space in the on-chip sram to execute the ECC function, or the execution of the ECC function by the remaining space may affect the normal operation of the on-chip sram, for example, reduce the access speed.

As an alternative implementation manner, when the memory load is lower than the execution threshold, a data operation instruction is generated based on the code to be executed and the preset character, a standard data operation instruction is generated, error correction information is added, and the processor can generate the standard data operation instruction, and add the error correction information to the instruction, so that a subsequent instruction analysis module can correctly execute error correction function expansion. For example, the processor may encode error correction information as additional bits or bytes and add it to the data manipulation instruction. And generating a customized data operation instruction, wherein the processor can generate the customized data operation instruction according to the code to be executed and the preset character so as to correctly execute the error correction function expansion in the subsequent instruction analysis process. For example, the processor may generate a set of specific instructions based on the code to be executed and the preset characters to enable the error correction function when performing the read and write operations and include necessary error correction information in the instructions. I.e. the data manipulation instruction generated by the processor contains or is associated with a preset character.

As another optional implementation manner, if the memory occupation situation corresponds to the load not being lower than the execution threshold, the data operation instruction is generated based on the code to be executed, where the data operation instruction is not associated with the preset character.

Illustratively, determining whether the code to be executed requires the error correction function to be enabled, the processor parses the code to be executed and checks whether a particular flag or indicator is included in the instruction to indicate whether the error correction function needs to be enabled. The memory occupation condition of the on-chip static random access memory is obtained, and the processor inquires the memory use condition of the on-chip static random access memory and calculates the current memory load condition. Generating a data operation instruction based on the code to be executed and the preset character, and if the code to be executed needs to enable the error correction function and the memory load is lower than the execution threshold value, generating the data operation instruction by the processor according to the code to be executed and the preset character. For example, for a read operation, the processor will generate a standard read instruction and append ECC check information to the instruction. For a write operation, the processor will generate a custom write instruction and include the necessary ECC check information in the instruction.

Due to the fact that the processor is adopted, whether a preset grandfather is added in a data operation instruction or not is determined according to the received code to be executed and the memory occupation condition of the on-chip random access memory, and then the on-chip random access memory is controlled to execute according to the data operation to determine whether to start an error correction function or not. The technical effect of dynamically executing error correction function expansion aiming at the memory without ECC function and improving instruction processing efficiency is achieved.

Based on the first embodiment, a third embodiment of the present application provides an instruction interaction method of an on-chip random access memory, referring to fig. 3, step S120 includes:

in step S310, if the data operation instruction includes the preset character, the storage occupancy value of the original data is determined based on the data operation instruction.

In this embodiment, if the data operation instruction includes the preset character, it indicates that the error correction function needs to be started, and then a storage occupancy value of the original data is determined according to the data operation instruction, where the storage occupancy value refers to the occupied storage space. When the data operation instruction is a read instruction, the original data is already stored in the on-chip random register, and a memory footprint value is determined from the determined original data. When the data operation instruction is a writing instruction, the original data is the instruction to be written, and is stored in the general register, and the data operation instruction sent to the on-chip random access memory by the processor contains the memory occupation value of the original data. The memory occupation value of the original data is determined by the random access memory in the chip according to the data operation instruction.

And step S320, determining the check area in the on-chip static random access memory based on the preset proportion and the memory occupation value.

In this embodiment, the predetermined ratio is the size ratio of the original data to the check data, because the check data and the original data are not stored one to one. The storage occupation value of the check data is determined according to the product of the preset proportion and the storage occupation value, and then the occupation space and the physical address of the check area are determined.

Step S330, determining the check address corresponding to the check area.

In this embodiment, the physical address of the check area is transmitted to the processor as a check address.

As an alternative implementation manner, the storage occupation value of the original data is determined, and when the data operation instruction contains the preset character, the processor first determines the storage occupation value of the original data according to the data operation instruction. This may include determining a storage address, a storage length, or other relevant information of the data for subsequent determination of the verification area. The check area is determined in the on-chip static random access memory based on the preset proportion and the memory occupancy value, and the next step is to determine the check area in the on-chip static random access memory based on the preset proportion and the memory occupancy value. The predetermined ratio may be a fixed ratio value for determining a ratio of the storage space occupied by the check area to the original data storage space. According to the memory occupation value and the preset proportion, the processor can calculate the memory address range where the check area is located. And determining the check address corresponding to the check area, and finally, according to the determined check area, determining the check address corresponding to the check area by the processor. This check address will be used to store error correction codes or check data for error correction and check operations on the original data when needed.

Illustratively, the ratio of the check data to the original data is determined to be one to four.

The verification area is determined based on the storage occupation value of the original data, the storage occupation value of the original data can be determined through the data operation instruction, and then the physical address and the occupation space of the verification area can be directly determined through the data operation instruction, so that the dynamic expansion of the on-chip random access memory is realized.

Based on the first embodiment, the fourth embodiment of the present application provides an instruction interaction method of an on-chip random access memory, and step S130 includes:

In step S410, when the data operation instruction is a read instruction, an original address corresponding to the original data is determined in the on-chip static random access memory, and the original address is stored in a first general register.

In this embodiment, when the data operation instruction is a read instruction, an original address corresponding to the original data is determined in the on-chip sram, and the original address is stored in the first general register. This memory address will be used for subsequent reading of the original data and verification data.

Step S420, storing the check address corresponding to the check area in a second general purpose register.

In this embodiment, the processor stores the check address corresponding to the check area in the second general purpose register, and the processor stores the check address corresponding to the check area in the second general purpose register according to the previously determined check area. This check address will be used for subsequent reading or writing of check data.

Step S430, executing the data operation instruction based on the first general purpose register and the second general purpose register, and storing the execution result to the destination register.

In this embodiment, the processor executes the data operation instruction based on the first general-purpose register and the second general-purpose register, and stores the execution result to the destination register, and executes the data operation instruction using the original address in the first general-purpose register and the check address in the second general-purpose register. For a read instruction, the processor will read data from both the original address and the check address and store the execution result to the destination register after performing the error correction operation. For write instructions, the processor will write data to the original address and the check address according to the instructions and perform the corresponding error correction code calculation and storage operations.

The processor performs these steps according to the specific architecture and instruction set design, ensuring that the read, write and error correction operations on the original data and the verification data are performed correctly. In addition, the processor performs other operations as needed, such as calculation of error correction codes, checksum repair, and the like.

Optionally, step S430 includes:

Step S431, based on the original address in the first general purpose register, acquires the original data in the on-chip sram.

In this embodiment, the processor acquires the original data in the on-chip sram based on the original address in the first general register, where the original data is encoded data, and the original address is a physical address where the original data is stored. I.e. the original data is decoded to obtain the data to be read.

Step S432, based on the check address in the second general purpose register, acquires check data from the on-chip sram.

In this embodiment, the processor obtains the check data at the corresponding location of the on-chip ram based on the check address in the second general purpose register.

And step S433, decoding operation is carried out on the original data based on the check data, and a decoding result is stored into the destination register.

In this embodiment, after decoding results, that is, the original data and the check data, are decoded successfully, the obtained data to be read is stored in the destination register.

As an alternative embodiment, the processor obtains the original data in the on-chip sram based on the original address in the first general purpose register, and the processor obtains the original data in the on-chip sram using the original address stored in the first general purpose register. This may be accomplished by a memory read operation, loading the raw data into an internal register or cache of the processor for subsequent operations. Based on the check address in the second general register, the check data is obtained in the on-chip static random access memory, and the processor uses the check address stored in the second general register to obtain the check data in the on-chip static random access memory. Similarly, this may also be accomplished by a memory read operation, loading the verification data into an internal register or cache of the processor. And decoding operation is carried out on the original data based on the check data, a decoding result is stored in a destination register, and the processor carries out decoding operation by using the obtained original data and the check data so as to execute decoding operation of the error correction code. The decoded result will be stored to the destination register for subsequent processing or transmission.

In performing these steps, the processor needs to ensure that the read and decode operations on the original data and the check data can be performed correctly and that the decoded results can be stored correctly in the destination registers. These operations ensure that the processor is able to accurately perform the relevant operations when the data is error corrected and verified as needed.

Based on the first embodiment, the fifth embodiment of the present application provides an instruction interaction method of an on-chip random access memory, referring to fig. 4, step S130 includes:

Step S510, when the data operation instruction is a write instruction, determining an original address of the original data writing area in the on-chip sram based on the memory occupation value of the original data.

In this embodiment, when the data operation instruction is a write instruction, that is, the processor needs to encode the original data in the general register into the data to be written, and write the data into the location corresponding to the on-chip random access memory. The original address is the physical address to which the data to be written needs to be written.

As an alternative embodiment, when the data operation instruction is a write instruction, the original address of the original data writing area is determined in the on-chip static random access memory based on the memory occupation value of the original data: and the processor calculates the original address of the original data writing area according to the storage occupation value of the original data carried in the instruction. This memory footprint value may be a byte offset, page number, etc., as determined by the particular memory architecture.

Step S520, storing the original data in a first general purpose register, and storing the check address corresponding to the check area in a second general purpose register.

In this embodiment, the original data is stored in the first general-purpose register, and the check address corresponding to the check area is stored in the second general-purpose register processor to store the original data in the first general-purpose register, so that the subsequent data operation instruction can be used. The processor determines a check address corresponding to the check area and stores the address to the second general purpose register for subsequent check operations.

Step S530, executing the data operation instruction based on the first general purpose register and the second general purpose register.

In this embodiment, the data operation instruction executing processor executes the corresponding data operation instruction based on the first general register and the second general register according to the operation type carried in the instruction, and the original data in the first general register and the check address in the second general register.

Step S540, storing the original address in a destination register.

In this embodiment, the original address is stored to the destination register, and if the data manipulation instruction is executed successfully, the processor stores the original address to the destination register for subsequent processing or transmission use.

Illustratively, assume that the processor needs to execute a write instruction to write the original data to the on-chip sram and update the parity data of the parity area at the same time. First, the original address of the original data writing area is calculated according to the storage occupation value of the original data, the storage occupation value is assumed to be byte offset, and the original address of the original data writing area is calculated according to the offset in the instruction. Storing the original data into a first general register, storing a check address corresponding to the check area into a second general register, and loading the original data to be written into the first general register. And determining a check address of the check area and storing the address into a second general purpose register. Executing the data operation instruction, executing the writing instruction by the processor, writing the original data in the first general register into the calculated original address, and simultaneously updating the check data of the check area. The original address is stored to the destination register and if the write operation is successful, the original address is stored to the destination register for subsequent processing or transmission use.

Optionally, step S530 includes:

step S531, encoding the original data in the first general register, and determining check data.

In this embodiment, the original data is encoded based on a preset ECC encoding algorithm, so as to obtain the check data and the encoded data to be written.

As an alternative implementation manner, the original data in the first general purpose register is encoded to determine the check data, and the processor encodes the original data in the first general purpose register to generate the corresponding check data. The encoding process employs various checking algorithms, such as cyclic redundancy check, hash algorithm, etc.

Step S532, writing the check data into the check area in the on-chip sram based on the check address in the second general purpose register.

In this embodiment, based on the check address in the second general register, the check data is written into the check area in the on-chip sram, and the processor writes the encoded check data into the check area in the on-chip sram according to the check address in the second general register, by means of memory mapping or direct access to the memory.

And step S533, writing the data to be written obtained after the original data is encoded into an original area in the on-chip static random access memory based on the original address.

In this embodiment, the encoded data to be written of the original data is written into the original area in the on-chip sram based on the original address, and the processor writes the encoded original data into the original area corresponding to the original address calculated in the on-chip sram.

Illustratively, the processor needs to execute a write instruction to write the original data to the on-chip sram and update the parity data of the parity area at the same time. And encoding the original data in the first general register, determining check data, and performing CRC encoding on the original data in the first general register by the processor to generate corresponding check data. Based on the check address in the second general register, writing the check data into the check area in the on-chip static random access memory, and writing the check data after CRC coding into the check area in the on-chip static random access memory according to the check address in the second general register by the processor. And writing the original data into an original area in the on-chip static random access memory based on the original address, and writing the original data subjected to CRC coding into the original area corresponding to the calculated original address in the on-chip static random access memory by the processor.

Because the data-based operation instruction is adopted, the processor executes different operations according to different instruction types, and the error correction function of the on-chip static random access memory is expanded by combining the error correction function expansion executed by the processor in the embodiment, so that the error correction function of the static random access memory is dynamically expanded according to the requirement of actual running conditions, and the use cost is reduced.

The application further provides an instruction interaction device of the on-chip random access memory, and referring to fig. 5, fig. 5 is a schematic diagram of the instruction interaction device of the on-chip random access memory of the hardware running environment according to the embodiment of the application.

As shown in fig. 5, the instruction interaction device of the on-chip random access memory may include: a processor 1001, such as a central processing unit (Central Processing Unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, a memory 1005. Wherein the communication bus 1002 is used to enable connected communication between these components. The user interface 1003 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may further include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., a wireless FIdelity (WI-FI) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM) memory or a stable non-volatile memory (NVM), such as a disk memory. The memory 1005 may also optionally be a storage device separate from the processor 1001 described above.

It will be appreciated by those skilled in the art that the architecture shown in fig. 5 does not constitute a limitation of the instruction interaction device of the on-chip random access memory, and may include more or fewer components than illustrated, or may combine certain components, or may be a different arrangement of components.

Optionally, the memory 1005 is electrically connected to the processor 1001, and the processor 1001 may be configured to control operation of the memory 1005, and may also read data in the memory 1005 to implement instruction interaction of the on-chip random access memory.

Alternatively, as shown in fig. 5, an instruction interaction program of an operating system, a data storage module, a network communication module, a user interface module, and an on-chip random access memory may be included in the memory 1005 as one storage medium.

Optionally, in the instruction interaction device of the on-chip random access memory shown in fig. 5, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the on-chip ram instruction interaction device of the present application may be disposed in the on-chip ram instruction interaction device.

As shown in fig. 5, the instruction interaction device of the on-chip random access memory invokes, through the processor 1001, an instruction interaction program of the on-chip random access memory stored in the memory 1005, and executes related step operations of the instruction interaction method of the on-chip random access memory provided by the embodiment of the present application:

Optionally, the processor 1001 may call an instruction interactive program of an on-chip random access memory stored in the memory 1005, and further perform the following operations: the processor analyzes the received code to be executed and determines whether the code to be executed needs to start an error correction function or not;

Optionally, the processor 1001 may call an instruction interactive program of an on-chip random access memory stored in the memory 1005, and further perform the following operations:

and determining the check address corresponding to the check area.

And storing the original address into a destination register.

In addition, the embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium is stored with an instruction interaction program of the on-chip random access memory, and the instruction interaction program of the on-chip random access memory realizes the relevant steps of any embodiment of the instruction interaction method of the on-chip random access memory when being executed by a processor.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flowchart and/or block of the flowchart illustrations and/or block diagrams, and combinations of flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. The method for interacting the instructions of the on-chip random access memory is characterized by comprising the following steps of:

2. The method for interaction of instructions in an on-chip ram according to claim 1, wherein before the step of determining whether the data operation instruction is associated with a preset character when the on-chip ram receives the data operation instruction sent by the processor, the method comprises:

3. The method for instruction interaction of on-chip ram according to claim 1, wherein if the data operation instruction includes the predetermined character, selecting a check area in the on-chip sram based on the data operation instruction to perform error correction function expansion comprises:

and determining the check address corresponding to the check area.

4. The method for instruction interaction of on-chip ram according to claim 1, wherein the step of executing the data operation instruction to the on-chip sram by the processor based on the check area and the raw data corresponding to the data operation instruction comprises:

5. The method of instruction interaction for an on-chip random access memory according to claim 4, wherein the step of executing the data operation instruction based on the first general purpose register and the second general purpose register and storing an execution result to a destination register comprises:

6. The method for instruction interaction of on-chip ram according to claim 1, wherein the step of executing the data operation instruction to the on-chip sram by the processor based on the check area and the raw data corresponding to the data operation instruction comprises:

And storing the original address into a destination register.

7. The method of instruction interaction for an on-chip random access memory according to claim 6, wherein the step of executing the data operation instruction based on the first general purpose register and the second general purpose register comprises:

8. The method for interaction of instructions in an on-chip random access memory according to claim 1, wherein before the step of executing the data operation instruction based on the check area and the original data corresponding to the data operation instruction, the method comprises:

9. An on-chip random access memory instruction interaction device, comprising a memory, a processor and an on-chip random access memory instruction interaction program stored on the memory and executable on the processor, wherein the processor implements the steps of the on-chip random access memory instruction interaction method according to any one of claims 1 to 8 when executing the on-chip random access memory instruction interaction program.

10. A computer readable storage medium, characterized in that it has stored thereon an instruction interaction program of an on-chip random access memory, which when executed by a processor, implements the steps of the instruction interaction method of an on-chip random access memory according to any of claims 1 to 8.