CN117907789A

CN117907789A - Reliability test method for semiconductor wafer

Info

Publication number: CN117907789A
Application number: CN202410309653.1A
Authority: CN
Inventors: 孙伟; 谭秋阳; 毛赛君
Original assignee: Chenxin Technology Shanghai Co ltd
Current assignee: Chenxin Technology Shanghai Co ltd
Priority date: 2024-03-19
Filing date: 2024-03-19
Publication date: 2024-04-19
Anticipated expiration: 2044-03-19
Also published as: CN117907789B

Abstract

The invention discloses a reliability test method of a semiconductor wafer, which comprises a start test module, a power module and a control module; the switching end of the first single-pole double-throw switch is controlled to be connected with the second end of the first single-pole double-throw switch; the switching end of the second single-pole double-throw switch is controlled to be connected with the third end of the second single-pole double-throw switch; controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch, and the source electrode of the bare chip to be tested to be connected with the reference voltage end; controlling the first source measuring unit to be in a wave sealing state, controlling the second source measuring unit to output first preset fixed voltage and current information, and obtaining first measurement data of the bare chip to be measured; acquiring a preset voltage threshold range; and judging the isolation state of the body diode in the bare chip to be tested according to the first measurement data and the preset voltage threshold range, so as to realize the reliability detection of the bare chip to be tested and improve the production yield.

Description

Reliability test method for semiconductor wafer

Technical Field

The invention relates to the technical field of semiconductor device monitoring, in particular to a reliability test method of a semiconductor wafer.

Background

With the rapid development of applications such as new energy automobiles and charging piles, and the improvement of requirements for high frequency, high power and the like in the power supply field, third-generation wide bandgap power semiconductor devices based on silicon carbide (SiC) and gallium nitride (GaN) materials are widely applied to the fields such as automobiles, industry, consumer electronics and the like. However, the maturity of the production and manufacturing process is still to be improved, the lower production yield of the device leads to higher cost, and the popularization and the application of the broadband semiconductor device are severely restricted. Therefore, it is necessary to perform screening test on chips from the wafer level, thereby improving the production yield and reducing the manufacturing cost.

The traditional high-temperature gate bias (HTGB) reliability test cannot truly simulate the high-temperature and high-frequency application working condition of a chip, and cannot effectively and accurately represent the dynamic reliability of a device. The dynamic high-temperature grid bias test (DYNAMIC HIGH-temperature gate bias, DHTGB) can better reflect the real operation condition of the broadband semiconductor, but the corresponding test equipment solutions on the market are less, and how to perform the dynamic high-temperature grid bias test on the wafer level is a problem to be solved urgently at present.

Disclosure of Invention

The invention provides a reliability test method of a semiconductor wafer, which is used for realizing the reliability test of the wafer level, ensuring the detection precision, improving the production yield and reducing the production cost.

According to one aspect of the present invention, there is provided a reliability test method of a semiconductor wafer, which is applied to a reliability test system of the semiconductor wafer;

the reliability test system of the semiconductor wafer comprises: the system comprises a source measurement module, a plurality of test modules, a power supply module and a control module;

The semiconductor wafer comprises a plurality of bare chips to be tested;

The source measurement module comprises a source measurement unit and a single-pole double-throw switch, the source measurement unit at least comprises a first source measurement unit and a second source measurement unit, the single-pole double-throw switch at least comprises a first single-pole double-throw switch and a second single-pole double-throw switch, and the test module at least comprises a driving unit and a switch array;

The power supply module is respectively connected with the driving unit, the control module and the switch array; the driving unit is connected with the control module; the first end of the first source measurement unit and the first end of the second source measurement unit are both connected to a reference voltage end;

the second end of the first source measuring unit is connected with the first end of the first single-pole double-throw switch, and the second end of the second source measuring unit is connected with the first end of the second single-pole double-throw switch;

The second end of the first single-pole double-throw switch is connected with the second end of the second single-pole double-throw switch; the third end of the first single-pole double-throw switch is connected with the third end of the second single-pole double-throw switch and is connected with the drain electrode of the bare chip to be tested; the grid electrode of the bare chip to be tested is connected with the second end of the driving unit or the first single-pole double-throw switch; the source electrode of the bare chip to be tested is connected with the reference voltage end or the grounding end; the switch array is respectively connected with a source electrode, a drain electrode and a grid electrode of the bare chip to be tested; the reliability test method of the semiconductor wafer comprises the following steps:

Starting a testing module, a power module and a control module;

the switching end of the first single-pole double-throw switch is controlled to be connected with the second end of the first single-pole double-throw switch;

the switching end of the second single-pole double-throw switch is controlled to be connected with the third end of the second single-pole double-throw switch;

controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch and the source electrode of the bare chip to be tested to be connected with the reference voltage end;

Controlling the first source measuring unit to be in a wave sealing state, controlling the second source measuring unit to output first preset fixed voltage and current information, and acquiring first measurement data of the bare chip to be measured;

acquiring a preset voltage threshold range;

judging whether the first measurement data is positioned in the preset voltage threshold range or not;

if yes, the body diode in the bare chip to be tested is considered to be in a cut-off state, and the test is continued;

If not, the communication state of the bare chip to be tested is considered to be abnormal.

Optionally, continuing the test includes:

Controlling the first source measuring unit to output second preset fixed voltage and current information and controlling the second source measuring unit to output third preset fixed voltage and current information, and obtaining second measurement data of the bare chip to be measured;

and determining the communication state of the bare chip to be tested according to the second measurement data.

Optionally, the second measurement data includes a gate-source voltage value, a source-drain voltage value, and a source-drain current value;

determining the communication state of the bare chip to be tested according to the second measurement data, including:

acquiring a preset gate-source voltage range, a preset source-drain voltage range and a preset source-drain current value;

Judging whether the gate-source voltage value is within the preset gate-source voltage range, whether the source-drain voltage value is within the preset source-drain voltage range and whether the source-drain current value is within the preset source-drain current range;

If yes, the communication state of the bare chip to be tested is considered to be normal;

Optionally, after the communication state of the bare chip to be tested is considered to be normal, the method further includes:

The control driving module is connected with the grid electrode of the bare chip to be tested and outputs PWM waves with preset duty ratio to the grid electrode of the bare chip to be tested;

And controlling the source electrode and the drain electrode of the bare chip to be tested to be connected, and controlling the source electrode to be switched to be connected with the grounding end and continuously communicated for a preset time.

Optionally, controlling the connection between the source and the drain of the die to be tested, and controlling the source to be switched to the ground, and after the duration of the preset time, further includes: controlling the second end of the first single-pole double-throw switch to be connected with the grid electrode of the bare chip to be tested;

controlling the source electrode of the bare chip to be tested to be connected with the reference voltage end;

controlling the starting states of the first source measuring unit and the second source measuring unit;

and acquiring the aging state of the bare chip to be tested according to the starting state and the PWM wave with the preset duty ratio.

Optionally, controlling the start-up states of the first source-measurement unit and the second source-measurement unit includes:

acquiring the aging state of the bare chip to be tested according to the starting state and the PWM wave with the preset duty ratio, wherein the method comprises the following steps:

Correspondingly acquiring the threshold voltage of the bare chip to be tested according to PWM waves with preset duty ratios at different moments;

and acquiring the aging state of the bare chip to be tested according to the threshold voltage.

Controlling the second source-measurement unit not to be started;

correspondingly acquiring the grid leakage current of the bare chip to be tested according to PWM waves with preset duty ratios at different moments;

and acquiring the aging state of the bare chip to be tested according to the gate leakage current.

The technical scheme of the embodiment of the invention provides a reliability test method of a semiconductor wafer, which comprises a start test module, a power module and a control module; the switching end of the first single-pole double-throw switch is controlled to be connected with the second end of the first single-pole double-throw switch; the switching end of the second single-pole double-throw switch is controlled to be connected with the third end of the second single-pole double-throw switch; controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch, and the source electrode of the bare chip to be tested to be connected with the reference voltage end; controlling the first source measuring unit to be in a wave sealing state, controlling the second source measuring unit to output first preset fixed voltage and current information, and obtaining first measurement data of the bare chip to be measured; acquiring a preset voltage threshold range; judging whether the first measurement data is in a preset voltage threshold range or not; if yes, the body diode in the bare chip to be tested is considered to be in a blocking state, and the test is continued; if not, the communication state of the bare chip to be tested is considered abnormal to realize the wafer-level reliability test, so that the detection precision is ensured, the production yield is improved, and the production cost is reduced.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for testing reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a system for testing reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating another exemplary system for testing the reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a portion of a system for testing the reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 5 is a flowchart of another method for testing the reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 6 is a flowchart of another method for testing the reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a portion of another exemplary system for testing the reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a gate waveform during a reliability test of a semiconductor wafer according to an embodiment of the present invention;

FIG. 9 is a flowchart of another method for testing the reliability of a semiconductor wafer according to an embodiment of the present invention;

FIG. 10 is a flowchart of another method for testing the reliability of a semiconductor wafer according to an embodiment of the present invention;

fig. 11 is a flowchart of another method for testing reliability of a semiconductor wafer according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a flowchart of a method for testing reliability of a semiconductor wafer according to an embodiment of the present invention, where the method may be performed by a reliability system of a semiconductor wafer, and the reliability system of the semiconductor wafer may be implemented in hardware and/or software, and the reliability system of the semiconductor wafer may be configured in a reliability testing device of the semiconductor wafer. Fig. 2 is a schematic structural diagram of a reliability testing system for a semiconductor wafer according to an embodiment of the present invention, and fig. 3 is a schematic structural diagram of another reliability testing system for a semiconductor wafer according to an embodiment of the present invention, where, as shown in fig. 1 and 2, a reliability testing system 100 for a semiconductor wafer includes: a source measurement module 101, a plurality of test modules 102, a power module 103, and a control module 104; the semiconductor wafer comprises a plurality of bare chips 1023 to be tested, the source measurement module 101 comprises a source measurement unit 105 and a single-pole double-throw switch 106, the source measurement unit 105 at least comprises a first source measurement unit 1051 and a second source measurement unit 1052, the single-pole double-throw switch 106 at least comprises a first single-pole double-throw switch 1061 and a second single-pole double-throw switch 1062, and the test module 102 at least comprises a driving unit 1021 and a switch array 1022; the power module 103 is connected with the driving unit 1021, the control module 104 and the switch array 1022 respectively; the driving unit 1021 is connected with the control module 104; the first terminal a of the first source-measurement unit 1051 and the first terminal a of the second source-measurement unit 1052 are both connected to the reference voltage terminal MGND; the second end b of the first source-measurement unit 1051 is connected to the first end a of the first single-pole double-throw switch 1061, and the second end b of the second source-measurement unit 1052 is connected to the first end a of the second single-pole double-throw switch 1062; the second end b of the first single pole double throw switch 1061 is connected to the second end b of the second single pole double throw switch 1062; the third end c of the first single-pole double-throw switch 1061 and the third end c of the second single-pole double-throw switch 1062 are connected and are both connected with the drain electrode D of the die 1023 to be tested; the grid G of the bare chip 1023 to be tested is connected with the second end b of the driving unit 1021 or the first single-pole double-throw switch 1061; the source S of the bare chip 1023 to be tested is connected with the reference voltage end MGND or the grounding end GND; the switch array 1022 is connected to the source S, drain D, and gate G of the die 1023 under test, respectively.

In which a plurality of Die 1023 to be tested are disposed on a semiconductor wafer, for a single semiconductor wafer source measurement module 101 including at least two or more source measurement units 105, the source measurement units 105 include a first source measurement unit 1051 and a second source measurement unit 1052, and typically, the number of the source measurement units 105 is an even multiple, the specific configuration depends on the number of Die in the semiconductor wafer and the burn-in period of the test system, for example, 720 Die (Die) are disposed on a semiconductor wafer, and assuming that the Die has completed a burn-in period of 10min, the scan period is 5min when using 4 source measurement units 105 (two are a group). The bare chip may be understood as a MOS transistor, and the exemplary diagram is shown with the bare chip 1023 to be tested as an N-type MOS transistor, specifically, the bare chip is reasonably set with the source measurement unit 105 according to the burn-in period. The source measurement unit 105 may include a high-precision measurement source table. The source measurement module 101 further includes a single-pole double-throw switch 106, where the single-pole double-throw switch 106 includes a first single-pole double-throw switch 1061 and a second single-pole double-throw switch 1062, and the connection manner of the switching ends of the single-pole double-throw switch 106 can be controlled according to actual use requirements, specifically, the first end of the first source measurement unit 1051 and the first end a of the second source measurement unit 1052 are both connected to the reference voltage end MGND; the second end b of the first source-measurement unit 1051 is connected to the first end a of the first single-pole double-throw switch 1061, and the second end b of the second source-measurement unit 1052 is connected to the first end a of the second single-pole double-throw switch 1062; the second end b of the first single pole double throw switch 1061 is connected to the second end b of the second single pole double throw switch 1062; the third end c of the first single-pole double-throw switch 1061 and the third end c of the second single-pole double-throw switch 1062 are connected and are both connected with the drain electrode D of the die 1023 to be tested; the grid G of the bare chip 1023 to be tested is connected with the second end b of the driving unit 1021 or the first single-pole double-throw switch 1061, and can be correspondingly switched according to the communication test requirement and the aging test requirement; meanwhile, the source S of the bare chip 1023 to be tested is connected with the reference voltage end MGND or the ground end GND, and can be switched according to actual testing requirements, so that the testing effect of the bare chip 1023 to be tested is ensured. The test module 102 is provided with a driving unit 1021 and a switch array 1022, and the power supply module 103 is respectively connected with the driving unit 1021, the control module 104 and the switch array 1022; the driving unit 1021 is connected with the control module 104. The driving unit 1021 amplifies the PWM signal output by the control circuit in the control module 104 to generate a gate driving signal of the die 1023 to be tested; the power module 103 mainly generates the working power required by each functional circuit in the test system, and provides the driving power in the driving unit 1021, such as +vcc, -VEE in fig. 2, which can be flexibly adjusted according to different burn-in parameter specifications. Providing an operating power supply for the switch array 1022; an operating power supply of the driving unit 1021 is provided and an operating power supply of the control module 104 is provided. The control module 104 serves as a common control core of the test system, and can perform PWM wave generation control and operation logic control of the switch array 1022 on the test module 102, and the control module 104 outputs a switch array control signal to the switch array 1022. The switch arrays are respectively connected with the source electrode, the drain electrode and the grid electrode of each bare chip 1023 to be tested in the semiconductor wafer, namely, the switch arrays 1022 are added to the periphery of the drain electrode D (Drain), the grid electrode G (gate) and the source electrode S (source) of the bare chip 1023 to be tested, the switches in the switch arrays 1022 are arranged in one-to-one correspondence with the bare chip 1023 to be tested, the switch arrays 1022 can be connected with an external controller for receiving control signals, correspondingly realizing different on-off actions of the switch arrays 1022, and the bare chip 1023 to be tested can work in an aging state by combining different actions of the switch arrays 1022, wherein the aging state is a PWM wave with fixed frequency and duty ratio is applied to the bare chip 1023 to be tested, so that the reliability test of the semiconductor wafer can be realized, the reliability test can be a dynamic high-temperature grid bias test (DYNAMIC HIGH-temperature gate bias, DHTGB), the dynamic reliability of a device is further represented accurately, and the production yield is further improved. By reasonably controlling the starting states of the single-pole double-throw switches 106 and the source measurement units 105 and the starting states of the switch arrays 1022, connectivity tests can be performed in advance, whether semiconductor wafers to be tested are communicated normally or not is judged, the semiconductor wafers with faults are screened in advance, then aging tests are performed, reliability test precision is guaranteed, meanwhile, the switch arrays 1022 are further arranged in the reliability test system, and peripheral circuits and control logic difficulties of the source measurement units 105 can be simplified.

With continued reference to fig. 2, the test module 102 includes a current limiting protection unit 107; the current limiting protection unit 107 is connected to the driving unit 1021, the control module 104, and the power supply module 103, respectively.

The current limiting protection unit 107 is configured to monitor, in real time, an abnormal current of the gate of the die 1023 to be tested during the PWM wave generation process, and once the gate leakage current exceeds a certain threshold value, the PWM wave sealing of the test module 102 is correspondingly performed. Meanwhile, the control module 104 is connected with the current-limiting protection unit 107, the current-limiting protection unit 107 feeds back a wave-sealing protection signal, and the control module 104 can monitor the current-limiting protection in real time, so that the test precision is ensured.

With continued reference to fig. 1, 2 and 3, the method for testing the reliability of the semiconductor wafer includes:

S201, starting a testing module, a power module and a control module.

S202, a switching end of the first single-pole double-throw switch is controlled to be connected with a second end of the first single-pole double-throw switch.

Wherein, the switching end of the first single-pole double-throw switch 1061 is controlled to be connected to the second end b of the first single-pole double-throw switch 1061, so that the first single-pole double-throw switch 1061 is connected to the gate G of the die 1023 to be tested.

S203, the switching end of the second single-pole double-throw switch is controlled to be connected with the third end of the second single-pole double-throw switch.

Wherein, the switching end of the second single-pole double-throw switch 1062 is controlled to be connected to the third end c of the second single-pole double-throw switch 1062, so that the second single-pole double-throw switch 1062 is connected to the drain D of the die 1023 to be tested.

S204, controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch and the source electrode of the bare chip to be tested to be connected with the reference voltage end.

The on state of the switch array 1022 is controlled by a certain control logic, so that the gate G of the die 1023 to be tested is connected to the second end b of the first single-pole double-throw switch 1061, and the source S of the die 1023 to be tested is connected to the reference voltage end MGND, where the reference voltage end MGND corresponds to the number of source measurement units, and may include MGND 1-MGNDn, where n is a positive integer greater than or equal to 1, so as to form a connectivity test loop, and ensure connectivity judgment on the die 1023 to be tested.

S205, controlling the first source measuring unit to be in a wave sealing state, controlling the second source measuring unit to output first preset fixed voltage and current information, and obtaining first measurement data of the bare chip to be measured.

Fig. 4 is a schematic diagram of a part of a structure of a reliability test system for a semiconductor wafer according to an embodiment of the present invention, as shown in fig. 4, a first source measurement unit 1051 is controlled to be in a wave-sealing state, that is, a PWM wave emitted is negative pressure or 0V, a gate G of a die 1023 to be tested is not turned on, a second source measurement unit 1052 is respectively connected to a source S and a drain D of the die 1023 to be tested, that is, connected to two ends of a body diode in the die 1023 to be tested, and the second source measurement unit 1052 is controlled to output first preset fixed voltage and current information, where the first preset fixed voltage and current information may include an output voltage value of 10V, and an output current is 1mA, so as to obtain first measurement data of the die 1023 to be tested, which is collected by the second source measurement unit 1052.

S206, acquiring a preset voltage threshold range.

The preset voltage threshold range V _DS is correspondingly determined according to the specific specification of the die 1023 to be tested, and the preset voltage threshold range is a preset source-drain voltage threshold range, and exemplary, the preset voltage threshold range may be 9.5V < V _DS < 10.5V.

S207, judging whether the first measurement data is within a preset voltage threshold range; if yes, go to step S208; if not, step S209 is performed.

S208, the body diode in the bare chip to be tested is considered to be in a cut-off state, and the test is continued.

S209, considering that the communication state of the bare chip to be tested is abnormal.

The connectivity detection is performed on the bare chip 1023 to be detected, whether the body diode in the bare chip 1023 to be detected is in a connected state or in a closed state is judged according to first measurement data, the first measurement data are normal, the body diode is in the closed state, and the body diode is considered to be fault-free and is in an isolated state; the first test data are abnormal, the body diode is in a communication state, the body diode is considered to have faults, and then when the aging detection is carried out subsequently, the fault bare chip is not detected subsequently, so that the accuracy of the detection result is ensured.

Specifically, under the condition that the first source measurement unit 1051 is in a wave-sealing state and the second source measurement unit 1052 outputs first preset fixed voltage and current information, first measurement data at two ends of the body diode are obtained, whether the first measurement data are in a preset voltage threshold range or not is further judged, and when the first measurement data are in the preset voltage threshold range, the body diode is considered to be in a normal off state and has no fault; when the first measurement data is not in the preset voltage threshold range, the body diode is considered to be in a non-blocking state, faults exist, the communication state of the bare chip 1023 to be tested is abnormal, the elimination can be performed, and the subsequent detection is not performed any more.

The embodiment of the invention starts the test module, the power module and the control module; the switching end of the first single-pole double-throw switch is controlled to be connected with the second end of the first single-pole double-throw switch; the switching end of the second single-pole double-throw switch is controlled to be connected with the third end of the second single-pole double-throw switch; the grid electrode of the bare chip to be tested is controlled to be connected with the second end of the first single-pole double-throw switch, and the source electrode of the bare chip to be tested is controlled to be connected with the reference voltage end, the first source measuring unit is controlled to be in a wave sealing state, the second source measuring unit is controlled to output first preset fixed voltage and current information, and first measuring data of the bare chip to be tested are obtained; the method comprises the steps of obtaining a preset voltage threshold range, judging whether first measurement data are located in the preset voltage threshold range, further determining the isolation state of a body diode in the bare chip to be tested, realizing connectivity test of the bare chip to be tested, guaranteeing that the bare chip to be tested is in a normal working state, and further guaranteeing follow-up detection accuracy and reliability.

Optionally, fig. 5 is a flowchart of another method for testing reliability of a semiconductor wafer according to an embodiment of the present invention, where, as shown in fig. 5, the method for testing reliability of a semiconductor wafer includes:

s301, starting a testing module, a power module and a control module.

S302, a switching end of the first single-pole double-throw switch is controlled to be connected with a second end of the first single-pole double-throw switch.

S303, controlling the switching end of the second single-pole double-throw switch to be connected with the third end of the second single-pole double-throw switch.

S304, controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch and the source electrode of the bare chip to be tested to be connected with the reference voltage end.

S305, controlling the first source measuring unit to be in a wave sealing state, controlling the second source measuring unit to output first preset fixed voltage and current information, and obtaining first measurement data of the bare chip to be measured.

S306, acquiring a preset voltage threshold range.

S307, judging whether the first measurement data is in a preset voltage threshold range; if yes, go to step S308; if not, step S311 is performed.

S308, the body diode in the bare chip to be tested is considered to be in a cut-off state, and the test is continued.

S309, controlling the first source measuring unit to output second preset fixed voltage and current information and controlling the second source measuring unit to output third preset fixed voltage and current information, and obtaining second measurement data of the bare chip to be measured.

After determining that the body diode in the die 1023 to be tested is in the off state, controlling the first source measurement unit 1051 and the second source measurement unit 1052 to be in the working state, where the first source measurement unit 1051 outputs second preset fixed voltage and current information and the second source measurement unit 1052 outputs third preset fixed voltage and current information, so as to obtain second measurement data of the die 1023 to be tested collected by the first source measurement unit 1051 and the second source measurement unit 1052, where the second preset fixed voltage and current information may include an output voltage of 6V and an output current of 1mA; the third preset fixed voltage and current information may include an output voltage of 2V and an output current of 1mA, and the second preset fixed voltage and current information and the third preset fixed voltage and current information may be set correspondingly according to an actual test requirement of the die 1023 to be tested.

S310, determining the communication state of the bare chip to be tested according to the second measurement data.

The connectivity detection is performed on the bare chip 1023 to be tested, the communication state of the bare chip 1023 to be tested is judged according to second measurement data, the second measurement data are normal, and the bare chip 1023 to be tested is considered to have no fault; the second test data is abnormal, the body diode is in a communication state, the bare chip 1023 to be tested is considered to have faults, and then the faulty bare chip is not detected any more when the ageing detection is carried out later, so that the accuracy of the detection result is ensured.

S311, the communication state of the bare chip to be tested is considered to be abnormal.

According to the embodiment of the invention, the first source measuring unit is controlled to be in a wave sealing state, the second source measuring unit is controlled to output first preset fixed voltage and current information, and first measuring data of the bare chip to be measured are obtained; acquiring a preset voltage threshold range, judging whether first measurement data are located in the preset voltage threshold range, further determining the isolation state of a body diode in the bare chip to be tested, controlling a first source measurement unit to output second preset fixed voltage and current information and controlling a second source measurement unit to output third preset fixed voltage and current information, acquiring second measurement data of the bare chip to be tested, determining the communication state of the bare chip to be tested according to the second measurement data, realizing connectivity test of the bare chip to be tested, ensuring that the bare chip to be tested is in a normal working state, and further ensuring the follow-up detection accuracy and reliability.

Optionally, fig. 6 is a flowchart of another method for testing reliability of a semiconductor wafer according to an embodiment of the present invention, fig. 7 is a schematic diagram of a part of a structure of another system for testing reliability of a semiconductor wafer according to an embodiment of the present invention, and fig. 8 is a schematic diagram of an action waveform of a gate electrode in a process of testing reliability of a semiconductor wafer according to an embodiment of the present invention, which reflects a change of a gate-source voltage in different test stages t1, t2, t3 and t4, as shown in fig. 6,7 and 8, where the second measurement data includes a gate-source voltage value, a source-drain voltage value and a source-drain current value.

The reliability test method of the semiconductor wafer comprises the following steps:

s401, starting a testing module, a power module and a control module.

S402, a switching end of the first single-pole double-throw switch is controlled to be connected with a second end of the first single-pole double-throw switch.

S403, controlling the switching end of the second single-pole double-throw switch to be connected with the third end of the second single-pole double-throw switch.

S404, controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch and the source electrode of the bare chip to be tested to be connected with the reference voltage end.

S405, controlling the first source measuring unit to be in a wave sealing state, controlling the second source measuring unit to output first preset fixed voltage and current information, and obtaining first measurement data of the bare chip to be measured.

S406, acquiring a preset voltage threshold range.

S407, judging whether the first measurement data is in a preset voltage threshold range; if yes, executing step S409; if not, step S408 is performed.

S408, the communication state of the bare chip to be tested is considered to be abnormal.

S409, the body diode in the bare chip to be tested is considered to be in a blocking state, and the test is continued.

S410, controlling the first source measuring unit to output second preset fixed voltage and current information and controlling the second source measuring unit to output third preset fixed voltage and current information, and obtaining second measurement data of the bare chip to be measured.

S411, acquiring a preset gate-source voltage range, a preset source-drain voltage range and a preset source-drain current value.

The preset gate-source voltage range V _GS V < V _GS < 6.5V, the preset source-drain voltage range V _DS < 1V, and the preset source-drain current value I _DS are correspondingly determined according to the specific specification of the die 1023 to be tested, and the preset gate-source voltage range V _DS and the preset source-drain current value I _DS are exemplary, and the preset gate-source voltage range may be 5.5V < V _GS < 6.5V, the preset source-drain voltage range may be 0V < V _DS < 1V, and the preset source-drain current value may be 0.9A < I _DS < 1.1A.

S412, judging whether the gate-source voltage value is within a preset gate-source voltage range, whether the source-drain voltage value is within a preset source-drain voltage range and whether the source-drain current value is within a preset source-drain current range; if yes, go to step S413; if not, step S414 is performed.

S413, the communication state of the bare chip to be tested is considered to be normal.

S414, regarding the communication state of the bare chip to be tested as abnormal.

Under the condition that the first source measurement unit 1051 outputs second preset fixed voltage and current information and the second source measurement unit 1052 outputs third preset fixed voltage and current information, second measurement data of the body diode are obtained, whether the second measurement data are in a preset gate source voltage range, a preset source drain voltage range and a preset source drain current value or not is further judged, and when the second measurement data are in the preset gate source voltage range, the preset source drain voltage range and the preset source drain current value, the bare chip 1023 to be tested is considered to be in a normal off state and has no faults; when the preset gate-source voltage range, the preset source-drain voltage range and the preset source-drain current value are not in the preset voltage threshold range, the bare chip 1023 to be tested is considered to be in a blocking state, faults exist, the communication state of the bare chip 1023 to be tested is abnormal, the exclusion can be performed, and the subsequent detection is not performed.

According to the embodiment of the invention, the first source measuring unit is controlled to output second preset fixed voltage and current information, and the second source measuring unit is controlled to output third preset fixed voltage and current information, so that second measurement data of the bare chip to be tested are obtained, the second measurement data comprise a gate source voltage value, a source drain voltage value and a source drain current value, a preset gate source voltage range, a preset source drain voltage range and a preset source drain current value are obtained, whether the gate source voltage value is within the preset gate source voltage range, whether the source drain voltage value is within the preset source drain voltage range and whether the source drain current value is within the preset source drain current range are judged, connectivity test of the bare chip to be tested is realized, the bare chip to be tested is guaranteed to be in a normal working state, and further, follow-up detection accuracy and reliability are guaranteed.

Optionally, fig. 9 is a flowchart of another method for testing reliability of a semiconductor wafer according to an embodiment of the present invention, where, as shown in fig. 9, the method for testing reliability of a semiconductor wafer includes:

s501, starting a test module, a power module and a control module.

S502, a switching end of the first single-pole double-throw switch is controlled to be connected with a second end of the first single-pole double-throw switch.

S503, controlling the switching end of the second single-pole double-throw switch to be connected with the third end of the second single-pole double-throw switch.

S504, controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch and the source electrode of the bare chip to be tested to be connected with the reference voltage end.

S505, the first source measuring unit is controlled to be in a wave sealing state, the second source measuring unit is controlled to output first preset fixed voltage and current information, and first measuring data of the bare chip to be measured are obtained.

S506, acquiring a preset voltage threshold range.

S507, judging whether the first measurement data is in a preset voltage threshold range or not; if yes, go to step S509; if not, step S508 is performed.

S508, the communication state of the bare chip to be tested is considered to be abnormal.

S509, the body diode in the bare chip to be tested is considered to be in a cut-off state, and the test is continued.

S510, controlling the first source measuring unit to output second preset fixed voltage and current information and controlling the second source measuring unit to output third preset fixed voltage and current information, and obtaining second measurement data of the bare chip to be measured.

S511, obtaining a preset gate source voltage range, a preset source drain voltage range and a preset source drain current value.

S512, judging whether the gate-source voltage value is within a preset gate-source voltage range, whether the source-drain voltage value is within a preset source-drain voltage range and whether the source-drain current value is within a preset source-drain current range; if yes, go to step S514; if not, step S513 is performed.

S513, the communication state of the bare chip to be tested is considered to be abnormal.

S514, the communication state of the bare chip to be tested is considered to be normal.

S515, the control driving module is connected with the grid electrode of the bare chip to be tested, and outputs PWM waves with preset duty ratio to the grid electrode of the bare chip to be tested.

The driving module 1021 outputs a PWM wave with a preset duty ratio to the gate G of the die 1023 to be tested, i.e. the control module 104 generates a PWM wave with a certain frequency and duty ratio.

S516, controlling the source electrode and the drain electrode of the bare chip to be tested to be connected, and controlling the source electrode to be switched to be connected with the grounding end and continuously communicated for a preset time.

S517, controlling the start-up states of the first source-measurement unit and the second source-measurement unit.

Wherein the first source-measuring unit 1051 and the second source-measuring unit 1052 are controlled to be in an operating state, or the first source-measuring unit 1051 is in an operating state and the second source-measuring unit 1052 is in an inactive state.

S518, acquiring the aging state of the bare chip to be tested according to the starting state and PWM waves with preset duty ratio.

The aging detection is performed on the die 1023 to be tested through the switch logic corresponding to the switch array 1022, and the state of the die 1023 to be tested is obtained according to the starting states of the first source measurement unit 1051 and the second source measurement unit 1052 and the PWM wave with the preset duty ratio, so that the performance of the semiconductor wafer is conveniently analyzed and judged.

According to the embodiment of the invention, the driving module is controlled to output PWM waves with the preset duty ratio to the grid electrode of the bare chip to be tested, the source electrode and the drain electrode of the bare chip to be tested are controlled to be connected, the source electrode is controlled to be switched to be connected with the grounding end and continuously communicated with the preset time, the aging process of the device is realized, the starting states of the first source measuring unit and the second source measuring unit are controlled, the aging state of the semiconductor wafer is obtained according to the starting states and the PWM waves with the preset duty ratio, the aging test of the bare chip to be tested is further simulated, the reliability detection of the semiconductor wafer is completed, and the detection accuracy and reliability are ensured.

Optionally, fig. 10 is a flowchart of another method for testing reliability of a semiconductor wafer according to an embodiment of the present invention, where, as shown in fig. 10, the method for testing reliability of a semiconductor wafer includes:

S601, starting a testing module, a power module and a control module.

S602, a switching end of the first single-pole double-throw switch is controlled to be connected with a second end of the first single-pole double-throw switch.

S603, controlling the switching end of the second single-pole double-throw switch to be connected with the third end of the second single-pole double-throw switch.

S604, controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch and the source electrode of the bare chip to be tested to be connected with the reference voltage end.

S605, controlling the first source measuring unit to be in a wave sealing state, controlling the second source measuring unit to output first preset fixed voltage and current information, and obtaining first measurement data of the bare chip to be measured.

S606, acquiring a preset voltage threshold range.

S607, judging whether the first measurement data is within a preset voltage threshold range; if yes, go to step S609; if not, step S608 is performed.

S608, the communication state of the bare chip to be tested is considered to be abnormal.

S609, the body diode in the bare chip to be tested is considered to be in a cut-off state, and the test is continued.

S610, controlling the first source measuring unit to output second preset fixed voltage and current information and controlling the second source measuring unit to output third preset fixed voltage and current information, and obtaining second measurement data of the bare chip to be measured.

S611, obtaining a preset gate source voltage range, a preset source drain voltage range and a preset source drain current value.

S612, judging whether the gate-source voltage value is within a preset gate-source voltage range, whether the source-drain voltage value is within a preset source-drain voltage range and whether the source-drain current value is within a preset source-drain current range; if yes, go to step S614; if not, step S613 is performed.

S613, the communication state of the bare chip to be tested is considered to be abnormal.

S614, the communication state of the bare chip to be tested is considered to be normal.

S615, the control driving module is connected with the grid electrode of the bare chip to be tested, and outputs PWM waves with preset duty ratio to the grid electrode of the bare chip to be tested.

S616, the source electrode and the drain electrode of the bare chip to be tested are controlled to be connected, the source electrode is controlled to be switched to be connected with the grounding end, and the source electrode is continuously communicated for a preset time.

The PWM wave with the preset duty ratio, which is output by the control driving module 1021, is received by the gate of the die 1023 to be tested, and controls the on or off state of the switch array 1022, so as to control the source S and the drain D of the die 1023 to be tested to be connected, and control the source S to be switched to be connected with the ground GND, and continuously communicate with the preset time, so as to simulate the working condition of the die 1023 to be tested in the application state, and perform the aging process.

S617, the second end of the first single-pole double-throw switch is controlled to be connected with the grid electrode of the bare chip to be tested.

S618, controlling the source electrode of the bare chip to be tested to be connected with the reference voltage end.

When the aging process is finished, the aging state of the aged bare chip 1023 needs to be measured, and then the on or off state of the switch array 1022 needs to be controlled again, so as to realize that the second end b of the first single pole double throw switch 1061 is connected with the gate G of the bare chip 1023 to be measured, and control that the source S of the bare chip 1023 to be measured is connected with the reference voltage end MGND, thereby ensuring the aging state measurement effect of the bare chip 1023 to be measured.

S619, the switching end of the first single-pole double-throw switch is controlled to be connected with the second end of the first single-pole double-throw switch.

S620, the switching end of the second single-pole double-throw switch is controlled to be connected with the third end of the second single-pole double-throw switch.

Wherein, the first source measurement unit 1051 is controlled to be connected between the source S and the drain D of the die 1023 to be tested, and the second source measurement unit 1052 is controlled to be connected between the gate G and the source S of the die 1023 to be tested, so as to ensure that the first source measurement unit 1051 and the second source measurement unit 1052 are both in a start state.

S621, the threshold voltage of the bare chip to be tested is correspondingly obtained according to PWM waves with preset duty ratios at different moments.

S622, obtaining the aging state of the bare chip to be tested according to the threshold voltage.

The PWM wave with the preset duty ratio output by the driving module 1021 at different moments is matched with the first source measurement unit 1051 and the second source measurement unit 1052 to be in a start state, so as to obtain the threshold voltage V _GS (th) of the die 1023 to be tested, and further reflect the aging state of the die 1023 to be tested after a certain time.

According to the embodiment of the invention, the driving module is controlled to be connected with the grid electrode of the bare chip to be tested, PWM waves with a preset duty ratio are output to the grid electrode of the bare chip to be tested, the source electrode of the bare chip to be tested is controlled to be connected with the drain electrode, the source electrode is controlled to be switched to be connected with the grounding end and continuously communicated with the preset time, the second end of the first single-pole double-throw switch is controlled to be connected with the grid electrode of the bare chip to be tested, the second end of the first single-pole double-throw switch is controlled to be connected with the second end of the first single-pole double-throw switch, the switching end of the second single-pole double-throw switch is controlled to be connected with the third end of the second single-pole double-throw switch, the threshold voltage of the bare chip to be tested is obtained according to the PWM waves with the preset duty ratio at different moments, the aging state of the bare chip to be tested is obtained according to the threshold voltage, the aging test of the bare chip to be tested is realized, and further the reliability test of the semiconductor wafer is finished, and the reliability test is guaranteed.

Optionally, fig. 11 is a flowchart of another method for testing reliability of a semiconductor wafer according to an embodiment of the present invention, where, as shown in fig. 11, the method for testing reliability of a semiconductor wafer includes:

S701, starting a test module, a power module and a control module.

S702, a switching end of the first single-pole double-throw switch is controlled to be connected with a second end of the first single-pole double-throw switch.

S703, controlling the switching end of the second single-pole double-throw switch to be connected with the third end of the second single-pole double-throw switch.

S704, controlling the grid electrode of the bare chip to be tested to be connected with the second end of the first single-pole double-throw switch and the source electrode of the bare chip to be tested to be connected with the reference voltage end.

S705, controlling the first source measuring unit to be in a wave sealing state and controlling the second source measuring unit to output first preset fixed voltage and current information, and acquiring first measurement data of the bare chip to be measured.

S706, acquiring a preset voltage threshold range.

S707, judging whether the first measurement data is within a preset voltage threshold range; if yes, go to step S709; if not, step S708 is performed.

S708, the communication state of the bare chip to be tested is considered to be abnormal.

S709, the body diode in the bare chip to be tested is considered to be in a cut-off state, and the test is continued.

S710, controlling the first source measuring unit to output second preset fixed voltage and current information and controlling the second source measuring unit to output third preset fixed voltage and current information, and obtaining second measurement data of the bare chip to be measured.

S711, acquiring a preset gate-source voltage range, a preset source-drain voltage range and a preset source-drain current value.

S712, judging whether the gate-source voltage value is within a preset gate-source voltage range, whether the source-drain voltage value is within a preset source-drain voltage range and whether the source-drain current value is within a preset source-drain current range; if yes, go to step S714; if not, step S713 is performed.

S713, the communication state of the bare chip to be tested is considered to be abnormal.

S714, the communication state of the bare chip to be tested is considered to be normal.

S715, the control driving module is connected with the grid electrode of the bare chip to be tested, and outputs PWM waves with preset duty ratio to the grid electrode of the bare chip to be tested.

S716, controlling the source electrode and the drain electrode of the bare chip to be tested to be connected, and controlling the source electrode to be switched to be connected with the grounding end and continuously communicated for a preset time.

S717, the second end of the first single-pole double-throw switch is controlled to be connected with the grid electrode of the bare chip to be tested.

S715, controlling the source electrode of the bare chip to be tested to be connected with the reference voltage end.

S719, controlling the switching end of the first single-pole double-throw switch to be connected with the second end of the first single-pole double-throw switch.

S720, controlling the second source measuring unit not to start.

Wherein, the first source measurement unit 1051 is controlled to start working and is respectively connected between the gate G and the source S of the die 1023 to be tested, and the second source measurement unit 1052 is controlled to not work, so that the source S and the drain D of the die 1023 to be tested are connected.

S721, correspondingly acquiring the grid leakage current of the bare chip to be tested according to PWM waves with preset duty ratios at different moments.

S722, the aging state of the bare chip to be tested is obtained according to the gate leakage current.

The PWM wave with the preset duty ratio output by the driving module 1021 at different moments is matched with the first source measurement unit 1051 to be in a start state and the second source measurement unit 1052 to be in a non-start state, so as to obtain the gate leakage current I _GSS of the die 1023 to be tested, and further reflect the aging state of the die 1023 to be tested after a certain time.

According to the embodiment of the invention, the driving module is controlled to be connected with the grid electrode of the bare chip to be tested, PWM waves with a preset duty ratio are output to the grid electrode of the bare chip to be tested, the source electrode and the drain electrode of the bare chip to be tested are controlled to be connected, the source electrode is controlled to be switched to be connected with the grounding end, the second end of the first single-pole double-throw switch is controlled to be connected with the grid electrode of the bare chip to be tested, the source electrode of the bare chip to be tested is controlled to be connected with the reference voltage end, the switching end of the first single-pole double-throw switch is controlled to be connected with the second end of the first single-pole double-throw switch, the second source measuring unit is controlled not to be started, the source electrode and the drain electrode of the bare chip to be tested are controlled to be connected, the grid leakage current of the bare chip to be tested is correspondingly obtained according to PWM waves with the preset duty ratio at different moments, the aging state of the bare chip to be tested is obtained according to the grid leakage current, and then the reliability detection of a semiconductor wafer is finished, and the detection accuracy and reliability are ensured.

The embodiment of the invention also provides a reliability testing device of the semiconductor wafer, which comprises the reliability testing system of the semiconductor wafer.

It should be noted that, since the reliability testing device for a semiconductor wafer provided in this embodiment includes any of the reliability testing systems for a semiconductor wafer provided in the embodiments of the present invention, the reliability testing systems for a semiconductor wafer have the same or corresponding beneficial effects, and are not described herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A reliability test method of a semiconductor wafer is characterized in that the reliability test method is applied to a reliability test system of the semiconductor wafer; the reliability test system of the semiconductor wafer comprises: the system comprises a source measurement module, a plurality of test modules, a power supply module and a control module;

The semiconductor wafer comprises a plurality of bare chips to be tested;

The second end of the first single-pole double-throw switch is connected with the second end of the second single-pole double-throw switch; the third end of the first single-pole double-throw switch is connected with the third end of the second single-pole double-throw switch and is connected with the drain electrode of the bare chip to be tested; the grid electrode of the bare chip to be tested is connected with the second end of the driving unit or the first single-pole double-throw switch; the source electrode of the bare chip to be tested is connected with the reference voltage end or the grounding end; the switch array is respectively connected with a source electrode, a drain electrode and a grid electrode of the bare chip to be tested;

Starting a testing module, a power module and a control module;

acquiring a preset voltage threshold range;

2. The method of claim 1, wherein continuing the test comprises:

3. The method of claim 2, wherein the second measurement data includes a gate-source voltage value, a source-drain voltage value, and a source-drain current value;

4. The method for testing the reliability of a semiconductor wafer according to claim 3, further comprising, after considering the state of connectivity of the die under test as normal:

The control driving module is connected with the grid electrode of the bare chip to be tested and outputs PWM waves with preset duty ratio;

5. The method of claim 4, wherein controlling the source and drain connections of the die under test and controlling the source to switch to ground for a predetermined time further comprises: controlling the second end of the first single-pole double-throw switch to be connected with the grid electrode of the bare chip to be tested;

6. The method of claim 5, wherein controlling the activation states of the first source-measurement unit and the second source-measurement unit comprises:

7. The method of claim 5, wherein controlling the activation states of the first source-measurement unit and the second source-measurement unit comprises:

Controlling the second source-measurement unit not to be started;