CN117895957A - Debugging method based on excitation signal and adjustable transmitter - Google Patents
Debugging method based on excitation signal and adjustable transmitter Download PDFInfo
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Abstract
The invention discloses a debugging method based on an excitation signal and an adjustable transmitter, and belongs to the technical field of transmitter debugging. The method comprises the following steps: the transmitter inputs an excitation signal to the first power divider to obtain a first signal and a second signal; inputting a second signal to a second power divider to obtain a detection signal and a frequency division signal, wherein the detection signal is subjected to a first comparator to obtain a first comparison signal and is input to a Field Programmable Gate Array (FPGA); the frequency division signal passes through a second comparator to obtain a second comparison signal and is input into a field programmable gate array FPGA; the field programmable gate array FPGA samples the second comparison signal to obtain frequency information of the excitation signal; and debugging the output power, the output power back-off and the output waveform of the first signal according to the frequency information. And compensating the grid voltage and the attenuation code of the transmitting link through the frequency information, so that the pulse power, the pulse waveform, the power fluctuation in the working frequency band and the pulse power rollback reach the index requirements.
Description
Technical Field
The invention relates to the technical field of transmitter debugging, in particular to a debugging method based on an excitation signal and an adjustable transmitter.
Background
At present, a transmitter in the technical field of airborne comprehensive avionics belongs to a multi-mode transmitter, and functions and signal formats of the transmitter generally comprise aviation control, ADS-B, DME, TACAN, data link, identification and the like.
The transmitter performs amplification of the radio frequency carrier signal, typically to kilowatt levels. The method has strict requirements on indexes such as pulse power, pulse waveform (including pulse width, pulse rising edge, pulse falling edge, pulse top irregularity and pulse sequence irregularity), power fluctuation in an operating frequency band, pulse power rollback and the like transmitted by a transmitter. The rising edge of the pulse is 50 ns-100 ns, the falling edge of the pulse is 50 ns-200 ns, the power fluctuation in the working frequency band is generally smaller than 1dB, and for a continuous series of pulses, the rising edge, the falling edge and the power fluctuation of the pulse meet the index requirements, and the debugging difficulty is very high.
The current multimode transmitter generally adopts a GaN power amplifier tube to realize the amplification function of 1000W-2000W order port power, and the modulation technical system generally adopts a drain high-voltage modulation technology to realize the radio frequency modulation of mode signals such as aviation control, ADS-B, DME, TACAN, data link and the like. The pulse envelope of the radio frequency signals in the DME mode and the TACAN mode utilizes the high-voltage pulse signal of the drain electrode to control the on/off working time of the GaN power amplifier tube, and a kilowatt-level clock-shaped pulse envelope radio frequency signal is generated. The power in modes such as data link and identification requires back-off use, and indexes such as power fluctuation in an operating frequency band are generally required. If all indexes are ensured only by means of the characteristics of the GaN power amplifier tube, the debugging difficulty is high, the change is large under the high-low temperature condition, and all indexes of the transmitter are not easy to meet. In the prior art, because the system has no frequency information, the main indexes of the transmitter are realized by means of hardware circuits, and for some indexes with harsh requirements, the debugging difficulty is high, or part of indexes can not be completely realized by the hardware circuits, and especially the requirements are met under different environments. The indexes such as pulse width, pulse rising edge, pulse falling edge, power program control and the like of the transmitted waveform are difficult to meet all requirements in different environments only through a hardware circuit.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a debugging method based on an excitation signal and an adjustable transmitter.
The aim of the invention is realized by the following technical scheme: the first aspect of the present invention provides: a debugging method based on an excitation signal comprises the following steps:
the transmitter inputs an excitation signal to the first power divider to obtain a first signal and a second signal; inputting the second signal to a second power divider to obtain a third signal and a fourth signal; inputting a third signal to a detector to obtain a detection signal, and obtaining a first comparison signal by the detection signal through a first comparator and inputting the first comparison signal to a Field Programmable Gate Array (FPGA); the fourth signal is input into a frequency divider to obtain a frequency division signal, the frequency division signal passes through a second comparator to obtain a second comparison signal, the second comparison signal is input into a field programmable gate array FPGA, the frequency division signal is a sine signal, and the second comparison signal is an LVTTL signal; the field programmable gate array FPGA samples the second comparison signal to obtain frequency information of the excitation signal; debugging the output power, the output power back-off and the output waveform of the first signal according to the frequency information;
the first power divider inputs a first signal to the driving amplifier, then enters the final-stage amplifier through the program-controlled attenuator, and finally passes through the circulator and the filter to be output; the output waveforms are debugged in the driver amplifier and the final amplifier, and the output power back-off are debugged in the program-controlled attenuator.
Preferably, the frequency information is obtained by:
recording frequency information as fin and MHz; the internal clock of the field programmable gate array FPGA is fs, and the unit is MHz; and (3) performing X frequency division on the fourth signal, wherein the period of the second comparison signal is X/fin, the field programmable gate array FPGA uses the second comparison signal and the internal clock fs as counting trigger signals, the counting of N periods is performed, and the counting length K of the internal clock fs is obtained when the counting is stopped, so that the following steps are obtained:
(X/fin) n= (1/fs) K, where fin= (X N/K) fs; the frequency information of the excitation signal can be obtained according to the counting length K of the internal clock fs when the counting is stopped.
Preferably, the step of adjusting the output power includes the steps of:
storing a plurality of attenuation values in a data memory, wherein each attenuation value corresponds to different frequency information; the frequency point of the lowest output power of the final amplifier in the working frequency band is recorded as P0, and the attenuation value of P0 is written as 0dB in a data memory; after the field programmable gate array FPGA obtains the frequency information, the attenuation value corresponding to the frequency information is transmitted to the program-controlled attenuator for reducing the input of the final-stage amplifier, so that the difference value between the output power of the final-stage amplifier at each frequency point and the output power of P0 is within a first preset value.
Preferably, the debugging of the output power back-off comprises the steps of:
when the transmitter is in a data chain mode or an identification mode and after the field programmable gate array FPGA obtains frequency information, different attenuation amounts are configured for each frequency point in an operating frequency band and are transmitted to a program-controlled attenuator, so that the difference value between the back-off amounts of the frequency points and the standard back-off amounts is within a second preset value.
Preferably, the debugging of the output waveform comprises the steps of:
storing a plurality of grid voltages in a data memory, wherein each grid voltage corresponds to different frequency information; when the transmitter is in the DME working mode or the TACAN working mode and after the field programmable gate array FPGA obtains the frequency information, the grid voltage corresponding to the frequency information is transmitted to the driving amplifier and the final-stage amplifier, so that the difference value between the output waveform of each frequency point in the working frequency band and the standard output waveform is within a third preset value.
A second aspect of the invention provides: an excitation signal-based tunable transmitter for implementing any one of the excitation signal-based tuning methods described above, comprising:
the digital board is connected with the radio frequency amplifying circuit and the power supply circuit; the digital board includes: the Field Programmable Gate Array (FPGA), a data memory, a configuration memory, a digital-to-analog converter (DAC) and an Amplifier (AMP); the radio frequency amplifying circuit includes: the power divider comprises a first power divider, a second power divider, a driving amplifier, a program-controlled attenuator, a final-stage amplifier, a circulator, a filter, a detector, a frequency divider, a first comparator and a second comparator; the first power divider is connected with the second power divider and the driving amplifier; the driving amplifier is connected with the program-controlled attenuator; the program-controlled attenuator is connected with the final-stage amplifier; the final amplifier is connected with the circulator; the circulator is connected with a filter; the second power divider is connected with the detector and the frequency divider; the detector is connected with the first comparator; the frequency divider is connected with the second comparator; the first comparator and the second comparator are connected with a field programmable gate array FPGA; the field programmable gate array FPGA is connected with the program-controlled attenuator, the data memory, the configuration memory, the power circuit, the DAC digital-to-analog converter and the AMP amplifier, and is used for outputting an attenuation control signal to the program-controlled attenuator and outputting a power amplifier source control signal to the power circuit; the AMP amplifier is connected with the driving amplifier and the final-stage amplifier, and is used for outputting the grid voltage of the driving amplifier to the driving amplifier and outputting the grid voltage of the final-stage amplifier to the final-stage amplifier; the power circuit is connected with the driving amplifier and the final-stage amplifier and is used for outputting the drain voltage of the driving amplifier to the driving amplifier and outputting the drain voltage of the final-stage amplifier to the final-stage amplifier.
Preferably, the digital board further comprises an isolation driving chip, and the field programmable gate array FPGA is connected with the RS485 serial communication interface and the waveform debugging interface through the isolation driving chip and receives or transmits RS485 level discrete control signals.
The beneficial effects of the invention are as follows:
1) The grid voltage and the attenuation code of the transmitting link are compensated through the frequency information, so that the pulse power, the pulse waveform (including pulse width, pulse rising edge, pulse falling edge, pulse top unevenness and pulse sequence unevenness), the power fluctuation in the working frequency band and the pulse power rollback reach the index requirements.
2) The debugging difficulty caused by hardware circuit cascading is avoided, so that the cost is reduced and the adjustability is greatly improved.
3) According to different environments, after the hardware circuit is debugged, the serial port tool is used for conveniently adjusting parameters such as the transmitting waveform, the power control and the like of the transmitter, and the index requirement of the navigation management for inquiring the transmitter is met.
4) The adjustability of the transmitter is improved, and the transmitter has the advantages of low cost, simple hardware, miniaturization and higher economic value.
Drawings
FIG. 1 is a block diagram of a tunable transmitter and a debugging method based on an excitation signal;
FIG. 2 is a flow chart of frequency information measurement;
FIG. 3 is a flow chart of a method for debugging output power and output power back-off;
FIG. 4 is a flow chart of an output waveform debugging method.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in the following examples, and it is obvious that the described examples are only some examples of the present invention, but not all examples. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present invention, based on the embodiments of the present invention.
Referring to fig. 1-4, the present invention provides a technical solution: the first aspect of the present invention provides: a debugging method based on an excitation signal comprises the following steps:
the transmitter inputs an excitation signal to the first power divider to obtain a first signal and a second signal; inputting the second signal to a second power divider to obtain a third signal and a fourth signal; inputting a third signal to a detector to obtain a detection signal, and obtaining a first comparison signal by the detection signal through a first comparator and inputting the first comparison signal to a Field Programmable Gate Array (FPGA); the fourth signal is input into a frequency divider to obtain a frequency division signal, the frequency division signal passes through a second comparator to obtain a second comparison signal, the second comparison signal is input into a field programmable gate array FPGA, the frequency division signal is a sine signal, and the second comparison signal is an LVTTL signal; the field programmable gate array FPGA samples the second comparison signal to obtain frequency information of the excitation signal; debugging the output power, the output power back-off and the output waveform of the first signal according to the frequency information;
the first power divider inputs a first signal to the driving amplifier, then enters the final-stage amplifier through the program-controlled attenuator, and finally passes through the circulator and the filter to be output; the output waveforms are debugged in the driver amplifier and the final amplifier, and the output power back-off are debugged in the program-controlled attenuator.
In some embodiments, the frequency information is obtained by:
recording frequency information as fin and MHz; the internal clock of the field programmable gate array FPGA is fs, and the unit is MHz; and (3) performing X frequency division on the fourth signal, wherein the period of the second comparison signal is X/fin, the field programmable gate array FPGA uses the second comparison signal and the internal clock fs as counting trigger signals, the counting of N periods is performed, and the counting length K of the internal clock fs is obtained when the counting is stopped, so that the following steps are obtained:
(X/fin) n= (1/fs) K, where fin= (X N/K) fs; the frequency information of the excitation signal can be obtained according to the counting length K of the internal clock fs when the counting is stopped.
The input excitation signal is generally between-12 dBm and 0dBm, the frequency information range is generally between 960MHz and 1280MHz, as shown in FIG. 2, in an embodiment, the frequency divider divides the fourth signal by 16 and then obtains a LVTTL signal (second comparison signal) of 60MHz to 80MHz after passing through the second comparator, and the field programmable gate array FGPA samples the LVTTL signal to obtain the frequency information. The frequency information fin (960 MHz-1280 MHz) is subjected to twice power division and then enters a frequency divider to be subjected to 16 frequency division, and the output sinusoidal signal (frequency division signal) is subjected to a second comparator to obtain an LVTTL signal (second comparison signal) with the frequency range of 60 MHz-80 MHz, wherein the period of the LVTTL signal (second comparison signal) is 16/fin. The field programmable gate array FPGA uses the signal as a count trigger signal to count N cycles (n=180); meanwhile, a clock (fs=200 MHz) known in the FPGA is also used as a counting trigger signal, and the counting length of the internal clock is K after N cycles are counted and stopped, so that the following steps are obtained: (16/fin) n= (1/fs) K so fin= (16×n/K) fs= (576000/K) MHz, i.e. the frequency information of the excitation signal can be obtained according to the count length K of the internal clock when the count is stopped.
Since the excitation signal is asynchronous with the internally known clock, the start and end times may be approximately 1 clock cycle less, i.e. the internal clock count length K is compared to the theoretical length K 0 With errors, found to be K 0 ±1；
Is found to be K 0 -1 error between test frequency and real frequencyThe method comprises the following steps:
=(576000/(K 0 -1)-576000/K 0 )MHz=(576000/(K 0 2 -K 0 ))MHz≈(576000/K 0 2 )MHz
is found to be K 0 At +1, the error between the test frequency and the true frequencyThe method comprises the following steps:
=(576000/(K 0 +1)-576000/K 0 )MHz=-(576000/(K 0 2 +K 0 ))MHz≈-(576000/K 0 2 )MHz
in summary, the error between the test frequency and the true frequency≈±(576000/K 0 2 ) MHz when the frequency information is 960MHz, K 0 600, at this point->About + -1.6 MHz; when the frequency information is 1280MHz, K 0 450, at this point->About + -2.84 MHz; it can be seen that when the frequency information of the excitation signal is between 960MHz and 1280MHz, the frequency information of the excitation signal obtained based on the method has small error from the true value, and the measurement result can be regarded as the frequency information of the current excitation signal.
In some embodiments, debugging the output power comprises the steps of:
storing a plurality of attenuation values in a data memory, wherein each attenuation value corresponds to different frequency information; the frequency point of the lowest output power of the final amplifier in the working frequency band is recorded as P0, and the attenuation value of P0 is written as 0dB in a data memory; after the field programmable gate array FPGA obtains the frequency information, the attenuation value corresponding to the frequency information is transmitted to the program-controlled attenuator for reducing the input of the final-stage amplifier, so that the difference value between the output power of the final-stage amplifier at each frequency point and the output power of P0 is within a first preset value.
Many indexes of the transmitter are related to the frequency information, so that after the frequency information of the excitation signal is obtained, many indexes can be debugged and qualified according to the frequency information. When the output power of the transmitter in the working frequency band is required to be larger than or equal to a certain value, the power fluctuation in the frequency band is generally required to be smaller than or equal to 1dB, namely the difference between the highest output power and the lowest output power in the frequency band is not larger than 1dB. When the transmitter works at different frequencies, if the power supplied to the input end of the final-stage amplifier is consistent, the final-stage amplifier shows different output powers along with the frequencies, which results in larger fluctuation of the output power in the working frequency band and is difficult to reach the index requirement. The difference value of the output power of the final-stage amplifier at each frequency point and the output power of P0 is within a first preset value, the output power of any frequency point of the transmitter in the whole working frequency band can be regulated to be basically consistent, and then the power fluctuation is qualified. The first preset value is not a fixed value, and the specific numerical range can be adjusted at any time according to different working modes and working environments.
In some embodiments, the debugging of the output power back-off comprises the steps of:
when the transmitter is in a data chain mode or an identification mode and after the field programmable gate array FPGA obtains frequency information, different attenuation amounts are configured for each frequency point in an operating frequency band and are transmitted to a program-controlled attenuator, so that the difference value between the back-off amounts of the frequency points and the standard back-off amounts is within a second preset value.
When the transmitter is in data-chain, identification mode, the port output power may require back-off usage, i.e., a consistent amount of output reduction, e.g., 20db±1dB back-off, throughout the operating frequency band. This is typically achieved by configuring the attenuation of the programmable attenuator to reduce the input to the final stage amplifier. Because the gain of the final-stage amplifier on the radio-frequency small signal shows larger difference in the whole frequency band, if frequency point information is not considered, the program-controlled attenuator is given to any frequency point with the same attenuation configuration, so that the backspacing quantity of some frequency points is unqualified and exceeds the scope of backspacing error under a certain required backspacing gear. The difference value between the back-off amount of each frequency point and the standard back-off amount is in a second preset value, and the back-off amount under a certain back-off gear can be adjusted to be qualified in the whole working frequency band. The second preset value is not a fixed value, and the specific numerical range can be adjusted at any time according to different working modes and working environments.
In some embodiments, the debugging of the output waveform includes the steps of:
storing a plurality of grid voltages in a data memory, wherein each grid voltage corresponds to different frequency information; when the transmitter is in the DME working mode or the TACAN working mode and after the field programmable gate array FPGA obtains the frequency information, the grid voltage corresponding to the frequency information is transmitted to the driving amplifier and the final-stage amplifier, so that the difference value between the output waveform of each frequency point in the working frequency band and the standard output waveform is within a third preset value.
Most of the power amplifiers in the existing transmitter are GaN power amplifiers with high output power and high working efficiency, and proper static working points (namely, negative grid voltage Vg and positive drain voltage Vd are added) are required to be set before small signal power amplification is realized, and the amplifiers are biased in different states (such as class AB or class C) by different grid voltage values. The output waveform of the amplifier is closely related to the frequency information again at the same gate voltage, i.e. the same bias state. When the transmitter is in DME and TACAN working modes, the requirements on various indexes (pulse width, pulse rising/falling edge and the like) of the output pulse waveform are harsh, if frequency point information is not considered, a fixed grid voltage is given to the amplifier for any frequency point, so that the amplifier works under the same bias condition, and the waveform indexes of some frequency points can not meet the requirements. The difference value between the output waveform of each frequency point in the working frequency band and the standard output waveform is within a third preset value, so that the output waveform index meets the requirement in the full frequency band. The third preset value is not a fixed value, and the specific numerical range can be adjusted at any time according to different working modes and working environments.
A second aspect of the invention provides: an excitation signal-based tunable transmitter for implementing any one of the excitation signal-based tuning methods described above, comprising:
the digital board is connected with the radio frequency amplifying circuit and the power supply circuit; the digital board includes: the Field Programmable Gate Array (FPGA), a data memory, a configuration memory, a digital-to-analog converter (DAC) and an Amplifier (AMP); the radio frequency amplifying circuit includes: the power divider comprises a first power divider, a second power divider, a driving amplifier, a program-controlled attenuator, a final-stage amplifier, a circulator, a filter, a detector, a frequency divider, a first comparator and a second comparator; the first power divider is connected with the second power divider and the driving amplifier; the driving amplifier is connected with the program-controlled attenuator; the program-controlled attenuator is connected with the final-stage amplifier; the final amplifier is connected with the circulator; the circulator is connected with a filter; the second power divider is connected with the detector and the frequency divider; the detector is connected with the first comparator; the frequency divider is connected with the second comparator; the first comparator and the second comparator are connected with a field programmable gate array FPGA; the field programmable gate array FPGA is connected with the program-controlled attenuator, the data memory, the configuration memory, the power circuit, the DAC digital-to-analog converter and the AMP amplifier, and is used for outputting an attenuation control signal to the program-controlled attenuator and outputting a power amplifier source control signal to the power circuit; the AMP amplifier is connected with the driving amplifier and the final-stage amplifier, and is used for outputting the grid voltage of the driving amplifier to the driving amplifier and outputting the grid voltage of the final-stage amplifier to the final-stage amplifier; the power circuit is connected with the driving amplifier and the final-stage amplifier and is used for outputting the drain voltage of the driving amplifier to the driving amplifier and outputting the drain voltage of the final-stage amplifier to the final-stage amplifier.
In some embodiments, the digital board further comprises an isolation driving chip, and the field programmable gate array FPGA is connected with the RS485 serial communication interface and the waveform debugging interface through the isolation driving chip, and receives or transmits the RS485 level discrete control signal.
To sum up, in order to make the output power fluctuation, power control, transmission waveform, etc. of the transmitter meet the use requirements, it is necessary to determine the frequency information of the current transmission signal. When the transmitter works in each mode, the excitation signal is sent to the FPGA for detection after power division and frequency division, and after the FPGA recognizes the current frequency information, the FPGA is combined with the current mode information to call the power amplification grid voltage and attenuation control code stored in Flash in advance to compensate the transmitting link, so that the index of the transmitting link meets the requirement. The circuit is based on an excitation signal frequency detection means, temperature information can be added to establish a ternary function relation of grid voltage and attenuation control codes on frequency point information, mode information and temperature information, corresponding data are written in advance, stored data are read immediately after the frequency information is detected, amplifier bias setting and program-controlled attenuator attenuation compensation are completed, and output power, emission waveforms (including pulse width, pulse rising edge, pulse falling edge, pulse top unevenness and pulse sequence unevenness) in a full-temperature section and a full-frequency band, power fluctuation and power rollback in an operating frequency band are guaranteed to meet index requirements. In practical application, the frequency and the temperature can be specifically segmented according to the use requirement and the hardware characteristic of the amplifier, for example, the frequency is divided into a low section, a middle section and a high section, and the temperature is divided into 3 sections or 5 sections according to the situation.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (7)
1. A debugging method based on an excitation signal is characterized by comprising the following steps of: the method comprises the following steps:
the transmitter inputs an excitation signal to the first power divider to obtain a first signal and a second signal; inputting the second signal to a second power divider to obtain a third signal and a fourth signal; inputting a third signal to a detector to obtain a detection signal, and obtaining a first comparison signal by the detection signal through a first comparator and inputting the first comparison signal to a Field Programmable Gate Array (FPGA); the fourth signal is input into a frequency divider to obtain a frequency division signal, the frequency division signal passes through a second comparator to obtain a second comparison signal, the second comparison signal is input into a field programmable gate array FPGA, the frequency division signal is a sine signal, and the second comparison signal is an LVTTL signal; the field programmable gate array FPGA samples the second comparison signal to obtain frequency information of the excitation signal; debugging the output power, the output power back-off and the output waveform of the first signal according to the frequency information;
the first power divider inputs a first signal to the driving amplifier, then enters the final-stage amplifier through the program-controlled attenuator, and finally passes through the circulator and the filter to be output; the output waveforms are debugged in the driver amplifier and the final amplifier, and the output power back-off are debugged in the program-controlled attenuator.
2. The excitation signal based debugging method of claim 1, wherein: the frequency information is obtained by the steps of:
recording frequency information as fin and MHz; the internal clock of the field programmable gate array FPGA is fs, and the unit is MHz; and (3) performing X frequency division on the fourth signal, wherein the period of the second comparison signal is X/fin, the field programmable gate array FPGA uses the second comparison signal and the internal clock fs as counting trigger signals, the counting of N periods is performed, and the counting length K of the internal clock fs is obtained when the counting is stopped, so that the following steps are obtained:
(X/fin) n= (1/fs) K, where fin= (X N/K) fs; the frequency information of the excitation signal can be obtained according to the counting length K of the internal clock fs when the counting is stopped.
3. The excitation signal based debugging method of claim 1, wherein: the debugging of the output power comprises the following steps:
storing a plurality of attenuation values in a data memory, wherein each attenuation value corresponds to different frequency information; the frequency point of the lowest output power of the final amplifier in the working frequency band is recorded as P0, and the attenuation value of P0 is written as 0dB in a data memory; after the field programmable gate array FPGA obtains the frequency information, the attenuation value corresponding to the frequency information is transmitted to the program-controlled attenuator for reducing the input of the final-stage amplifier, so that the difference value between the output power of the final-stage amplifier at each frequency point and the output power of P0 is within a first preset value.
4. The excitation signal based debugging method of claim 1, wherein: the debugging of the output power back-off comprises the steps of:
when the transmitter is in a data chain mode or an identification mode and after the field programmable gate array FPGA obtains frequency information, different attenuation amounts are configured for each frequency point in an operating frequency band and are transmitted to a program-controlled attenuator, so that the difference value between the back-off amounts of the frequency points and the standard back-off amounts is within a second preset value.
5. The excitation signal based debugging method of claim 1, wherein: the debugging of the output waveform comprises the following steps:
storing a plurality of grid voltages in a data memory, wherein each grid voltage corresponds to different frequency information; when the transmitter is in the DME working mode or the TACAN working mode and after the field programmable gate array FPGA obtains the frequency information, the grid voltage corresponding to the frequency information is transmitted to the driving amplifier and the final-stage amplifier, so that the difference value between the output waveform of each frequency point in the working frequency band and the standard output waveform is within a third preset value.
6. An excitation signal based tunable transmitter, characterized by: a method for implementing stimulus signal-based debugging according to any one of claims 1-5, comprising:
the digital board is connected with the radio frequency amplifying circuit and the power supply circuit; the digital board includes: the Field Programmable Gate Array (FPGA), a data memory, a configuration memory, a digital-to-analog converter (DAC) and an Amplifier (AMP); the radio frequency amplifying circuit includes: the power divider comprises a first power divider, a second power divider, a driving amplifier, a program-controlled attenuator, a final-stage amplifier, a circulator, a filter, a detector, a frequency divider, a first comparator and a second comparator; the first power divider is connected with the second power divider and the driving amplifier; the driving amplifier is connected with the program-controlled attenuator; the program-controlled attenuator is connected with the final-stage amplifier; the final amplifier is connected with the circulator; the circulator is connected with a filter; the second power divider is connected with the detector and the frequency divider; the detector is connected with the first comparator; the frequency divider is connected with the second comparator; the first comparator and the second comparator are connected with a field programmable gate array FPGA; the field programmable gate array FPGA is connected with the program-controlled attenuator, the data memory, the configuration memory, the power circuit, the DAC digital-to-analog converter and the AMP amplifier, and is used for outputting an attenuation control signal to the program-controlled attenuator and outputting a power amplifier source control signal to the power circuit; the AMP amplifier is connected with the driving amplifier and the final-stage amplifier, and is used for outputting the grid voltage of the driving amplifier to the driving amplifier and outputting the grid voltage of the final-stage amplifier to the final-stage amplifier; the power circuit is connected with the driving amplifier and the final-stage amplifier and is used for outputting the drain voltage of the driving amplifier to the driving amplifier and outputting the drain voltage of the final-stage amplifier to the final-stage amplifier.
7. The excitation signal based tunable transmitter of claim 6, wherein: the digital board also comprises an isolation driving chip, and the field programmable gate array FPGA is connected with the RS485 serial communication interface and the waveform debugging interface through the isolation driving chip and receives or transmits RS485 level discrete control signals.
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