CN117894844A - Semiconductor device terminal structure based on multistage groove - Google Patents
Semiconductor device terminal structure based on multistage groove Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
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- 238000004088 simulation Methods 0.000 description 31
- 230000005684 electric field Effects 0.000 description 27
- 238000009826 distribution Methods 0.000 description 14
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
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- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention provides a semiconductor device terminal structure based on a multistage groove, and belongs to the technical field of semiconductor devices. The semiconductor device terminal structure comprises a substrate, a drift region positioned on the substrate, a cathode positioned on the back surface of the substrate and an anode; the drift region includes a main junction region and a junction termination region adjacent to the main junction region; the main junction region comprises a first doped region; the junction terminal region comprises at least one third doped region connected with the first doped region and at least one multilevel groove with a step structure; the outer wall of the multistage groove is provided with a second doped region, and the inside of the multistage groove is filled with a dielectric layer; the anode is electrically connected with the first doped region and the third doped region. The doping types of the substrate and the drift region are the same; the doping types of the second doping region, the third doping region and the first doping region are the same and opposite to the doping type of the substrate. The terminal structure of the semiconductor device can realize charge balance between the main junction region and the terminal region and improve the breakdown voltage of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor device terminal structure based on multistage grooves.
Background
In a blocking state, a metal-oxide-semiconductor field effect transistor (MOSFET) mainly bears a voltage through a depletion region formed by a PN junction under reverse bias, and according to poisson's equation, a peak value of electric field intensity in the depletion region is located near the PN junction, and when the peak value of electric field intensity reaches a critical breakdown electric field intensity of a semiconductor material, the device is broken down. The breakdown voltage of the device is determined only by the doping concentration and the thickness of the substrate or epitaxial layer, without considering the effect of junction termination. However, in an actual semiconductor device, because the size of the device is limited, the PN junction is discontinuous at the edge of the device, so that curvature exists at the edge and four corners of the PN junction, and under the effect of curvature effect, the electric field on the surface of the device is more concentrated, so that the blocking performance of the device is seriously degraded, and the breakdown voltage is far lower than that of an ideal situation.
Therefore, in the actual manufacturing process of the MOSFET device, in order to alleviate the problem that the blocking capability of the device is reduced due to the fact that the edges and four corners of the PN junction are broken down in advance due to the curvature effect, a junction terminal (terminal) structure is often formed around the PN junction (main junction), and the introduced junction terminal structure can disperse the electric field originally gathered at the edges of the main junction, so that the electric field strength at the edges of the main junction is reduced, and the breakdown voltage of the device is improved. However, for SiC materials, due to the extremely low diffusion coefficient of impurities in the SiC materials, the doping of the SiC materials tends to form a PN shallow junction by high-temperature ion implantation, which results in a smaller radius of curvature of the PN junction of the SiC power device, easier concentration of an electric field, and further reduction of blocking capability of the device and protection capability of junction terminals. Further, for the SiC superjunction device, the formed P-pillar structure goes deep into the drift region of the device, the electric field is concentrated deep into the drift region, while the conventional terminal structure is limited by the structural design and the depth of ion implantation in SiC, so that the problem of the electric field near the surface of the drift region can only be relieved, and the PN junction deep into the drift region cannot be protected. Therefore, it is necessary to develop a new junction termination structure to alleviate the problem of electric field strength concentration of a PN junction (main junction) represented by a superjunction or a structure in which the PN junction (main junction) goes deep into a drift region and to solve the problem of charge imbalance between the main junction region and the termination region.
Disclosure of Invention
In order to solve the problems, the invention provides a semiconductor device junction termination structure based on a multi-level trench. The semiconductor device junction terminal structure can reduce the electric field at the edge of the main junction region in the depth of the drift region, ensure charge balance between the main junction region and the terminal region, and improve terminal efficiency.
Specifically, the invention adopts the following technical scheme:
a semiconductor device terminal structure based on multistage grooves comprises a substrate, a drift region, a cathode and an anode, wherein the drift region is arranged on the substrate, the cathode is arranged on one side of the substrate away from the drift region, and the anode is arranged on the other side of the substrate; the drift region includes a main junction region and a junction termination region adjacent to the main junction region; the main junction region comprises a first doped region; the junction termination region comprises at least one third doped region and at least one multi-level trench having a stepped structure; the third doped region is connected with the first doped region, and the multistage groove is positioned at one side of the third doped region far away from the first doped region; the number n of the multistage grooves is an integer more than or equal to 2; the multilevel trenches extend from a side surface of the drift region facing away from the substrate in a direction of the substrate; the outer wall of the multistage groove is provided with a second doped region; a dielectric layer is filled in the multistage groove; at least one part of the anode is positioned on the surface of the first doped region on the side away from the substrate and extends to the surface of the third doped region on the side away from the substrate; the doping types of the substrate and the drift region are the same; the doping types of the second doping region, the third doping region and the first doping region are the same, and are opposite to the doping type of the drift region.
In some embodiments, the dielectric layer is an insulating dielectric layer extending from a surface of the drift region on a side facing away from the substrate to an interior of the multi-level trench; the anode extends from the surface of the third doped region, which is away from the substrate, to the surface of the insulating medium layer, which is away from the drift region, and a field plate is formed on the surface of the insulating medium layer.
In some embodiments, in the direction from the drift region to the substrate, a junction termination extension structure formed by at least one fourth doped region is disposed on a side of the multilevel trench away from the third doped region, wherein the fourth doped region is directly connected with the second doped region, and the doping type of the fourth doped region is the same as that of the second doped region.
In some embodiments, a surface of the drift region facing away from the substrate forms a slope on a side of the multi-level trench facing away from the third doped region.
In some embodiments, a side of the multilevel trench away from the third doped region is provided with a plurality of floating field limiting rings formed by a plurality of fifth doped regions, and the plurality of floating field limiting rings are sequentially arranged along the direction from the main junction region to the junction terminal region.
In some embodiments, the sidewalls of opposite sides of the multi-level trench are of a stepped structure, and a second doped region is disposed around the outer wall of the multi-level trench. In other embodiments, only one side wall of the multi-level trench is in a step structure, and a second doping region is arranged along the outer wall of the step structure to the outer wall of the bottom of the multi-level trench. In other embodiments, the multi-level trench has a stepped structure on only one side wall, and a second doped region is disposed around the outer wall of the multi-level trench.
In some embodiments, the opposing side walls of the multi-level trench are symmetrical step structures. In other embodiments, the opposing side walls of the multilevel trench are asymmetric stepped structures.
In some embodiments, the anode extends in a direction along the main junction region to the junction termination region to cover the plurality of multilevel trenches and is electrically connected with the plurality of second doped regions; or at one side close to the first doped region, the third doped region and a part of the multistage grooves are alternately arranged, the third doped region is directly connected with the second doped region, the anode is electrically connected with the third doped region between two adjacent multistage grooves, and the other part of the third doped region is in a floating state, which is far away from one side of the first doped region, of the second doped region on the outer wall of the multistage groove. In other embodiments, all of the second doped regions on the outer walls of the multi-level trench are in a floating state.
In some embodiments, the doping concentration of at least two of the first doped region, the second doped region, and the third doped region is the same.
In some embodiments, the spacing between the multilevel trenches increases gradually in a direction from the main junction region to the junction termination region. In other embodiments, the spacing between the multilevel trenches is equal along the direction of the main junction region to the junction termination region.
In some embodiments, the number of stages of each of the multilevel trenches is the same. In other embodiments, the number of steps of the multi-step trench decreases gradually in a direction from the main junction region to the junction termination region.
In some embodiments, each level step of the multi-level trench has a different width in a direction along the main junction region to the junction termination region.
In some implementations, each level of step of the multi-level trench is the same height in a direction along the substrate to the drift region.
In some embodiments, the depth of the second doped region is the same as the depth of the first doped region along the drift region in the direction to the substrate. In other embodiments, the depth of the second doped region is less than the depth of the first doped region along the drift region in the direction to the substrate. In other embodiments, the depth of the second doped region is greater than the depth of the first doped region along the drift region in the direction to the substrate.
In some embodiments, the dielectric layer is a semiconductor layer having a doping type that is the same as a doping type of the first doped region.
The invention has the following beneficial effects: according to the semiconductor device terminal structure, at least one groove with a multi-stage step structure is arranged in the junction terminal region, and the second doped region is arranged on the side wall of the groove, so that when the device is in a reverse blocking state, the second doped region in the deep part of the drift region can ensure charge balance between the main junction region and the junction terminal region in the direction from the main junction region to the junction terminal region. The dielectric layers in the multistage grooves can disperse and bear an electric field, so that the problem that the PN junction at the edge of the main junction region is broken down in advance is solved, and the breakdown voltage of the device is improved.
Drawings
Fig. 1 is a schematic diagram of a terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 8 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 9 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 10 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 11 is a schematic diagram of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 12 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 13 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 14 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 15 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 16 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 17 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 18 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
fig. 19 is a schematic view of another terminal structure of a semiconductor device according to an embodiment of the present invention;
FIG. 20 is a schematic diagram of a simulation structure I;
FIG. 21 is a schematic diagram of a doping concentration distribution of a simulation structure I;
FIG. 22 is a schematic diagram showing the electric field intensity distribution of a simulation structure at the time of breakdown;
FIG. 23 is a schematic diagram of a second simulation structure;
FIG. 24 is a schematic diagram showing the doping concentration distribution of a second simulation structure;
FIG. 25 is a schematic diagram showing the electric field intensity distribution of the second simulation structure at the time of breakdown;
FIG. 26 is a schematic diagram of a third simulation structure;
FIG. 27 is a schematic illustration of the doping concentration profile of a third simulation structure;
FIG. 28 is a schematic diagram of the electric field intensity distribution of the third simulation structure at the time of breakdown;
FIG. 29 is a schematic diagram of a fourth simulation structure;
FIG. 30 is a schematic diagram of the doping concentration distribution of the fourth simulation structure;
FIG. 31 is a schematic diagram showing the electric field intensity distribution of the fourth simulation structure at the time of breakdown;
fig. 32 is a graph showing comparison of breakdown characteristics of simulation structures one, two, three and four.
In the figure: 101. a substrate; 102. a drift region; 103. a cathode; 104. an anode; 105. a first doped region; 106. a third doped region; 107. a multi-level trench; 108. a second doped region; 109. a dielectric layer; 110. a field plate; 111. a fourth doped region; 112. an inclined plane; 113. a fifth doped region; A. a main junction region; B. and a junction termination region.
Detailed Description
The following description sets forth a clear and complete description of the present invention, in connection with embodiments, so that those skilled in the art will fully understand the present invention. It will be apparent that the described embodiments are only some, but not all, of the preferred embodiments of the invention. Any equivalent alterations or substitutions for the following embodiments without any inventive effort by those of ordinary skill in the art are intended to be within the scope of the present invention.
Directional terms referred to herein, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., are based on the orientation or positional relationship in the drawings of the specification or the orientation or positional relationship in which the product of the present invention is conventionally put in use, and are merely for convenience of description and understanding of the structure of the product of the present invention, and thus the directional terms should not be construed as limiting the present invention. In the present invention, unless explicitly defined otherwise, the expression "on", "over" and "upper surface" of a second feature means that the first feature and the second feature may be in direct contact or in indirect contact through an intermediate medium; it may be that the first feature is directly above or obliquely above the second feature, or simply that the first feature is higher in level than the second feature. The expressions "under", "beneath" and "lower surface" of a first feature mean that the first feature and the second feature may be in direct contact or indirect contact via an intermediary; it may be that the first feature is directly below or obliquely below the second feature, or simply that the first feature is level less than the second feature. Ordinal numbers such as "first," "second," etc., used in this disclosure are used for descriptive purposes only to distinguish between similar objects and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
In order to better understand the present invention, specific embodiments of the semiconductor device termination structure of the present invention are described in detail below with reference to fig. 1-19. In the figure, A is a main junction region and also has the function of a transition region.
Fig. 1 is a schematic diagram of a semiconductor device terminal structure based on a multi-level trench according to an embodiment of the present invention. The semiconductor device termination structure includes a substrate 101, a drift region 102 on the substrate 101, a cathode 103, and an anode 104. The cathode 103 is located on the side of the substrate 101 facing away from the drift region 102, i.e. the cathode 103 is located on the bottom surface of the substrate 101. The drift region 102 includes a main junction region a and a terminal region B adjacent to the main junction region a. The main junction region a includes a first doped region 105. The junction termination region B includes a third doped region 106 and a plurality of multilevel trenches 107. The third doped region 106 is directly connected to the first doped region 105. The multilevel trench 107 is located on a side of the third doped region 106 remote from the first doped region 105. The opposite side walls of the multi-level trench 107 have symmetrical step structures, and the number n of the trench levels is an integer greater than or equal to 2 (for example, n=3). The multi-level trench 107 extends from a side surface of the drift region 102 facing away from the substrate 101 towards the substrate 101, and each level of sub-trench gradually decreases in size in a direction along the main junction region a to the junction termination region B in a direction along the drift region 102 to the substrate 101. I.e. the multi-level trenches 107 extend from the upper surface of the drift region 102 towards the inside of the drift region 102, with openings in the upper surface of the drift region 102, and each level of sub-trenches gradually decreases in size from its opening to its bottom. A second doped region 108 is provided around the outer wall of the multilevel trench 107, the second doped region 108 being directly connected to the third doped region 106. The second doped region 108 may be formed by means of homoepitaxy after etching the multilevel trenches. The multilevel trench 107 is filled with a dielectric layer 109, and the dielectric layer 109 is an insulating dielectric layer. The anode 104 is located on the side of the main junction region a facing away from the substrate 101 and extends to the side of the third doped region 106 facing away from the substrate 101. I.e., the anode 104 is located on the upper surfaces of the first doped region 105 and the third doped region 106 such that the third doped region 106 is electrically connected to the anode 104, while also electrically connecting the second doped region 108 directly connected to the third doped region 106 to the anode 104. The doping type of the substrate 101 is the same as the doping type of the drift region 102, the doping type of the second and third doped regions 108, 106 is the same as the doping type of the first doped region 105, but the doping type of the first doped region 105 is opposite to the doping type of the substrate 101 (or drift region 102). That is, when the substrate 101 is doped n-type, the drift region 102 is doped n-type, and the first doped region 105, the second doped region 108, and the third doped region 106 are doped p-type, so that the pn junction formed by the first doped region 105 and the drift region 102 in the main junction region a is the main junction. When the substrate 101 is doped p-type, the drift region 102 is doped p-type, and the first doped region 105, the second doped region 108, and the third doped region 106 are doped n-type, so that the pn junction formed by the first doped region 105 and the drift region 102 in the main junction region a is the main junction.
It is understood that the number of the second doped regions 108 (or the number of the trenches 107) and the doping concentration, the spacing between the trenches 107, the dimension of each step of the trenches 107 along the direction from the main junction region a to the junction terminal region B, the dimension of each step of the trenches 107 along the drift region to the substrate, the number of steps of each trench 107, and the material of the filling medium inside the trenches 107 may be adjusted according to practical requirements.
The doping depth of the second doped region 108 may be the same as the doping depth of the first doped region 105, may be smaller than the doping depth of the first doped region 105 (as shown in fig. 2), or may be larger than the doping depth of the first doped region 105 (as shown in fig. 3) in the direction along the drift region 102 to the substrate 101. The doping concentrations of the first doped region 105, the second doped region 108, and the third doped region 106 may be completely different as shown in fig. 1, may be completely the same as shown in fig. 4, or may be the same as each other. The number of steps of each multi-step trench 107 may be the same as shown in fig. 1 or may be gradually reduced as shown in fig. 5 in a direction along the main junction region a to the junction terminal region B. The multi-level trench 107 may be provided with symmetrical step structures on opposite side walls as shown in fig. 1, or may be provided with asymmetrical step structures on opposite side walls as shown in fig. 6 and 7, and the second doped region 108 is disposed around the outer wall of the multi-level trench 107; it is also possible that a step structure is provided on only one side wall as shown in fig. 8 and 9, and the second doping region 108 is provided around the outer wall of the multi-level trench 107; it is also possible to provide a step structure on the sidewall of only one side as shown in fig. 10, and the second doping region 108 is provided along the outer wall of the multi-level trench 107 having the step structure to the bottom thereof and around the outer wall of the first-level sub-trench at the opening of the multi-level trench 107.
In other embodiments, as shown in fig. 11, the anode 104 continues to extend and cover the plurality of multilevel trenches 107 in a direction along the main junction region a to the junction termination region B, such that the plurality of second doped regions 108 are in direct contact with the anode.
As shown in fig. 12, in other embodiments, the number of the third doped regions 106 may be plural, and in a direction along the main junction region a to the junction termination region B, the third doped regions 106 are alternately arranged with a portion (e.g., two) of the multi-level trenches 107 on a side close to the first doped region 105 and the third doped regions 106 are directly connected with the second doped regions 108 of the sidewalls of the multi-level trenches 107, and another portion(s) of the multi-level trench(s) 107 on a side away from the third doped region 106 are in a floating state. The anode 104 is in direct contact with the third doped region 106 between two adjacent multilevel trenches 107 such that the third doped region 106 and the plurality of second doped regions 108 are electrically connected to the anode 104.
In other embodiments, as shown in fig. 13, all of the second doped regions 108 are in a floating state, i.e., the second doped region 108 nearest to the third doped region 106 is not electrically connected to either the third doped region 106 or the anode 104, while a plurality of multi-level trenches 107 are spaced apart in the drift region 102.
In other embodiments, as shown in fig. 14, the dielectric layer 109 filled in the multi-level trench 107 is a semiconductor layer having the same doping type as the first doping region 105. That is, when the first doped region 105 is p-type doped, the dielectric layer 109 is a p-type doped semiconductor layer; when the first doped region 105 is n-doped, the dielectric layer 109 is an n-doped semiconductor layer. When the dielectric layer 109 is a semiconductor layer, the preparation method of the semiconductor terminal structure of the present invention may have various options, for example, may be implemented by etching a trench-epi filling, multiple epi-ion implantation, etc., and the preparation of the terminal structure may be consistent with the process route of the cellular region, so as to reduce the cost.
Further, as shown in fig. 15, in other embodiments, the dielectric layer 109 is an insulating dielectric layer. In the junction termination region B, a dielectric layer 109 extends from the drift region 102 on a side surface facing away from the substrate 101 into the multilevel trench 107. The anode 104 extends from the main junction region a to the upper surface of the dielectric layer 109, and a field plate 110 is formed on the surface of the dielectric layer 109 on the side facing away from the drift region 102.
Further, as shown in fig. 16, in other embodiments, a junction termination extension structure formed by a fourth doped region 111 is disposed on a side of the multi-level trench 107 remote from the third doped region 106. The fourth doped region 111 is directly connected to the second doped region 108, and has the same doping type as the first doped region 105, the second doped region 108 and the third doped region 106, and a doping concentration lower than that of the first doped region 105. In other embodiments, as shown in fig. 17, a junction termination extension formed by a plurality of fourth doped regions 111 is provided on a side of the multi-level trench 107 remote from the third doped region 106. The sidewall of the multilevel trench 107 far from the third doped region 106 is of a step structure, a plurality of fourth doped regions 111 are arranged along the direction from the drift region 102 to the substrate 101, and each fourth doped region 111 is directly contacted with the second doped region 108 on the outer wall of the step structure.
Further, as shown in fig. 18, in some other embodiments, in the direction from the substrate 101 to the drift region 102, the height of the opening of the multi-level trench 107 is greater than the height of the upper surface of the drift region 102 on the side of the multi-level trench 107 away from the third doped region 106, and the surface of the drift region 102 on the side facing away from the substrate 101 forms a slope 112 on the side of the multi-level trench 107 away from the third doped region 106. An insulating dielectric layer is covered from the upper surface of the multilevel trench 107 along the inclined plane 112 to the upper surface of the drift region 102 on the side of the multilevel trench 107 remote from the third doped region 106.
Further, as shown in fig. 19, in other embodiments, on a side of the multilevel trench 107 away from the third doped region 106, a plurality of floating field limiting rings formed by a plurality of fifth doped regions 113 are sequentially arranged along the direction from the main junction region a to the junction termination region B. The doping type of the fifth doped region 113 is the same as the type of the first doped region 105.
It will be appreciated that in other embodiments, the number of floating field limiter rings formed by the fifth doped region 113 may be adjusted as desired. The width of each fifth doped region 113 may be the same or different in the direction along the main junction region a to the junction termination region B; the spacing between two adjacent fifth doped regions 113 may be equal or unequal; the concentration of each fifth doped region 113 may be the same or different.
In the present invention, when the substrate 101, the drift region 102, and the dielectric layer 109 are semiconductor layers, the semiconductor material used is any one of silicon carbide, silicon, gallium nitride, gallium oxide, aluminum nitride, diamond, and indium phosphide.
The performance of the terminal structure of the semiconductor device provided by the invention is verified through Silvaco simulation software. As shown in fig. 20, the first simulation structure is an ideal multi-level trench half super-junction cell structure, fig. 21 is a schematic diagram of doping concentration distribution of the first simulation structure, and fig. 22 is a schematic diagram of electric field intensity distribution of the first simulation structure at breakdown time. As can be seen from fig. 22, the breakdown voltage of the simulation structure one is 1915V; in this structure, the peak of the electric field intensity at the time of breakdown is mainly at the bottom of the first doped region, deep into the drift region.
As shown in fig. 23, the second simulation structure is a structure in which the terminal structure is not added to the edge portion of the multilevel trench half super-junction cell, fig. 24 is a schematic diagram of doping concentration distribution of the second simulation structure, and fig. 25 is a schematic diagram of electric field intensity distribution of the second simulation structure at breakdown time. As can be seen from fig. 25, the breakdown voltage of the simulation structure two is 1308V. When no terminal structure is provided, the electric field intensity is concentrated in the oxide layer at the edge of the cell, and the reason for this phenomenon is that: the curvature effect is relieved without a terminal structure, a strong electric field is concentrated at the edge of a cell by the curvature effect, the first doped region is completely consumed, a transverse PN junction formed by the first doped region and the drift region is penetrated, and the strong electric field is directly applied to an insulating medium in the multistage groove.
As shown in FIG. 26, the third simulation structure is a terminal structure with JTE+ field limiting rings arranged at the edges of the half super-junction cells, and specifically comprises a JTE with a length of 3 μm and 9 floating field limiting rings. Fig. 27 is a schematic diagram of the doping concentration profile of the third simulation structure. Fig. 28 is a schematic diagram of electric field intensity distribution of the third simulation structure at the time of breakdown, and as can be seen from the figure, the breakdown voltage is 1395V, and the terminal efficiency is only 73%. This means that the common junction termination structure hardly relieves the electric field accumulated at the cell edge, the lateral PN junction is penetrated, and a strong electric field is applied to the insulating medium.
As shown in fig. 29, the simulation structure four is to set a terminal structure provided in the present invention at the edge of the half super-junction cell, and the terminal structure has 3 multilevel trenches therein. Fig. 30 is a schematic diagram of a doping concentration distribution of a fourth simulation structure. Fig. 31 is a schematic diagram of electric field intensity distribution of a simulation structure four at breakdown time, and as can be seen from the figure, the breakdown voltage of the structure is 1875V, and the terminal efficiency reaches 98%. This illustrates that the termination structure provided in the present invention not only can achieve charge balance between the main junction region (or transition region) and the junction termination region through the second doped region on the outer wall of the multi-level trench, but also can disperse and bear the electric field through the dielectric layer within the multi-level trench.
Fig. 32 shows breakdown characteristics of the first, second, third and fourth simulation structures, and it can be seen from the graph that the breakdown characteristic of the fourth simulation structure is closest to the breakdown characteristic of the ideal multi-level trench half super-junction cell structure (the first simulation structure), which indicates that the efficiency of the fourth simulation structure is highest.
The foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Various modifications and alterations of this invention will occur to those skilled in the art. Any and all such simple and equivalent variations and modifications are intended to be included within the scope of this invention.
Claims (10)
1. The semiconductor device terminal structure based on the multistage groove is characterized by comprising a substrate, a drift region, a cathode and an anode, wherein the drift region is positioned on the substrate, and the cathode is positioned on one side of the substrate away from the drift region; the drift region includes a main junction region and a junction termination region adjacent to the main junction region; the main junction region comprises a first doped region; the junction termination region comprises at least one third doped region and at least one multi-level trench having a stepped structure; the third doped region is connected with the first doped region, and the multistage groove is positioned at one side of the third doped region far away from the first doped region; the number n of the multistage grooves is an integer more than or equal to 2; the multilevel trenches extend from a side surface of the drift region facing away from the substrate in a direction of the substrate; the outer wall of the multistage groove is provided with a second doped region; a dielectric layer is filled in the multistage groove; at least one part of the anode is positioned on the surface of the first doped region on the side away from the substrate and extends to the surface of the third doped region on the side away from the substrate; the doping types of the substrate and the drift region are the same; the doping types of the second doping region, the third doping region and the first doping region are the same, and are opposite to the doping type of the drift region.
2. The multi-level trench-based semiconductor device termination structure of claim 1, wherein the dielectric layer is an insulating dielectric layer extending from a surface of the drift region on a side facing away from the substrate to an interior of the multi-level trench; the anode extends from the surface of the third doped region, which is away from the substrate, to the surface of the insulating medium layer, which is away from the drift region, and a field plate is formed on the surface of the insulating medium layer.
3. The multi-level trench based semiconductor device termination structure of claim 1, wherein a side of the multi-level trench away from the third doped region is provided with a junction termination extension structure formed by at least one fourth doped region directly connected to the second doped region and having a doping type identical to a doping type of the second doped region in a direction along the drift region to the substrate.
4. The multi-level trench based semiconductor device termination structure of claim 1, wherein a surface of the drift region on a side facing away from the substrate forms a bevel on a side of the multi-level trench facing away from the third doped region.
5. The semiconductor device termination structure according to claim 1, wherein a side of the multilevel trench away from the third doped region is provided with a plurality of floating field limiting rings formed by a plurality of fifth doped regions, and the plurality of floating field limiting rings are sequentially arranged along a direction from the main junction region to the junction termination region.
6. The multi-level trench based semiconductor device termination structure of claim 1, wherein sidewalls of opposite sides of the multi-level trench are each of a stepped structure, and a second doped region is disposed around an outer wall of the multi-level trench.
7. The multi-level trench based semiconductor device termination structure of claim 1, wherein the anode extends in a direction along the main junction region to the junction termination region to cover a plurality of the multi-level trenches and is electrically connected to a plurality of the second doped regions; or at one side close to the first doping region, the third doping region and a part of the multistage trenches are alternately arranged, the third doping region is directly connected with the second doping region, the anode is electrically connected with the third doping region between two adjacent multistage trenches, and the other part of the multistage trenches far away from one side of the first doping region are in a floating state.
8. The multi-level trench based semiconductor device termination structure of claim 1, wherein doping concentrations of at least two of the first, second, and third doped regions are the same.
9. The multi-level trench based semiconductor device termination structure of claim 1, wherein a depth of the second doped region is the same as a depth of the first doped region along a direction of the drift region to the substrate.
10. The multi-level trench based semiconductor device termination structure of claim 1, wherein the dielectric layer is a semiconductor layer having a doping type that is the same as a doping type of the first doped region.
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