CN117894681A

CN117894681A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN117894681A
Application number: CN202311703487.5A
Authority: CN
Inventors: 黄禹轩; 陈豪育; 锺政庭; 蔡劲
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-12-12
Filing date: 2023-12-12
Publication date: 2024-04-16

Abstract

A method for forming a vertical gate around a transistor includes forming a stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and three layers on the second layer. The first layer and the third layer have substantially the same composition and are selectively etchable relative to the second layer. The first and second layers may be selectively removed and replaced with internal spacers. The second layer may be selectively removed and replaced with a gate electrode. The embodiment of the application also discloses a semiconductor device and a manufacturing method thereof.

Description

Semiconductor device and method for manufacturing the same

Technical Field

Embodiments of the present application relate to a semiconductor device and a method of manufacturing the same.

Background

The semiconductor integrated circuit industry has experienced an exponential growth. Technological advances in integrated circuit materials and design have resulted in a generation of integrated circuits that are each smaller and more complex than the previous generation. During the development of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. Such a scaling down process generally provides benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing integrated circuits.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a method of manufacturing a semiconductor device, including: forming a trench adjacent to a channel region of the first vertical transistor in the stack of semiconductor layers over a lower source/drain region of the first vertical transistor; exposing portions of the channel region by selectively removing the first layer in the stack relative to the second layer of the stack via the trench using a first etching process; forming an upper inner spacer in contact with the channel region to replace the first layer; removing the second layer of the stack via the trench using a second etching process; forming a gate metal in place of the second layer; and forming upper source/drain regions of the first vertical transistor on the channel region and the upper inner spacers.

According to another aspect of an embodiment of the present application, there is provided a method of manufacturing a semiconductor device, including: forming a first channel region of the first vertical transistor, the first channel region extending vertically from a first lower source/drain region of the first vertical transistor; forming a first lower inner spacer in contact with the first channel region; forming a first upper inner spacer above the first lower inner spacer and in contact with the first channel region in the same deposition process as the first lower inner spacer; after forming the first lower inner spacer and the first upper inner spacer, forming a gate dielectric on top of the first lower inner spacer, on sidewalls of the first channel region between the first upper inner spacer and the first lower inner spacer, and on bottom of the first upper inner spacer; depositing a gate metal between the first upper and lower inner spacers; and forming upper source/drain regions of the first vertical transistor in contact with the top of the first channel region and the top of the first upper inner spacer.

According to still another aspect of an embodiment of the present application, there is provided a semiconductor device including a first vertical transistor. The first vertical transistor includes: a first lower source/drain region; a first channel region extending vertically from the first lower source/drain region; a first lower internal spacer in contact with the first channel region and the first lower source/drain region; and a first gate electrode positioned on the first lower inner spacer and laterally surrounding the first channel region. The semiconductor device further includes: shallow trench isolation regions in contact with the first lower source/drain regions; and an interlayer dielectric layer extending vertically from the shallow trench isolation region and contacting sidewalls of the first lower internal spacer and sidewalls of the first gate electrode.

Drawings

The various aspects of the disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1Z, 2A-2F are cross-sectional and top views of an integrated circuit at different stages of processing according to some embodiments.

Fig. 3A-3B, 4-15 include cross-sectional and top views of an integrated circuit including variations of the integrated circuits shown in fig. 1A-1Z, 2A-2F, according to some embodiments.

Fig. 16 is a flow chart of a method for forming an integrated circuit, according to some embodiments.

Fig. 17 is a flow chart of a method for forming an integrated circuit, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

Terms indicating relative degrees, such as "about," "substantially," and the like, should be construed as understood by one of ordinary skill in the art in view of the present specification.

The present disclosure relates generally to semiconductor devices, and more particularly to Field Effect Transistors (FETs), such as planar FETs, three-dimensional fin FETs (finfets), or nanostructured devices. Examples of nanostructure devices include full Gate (GAA) devices, nanoflake FETs (NSFETs), nanowire FETs (NWFETs), and the like. In prior art nodes, the active inter-interval spacing between nanostructure devices is typically uniform, the source/drain epitaxial structure is symmetrical, and the metal gate surrounds four sides of the nanostructure (e.g., nanoplatelets). The gate-drain capacitance ("Cgd") increases due to the larger metal gate cap (endcap) and the increased source/drain epi size.

Embodiments of the present disclosure reduce active area pitch and improve scaling of integrated circuit cell sizes. In some embodiments, vertical nanostructure transistors are formed. The vertical nanostructure transistor may include a lower source/drain region and an upper source/drain region, and a semiconductor nanostructure channel region extending vertically between the upper source/drain region and the lower source/drain region. The gate electrode laterally surrounds the semiconductor nanostructure channel region. A process for forming a vertical nanostructure transistor may include forming a stack of semiconductor layers having different material concentrations such that the individual layers of the semiconductor stack may be selectively etched relative to one another. The formation of the semiconductor layer stack enables precise control and definition of the dimensions of the internal spacers, gate electrodes and other structures of the vertical nanostructure transistor. The result is a more efficient use of the integrated circuit area, simpler and more compact formation of source/drain contacts, and reduced various other damage.

The nanostructure transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, a double patterning or multiple patterning process combines lithography and a self-aligned process, allowing creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the nanostructured transistor structure.

Fig. 1A is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to one embodiment. Fig. 1B is a top view of the integrated circuit 100 of fig. 1A according to one embodiment. In the cross-sectional view of fig. 1A, the z-axis corresponds to the vertical axis, and the x-axis corresponds to the horizontal axis that is substantially orthogonal to the z-axis. In the top view of fig. 1B, the y-axis and the x-axis are mutually orthogonal transverse axes. Fig. 1B shows a cutting line a corresponding to the line along which the section of fig. 1A is taken. In the subsequent illustrations, when the cross-sectional view is juxtaposed with the top view and the cut line is not shown, the cut line may correspond to the cut line a of fig. 1B.

The integrated circuit 100 includes a substrate 102. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 102 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates may be used, such as single layer, multi-layer or gradient substrates.

Referring to fig. 1A, lower source/drain regions 104 have been formed in substrate 102. The lower source/drain regions 104 may correspond to the same semiconductor material as the substrate 102, but are doped with dopant atoms to impart N-type or P-type conductivity, as the case may be. The vertical thickness of the source/drain regions 104 may be between 5nm and 20nm, although other thicknesses may be used without departing from the scope of the present disclosure. Although fig. 1A shows the source/drain regions 104 as having rounded edges, in practice, the source/drain regions 104 may have other shapes and contours without departing from the scope of the present disclosure.

In some embodiments, the source/drain regions 104 are epitaxially grown from the substrate 102. In one example, the substrate 102 is silicon and the source/drain regions 104 are silicon germanium. In some embodiments, the source/drain regions 104 comprise between 40% and 50% germanium, although other concentrations of germanium may be used without departing from the scope of the present disclosure. The source/drain regions 104 may be doped in-situ during the epitaxial growth process that forms the source/drain regions.

In one embodiment, the source/drain regions 104 are formed using a dopant implantation process. A dopant implantation process may implant selected dopant species into the upper region of the substrate 102 to form the source/drain regions 104. In examples where the source/drain regions are N-type source/drain regions, the dopant implantation process may implant phosphorus or other types of N-type dopant species. In examples where source/drain region 104 is a P-type source/drain region, the dopant implantation process may implant boron or other types of P-type dopant species. The source/drain region 104 is described as a "lower" source/drain region because the upper source/drain region will eventually form over the lower source/drain region 104, with the semiconductor nanostructure channel region extending between the source/drain region 104 and the upper source/drain region. The term "source/drain region" may correspond to a source region or a drain region of a transistor. Typically, a transistor may include a source region and a drain region. The source and drain regions are similar in the configuration of the corresponding circuit and determine whether a region is a source or drain region. Thus, the term source/drain region is used because this region may be a source region or a drain region.

The top view of fig. 1B shows that the second lower source/drain regions 106 have been formed. The second source/drain region 106 may have an opposite conductivity type to the source/drain region 104. For example, if the source/drain region 104 is a P-type source/drain region, the source/source region 106 will be an N-type source/drain region, and vice versa. The source/drain regions 106 may be formed in the same manner as described with respect to the source/drain regions 104. In the case of dopant implantation, a mask may be formed and patterned to achieve the separate doping processes of the source/drain regions 104 and 106. For example, a first mask may cover the regions of the source/drain regions 106 while implanting dopant species to form the source/drain regions 104. A second mask may then cover the regions of the source/drain regions 104 while implanting dopant species to form the source/drain regions 106. Various processes may be utilized to form source/drain regions 104 and 106 without departing from the scope of the present disclosure.

As will be explained in more detail below, the source/drain regions 104 will correspond to lower source/drain regions 104 for a plurality of vertical nanostructure transistors, wherein current will flow vertically through the semiconductor nanostructure channel region between the lower source/drain regions 104 and the upper source/drain regions, as will be further described below.

Fig. 1C is a cross-sectional view of an integrated circuit 100 according to some embodiments. In fig. 1C, a semiconductor layer stack 108 has been formed on the substrate 102. Specifically, the semiconductor layer stack 108 has been formed on the top surface of the source/drain regions 104. The semiconductor layer stack 108 includes a plurality of semiconductor material layers. As will be explained in more detail below, the formation of the semiconductor layer stack 108 enables precise control of the shape and size of the structure of the vertical nanostructure transistor to be formed. In particular, the formation of semiconductor layer stack 108 may help control the shape and size of the semiconductor nanostructures corresponding to the channel regions of the nanostructure transistors. The semiconductor layer stack 108 may correspond to a lattice of semiconductor layers or a superlattice of semiconductor layers.

In some embodiments, the semiconductor layer stack 108 includes a first semiconductor layer 110. The first semiconductor layer 110 is located directly on the source/drain region 104. The first semiconductor layer 110 may be formed from the source/drain region 104 through an epitaxial growth process. The first semiconductor layer 110 may include silicon germanium having a different germanium concentration than the source/drain regions 104 (in examples where the source/drain regions 104 include silicon germanium). For example, the source/drain regions 104 may include a germanium concentration between 40% and 50%, while the first semiconductor layer 110 may include a germanium concentration between 15% and 25%. The difference in germanium concentration between the first semiconductor layer 110 and the source/drain regions 104 may enable the first semiconductor layer to be selectively etched with respect to the source/drain regions 104. The first semiconductor layer 110 may have a thickness between 5nm and 10 nm. Other thicknesses, materials, deposition processes, and material concentrations may be used for the first semiconductor layer 110 of the semiconductor layer stack 108 without departing from the scope of the present disclosure.

In some embodiments, the semiconductor layer stack 108 includes a second semiconductor layer 112. The second semiconductor layer 112 is directly on the first semiconductor layer 110. The second semiconductor layer 112 may be formed from the first semiconductor layer 110 through an epitaxial growth process. The second semiconductor layer 112 may include silicon germanium having a different concentration of germanium than the first semiconductor layer 110 (in the example where the first semiconductor layer includes silicon germanium). For example, the second semiconductor layer 112 may have a germanium concentration between 30% and 50%. The difference in germanium concentration between the first semiconductor layer 110 and the second semiconductor layer 112 may enable the second semiconductor layer 112 to be selectively etched with respect to the first semiconductor layer 110. The second semiconductor layer 112 may have a thickness between 10nm and 15 nm. Other thicknesses, materials, deposition processes, and material concentrations may be used for the second semiconductor layer 112 of the semiconductor layer stack 108 without departing from the scope of the present disclosure.

In some embodiments, the semiconductor layer stack 108 includes a third semiconductor layer 114. The third semiconductor layer 114 is directly on the second semiconductor layer 112. The third semiconductor layer 114 may be formed from the second semiconductor layer 112 through an epitaxial growth process. The third semiconductor layer 114 may include silicon germanium having a different concentration of germanium than the second semiconductor layer 112. For example, the third semiconductor layer 114 may have the same germanium concentration (between 15% and 25%) as the first semiconductor layer 110, and may have the same thickness (between 5nm and 10 nm) as the first semiconductor layer 110. The difference in germanium concentration between the third semiconductor layer 114 and the second semiconductor layer 112 may enable the second semiconductor layer 112 to be selectively etched with respect to the third semiconductor layer 114. Other thicknesses, materials, deposition processes, and material concentrations may be used for the third semiconductor layer 114 of the semiconductor layer stack 108 without departing from the scope of the present disclosure.

In some embodiments, the semiconductor layer stack 108 includes a fourth semiconductor layer 116. The fourth semiconductor layer 116 is directly formed on the third semiconductor layer 114. In an example in which the third semiconductor layer 114 is silicon germanium, the fourth semiconductor layer 116 may include silicon. The fourth semiconductor layer 116 may be formed from the third semiconductor layer 114 through an epitaxial growth process. The fourth semiconductor layer 116 may include an intrinsic semiconductor. The fourth semiconductor layer 116 may have a thickness between 5nm and 20 nm. Other thicknesses, materials, and deposition processes may be used for the fourth semiconductor layer 116 without departing from the scope of the present disclosure.

Although fig. 1C shows a semiconductor layer stack 108 having four semiconductor layers, other configurations of semiconductor layer stack 108 may be used without departing from the scope of the present disclosure. For example, the semiconductor layer stack 108 may have a different number of layers, different materials, and different configurations without departing from the scope of the present disclosure.

Fig. 1D is a cross-sectional view of an integrated circuit 100 according to some embodiments. Fig. 1E is a top view of integrated circuit 100 at the stage of processing shown in fig. 1D. In fig. 1D, a hard mask layer 118 has been deposited over the fourth semiconductor layer 116. The hard mask layer 118 may comprise amorphous silicon, silicon nitride, siCN, siOC, siOCN, hfO ₂、ZrO₂、HfAlO、HfSiO、Al₂O₃, or other suitable materials. The hard mask layer 118 may have a thickness between 40nm and 60 nm. The hard mask layer 118 may be deposited by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or other suitable deposition process. The hard mask layer 118 may include other thicknesses, materials, and deposition processes without departing from the scope of the present disclosure.

In fig. 1D and 1E, a trench 120 has been formed in the hard mask layer 118. The trench 120 exposes selected portions of the fourth semiconductor layer 116. The trench 120 may have a width between 10nm and 80 nm. Further, the grooves 120 may have different widths from each other. For example, the right-most groove 120 has a greater width than the other grooves 120. The trench 120 may be formed using a photolithographic process that includes patterning the hard mask layer 118 according to a photolithographic mask.

Fig. 1F is a cross-sectional view of an integrated circuit 100 according to some embodiments. Fig. 1G is a top view of integrated circuit 100 at a stage of processing of fig. 1F, according to some embodiments. In fig. 1F, trench 120 has extended through the layers of semiconductor layer stack 108 to source/drain region 104. The trench 120 may extend through the semiconductor layer stack 108 by performing one or more etching processes. The etching process may include an isotropic etching process that selectively etches in a downward direction. The etching process may include a dry etch, a wet etch, or other type of etching process. The etching process etches portions of the first, second, third, and fourth semiconductor layers 110-116 below the openings in the hard mask layer 118. The etching process stops at the source/drain regions 104. Thus, the source/drain regions 104 may correspond to an etch stop layer. In some embodiments, a small portion of the source/drain regions 104 are also etched. For example, the trench 120 may extend into the source/drain region 104 to a depth between 0nm and 5 nm. In some embodiments, if the trench 120 extends into the source/drain region 104 beyond 5nm, the resistance associated with the source/drain region 104 may become too high.

The trench 120 may correspond to a channel trench. This is because the semiconductor nanostructure corresponding to the channel region of the vertical nanostructure transistor will be formed in the trench 120 in contact with the source/drain region 104.

Fig. 1H is a cross-sectional view of an integrated circuit 100 according to some embodiments. Fig. 1I is a top view of the integrated circuit 100 of fig. 1H, according to some embodiments. Semiconductor nanostructures 122 have been formed in trenches 120. The semiconductor nanostructure 122 may be formed by epitaxial growth from various exposed semiconductor layers including the source/drain regions 104 and one or more of the first, second, third, and fourth semiconductor layers 110-116 of the semiconductor layer stack 108.

Semiconductor nanostructure 122 may comprise silicon, silicon germanium, or other suitable semiconductor materials. Semiconductor nanostructure 122 may correspond to a channel region of a transistor. In particular, each semiconductor nanostructure 122 may correspond to a vertical channel region of a respective vertical nanostructure transistor.

The top of the semiconductor nanostructure 122 may be substantially flush with the top surface of the fourth semiconductor layer 116. Or the top of the semiconductor nanostructure 122 may be above or below the top surface of the fourth semiconductor layer 116. In some embodiments, the top of the semiconductor nanostructure 122 is within 2nm of the top surface of the fourth semiconductor layer 116.

Fig. 1J is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1K is a top view of integrated circuit 100 at a stage of processing of fig. 1J, according to some embodiments. In fig. 1J and 1K, a hard mask refill process is performed. Specifically, a hard mask material 124 has been deposited in the trench 120 over the semiconductor nanostructure 122. The hard mask material 124 is configured as a column of material within the hard mask 118. The hard mask material 124 is in contact with the top surface of the semiconductor nanostructure 122. Although not shown in fig. 1J and 1K, a hard mask material 124 may be initially deposited on the top surface of the hard mask layer 118. A Chemical Mechanical Planarization (CMP) process is then performed to remove the hard mask material 124 from the top surface of the hard mask layer 118.

In some embodiments, the hard mask material 124 is a different material than the hard mask layer 118. Specifically, the hard mask material 124 may be selected to have an etch selectivity with respect to the hard mask layer 118. The hard mask material may comprise amorphous silicon, siN, SICN, siOC, siOCN, hfO ₂、ZrO₂、HfAlO、HfSiO、Al₂O₃, or other suitable material. The hard mask material 124 may be deposited by CVD, PVD or ALD. Other materials and deposition processes may be used for the hard mask material 124 without departing from the scope of the present disclosure.

Fig. 1L is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1M is a top view of integrated circuit 100 at a stage of processing of fig. 1L, according to some embodiments. In fig. 1L, the hard mask layer 118 has been removed. The hard mask layer 118 may be removed by an etching process such as wet etching or dry etching. Because the hard mask layer 118 is selectively etchable relative to the hard mask material 124, the hard mask material 124 remains after the hard mask film 118 is removed. Specifically, the hard mask material 124 remains as pillars on the semiconductor nanostructures 122. The top view of fig. 1M shows that the spacers 126 laterally surround the hard mask material 124.

After removing the hard mask layer 118, spacers 126 are formed on the sidewalls of the hard mask material 124. The spacer 126 may comprise SiO ₂, siN, siCN, siOC, siOCN, or other suitable material. The spacer 126 may be formed by conformally depositing a spacer layer on the integrated circuit 100 and then performing an anisotropic etching process for a period of time that results in the removal of the spacer layer 126 from the top surface of the hard mask material 124 and from the portions of the surface of the fourth semiconductor layer 116 where the vertical thickness is minimal. The spacers 126 remain on the sidewalls of the hard mask material 124 due to the greater vertical thickness at those locations on these sidewalls. The hard mask material may be deposited by CVD, PVD, ALD or other suitable processes.

Fig. 1N is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1O is a top view of integrated circuit 100 at a stage of processing of fig. 1N, according to some embodiments. An etching process has been performed to form trenches 128 through the layers of the semiconductor stack 108, the source/drain regions 104, and partially into the substrate 102. The etching process forms trenches 128 in all areas not directly under the spacers 126 and hard mask material 124. As will be described in more detail below, the trenches 128 are used to form Shallow Trench Isolation (STI) regions. The etching process to form trench 128 may include a single etching step or multiple etching steps. The etching process may include wet etching, dry etching, or other types of etching processes. The etching process exposes the semiconductor substrate 102. According to some embodiments, the trench 128 may extend between 10nm and 20nm into the substrate 102, although other depths may be used without departing from the scope of the present disclosure.

Fig. 1P is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1Q is a top view of integrated circuit 100 at a stage of processing of fig. 1P, according to some embodiments. Recesses 130 have been formed. Specifically, an etching process of selectively etching the first semiconductor layer 110 and the third semiconductor layer 114 with respect to the second semiconductor layer 112, the fourth semiconductor layer 116, the source/drain region 104, and the semiconductor substrate 102 has been performed. This illustrates one of the advantages of the first and third semiconductor layers 110 and 114 being selectively etchable relative to the other semiconductor layers. The recess 130 is formed very precisely to replace the first semiconductor layer 110 and the third semiconductor layer 114. The recess 130 exposes a portion of the semiconductor nanostructure 122. The recess 130 is not apparent in the top view of fig. 1Q.

Fig. 1R is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1S is a top view of integrated circuit 100 at a stage of processing of fig. 1R, in accordance with some embodiments. An inner spacer 132 has been formed in the recess 130. As will be explained in more detail below, the internal spacers 132 serve to electrically isolate the semiconductor nanostructures 122 and the source/drain regions 104 from gate metal that will be deposited later.

Spacers (e.g., inner spacers 132) may be formed by depositing a dielectric material in recesses 130 and trenches 128. After deposition of the dielectric material, an anisotropic etch process is performed to remove the dielectric material from all locations not directly under the spacers 126 and the hard mask material 124. The dielectric material may include a low-K dielectric material such as SiO ₂, siN, siCN, siOC, siOCN, or other suitable dielectric material. Although fig. 1R shows substantially vertical sidewalls of the spacers 132, in practice, the inner spacers 132 may have concave sidewalls, which are recesses 115 (see fig. 4). The dielectric material of the inner spacer 132 may be deposited by CVD, PVD, ALD or other suitable deposition process. The inner spacer 132 is not apparent in the top view of fig. 1S.

Fig. 1T is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1U is a top view of integrated circuit 100 at a stage of processing of fig. 1T, according to some embodiments. An etching process has been performed to laterally widen the trench 128 under the semiconductor layer stack 108. This results in extended trench regions 134 in the source/drain regions 104 and the substrate 102. Specifically, the gap extends laterally under the inner spacer 132. The extended trench region 134 may extend laterally between 3nm and 7nm under the inner spacer 132, although other dimensions may be used without departing from the scope of the present disclosure.

The etching process selectively etches the material of the substrate 102 and the source/drain regions 104 relative to the second semiconductor layer 112 and the inner spacers 132. Although not shown in fig. 1T and 1U, before the etching process, since the material of the fourth semiconductor layer 116 is the same as that of the substrate 102 in some embodiments, a cap layer has been formed on the sidewalls of the fourth semiconductor layer 116 to prevent etching of the fourth semiconductor layer 116. This may result in undesirable etching of the semiconductor layer 116 at this stage of the process. The cap layer may be formed by forming a barrier structure in trench 128, etching back the barrier structure to expose sidewalls of fourth semiconductor layer 116, and oxidizing the exposed sidewalls. Or the cap layer may be formed by selectively depositing an oxide or nitride layer on the sidewalls of the cap layer.

Fig. 1V is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1W is a top view of integrated circuit 100 at a stage of processing of fig. 1V, according to some embodiments. Shallow trench isolation regions 138 have been formed in the extended trench regions 134 according to some embodiments. Shallow trench isolation regions 138 may be formed by depositing a dielectric material in trenches 128 and on exposed surfaces of integrated circuit 100. A CMP process may then be performed to remove the dielectric material over the hard mask material 124 and the spacers 126. An etching process may then be performed to etch back the dielectric material to the level shown in fig. 1V. The shallow trench isolation region may comprise silicon oxide, silicon nitride, or other suitable dielectric material. Although fig. 1V shows the surface of the shallow trench isolation region 138 below the bottom surface of the inner spacer 132, in practice, the top surface of the shallow trench isolation region 138 may extend higher in the trench 128 than the bottom surface of the inner spacer. Other processes and materials may be used for the shallow trench isolation region 138 without departing from the scope of the present disclosure.

Fig. 1X is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 1Y is a top view of integrated circuit 100 at a stage of processing of fig. 1X, according to some embodiments. Gate dielectric 140 has been deposited over the exposed portions of inner spacer 132, semiconductor layer 116, semiconductor nanostructure 122, spacer 126, and hard mask material 124.

Although a single gate dielectric layer (i.e., gate dielectric) 140 is shown, in practice, gate dielectric layer 40 may include an interfacial gate dielectric layer and a high-K gate dielectric layer. An interfacial gate dielectric layer is on the surface of semiconductor nanostructure 122 and on other surfaces. An interfacial gate dielectric layer is deposited on all exposed surfaces of semiconductor nanostructure 122. The interfacial gate dielectric layer laterally surrounds the semiconductor nanostructure 122. The interfacial gate dielectric layer may comprise a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. The interfacial gate dielectric layer may comprise a relatively low-K dielectric relative to a high-K dielectric such as hafnium oxide or other high-K dielectric material that may be used for the gate dielectric of a transistor. The high-K dielectric may comprise a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon oxide. The interfacial gate dielectric layer may be formed by a thermal oxidation process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process. The interfacial gate dielectric layer may have a thickness between 0.5nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interfacial gate dielectric layer without departing from the scope of the present disclosure.

A high K gate dielectric layer of gate dielectric 140 is deposited in a conformal deposition process. A conformal deposition process deposits a high K dielectric layer over the interfacial gate dielectric layer, the inner spacers 132, the spacers 126, the hard mask material 124, and the shallow trench isolation regions 138. A high K gate dielectric layer surrounds the semiconductor nanostructure 122. The high-K gate dielectric layer has a thickness between 1nm and 3 nm. The high-K dielectric layer includes one or more layers of dielectric materials such as HfO ₂, hfSiO, hfSiON, hfTaO, hfTiO, hf ZrO, zirconia, alumina, titania, hafnium oxide-alumina (HfO ₂-Al₂O₃) alloy, other suitable high-K dielectric materials, and/or combinations thereof. The high-K dielectric layer may be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-K dielectric layer without departing from the scope of the present disclosure.

Gate metal 142 has been deposited. Gate metal 142 is deposited on all exposed surfaces of the high K dielectric layer. Gate metal 142 substantially surrounds semiconductor nanostructure 122. Although the gate metal 142 is shown as a single layer in fig. 1X and 1Y, in practice the gate metal 142 may include one or more conductive liner layers, work function layers, and gate fill layers, which together comprise the gate metal. The gate metal may include one or more of Ti, tiN, ta, taN, al, cu, co, ru, W, au or other suitable conductive materials. The gate metal 142 may be deposited by PVD, ALD, or CVD. Other configurations, materials, and deposition processes may be used for gate metal 142 without departing from the scope of this disclosure. Lateral expansion of the shallow trench isolation regions 138 may help prevent shorting between the gate metal 142 and the source/drain regions 104.

Fig. 1Z is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 2A is a top view of integrated circuit 100 at a stage of processing of fig. 1Z, according to some embodiments. An etch back process has been performed to reduce the height of gate metal 142 within trench 128. In the initial etch back process, no mask is present and gate metal 142 is recessed to the position shown above right trench 128.

In the example of fig. 1Z, three vertical transistors will ultimately be formed, one for each semiconductor nanostructure 122. The gate metal 142 laterally surrounds each semiconductor nanostructure 122 in a gate-around configuration. In the example of fig. 1Z, the gate metal 142 of the left side transistor will be electrically isolated from the gate metal 142 of the middle and right side transistors. The gate metals of the middle transistor and the right side transistor are shorted together.

Accordingly, after the etch back process, a hard mask layer (not shown) is formed and patterned. Specifically, the hard mask is patterned to cover the right trenches 128 and expose the left trenches 128. An anisotropic etching process is then performed to selectively etch the gate metal 142 in a downward direction. This corresponds to a cut gate process in which the gate metal 142 is cut to isolate the gate electrode of the selected transistor. In the example of fig. 1Z, the gate metal 142 surrounding the left side nanostructure 122 is cut and electrically isolated from the gate metal surrounding the sensor semiconductor nanostructure 122. The gate metal 142 surrounding the middle nanostructure 122 and the right nanostructure 122 is not cut. The hard mask layer is then removed. As a result, the gate interconnect 144, which is made up of the gate metal 142, electrically connects the gate electrodes of the middle and right side transistors. The gate electrodes in the other regions may be connected by interconnect structures, such as metal interconnects formed over the transistors and conductive vias. This process produces fewer conductive vias in the metal layer. This may lead to a reduction in the size of the layout. The gate cutting process may also etch to between 0nm and 20nm into the shallow trench isolation region 138.

Fig. 2B is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 2C is a top view of integrated circuit 100 at a stage of processing of fig. 2B, in accordance with some embodiments. An interlayer dielectric layer 146 has been deposited. Interlayer dielectric 146 fills the remainder of trench 128. In the left trench 128, the interlayer dielectric 146 contacts the shallow trench isolation region 138. In the right side trench 128, an interlayer dielectric 146 contacts the gate metal 142. The interlayer dielectric layer may comprise silicon oxide, silicon nitride, or other suitable dielectric layer. Interlayer dielectric 146 may be formed by CVD, PVD, ALD or other suitable deposition processes. The interlayer dielectric layer 146 may correspond to the first interlayer dielectric layer 146.

In some embodiments, a gate insulating material may be deposited prior to depositing interlayer dielectric layer 146. The gate insulating material may include silicon oxide, silicon nitride, siCN, siCON, siCO, or other suitable dielectric material. An interlayer dielectric layer 146 may then be deposited. The material of the gate insulating material may be different from the material of the interlayer dielectric layer 146.

After depositing interlayer dielectric layer 146, a CMP process is performed. The CMP process completely removes the spacers 126 and the hard mask material 124 and exposes the top surfaces of the semiconductor nanostructures 122 and the fourth semiconductor layer 116.

Fig. 2D is a cross-sectional view of integrated circuit 100 at an intermediate stage of processing according to some embodiments. Fig. 2E is a top view of integrated circuit 100 at the processing stage of fig. 2D, in accordance with some embodiments. An etch back process has been performed to remove the fourth semiconductor layer 116 and etch back the semiconductor nano-structures 122 to a level substantially flush with the top surface of the upper inner spacers 132. Upper source/drain regions 105 are then formed on the top surfaces of the upper inner spacers 132, and the source/drain regions 105 are in contact with the top surfaces of the semiconductor nanostructures 122. The upper source/drain regions 105 may comprise silicon, silicon germanium, or other suitable semiconductor materials. The source/drain regions 105 may be formed by epitaxial growth from the semiconductor nanostructure 122. Doping of the source/drain regions 105 may be accomplished in situ.

After forming the upper source/drain regions 105, a dielectric layer 148 is deposited over the upper source/drain regions 105a and the interlayer dielectric layer 146. Dielectric layer 148 may include silicon oxide, silicon nitride, siCN, siCON, siCO, or other suitable dielectric materials. Dielectric layer 148 may be deposited by CVD, PVD, ALD or other suitable deposition process. Dielectric layer 148 may correspond to a second interlayer dielectric layer over first interlayer dielectric layer 146.

The dielectric layer 148 is then patterned to expose portions of the upper source/drain regions 105. Patterning of dielectric layer 148 may also form connections between adjacent upper source/drain regions 105, as shown in fig. 2E. Patterning of dielectric layer 148 may be accomplished by a photolithographic process.

After patterning the dielectric layer 148, a silicide layer 150 is formed in contact with the source/drain regions 105. Silicide layer 150 may comprise nickel silicide, titanium silicide, or other types of silicides.

After the silicide layer 150 is formed, source/drain metal 152 is deposited to contact the silicide layer 150. The source/drain metal 152 may comprise one or more of titanium, tantalum, tungsten, copper, aluminum, tantalum nitride, titanium nitride, or other suitable conductive material. The integrated circuit may also include source/drain metal pads 153 laterally surrounding the source/drain metal 152. The source/drain metal pad 153 may comprise titanium nitride, tantalum nitride, or other suitable conductive material. As shown in fig. 2E, the source/drain metal 152 may interconnect the source/drain regions 105 of some adjacent transistors. The source/drain metal 152, the silicide layer 150, and the liner 153 may collectively correspond to source/drain contacts.

In fig. 2D and 2E, the front-end processing is substantially complete, and the transistor 101 has been formed. Fig. 2D shows three vertical nanostructure transistors 101. Fig. 2E shows five vertical nanostructure transistors 101. Each transistor 101 includes a semiconductor nanostructure 122 extending between a lower source/drain region 104 and an upper source/drain region 105. Semiconductor nanostructure 122 corresponds to a channel region of transistor 101. Each transistor includes a gate metal 142, the gate metal 142 laterally surrounding the semiconductor nanostructure 122 and separated from the semiconductor nanostructure 122 by a gate dielectric 140. Each transistor includes an internal spacer 132 that electrically isolates the gate metal 142 from the lower source/drain region 104 and the upper source/drain region 105. Each transistor 101 includes a source/drain metal 152 through which a voltage can be applied to the source/drain region 105 by the source/drain metal 152. Although not shown in fig. 2D, a gate metal contact may be formed to connect to the gate metal 142 so as to apply a voltage to the gate metal 142 of each transistor 101.

The design of the source/drain metal 152 may provide a higher degree of freedom without the use of additional vias. If the source/drain metal 152 is formed on the same level as the gate metal 142, the connection of the source/drain metal 152 may be blocked by the gate metal 142 and additional conductive vias may be required to the overlying metal interconnect layer in order to connect the source/drain metal 152 in different regions. Thus, the source/drain metal 152 is formed in the second interlayer dielectric layer 148 over the first interlayer dielectric layer 146, and the gate metal 142 is formed in the first interlayer dielectric layer 146, enabling a more compact layout without the risk of undesired shorts and complex interconnect designs.

Fig. 2F illustrates backside source/drain contacts according to some embodiments. Specifically, after the front-end processing is complete, the integrated circuits (i.e., the wafer prior to dicing) may be flipped so that the bottom of the substrate 102 is exposed. Trenches may be etched through the substrate 102 to expose the bottoms of the source/drain regions 104. The silicide layer 157 may be formed in contact with the source/drain regions 104. Silicide layer 157 may be substantially similar to silicide layer 150.

After the silicide layer 157 is formed, source/drain metal 156 is deposited to contact the silicide layer 57. The source/drain metal 156 may comprise one or more of titanium, tantalum, tungsten, copper, aluminum, tantalum nitride, titanium nitride, or other suitable conductive material. The integrated circuit may also include source/drain metal pads (not shown) laterally surrounding the source/drain metal 152. The source/drain metal pad may comprise titanium nitride, tantalum nitride, or other suitable conductive material. The source/drain metal 156, silicide 157, and pad may collectively correspond to a source/drain contact.

Various other processes and configurations may be used to form vertical nanostructure transistor 101. The structures and processes shown and described in connection with fig. 1A-2E are given by way of example, and other structures, processes, and configurations may be used without departing from the scope of the present disclosure.

Fig. 3A is a cross-sectional view of integrated circuit 100 at a stage of processing shown in fig. 1H, in accordance with some embodiments. Fig. 3A differs from fig. 1H in that the top surface of the semiconductor nanostructure 122 is higher than the top surface of the fourth semiconductor layer 116. The top surface of the semiconductor nanostructure 122 may be between 0nm and 2nm higher than the top surface of the fourth semiconductor layer 116, although other dimensions may be used without departing from the scope of the present disclosure.

Fig. 3B is a cross-sectional view of integrated circuit 100 at the processing stage shown in fig. 1H, in accordance with some embodiments. Fig. 3B differs from fig. 1H in that semiconductor nanostructure 122 has been formed with a top surface that is lower than the top surface of fourth semiconductor layer 116. The top surface of the semiconductor nanostructure 122 may be between 0nm and 2nm lower than the top surface of the fourth semiconductor layer 116, although other dimensions may be used without departing from the scope of the present disclosure.

Fig. 4 is an enlarged cross-sectional view of integrated circuit 100 according to some embodiments. Specifically, the view of FIG. 4 is at the stage of processing shown in FIG. 1R. However, in the view of fig. 4, the recess 115 has been formed in the inner spacer 132. This may be due to an etching process that removes dielectric material from trench 128 after a deposition process of material that forms inner spacers 132. The recess 115 may be formed as a result of the etching process not being entirely anisotropic.

Fig. 5 is an enlarged cross-sectional view of integrated circuit 100 according to some embodiments. Specifically, the view of FIG. 5 is at the stage of processing shown in FIG. 1R. However, in the view of fig. 5, the seam 135 and recess 115 have been formed in the interior spacer 132. When the material of the inner spacer 132 is deposited using conformal deposition grown from all exposed surfaces, the seams 135 may be created. If the duration of the conformal deposition is carefully selected, the dielectric material of the inner spacers 132 will not completely fill the gap between the semiconductor layers 112 and 116. The result is a seam 135 formed in the inner spacer 132. The recess 115 may be created as described with respect to fig. 4. Seam 135 and recess 115 may remain after the process is completed. The seam 135 may remain as a void or may be filled with a dielectric material from a subsequent deposition process, such as the material of the gate dielectric 140, the material of the interlayer dielectric region 146, or the material of the trench isolation region 138 in the example where the top of the trench isolation region 138 extends above the top surface of the source/drain region 104. The recess 115 may likewise be filled with dielectric material from a subsequent deposition process described above with respect to the seam 135.

Fig. 6 is an enlarged cross-sectional view of integrated circuit 100 according to some embodiments. Specifically, the view of FIG. 6 is at the stage of processing shown in FIG. 1R. However, in the view of fig. 6, the inner spacer 132 is formed of two materials. The first dielectric material 133 is a material deposited to form the inner spacers 132 in fig. 1R. The deposition of the first material is performed with a conformal deposition process, the duration of which is selected to ensure that the gap between semiconductor layers 116 and 112 is not completely filled with the first dielectric material 133. A second dielectric material 137 is then deposited. The second dielectric material 137 fills the remaining space between the first semiconductor layer 116 and the second semiconductor layer 112. The etching process may then remove the first and second dielectric materials 133 and 137 from the trench 128, leaving the inner spacers 132, as shown in fig. 6. The recess 115 may be formed as described with respect to fig. 4. The second dielectric material 137 may include one or more of SiO ₂, siN, siCN, siOC, siOCN, or other suitable dielectric material. The second dielectric material 137 may be different from the first dielectric material 133. In one example, the first dielectric material 133 is silicon oxide and the second dielectric material 137 is silicon nitride. Other materials may be used without departing from the scope of the present disclosure.

Fig. 7 is an enlarged cross-sectional view of integrated circuit 100 according to some embodiments. Specifically, the view of FIG. 7 is at the stage of processing shown in FIG. 6. Similar to fig. 6, the inner spacer 132 of fig. 7 includes a first dielectric material 133 and a second dielectric material 137. Both the first dielectric material 133 and the second dielectric material 137 are formed using a conformal deposition process. The duration of each deposition process is selected to ensure that the seams 135 remain after the deposition of the second dielectric material 137. As a result, the seam 135 remains in the interior spacer 132. Recess 115 may also be substantially as described with respect to fig. 4.

Fig. 8 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In particular, the view of FIG. 8 is at a processing stage associated with FIG. 1X. However, in fig. 8, a gap 143 has been formed in the gate metal 142. Specifically, the gap 143 is formed to be vertically horizontal in the middle of the upper and lower inner spacers 132, and at a lateral position corresponding to the position of the groove 128. The seam 143 may result in the case where the gate metal 142 is deposited using a conformal deposition process (e.g., an ALD process). The conformal growth may result in the upper portion of trench 128 being completely filled with gate metal 142, and then the wider portion of gate metal 142 may be completely filled.

Fig. 9 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In particular, the view of FIG. 9 is at a processing stage associated with FIG. 1X. However, fig. 9 shows that the gate electrode includes gate metal 142 and gate fill material 145. In some embodiments, the initial deposition of gate metal 142 (which may include multiple layers) does not completely fill trench 128. Gate fill material 145 may then be deposited filling the remaining space in trench 128. The gate fill material 145 may comprise tungsten or other suitable conductive material. The gate fill material 145 may be deposited by ALD, PVD, or other suitable deposition process.

Fig. 10 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In particular, the view of FIG. 10 is at a processing stage associated with FIG. 9. In fig. 10, gate fill material 145 has been deposited as described in fig. 9. In fig. 10, the seam 143 remains in the gate metal 142 as described with respect to fig. 8. Gate fill material 145 extends down through seam 143. The result is a seam 143 that laterally surrounds the downward extension of gate fill material 145.

Fig. 11 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Specifically, the view of FIG. 11 is at the stage of processing shown in FIG. 2D. However, the view of fig. 11 shows gate fill material 145 and gap 143, as described with respect to fig. 10. Fig. 11 shows that a gate fill material 145 is present in the right side trench 128 between the middle and right side transistors 101. Gate fill material 145 is not present in left trench 128 between left transistor 101 and middle transistor 101, where a gate cutting process has been performed to electrically isolate the gate electrodes of the left transistor and middle transistor. The gap 143 is also present in the right groove 128, but not in the left groove 128.

In some embodiments, transistor 101 and dimension D1 correspond to a gate pitch. The dimension D1 may be between 25nm and 45 nm. The transistor 101 has a second dimension D2 corresponding to the space between the lower portions of adjacent shallow trench isolation regions 138. The dimension D2 may be between 15nm and 20 nm. Dimension D2 may correspond to the width of source/drain regions 104. The transistor 101 has a dimension D3 corresponding to the height of the transistor 101. In particular, D3 corresponds to the vertical distance between the bottom of the lower source/drain region 104 and the top of the upper source/drain region 105. The dimension D3 may be between 40nm and 70 nm. The transistor 101 may have a dimension D4 corresponding to the width of the upper source/drain region 105. The dimension D4 may be between 15nm and 30 nm. The transistor 101 may have a fifth dimension D5 corresponding to the height of the source/drain contact 152. Dimension D5 may correspond to the combined height of source/drain contacts 152 and silicide 150. The dimension D5 may be between 5nm and 20 nm. Other sizes and configurations of transistor 101 may be used without departing from the scope of the present disclosure. Although the source/drain contacts 152 are shown separate from the silicide 150, the silicide 150 may be considered part of the source/drain contacts 152.

Fig. 12 and 13 are enlarged cross-sectional views of integrated circuit 100 at a stage of the process shown in fig. 2D, according to some embodiments. Fig. 12 and 13 show a dimension W corresponding to the width of the trench 128. If W is small enough, then gate fill material 145 may not be present in trench 128 because gate metal 142 completely fills trench 128, leaving only small seams 143 with vertical and horizontal portions, as shown in fig. 12. If W is large enough, then gate fill material 145 may extend down between gate metals 142, as shown in FIG. 13. For fig. 12, w may be between 15nm and 20nm, although other dimensions may be used without departing from the scope of the present disclosure. For fig. 13, w may be greater than 30nm, although other dimensions may be used without departing from the scope of the present disclosure.

Fig. 14 is a cross-sectional view of integrated circuit 100 at a processing stage similar to that shown in fig. 1V, in accordance with some embodiments. In fig. 14, the top surface of the trench isolation regions 138 extends higher than the top surface of the source/drain regions 104. In some embodiments, the top surface of trench isolation region 138 may be at a level below the top surface of lower inner spacer 132 and above the bottom surface of lower inner spacer 132. The trench isolation region 138 may have other configurations without departing from the scope of this disclosure.

Fig. 15 is an enlarged cross-sectional view of a portion of integrated circuit 100 at a processing stage intermediate to that shown in fig. 1P and 1R, in accordance with some embodiments. In fig. 15, the dielectric material of the inner spacer 132 has been deposited in the trench 128, but an etching process has not been performed to remove excess material of the inner spacer 132 from the trench 128. Fig. 15 shows a seam 161 formed in the inner spacer 132 due to a conformal deposition process. Seam 161 may be identical to seam 135. After the process is complete, the seam 161 may remain in the interior spacer 132. This may correspond to a void in the inner spacer 132. Alternatively, the seam 161 may be filled with a dielectric material, such as the gate dielectric material 140 or the interlayer dielectric 146, from a subsequent deposition process.

Fig. 16 is a flow chart of a method 1600 for forming an integrated circuit, according to some embodiments. Method 1600 may utilize the structures, components, and processes described with respect to fig. 1A-13. At 1602, method 1600 includes forming a trench in a semiconductor layer stack over a lower source/drain region of a first vertical transistor adjacent to a channel region of the first vertical transistor. One example of a first vertical transistor is vertical transistor 101 of fig. 2D. One example of a lower source/drain region is lower source/drain region 104 in fig. 1C. One example of a channel region is channel region 122 of fig. 2D. One example of a trench is trench 128 in fig. 1N. At 1604, the method 1600 includes exposing a portion of the channel region by selectively removing the first layer of the stack relative to the second layer of the stack via the trench using a first etching process. One example of a first layer is the first semiconductor layer 110 in fig. 1C. One example of a second layer is the second semiconductor layer 112 in fig. 1C. At 1606, method 1600 includes forming an upper inner spacer in contact with the channel region in place of the first layer. One example of an upper inner spacer is upper inner spacer 132 in fig. 1R. At 1608, the method 1600 includes removing a second layer of the stack via the trench using a second etching process. At 1610, method 1600 includes forming a gate metal in place of the second layer. At 1612, method 1600 includes forming an upper source/drain region of a first vertical transistor over the channel region and the upper inner spacer. One example of an upper source/drain region is upper source/drain region 105 of fig. 2D.

Fig. 17 is a flow chart of a method 1700 for forming an integrated circuit according to some embodiments. The method 1700 may utilize the structures, components, and processes described with respect to fig. 1A-13. At 1702, method 1700 includes forming a first channel region in a first vertical transistor that extends vertically from a first lower source/drain region of the first vertical transistor. One example of a first vertical transistor is vertical transistor 101 of fig. 2D. One example of a first channel region is the semiconductor nanostructure 122 of fig. 2D. One example of a first lower source/drain region is the lower source/drain region 104 of fig. 2D. At 1704, the method 1700 includes forming a first lower inner spacer in contact with the first channel region. One example of a first lower inner spacer is lower inner spacer 132 of fig. 2D. At 1706, the method 1700 includes forming a first upper inner spacer above the first lower inner spacer and in contact with the first channel region in a same deposition process as the first lower inner spacer. One example of a first upper inner spacer is upper inner spacer 132 of fig. 2D. At 1708, the method includes forming a gate dielectric on top of the first lower inner spacer, on sidewalls of the first channel region between the first upper inner spacer and the first lower inner spacer, and on bottom of the first upper inner spacer after forming the first lower inner spacer and the first upper inner spacer. One example of a gate dielectric is gate dielectric 140 of fig. 2D. At 1710, the method 1700 includes depositing gate metal between the first upper inner spacer and the first lower inner spacer. One example of a gate metal is gate metal 142 of fig. 2D. At 1712, the method 1700 includes forming upper source/drain regions of the first vertical transistor in contact with the top of the first channel region and the top of the first upper inner spacer. One example of an upper source/drain region is upper source/drain region 105 of fig. 2D.

Embodiments of the present disclosure reduce active area pitch and improve scaling of integrated circuit cell sizes. In some embodiments, vertical nanostructure transistors are formed. The vertical nanostructure transistor may include a lower source/drain region and an upper source/drain region, and a semiconductor nanostructure channel region extending vertically between the upper source/drain region and the lower source/drain region. The gate electrode laterally surrounds the semiconductor nanostructure channel region. A process for forming a vertical nanostructure transistor may include forming semiconductor layer stacks having different material concentrations such that individual layers of the semiconductor stacks may be selectively etched relative to one another. The formation of the semiconductor layer stack enables precise control and definition of the dimensions of the internal spacers, gate electrodes and other structures of the vertical nanostructure transistor. The result is a more efficient use of integrated circuit area, simpler and more compact formation of source/drain contacts, and reduced various other damage.

In one embodiment, a method includes: forming a trench adjacent to a channel region of the first vertical transistor in the stack of semiconductor layers over a lower source/drain region of the first vertical transistor; exposing portions of the channel region by selectively removing the first layer in the stack relative to the second layer of the stack via the trench using a first etching process; an upper inner spacer in contact with the channel region is formed in place of the first layer. The method comprises the following steps: the second layer of the stack is removed via the trench using a second etch process, forming a gate metal in place of the second layer, and forming upper source/drain regions of the first vertical transistor over the channel region and the upper inner spacers.

In some embodiments, the first etching process removes a third layer of the stack, wherein the second layer is located between the first layer and the third layer prior to the first etching process.

In some embodiments, a method comprises: instead of the third layer, a lower internal spacer is formed in contact with the channel region and the lower source/drain.

In some embodiments, a method comprises: removing gate metal from the trench using a third etching process; and filling the trench with a first interlayer dielectric layer in contact with the remaining portion of the gate metal and the upper and lower inner spacers after the second etching process.

In some embodiments, a method comprises: portions of the source/drain regions under the lower internal spacers are removed via the trenches prior to depositing the gate metal.

In some embodiments, a method comprises: shallow trench isolation regions are formed by depositing a dielectric material at the bottom of the trench and in contact with the bottom surface of the lower inner spacer.

In some embodiments, the first interlayer dielectric layer is in contact with the dielectric material of the shallow trench isolation region.

In some embodiments, a method comprises: forming a second interlayer dielectric layer on the first interlayer dielectric layer and on the upper source/drain region; patterning the second interlayer dielectric layer to expose the upper source/drain regions; and forming source/drain contacts in the second interlayer dielectric layer in contact with the upper source/drain regions.

In some embodiments, patterning the second inter-dielectric layer includes exposing an upper source/drain region of the second vertical transistor, wherein forming the source/drain contact includes depositing a source/drain metal in the second inter-dielectric layer, the source/drain metal electrically connecting the upper source/drain region of the first vertical transistor to the upper source/drain region of the second vertical transistor.

In some embodiments, the first layer and the third layer comprise silicon germanium having a first concentration of germanium, wherein the second layer comprises silicon germanium having a second concentration of germanium different than the first concentration.

In one embodiment, a method includes: the method includes forming a first channel region of a first vertical transistor, the first channel region extending vertically from a first lower source/drain region of the first vertical transistor, forming a first lower inner spacer in contact with the first channel region, and forming a first upper inner spacer above the first lower inner spacer and in contact with the first channel region in a same deposition process as the first lower inner spacer. The method comprises the following steps: after forming the first lower inner spacer and the first upper inner spacer, a gate dielectric is formed on top of the first lower inner spacer, on sidewalls of the first channel region between the first upper inner spacer and the first lower inner spacer, and on bottom of the first upper inner spacer, a gate metal is deposited between the first upper and lower inner spacers, and an upper source/drain region of the first vertical transistor is formed in contact with the top of the first channel region and the top of the first upper inner spacer.

In some embodiments, a method comprises: forming a second channel region of the second vertical transistor, the second channel region extending vertically from a second lower source/drain region of the second vertical transistor; forming a second lower inner spacer in contact with the second channel region; forming a second upper inner spacer located above the second lower inner spacer and in contact with the second channel region in the same deposition process as the second lower inner spacer; forming a gate dielectric on top of the second lower inner spacer, on sidewalls of the second channel region between the second upper inner spacer and the second lower inner spacer, and on bottom of the second upper inner spacer after forming the second lower inner spacer and the second upper inner spacer; depositing a gate metal between the second upper inner spacer and the second lower inner spacer; and forming upper source/drain regions of the second vertical transistor in contact with the top of the second channel region and the top of the second upper inner spacer.

In some embodiments, a method comprises: forming a first shallow trench isolation region separating the first lower source/drain region and the second lower source/drain region; and electrically isolating the gate metal of the first vertical transistor by removing a portion of the gate metal over the first shallow trench isolation region using an etching process; and depositing an interlayer dielectric layer between a first portion of the gate metal corresponding to the gate electrode of the first vertical transistor and a second portion of the gate metal corresponding to the gate electrode of the second vertical transistor, wherein the interlayer dielectric layer is in contact with a top of the first shallow trench isolation region.

In some embodiments, a method comprises: forming a third channel region of a third vertical transistor, the third channel region extending vertically from a third lower source/drain region of the third vertical transistor; forming a third lower inner spacer in contact with the third channel region; forming a third upper inner spacer located above the third lower inner spacer and in contact with the third channel region in the same deposition process as the third lower inner spacer; forming a gate dielectric on top of the third lower inner spacer, on sidewalls of the third channel region between the third upper inner spacer and the third lower inner spacer, and on bottom of the third upper inner spacer after forming the third lower inner spacer and the third upper inner spacer; depositing a gate metal between the third upper inner spacer and the third lower inner spacer; forming upper source/drain regions of the third vertical transistor in contact with the top of the third channel region and the top of the third upper inner spacers; forming a second shallow trench isolation region separating the second lower source/drain region and the third lower source/drain region; and protecting the gate metal between the second channel region and the third channel region from the etching process such that the gate electrode of the second vertical transistor is shorted to the gate electrode of the third vertical transistor.

In some embodiments, the gate dielectric is in contact with the second shallow trench isolation region and is not in contact with the first shallow trench isolation region.

In some embodiments, there is a void in the gate metal between the first channel region and the second channel region.

In one embodiment, a device includes a first vertical transistor. The first vertical transistor includes a first lower source/drain region, a first channel region extending vertically from the first lower source/drain region, a first lower inner spacer in contact with the first channel region and the first lower source region, and a first gate electrode positioned on the first lower inner spacer and laterally surrounding the first channel region. The device includes a shallow trench isolation region in contact with the first lower source/drain region and an interlayer dielectric layer extending perpendicularly from the shallow trench isolation region and in contact with sidewalls of the first lower inner spacer and sidewalls of the first gate electrode.

In some embodiments, the device includes a second vertical transistor. The second vertical transistor includes: a second lower source/drain region in contact with the shallow trench isolation region; a second channel region extending vertically from the second lower source/drain region; a second lower inner spacer in contact with the second channel region and the second lower source/drain region; and a second gate electrode positioned between the second upper inner spacer and the second lower inner spacer, wherein the interlayer dielectric layer is in contact with a sidewall of the second lower inner spacer and a sidewall of the first gate electrode, and is positioned between the first lower inner spacer and the second lower inner spacer and between the first gate electrode and the second gate electrode.

In some embodiments, the first lower inner spacer includes a void.

In some embodiments, the first gate electrode includes a void.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a trench adjacent to a channel region of a first vertical transistor in a stack of semiconductor layers above a lower source/drain region of the first vertical transistor;

Exposing a portion of the channel region by selectively removing a first layer in the stack relative to a second layer of the stack via the trench using a first etching process;

forming an upper inner spacer in contact with the channel region to replace the first layer;

Removing the second layer of the stack via the trench using a second etching process;

forming a gate metal to replace the second layer; and

Upper source/drain regions of the first vertical transistor are formed on the channel region and the upper inner spacer.

2. The method of claim 1, wherein the first etching process removes a third layer of the stack, wherein the second layer is located between the first layer and the third layer prior to the first etching process.

3. The method according to claim 2, comprising: lower internal spacers in contact with the channel region and the lower source/drain are formed in place of the third layer.

4. A method according to claim 3, comprising:

Removing the gate metal from the trench using a third etching process; and

After the second etching process, the trench is filled with a first interlayer dielectric layer in contact with the remaining portion of the gate metal and the upper and lower inner spacers.

5. The method of claim 4, comprising: portions of the source/drain regions under the lower internal spacers are removed via the trenches prior to forming the gate metal.

6. The method of claim 5, comprising: shallow trench isolation regions are formed by depositing a dielectric material at the bottom of the trench and in contact with the bottom surface of the lower inner spacer.

7. The method of claim 6, wherein the first interlayer dielectric layer is in contact with a dielectric material of the shallow trench isolation region.

8. The method of claim 4, comprising:

Forming a second interlayer dielectric layer on the first interlayer dielectric layer and on the upper source/drain region;

patterning the second interlayer dielectric layer to expose the upper source/drain regions; and

Source/drain contacts are formed in the second interlayer dielectric layer in contact with the upper source/drain regions.

9. A method of manufacturing a semiconductor device, comprising:

Forming a first channel region of a first vertical transistor, the first channel region extending vertically from a first lower source/drain region of the first vertical transistor;

forming a first lower inner spacer in contact with the first channel region;

Forming a first upper inner spacer located above the first lower inner spacer and in contact with the first channel region in the same deposition process as the first lower inner spacer;

After forming the first lower inner spacer and the first upper inner spacer, forming a gate dielectric on top of the first lower inner spacer, on sidewalls of the first channel region between the first upper inner spacer and the first lower inner spacer, and on bottom of the first upper inner spacer;

Depositing a gate metal between the first upper inner spacer and the first lower inner spacer; and

Upper source/drain regions of the first vertical transistor are formed in contact with the top of the first channel region and the top of the first upper inner spacer.

10. A semiconductor device, comprising:

a first vertical transistor, the first vertical transistor comprising:

A first lower source/drain region;

A first channel region extending vertically from the first lower source/drain region;

a first lower inner spacer in contact with the first channel region and the first lower source/drain region; and

A first gate electrode positioned on the first lower inner spacer and laterally surrounding the first channel region;

shallow trench isolation regions in contact with the first lower source/drain regions; and

An interlayer dielectric layer extending vertically from the shallow trench isolation region and contacting sidewalls of the first lower internal spacers and sidewalls of the first gate electrode.