CN116682823A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN116682823A
CN116682823A CN202310537785.5A CN202310537785A CN116682823A CN 116682823 A CN116682823 A CN 116682823A CN 202310537785 A CN202310537785 A CN 202310537785A CN 116682823 A CN116682823 A CN 116682823A
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China
Prior art keywords
dielectric layer
semiconductor
gate
shell
layer
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CN202310537785.5A
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Chinese (zh)
Inventor
郑嵘健
江国诚
朱熙甯
陈冠霖
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US18/165,853 external-priority patent/US20230369396A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116682823A publication Critical patent/CN116682823A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

An embodiment of the present invention provides a semiconductor device including: a semiconductor substrate; a first transistor including a plurality of first stacked channels over a semiconductor substrate; a second transistor including a plurality of second stacked channels over the semiconductor substrate; an isolation structure comprising a core dielectric layer between the channels of the first stack and the channels of the second stack; and a high-K gate dielectric layer on the first and second stacked channels and on sidewalls of the core dielectric layer between the first and second stacked channels and the core dielectric layer. Embodiments of the present invention also provide methods of forming semiconductor devices.

Description

Semiconductor device and method of forming the same
Technical Field
Embodiments of the present invention relate to semiconductor devices and methods of forming the same.
Background
The semiconductor integrated circuit industry has experienced an exponential growth. Technological advances in integrated circuit materials and design have resulted in multi-generation integrated circuits, where each generation has smaller and more complex circuitry than the previous generation. During the development of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. Such scaling down also increases the complexity of processing and manufacturing integrated circuits.
Disclosure of Invention
Some embodiments of the present invention provide a semiconductor device including: a semiconductor substrate; a first transistor including a plurality of first stacked channels over a semiconductor substrate; a second transistor including a plurality of second stacked channels over the semiconductor substrate; an isolation structure comprising a core dielectric layer between the channels of the first stack and the channels of the second stack; and a high-K gate dielectric layer on the first and second stacked channels and on sidewalls of the core dielectric layer between the first and second stacked channels and the core dielectric layer.
Further embodiments of the present invention provide a method of forming a semiconductor device, the method comprising: forming an isolation structure between the stacked first semiconductor nanostructure of the first transistor and the stacked second semiconductor nanostructure of the second transistor, the isolation structure comprising: a core dielectric layer having a top surface above all of the first semiconductor nanostructures and the second semiconductor nanostructures; and a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the first semiconductor nanostructures and the second semiconductor nanostructures; and forming a high-K gate dielectric layer in contact with the sidewalls of the core dielectric layer.
Still further embodiments of the present invention provide a semiconductor device including: a semiconductor substrate; a first transistor comprising a plurality of stacked first semiconductor nanostructures located over a semiconductor substrate corresponding to channel regions of the first transistor; a second transistor comprising a plurality of stacked second semiconductor nanostructures over the semiconductor substrate corresponding to channel regions of the second transistor; an isolation structure comprising: a core dielectric layer located between the first semiconductor nanostructure and the second semiconductor nanostructure, and having a top surface higher than all of the first semiconductor nanostructure and the second semiconductor nanostructure; and a shell dielectric layer having: a base portion surrounding a lower region of the core dielectric layer, and the base portion having a top surface lower than all of the first semiconductor nanostructures and the second semiconductor nanostructures; and a plurality of remnants, each of the remnants being located between the core dielectric layer and a respective one of the first semiconductor nanostructure and the second semiconductor nanostructure.
Still other embodiments of the present invention provide field effect transistors and methods having dual layer isolation structures.
Drawings
Aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-1T are perspective, side cross-sectional and plan views of an integrated circuit at an intermediate stage of processing according to some embodiments.
Fig. 2A-2H are perspective, side cross-sectional and plan views of an integrated circuit at an intermediate stage of processing according to some embodiments.
Fig. 3 is a side cross-sectional view of an integrated circuit according to some embodiments.
Fig. 4A-4D are perspective and side cross-sectional views of an integrated circuit at an intermediate stage of processing, according to some embodiments.
Fig. 5 is a flow chart of a method of forming an integrated circuit, according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, of the different components used to implement the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms such as "under …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Terms of relative degree such as "about", "substantially", and the like, should be construed as interpreted by one of ordinary skill in the art in accordance with the present specification.
The present invention relates generally to semiconductor devices, and more particularly to Field Effect Transistors (FETs), such as planar FETs, three-dimensional fin FETs (finfets), or nanostructured devices. Examples of nanostructure devices include full Gate (GAA) devices, nanoflake FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active inter-interval between nanostructure devices is typically uniform, the source/drain epitaxial structure is symmetrical, and the metal gate surrounds four sides of the nanostructure (e.g., nanoplatelets). The gate-drain capacitance ("Cgd") increases due to the larger metal gate cap and increased source/drain epi dimensions.
Embodiments of the present invention reduce active area pitch and improve scaling of integrated circuit cell size (e.g., height). In some embodiments, isolation structures are formed between adjacent stacks of semiconductor nanostructures corresponding to channel regions of adjacent transistors. The isolation structure may have a shell dielectric layer and a core dielectric layer. Initially, the shell dielectric layer is in contact with the sides of the semiconductor nanostructure. However, the etching process completely removes the shell dielectric layer from between the core dielectric layer and the semiconductor nanostructure. Subsequently, a high-K gate dielectric layer is conformally deposited over the semiconductor nanostructure and the surface of the core dielectric layer. The result is that the high-K gate dielectric layer completely fills the space between the semiconductor nanostructure and the core dielectric layer. This helps control the profile of the subsequently deposited gate metal, preventing undesirable overlap between the gate metal and the source/drain regions. The result is an improved wafer yield and integrated circuits with improved performance.
The nanostructure transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithographic processes, including a double patterning process or a multiple patterning process. Typically, a double patterning process or a multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns with smaller pitches than those obtainable using a single direct lithographic process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the nanostructure transistor structure.
Fig. 1A-1T are perspective and cross-sectional top and side views of a portion of an integrated circuit 100 fabricated in accordance with some embodiments of the present invention. The fabrication process produces a plurality of semiconductor nanostructure transistors 103, as will be described in more detail below.
Fig. 1A is a perspective view of an integrated circuit 100 in an intermediate processing state. The integrated circuit 100 includes a substrate 102. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 102 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; combinations thereof. Other substrates may be used, such as single layer, multi-layer or gradient substrates.
The integrated circuit 100 includes a semiconductor stack 104, the semiconductor stack 104 including a plurality of semiconductor layers 106 and sacrificial semiconductor layers 108 alternating with one another. As will be described in further detail below, the semiconductor layer 106 will be patterned to form semiconductor nanostructures for a plurality of transistors. As set forth in more detail below, the final sacrificial semiconductor layer 108 will be completely removed and used to enable the formation of other structures around the gate metal and semiconductor nanostructures.
In some embodiments, the semiconductor layer 106 may be formed of a first semiconductor material suitable for n-type semiconductor nanostructure transistors, such as silicon, silicon carbide, etc., and the sacrificial semiconductor layer 108 may be formed of a second semiconductor material suitable for p-type semiconductor nanostructure transistors, such as silicon germanium, etc. Each layer of the multilayer stack 104 may be epitaxially grown using a process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), or the like.
As shown in fig. 1A, integrated circuit 100 may include an optional sacrificial semiconductor layer 114, a dielectric layer 110, and a hard mask layer 112 formed over top semiconductor layer 106. In some embodiments, layer 110 is a pad oxide layer and hard mask layer 112 may comprise silicon. In some embodiments, the sacrificial semiconductor layer 114 is not present. Other materials may be used for the dielectric layer 110 and the hard mask layer 112 without departing from the scope of the present invention.
Three layers of each of the semiconductor layer 106 and the sacrificial semiconductor layer 108 are shown. In some embodiments, the multi-layer stack 104 may include one, or two, or four, or more, of each of the semiconductor layers 106 and the sacrificial semiconductor layer 108. Although the multi-layer stack 104 is shown as including the sacrificial semiconductor layer 108 as the bottommost layer of the multi-layer stack 104, in some embodiments, the bottommost layer of the multi-layer stack 104 may be the semiconductor layer 106.
Due to the high etch selectivity between the materials of the semiconductor layer 106 and the sacrificial semiconductor layer 108, the sacrificial semiconductor layer 108 of the second semiconductor material may be removed without significantly removing the semiconductor layer 106 of the first semiconductor material, thereby allowing the semiconductor layer 106 to be released to form the channel region of the semiconductor nanostructure transistor.
In fig. 1B, an etching process is performed together with a photolithography mask. The etching process may include an anisotropic etching process that etches in a downward direction. The etching process defines fins 118a-118d by forming trenches 120 through hard mask layer 112, dielectric layer 110, sacrificial semiconductor layer 114, sacrificial semiconductor layer 108, semiconductor layer 106, and substrate 102. Each fin 118a-118d includes a plurality of semiconductor nanostructures 107 patterned from the semiconductor layer 106. Each fin 118 includes a plurality of sacrificial semiconductor nanostructures 109 patterned from sacrificial semiconductor layer 108. As will be explained in more detail below, the semiconductor nanostructures 107 will serve as channel regions for nanostructure transistors. The semiconductor nanostructures 107 may be referred to as stacked channels. When referring generally to fins, the fins 118a-118d may be referred to simply as the fins 118 without suffixes. While reference is generally made to semiconductor nanostructures and sacrificial semiconductor nanostructures, the semiconductor nanostructures 107a-107d and the sacrificial semiconductor nanostructures 109a-109d may also be referred to simply as semiconductor nanostructures 107 and sacrificial semiconductor nanostructures 109 without suffixes.
The distance between adjacent fins 118a and 118b and between adjacent fins 118c and 118d in the Y direction may be different from the distance between adjacent fins 118b and 118 c. In other words, the grooves 120 may have different widths in the Y direction. For example, the distance between fins 118a and 118b and the distance between fins 118c and 118d may be between 20nm and 40 nm. The distance between fin 118b and fin 118c may be between 40nm and 60 nm. The semiconductor nanostructures 107 of each fin 118 may be referred to as a stack of semiconductor nanostructures. Other distances may be utilized without departing from the scope of the present invention. In some embodiments, the distance between all four adjacent fins may be the same.
Fin 118 and semiconductor nanostructure 107 may be patterned by any suitable method. For example, the fins 118 and the semiconductor nanostructures 107 may be formed using one or more photolithographic processes, including a double patterning process or a multiple patterning process. Typically, a double patterning process or multiple patterning process combines a lithographic process and a self-aligned process, allowing for smaller pitches than those obtainable using a single direct lithographic process. As an example of a multiple patterning process, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins 118. In some embodiments, the hard mask layer 112 is patterned, for example, by a photolithographic process, and then the pattern is transferred by an etching process to form the fins 118 and the semiconductor nanostructures 107. Each fin 118 and the semiconductor nanostructures 107 thereon may be collectively referred to as a "fin stack".
Fig. 1B shows a fin 118 with vertical straight sidewalls. In some embodiments, the sidewalls are substantially vertical (non-tapered) such that the widths of the fins 118 and the semiconductor nanostructures 107 are substantially similar, and the shape of the semiconductor nanostructures 107 is rectangular (e.g., having a rectangular profile in the Y-Z plane). In some embodiments, fins 118 have tapered sidewalls such that the width of each fin 118 and/or semiconductor nanostructure 107 increases continuously in a direction toward substrate 102. In such embodiments, the semiconductor nanostructures 107 may have different widths from one another, and the shape of the semiconductor nanostructures 107 may be trapezoidal (e.g., have a trapezoidal profile in the Y-Z plane).
In fig. 1C, isolation structures 122a and 122b have been formed in some trenches 120. In particular, isolation structures 122 have been formed in trench 120 between fins 118a and 118b and in trench 120 between fins 118c and 118 d. There is no isolation structure between fin 118b and fin 118 c.
In some embodiments, each isolation structure 122 includes a shell dielectric layer 124. A shell dielectric layer 124 is conformally deposited on the sidewalls and bottom of the corresponding trench 120. The shell dielectric layer 124 contacts the sidewalls of the substrate 102 at the bottom of the trench 120. In trench 120, shell dielectric layer 124 is in contact with the sidewalls of substrate 102, with the sidewalls of semiconductor nanostructures 107, with the sidewalls of sacrificial semiconductor nanostructures 109, with the sidewalls of dielectric layer 110, and with the sidewalls of hard mask layer 112.
The shell dielectric layer may be deposited by CVD, ALD, PVD or other suitable deposition process. The shell dielectric layer 124 may be formed of a low-k dielectric material. The low-K dielectric material of the shell dielectric layer 124 may include SiN, siCN, siOC, siOCN or other suitable dielectric material. The shell dielectric layer 124 may have a thickness between 2nm and 6 nm. Other materials, deposition processes, and thicknesses may be used for the shell dielectric layer 124 without departing from the scope of the present invention. The shell dielectric layer 124 may be referred to as a dielectric liner layer.
The isolation structure 122 may include a core dielectric layer 126. A core dielectric layer 126 may be deposited over the shell dielectric layer 124 in the appropriate trench 120. The core dielectric layer 126 may fill the remainder of the trench 120 not filled by the shell dielectric layer 124. The core dielectric layer may have a thickness in the Y direction of between 8nm and 36 nm. The core dielectric layer may be deposited by CVD, ALD, PVD or other suitable deposition process. The core dielectric layer 126 may be or include SiN, siCN, siOC, siOCN. Other dimensions, materials, and deposition processes may be used for the core dielectric layer 126 without departing from the scope of the present invention.
In some embodiments, the material of the shell dielectric layer 124 is different than the material of the core dielectric layer 126. In some embodiments, the shell dielectric layer 124 is either SiOC or SiOCN and the core dielectric layer 126 is either SiN or SiCN. In some embodiments, the shell dielectric layer 124 is either SiN or SiCN, and the core dielectric layer 126 is either SiOC or SiOCN. In some embodiments, the core dielectric layer 126 has a lower dielectric constant than the shell dielectric layer 124. This may help to reduce the capacitance associated with the transistor, since the core dielectric layer 126 is relatively thick compared to the shell dielectric layer 124.
Following deposition of the shell dielectric layer 124 and the core dielectric layer 126, an etch back process may be performed to recess the isolation structures 122 relative to the top surface of the hard mask layer 112. In some embodiments, shell dielectric layer 124 and core dielectric layer 126 may be deposited in all trenches 120. The shell dielectric layer 124 and the core dielectric layer 126 may then be selectively removed from some of the trenches 120 via a photolithographic process or other process in order to ensure that the isolation structures 122 are not present in some of the trenches 120 as shown in fig. 1C.
In fig. 1D, trench isolation regions 128, which may be Shallow Trench Isolation (STI) regions, are formed in the trenches 120 where the isolation structures 122 are not formed. Accordingly, shallow trench isolation regions 128 are formed between fins 118b and 118c and to the left of fin 118 a. Trench isolation regions 128 may be formed by depositing a dielectric material. In some embodiments, a dielectric material is formed over the substrate 102, the fins 118, and the semiconductor nanostructures 107, and between adjacent fins 118 and semiconductor nanostructures 107. The dielectric material may be an oxide such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not separately shown) may be first formed along the surfaces of the substrate 102, fin 118, and semiconductor nanostructure 107. Thereafter, a dielectric material may be formed over the liner of materials such as those discussed above.
In fig. 1D, a Chemical Mechanical Polishing (CMP), an etchback process, a combination thereof, or the like, has been performed to remove excess insulating material of the dielectric material over the hard mask layer 112, as shown in fig. 1D. A portion of the material of the shallow trench isolation region 128 remains on top of the isolation structure 122.
In fig. 1E, several etching processes have been performed. The first etch process may remove the hard mask layer 112, the dielectric layer 110, and the sacrificial semiconductor layer 114 from on top of the fin 118. The etching process may include one or more etching steps including wet etching, dry etching, or other types of etching processes. A second etching process may then be performed to recess the shallow trench isolation regions 128. The second etching process may include wet etching, dry etching, timed etching, or other types of etching processes that may recess the height of the shallow trench isolation regions 128. The result is that the top of fin 118 is exposed. Specifically, the top semiconductor nanostructure 107 of each fin 118 is exposed. The top of the isolation structure 122 is also exposed. The sidewalls of the semiconductor nanostructures 107 and the sacrificial semiconductor nanostructures 109 are exposed at locations where the shallow trench isolation regions 128 are recessed. A CMP process may then be performed to ensure that the top surface of fin 118 is substantially coplanar with the top surfaces of isolation structures 122.
Although not shown in fig. 1E, suitable wells (not shown separately) may also be formed in fin 118, semiconductor nanostructure 107, and/or trench isolation region 128. Using the mask, an n-type dopant implantation may be performed in the p-type region of the substrate 102, and a p-type dopant implantation may be performed in the n-type region of the substrate 102. Exemplary n-type dopants may include phosphorus, arsenic, antimony, and the like. Exemplary p-type dopants may include boron, boron fluoride, indium, and the like. An anneal may be performed after implantation to repair the implant damage and activate the p-type and/or n-type dopants. In some embodiments, in-situ doping during epitaxial growth of fin 118 and semiconductor nanostructure 107 may avoid separate implants, however in-situ doping and implant doping may be used together.
In fig. 1F, a sacrificial gate structure 130 has been formed over fin 118, isolation structure 122, trench isolation region 128, and semiconductor nanostructure 107. Two sacrificial gate structures 130 are shown in fig. 1F. In practice, many additional sacrificial gate structures 130 may be formed substantially parallel to the sacrificial gate structure 130 shown in fig. 1F and simultaneously with the sacrificial gate structure 130 shown in fig. 1F.
In fig. 1F, a sacrificial gate dielectric layer 132 has been formed prior to forming the sacrificial gate structure 130. Sacrificial gate dielectric layer 132 may comprise SiO or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer 132 has a low-K dielectric material. Sacrificial gate dielectric layer 132 may be deposited by CVD, ALD, or PVD.
The sacrificial gate structure includes a sacrificial gate layer 134 on a sacrificial gate dielectric layer 132. The sacrificial gate layer may comprise a material having a high etch selectivity with respect to the trench isolation regions 128. The sacrificial gate layer 134 may be a conductive, semiconductive, or nonconductive material, and may be or include amorphous silicon, polysilicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide, and metal. Sacrificial gate layer 134 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material.
Sacrificial gate structure 130 includes a dielectric layer 136 on sacrificial gate layer 134 and a dielectric layer 138 on dielectric layer 136. Dielectric layer 136 and dielectric layer 138 may correspond to a first mask layer and a second mask layer. Dielectric layer 136 may comprise silicon nitride, silicon oxynitride, or other suitable dielectric material. Dielectric layer 138 may comprise silicon nitride, silicon oxynitride, or other suitable dielectric material. Dielectric layer 136 and dielectric layer 138 are of different materials from each other, and dielectric layer 136 and dielectric layer 138 may be deposited using CVD, ALD, PVD or other suitable deposition process. Other materials and deposition processes may be used for dielectric layer 136 and dielectric layer 138 without departing from the scope of the present invention.
After depositing layer 132, layer 134, layer 136, and layer 138, dielectric layer 136 and dielectric layer 138 may be patterned to act as masking layers. An etching process may then be performed in the presence of the patterned dielectric layer to etch the exposed areas of the sacrificial gate layer 134 and the sacrificial gate dielectric layer 132. This results in the structure shown in fig. 1F.
In fig. 1G, after forming the sacrificial gate structure 130, one or more gate spacer layers 140 have been formed to cover the sacrificial gate structure 130, the fins 118, the trench isolation regions 128, and the isolation structures 122. The gate spacer layer 140 may be formed by PVD, CVD, ALD or other suitable deposition process. After forming gate spacer layer 140, horizontal portions (e.g., in the X-Y plane) of gate spacer layer 140 may be removed, thereby exposing upper surfaces of fin 118, isolation structures 122, and trench isolation regions 128. The gate spacer layer 140 may include one or more of SiO, siN, siON, siCN, siOCN, siOC or other suitable dielectric materials.
In fig. 1H, one or more etching operations have been performed to recess fin 118, isolation structures 122, and trench isolation regions 128 exposed by gate spacer layer 140. The removal operation may include a suitable etching operation to remove the material of semiconductor nanostructure 107, sacrificial semiconductor nanostructure 109, fin 118, isolation structure 122, and trench isolation region 128. The etching process may include Reactive Ion Etching (RIE), neutral Beam Etching (NBE), atomic Layer Etching (ALE), or the like. An etching process may form trenches 142 through fin 118 in the areas exposed by gate spacer layer 140. In practice, a large number of trenches 142 may be formed through the fin 118 between a large number of sacrificial gate structures 130. The result is a large number of stacked semiconductor nanostructures 107 formed from each fin 118. In fig. 1H, the stack of semiconductor nanostructures 107d and 107e have been defined from fin 118d to each other. The semiconductor nanostructure 107d will serve as a channel for the stack of transistors. The semiconductor nanostructure 107e will serve as a channel for the stack of individual transistors. The trenches 142 correspond to source/drain trenches. In particular, source/drain regions will be formed at those locations where fin 118 has been recessed, as will be explained in more detail below.
In some embodiments, at the processing stage of fig. 1H, dielectric support elements 141 remain on trench isolation regions 128. The dielectric support element 141 is a residue of the gate spacer layer 140. As will be explained in more detail below, the dielectric support element 141 may be used to guide or limit the growth of the source/drain regions.
In some embodiments, the shell dielectric layer 124 and the dielectric support element 141 are different materials. At the stage of the process shown in fig. 1H, the shell dielectric layer 124 and the dielectric support element 141 may extend to different vertical heights. Alternatively, in some embodiments, the shell dielectric layer 124 and the dielectric support element 141 may extend to the same height.
In fig. 1I, the inner spacers 144 have been formed. A selective etching process is performed to recess the exposed ends of the sacrificial semiconductor nano-structures 109 without substantially etching the semiconductor nano-structures 107. Next, internal spacers are formed by depositing a dielectric material to fill the grooves formed between the semiconductor nanostructures 107 by the previous selective etching process. The internal spacers 144 may be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or the like, formed by a suitable deposition method, such as Physical Vapor Deposition (PVD), CVD, ALD, or the like. An etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacers 144 disposed outside the recesses in the sacrificial semiconductor nano-structures 109. The remainder of the dielectric layer corresponds to the inner spacer 144 shown in fig. 1I.
In fig. 1J, source/drain regions 146a-146d have been formed. In the illustrated embodiment, the source/drain regions 146 are epitaxially grown from an epitaxial material. Source/drain regions 146 are grown on the exposed portions of fin 118, and source/drain regions 146 contact semiconductor nanostructures 107. Initially, source/drain regions 146 are grown between adjacent isolation structures 128 or between isolation structures 128 and isolation structures 122. Dielectric isolation structures 122 may be formed at cell boundaries. However, the dielectric isolation structures 122 may also be formed within the cell.
For each stack of semiconductor nanostructures 107, there are two source/drain regions 146. For stacks of semiconductor nanostructures 107a, the source/drain regions 146a are in direct contact with the semiconductor nanostructures 107 a. Only a single source/drain region 146a is visible in fig. 1J. This is because the source/drain regions 146a are located on opposite sides of the semiconductor nanostructure 107a in the X-direction and are obscured in the view of fig. 1J. Accordingly, the semiconductor nanostructure 107a extends in the X-direction between two source/drain regions 146 a. Also, the semiconductor nanostructure 107b extends in the X-direction between two source/drain regions 146 b. The semiconductor nanostructure 107c extends in the X-direction between two source/drain regions 146 c. The semiconductor nanostructure 107d extends in the X-direction between two source/drain regions 146d. Fig. 1J also shows that semiconductor nanostructure 107d and semiconductor nanostructure 107e share source/drain regions 146d/e. Each of these stacks of semiconductor nanostructures 107 may share source/drain regions 146 with stacks of semiconductor nanostructures 107 adjacent in the X-direction.
The dielectric support element 141 remaining on the trench isolation region 128 laterally restricts the growth of the source/drain regions 146 as the source/drain regions 146 grow upward from the fin 118. In some embodiments, the source/drain regions 146 exert stress in the respective semiconductor nanostructures 107, thereby improving performance. The source/drain regions 146 are formed such that each sacrificial gate structure 130 is disposed between an adjacent pair of the respective source/drain regions 146. In some embodiments, spacer layer 140 and internal spacers 144 separate source/drain regions 146 from sacrificial gate layer 134 by an appropriate lateral distance (e.g., in the X-axis direction) to prevent electrical bridging to the gate of the resulting device that is subsequently formed.
As previously set forth, in some embodiments, the shell dielectric layer 124 and the dielectric support element 141 may extend to different vertical heights. This creates an asymmetry in the source/drain regions 146. For example, if the shell dielectric layer 124 extends to a height greater than the dielectric support element 141, during the epitaxial growth process, the source/drain regions 146 will be able to begin to grow laterally in the Y direction earlier on top of the dielectric support element than on top of the shell dielectric layer 124. Accordingly, in some embodiments, the shape of the source/drain regions 146 may be asymmetric.
Source/drain regions 146 may comprise any acceptable material, such as suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source/drain regions 146 comprise a material that imparts a tensile strain in the channel region, such as silicon, siC, siCP, siP, and the like. According to some embodiments, when forming a p-type device, the source/drain regions 146 comprise a material that imparts a compressive strain in the channel region, such as SiGe, siGeB, ge, geSn and the like. The source/drain regions 146 may have surfaces protruding from the corresponding surfaces of the fins and may have facets. In some embodiments, adjacent source/drain regions 146 may merge to form a single source/drain region 146 over two adjacent fins of fins 118.
The source/drain regions 146 may be implanted with dopants and then subjected to an annealing process. The source/drain regions 146 may have a thickness of between about 10 19 cm -3 About 10 21 cm -3 Dopant concentration between. The N-type and/or p-type dopants of source/drain regions 146 may be any of the dopants previously discussed. In some embodiments, the source/drain regions 146 are doped in-situ during growth.
In fig. 1K, a Contact Etch Stop Layer (CESL) 148 and an interlayer dielectric (ILD) 150 have been formed. CESL 148 may include a thin dielectric layer that may be conformally deposited over exposed surfaces of source/drain regions 146, isolation structures 122, dielectric support elements 141, and trench isolation regions 128. CESL 148 may include SiN, siC, siOC, siOCN, siON or other suitable dielectric materials. CESL 148 may be deposited by CVD, ALD, PVD or other suitable deposition process.
A dielectric layer 150 covers CESL 148. The dielectric layer 150 may include SiO, siON, siN, siC, siOC, siOCN, siON or other suitable dielectric materials. The dielectric layer 150 may be deposited by CVD, ALD, PVD or other suitable deposition process.
In fig. 1L, the sacrificial gate structure 130 has been removed from between the gate spacer layers 140. The view of FIG. 1L is taken further inward in the X direction than the view of FIG. 1K, such that the source/drain regions 146a-146d are not visible. Specifically, the view of fig. 1L is taken along the cutting line 1L of fig. 1K. Source/drain regions 146d/e coupled to the distal side of semiconductor nanostructure 107d and source/drain regions 146e coupled to the distal side of semiconductor nanostructure 107e are visible in fig. 1L. Removal of the sacrificial gate structure 130 includes removing the dielectric layers 132, 134, 136, and 138 via one or more etching processes.
Removal of the sacrificial gate structure may include first performing a planarization process, such as CMP, to level the top surfaces of the sacrificial gate layer 134 and the gate spacer layer 140. The planarization process may also remove portions of dielectric layer 136 and dielectric layer 138 and gate spacer layer 140 along sidewalls of dielectric layer 136 and dielectric layer 138 on sacrificial gate layer 134. Accordingly, the top surface of the sacrificial gate layer 134 is exposed.
Next, the sacrificial gate layer 134 may be removed in an etching process, thereby forming a recess. In some embodiments, the sacrificial gate layer 134 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 134 without etching the spacer layer 140. When the sacrificial gate layer 134 is etched, the sacrificial gate dielectric layer 132 (when present) may be used as an etch stop layer. The sacrificial gate dielectric layer 132 may then be removed after the sacrificial gate layer 134 is removed.
In fig. 1M, semiconductor nanostructure 107 is released by removing sacrificial semiconductor nanostructure 109. Sacrificial semiconductor nano-structure 109 is removed to release semiconductor nano-structure 107. The sacrificial semiconductor nano-structures 109 may be removed by a selective etching process using an etchant selective to the material of the sacrificial semiconductor nano-structures 109 such that the sacrificial semiconductor nano-structures 109 are removed without substantially etching the semiconductor nano-structures 107. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas comprises F 2 And the presence of HF,and the carrier gas may be an inert gas such as Ar, he, N 2 Combinations thereof, and the like. In some embodiments, the sacrificial semiconductor nanostructure 109 is removed and the semiconductor nanostructure 107 is patterned to form channel regions for both PFETs and NFETs.
In some embodiments, the semiconductor nanostructures 107 are reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping may be performed by an isotropic etching process selective to the semiconductor nanostructure 107. After the reshaping, the semiconductor nano-structure 107 may exhibit a dog-bone shape in which a middle portion of the semiconductor nano-structure 107 is thinner than a peripheral portion of the semiconductor nano-structure 107 along the X-axis direction.
In fig. 1N, after releasing the semiconductor nanostructures 107, the shell dielectric layer 124 of the isolation structures 122 is trimmed. Specifically, an etching process is performed to reduce the height of the shell dielectric layer 124 of the isolation structures 122. The etching process selectively etches the material of the shell dielectric layer 124 relative to the material of the core dielectric layer 126 and the semiconductor nanostructures 107. The etching process may include an anisotropic etching process that selectively etches in a downward direction. The etching may be timed to select the final height of the top surface 154 of the shell dielectric layer 124. Alternatively, the etching process may include a timed isotropic etching process. The etching process may include wet etching, dry etching, or other suitable etching process. The duration of the etching process may be selected to ensure that the shell dielectric layer 124 over the top surface 158 of the substrate 102 is completely removed. In some embodiments, portions of the shell dielectric layer may remain over the top surface 158 of the substrate 102.
After the etching process, the shell dielectric layer has a top surface 154 that is lower than the top surface 156 of the core dielectric layer 126. The top surface 154 of the shell dielectric layer 124 is below the lowermost semiconductor nanostructure 107 of each stack. In some embodiments, the top surface 154 of the shell dielectric layer 124 is lower than the top surface 158 of the substrate 102, as shown in fig. 1N, the top surface 154 of the shell dielectric layer 124 may be substantially flush with the top surface 160 of the trench isolation region 128.
Another result of the etching process of the shell dielectric layer 124 is that the shell dielectric layer 124 can be completely removed between the semiconductor nanostructures 107 and the core dielectric layer 126. Accordingly, at the processing stage shown in fig. 1N, there is a gap between the end of the semiconductor nanostructure 107 and the adjacent core dielectric layer 126. The gap between the ends of the semiconductor nanostructures 107 and the adjacent core dielectric layer 126 has a dimension in the Y direction between 2nm and 6nm, which is essentially the thickness of the shell dielectric layer 124 prior to etching. If the shell dielectric layer 124 is not completely removed, a gap may exist between the semiconductor nanostructures 107 and the shell dielectric layer 124.
In fig. 1O, an interfacial gate dielectric layer 162 has been deposited. An interfacial gate dielectric layer 162 is deposited on all exposed surfaces of the semiconductor nanostructure 107. An interfacial gate dielectric layer 162 surrounds the semiconductor nanostructure 107. The interfacial gate dielectric 162 may comprise a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. Interfacial gate dielectric layer 162 may comprise a relatively low K dielectric relative to a high K dielectric such as hafnium oxide or other high K dielectric material that may be used in the gate dielectric of a transistor. The high-K dielectric may comprise a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon oxide. The interfacial gate dielectric layer 162 may be formed by a thermal oxidation process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process. The interfacial gate dielectric layer 162 may have a thickness between 0.5nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interfacial gate dielectric layer 162 without departing from the scope of the present invention.
In fig. 1O, a high-K dielectric layer 164 has been deposited. The high-K dielectric layer 164 is deposited in a conformal deposition process. A conformal deposition process deposits a high-K dielectric layer 164 on the interfacial gate dielectric layer 162, on the top surface of the shell dielectric layer 124, and on the sidewalls of the core dielectric layer 126. A high K dielectric layer 164 is also deposited on the sidewalls of gate spacer layer 140. A high K gate dielectric layer 164 surrounds the semiconductor nanostructures 107. The high-K gate dielectric layer 164 has a thickness between 1nm and 3 nm. The high-K gate dielectric layer 164 fills the remaining gap between the interfacial gate dielectric layer 162 and the sidewalls of the core dielectric layer 126. The high-K dielectric layer comprises one layer orMultilayer dielectric materials, such as HfO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, titania, hafnia-alumina (HfO 2 -Al 2 O 3 ) Alloys, other suitable high-K dielectric materials, and/or combinations thereof. The high-K dielectric layer 164 may be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for high-K dielectric layer 164 without departing from the scope of the invention.
In fig. 1O, gate metal 166 has been deposited. Gate metal 166 is deposited on all exposed surfaces of high-K dielectric layer 164. Gate metal 166 substantially surrounds semiconductor nanostructure 107. Although gate metal 166 is shown as a single layer in fig. 1O, in practice gate metal 166 may include one or more of a conductive liner layer, a work function layer, and a gate fill layer that together form the gate metal. The gate metal may include one or more of Ti, tiN, ta, taN, al, cu, co, ru, W, au or other suitable conductive materials. The gate metal 166 may be deposited by PVD, ALD, or CVD. Other configurations, materials, and deposition processes may be used for gate metal 166 without departing from the scope of the invention.
In some embodiments, if the thickness of high-K dielectric layer 164 is insufficient to fill the gap between interfacial dielectric layer 162 and core dielectric layer 126, it is possible to deposit an amount of gate metal 166 in the region between semiconductor nanostructure 107 and core dielectric layer 126 not occupied by high-K dielectric layer 164. If the remaining gap is too small, gate metal 166 may not be deposited.
At the processing stage shown in FIG. 1O, transistors 103a-103e are substantially complete. The transistor 103a includes a semiconductor nanostructure 107a that extends between the source/drain regions 146a and serves as a channel for the stack of transistors 103 a. The gate metal 166 serves as a gate electrode surrounding the semiconductor nanostructure 107a. The transistor 103b includes a semiconductor nanostructure 107b that extends between the source/drain regions 146b and serves as a channel for the stack of transistors 103 b. The gate metal 166 serves as a gate electrode surrounding the semiconductor nanostructure 107b. The transistor 103c includes a semiconductor nanostructure 107c extending between the source/drain regions 146c and serving as a channel for the stack of transistors 103 c. The gate metal 166 serves as a gate electrode surrounding the semiconductor nanostructure 107c. The transistor 103d includes a semiconductor nanostructure 107d that extends between the source/drain region 146d and the source/drain region 146d/e and serves as a channel for the stack of transistors 103 d. The gate metal 166 serves as a gate electrode surrounding the semiconductor nanostructure 107d. The transistor 103e includes a semiconductor nanostructure 107e that extends between the source/drain regions 146d/e and the source/drain regions 146e and serves as a channel for the stack of transistors 103 e. The gate metal 166 serves as a gate electrode surrounding the semiconductor nanostructure 107e.
In fig. 1O, there is no break in gate metal 166 so that the gate electrodes of transistors 103a-103d are all shorted together. Although not shown in fig. 1O, in a further processing step, an etching process may be performed to electrically isolate portions of gate metal 166 to form electrically isolated gate electrodes for transistors 103a-103 d.
Fig. 1P is a side view of integrated circuit 100 at a stage of processing of fig. 1O, according to some embodiments. In fig. 1P, the width of the trench between fins 118a and 118b is dimension D 1 . Dimension D 1 May be between 20nm and 40 nm. The width of the trench between fins 118b and 118c is dimension D 2 . Dimension D 2 Between 40nm and 60 nm. Other values may be used for dimension D without departing from the scope of the invention 1 And D 2 。
Fig. 1P more clearly shows how high-K dielectric layer 164 is conformally deposited on both semiconductor nanoplatelets 107 and the sidewalls of core dielectric layer 126. Portions of high-K dielectric layer 164 grown on semiconductor nanostructures 107 are merged with portions of high-K dielectric layer 164 grown on sidewalls of core dielectric layer 126.
Fig. 1Q is an enlarged view of a portion of the integrated circuit 100 of fig. 1P, according to some embodiments. The view of FIG. 1Q is taken from block 1Q in FIG. 1P. FIG. 1Q shows interfacial gate dielectric layer 162 having a thickness dimension D 3 . Dimension D 3 Between 0.5nm and 2 nm. high-K gate dielectric layer 164 has a width dimension D 4 . Dimension D 4 Between 1nm and 3 nm. Semiconductor nanoplatelets 107 are separated from core dielectric layer 126 by a width dimension D 5 . Dimension D 5 Has a value between 2nm and 6 nm. Dimension D may be utilized without departing from the scope of the present invention 3 、D 4 And D 5 Other values of (2).
Fig. 1R is a further enlarged view of integrated circuit 100 corresponding to block 2R of fig. 1Q, in accordance with some embodiments. Fig. 1R shows gate metal 166 extending to a depth substantially equivalent to the top surface of semiconductor nanostructure 107 b. Near each semiconductor nanostructure 107, gate metal 166 has a corner region 167 where gate metal 166 reaches a point where high-K dielectric layer 164 grown from interfacial gate dielectric layer 162 meets the portion of high-K dielectric layer 164 grown from core dielectric layer 126. In some embodiments, the lowest point of gate metal in corner region 167 is substantially flush with the top surface of the corresponding semiconductor nanostructure 107.
Fig. 1S is an enlarged view of an integrated circuit 100 similar to fig. 1R but having a slightly different structure, according to some embodiments. In fig. 1S, corner regions 167 of gate metal 166 extend to a depth dimension D below the top surface of adjacent semiconductor nanostructure 107 6 . Dimension D 6 May have a value between 0nm and 1 nm. Dimension D may be utilized without departing from the scope of the present invention 6 Other values of (2). The depth to which corner regions 167 of gate metal 166 extend may be adjusted by adjusting the thicknesses of interfacial gate dielectric layer 162 and high-K gate dielectric layer 164. However, if corner region 167 extends to a depth of greater than 1nm below the top surface of semiconductor nanostructure 107, it may be difficult to maintain uniform gate metal extension and uniform device performance.
Fig. 1T is an enlarged plan view of the integrated circuit 100 of fig. 1P, taken along cut line 1T, according to some embodiments. Fig. 1T shows semiconductor nanostructures 107b extending in the X-direction between source/drain regions 146 b. Fig. 1T shows an interfacial gate dielectric layer 162 between the semiconductor nanostructure 107b and the gate metal 166 and between the semiconductor nanostructure 107b and the core dielectric layer 126. In some embodiments, the thickness of the interfacial gate dielectric layer is the same on opposite sides of the semiconductor nanostructure 107b adjacent to the core dielectric layer 126 and except for the gate metal 166. Fig. 1T also shows the internal spacers 144 that electrically isolate the gate metal 166 from the source/drain regions 146 b.
Fig. 2A-2H are perspective, cross-sectional, and plan views of integrated circuit 100 at various stages of processing according to some embodiments. Fig. 2A is a perspective view of integrated circuit 100 at a processing stage substantially corresponding to that shown in fig. 1M, in accordance with some embodiments. The integrated circuit 100 of fig. 2A differs from the integrated circuit 100 of fig. 1M in that the isolation structure 122 of fig. 2A has a different layer configuration than the isolation structure 122 of fig. 1M. Specifically, isolation structure 122 of fig. 2A has a first shell dielectric layer 170, a second shell dielectric layer 172, and a core dielectric layer 126. Accordingly, the isolation structure 122 of fig. 2A has a double shell dielectric layer.
The isolation structure 122 of fig. 2A may be formed at a processing stage of fig. 1C. A first shell dielectric layer 170 is conformally deposited on the sidewalls and bottom of the corresponding trench 120. The first shell dielectric layer 170 contacts the sidewalls of the substrate 102 at the bottom of the trench 120. In trench 120, first shell dielectric layer 170 is in contact with the sidewalls of substrate 102, with the sidewalls of semiconductor nanostructures 107, with the sidewalls of sacrificial semiconductor nanostructures 109, with the sidewalls of dielectric layer 110, and with the sidewalls of hard mask layer 112. .
The shell dielectric layer first shell dielectric layer 170 may be deposited by CVD, ALD, PVD or other suitable deposition process. The first shell dielectric layer 170 may be formed of a low-k dielectric material. The low-K dielectric material of the shell dielectric layer 170 may include SiN, siCN, siOC, siOCN or other suitable dielectric material. The first shell dielectric layer 170 may have a thickness between 0.5nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the first shell dielectric layer 170 without departing from the scope of the present invention. The first shell dielectric layer 170 may be referred to as a first dielectric liner layer.
A second shell dielectric layer 172 is conformally deposited over the first shell dielectric layer 170. The second shell dielectric layer 172 may be deposited by CVD, ALD, PVD or other suitable deposition process. The second shell dielectric layer 172 may be formed of a low-k dielectric material. The low-K dielectric material of the second shell dielectric layer 172 may include SiN, siCN, siOC, siOCN or other suitable dielectric material. The second shell dielectric layer 172 may have a thickness between 1.5nm and 5 nm. Other materials, deposition processes, and thicknesses may be used for the second shell dielectric layer 172 without departing from the scope of the present invention. The second shell dielectric layer 172 may be referred to as a second dielectric liner layer.
The core dielectric layer 126 may be deposited on the second shell dielectric layer 172 in the appropriate trench 120. The core dielectric layer 126 may fill the remaining portion of the trench 120 not filled by the shell dielectric layer 170 and the shell dielectric layer 172. The core dielectric layer 126 may be deposited by CVD, ALD, PVD or other suitable deposition process. The core dielectric layer 126 may be or include SiN, siCN, siOC, siOCN. Other dimensions, materials, and deposition processes may be used for the core dielectric layer 126 without departing from the scope of the present invention.
In some embodiments, the material of the first shell dielectric layer 170 is different than the material of the second shell dielectric layer 172. In some embodiments, the first shell dielectric layer 170 is either SiOC or SiOCN and the second shell dielectric layer 172 is either SiN or SiCN. In some embodiments, the first shell dielectric layer 170 is either SiN or SiCN, and the second shell dielectric layer 172 is either SiOC or SiOCN. In some embodiments, the core dielectric layer 126 and the first shell dielectric layer 170 may have the same material.
In fig. 2B, an etching process has been performed. The etching process selectively etches the first shell dielectric layer 170 relative to the second shell dielectric layer 172. The etching process may selectively etch in the lateral direction such that dielectric residues 174 from the first shell dielectric layer 170 remain between the semiconductor nanostructures 107 and the second shell dielectric layer 172.
In fig. 2C, an etching process has been performed. The etching process selectively etches the second shell dielectric layer 172 relative to the core dielectric layer 126. The etching process may selectively etch in the lateral direction such that dielectric residue 176 from the second shell dielectric layer 172 remains between the dielectric residue 174 and the core dielectric layer 126.
Fig. 2D is a view of integrated circuit 100 at a substantially similar processing stage as shown in fig. 1O, except that dielectric residues 174 and 176 of first shell dielectric layer 170 and second shell dielectric layer 172 are present between semiconductor nanostructures 107 and core dielectric layer 126. An interfacial gate dielectric layer 162, a high-K gate dielectric layer 164, and a gate metal 166 have been deposited. The formation of the transistors 103 a-103 d is substantially complete.
Fig. 2E is a side view of integrated circuit 100 at a substantially similar processing stage as shown in fig. 1P, except that dielectric residues 174 and 176 of first shell dielectric layer 170 and second shell dielectric layer 172 are present between semiconductor nanostructures 107 and core dielectric layer 126.
Fig. 2F is an enlarged view of a portion of the integrated circuit 100 of fig. 2E corresponding to block 2F in fig. 2E. Fig. 2F shows the vertical dimension D of high-K dielectric layer 164 impinging into dielectric residue 176 7 Vertical dimension D 7 Above the bottom surface of the adjacent semiconductor nanostructure 107b and similarly below the top surface of the adjacent semiconductor nanostructure 107 b. Vertical dimension D 7 May be between 0nm and 2nm, but other dimensions may be utilized without departing from the scope of the present invention.
Fig. 2G is an enlarged plan view taken along cut line 2G in fig. 2E, according to some embodiments. The view of fig. 2G is substantially similar to the view of fig. 1T, with dielectric residues 174 and 176 being present between semiconductor nanostructure 107 and core dielectric layer 126, rather than high-K dielectric layer 164 filling the space in fig. 1T. In addition, an interfacial gate dielectric layer 162 has been grown between the semiconductor nanostructure 107b and the dielectric layer 174, the portion of the interfacial gate dielectric layer 162 grown adjacent to the dielectric residue 174 being caused by diffusion, while the portion of the interfacial gate dielectric layer 162 located between the high-K dielectric layer 164 and the semiconductor nanostructure 107b is formed due to direct oxidation. Since portions of the interfacial gate dielectric layer 162 are grown differently, the interfacial gate dielectric layer 162 adjacent to the dielectric residue 174 has a thickness scaleCun D 8 Less than the thickness dimension D of the interfacial gate dielectric 162 adjacent to the high-K dielectric 164 9 。
Fig. 2H is an enlarged plan view taken along cut line 2H in fig. 2E, according to some embodiments. The cut line 2H does not pass through the semiconductor nanostructure 107. In contrast, fig. 2G shows how portions of gate metal 166 and interfacial gate dielectric 164 fill the space left by removing portions of first shell dielectric 170 and second shell dielectric 172. In addition, FIG. 2H shows offset dimension D of high-K dielectric layer 164 adjacent dielectric residues 174 and 176 in the X direction 10 . Dimension D 10 Lateral losses of the thickness of dielectric residues 174 and 176 are shown. Dimension D 10 May be between 0nm and 2 nm.
Fig. 3 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In fig. 3, integrated circuit 100 is at a processing stage corresponding to that shown in fig. 1J. However, the dielectric isolation structure 122 in fig. 3, the dielectric isolation structure 122 has a top surface that is higher than the top surface of the dielectric support element 141 on the trench isolation region 128. This height mismatch results in an asymmetric formation of source/drain regions 146. In particular, the source/drain regions 146 have a lateral extension D from the edge of the semiconductor nanostructure 107 on the side closest to the dielectric support element 141 11 . The source/drain regions 146 have a lateral extension dimension D from the edge of the semiconductor nanostructure 107 on the side closest to the isolation structure 122 12 . In some embodiments, D 11 Between 10nm and 20 nm. D (D) 12 Between 5nm and 10 nm. D (D) 12 Less than D 11 . This is different from the source/drain regions 146 of FIG. 1J, in which source/drain regions 146 of FIG. 1J, D 11 And D 12 Are substantially identical and the source/drain regions are substantially symmetrical. Other sizes and configurations may be utilized without departing from the scope of the present invention.
Fig. 4A is a perspective view of integrated circuit 100 according to some embodiments. The view of fig. 4A may correspond to a process step shortly after the view of fig. 1O. Specifically, an etching process has been performed. An etching process may be performed according to the patterned photolithographic mask to form trenches 180 in the integrated circuit 100. Trenches 180 are cut through gate metal 166, gate spacers 140, dielectric layer 150, source/drain regions 146, and other structures. Trenches are formed to electrically isolate gate metal 166 of adjacent transistor 103. This process may be referred to as a cut metal gate process. The etching process may include multiple etching steps or a single etching step. Trench 180 extends partially into core dielectric layer 126 of isolation structure 122. Accordingly, trenches 180 are formed between the semiconductor nanostructures 107 of adjacent transistors 103. In fig. 4A, the isolation structure 122 has a composition different from that shown in fig. 1O or fig. 2A. However, in practice, the isolation structure 122 of fig. 4A may be the same as the isolation structure 122 of fig. 1O or fig. 2A.
In fig. 4B, trench 180 has been filled with dielectric material 182. The dielectric material 182 may include one or more of SiO, siN, siON, siOC, siOCN or other suitable dielectric materials. Dielectric material 182 extends from the top surface of gate metal 166 down into core dielectric layer 126 to a level below the lowest semiconductor nanostructure 107. In some embodiments, the dielectric material 182 does not extend below a vertical level at the top of the substrate 102. The dielectric material 182 may have various configurations without departing from the scope of the invention. The dielectric material 182 may be deposited by CVD, ALD, PVD or other suitable deposition process. After forming the dielectric material 182, a CMP process may be performed to planarize a top surface of the integrated circuit 100.
Fig. 4C is a cross-sectional view of integrated circuit 100 taken further along the X-direction so that source/drain regions 146 are visible. The view of fig. 4C shows that trench 180 passes through source/drain regions 146 and dielectric layer 148. Specifically, dielectric material 182 is in contact with source/drain regions 146 and dielectric layer 148. The formation of trench 180 causes source/drain regions 146 to become asymmetric. Trench 180 and dielectric material 182 may serve as isolation between adjacent source/drain regions 146. In particular, the source/drain regions 146 have a lateral extension D from the edge of the semiconductor nanostructure 107 on the side closest to the dielectric support element 141 13 . Source electrodeThe/drain region 146 has a lateral extension dimension D from an edge of the semiconductor nanostructure 107 on a side closest to the isolation structure 122 14 . In some embodiments, D 13 Between 10nm and 20 nm. D (D) 14 Between 5nm and 10 nm. D (D) 14 Less than D 13 . This is different from the source/drain regions 146 of FIG. 1J, in which source/drain regions 146 of FIG. 1J, D 13 And D 14 Are substantially identical and the source/drain regions are substantially symmetrical. Other sizes and configurations may be utilized without departing from the scope of the present invention.
Fig. 4D is a cross-sectional view of integrated circuit 100 at the same processing stage as fig. 1B, in accordance with some embodiments. Fig. 4D clearly shows how dielectric material 182 extends down into core dielectric layer 126 and substantially stops on the surface of trench isolation structure 128. Accordingly, trench 180 is cut through high-K dielectric layer 164 but does not substantially attack trench isolation region 128. Other configurations of trenches 180 and dielectric material 182 may be utilized without departing from the scope of the invention.
Fig. 5 is a flow chart of a method 500 of forming an integrated circuit, according to some embodiments. The method 500 may utilize the structures, processes, and systems described with respect to fig. 1A-4D. At 502, the method 500 includes forming an isolation structure between a stacked first semiconductor nanostructure of a first transistor and a stacked second semiconductor nanostructure of a second transistor, the isolation structure including a core dielectric layer having a top surface above all of the first semiconductor nanostructure and the second semiconductor nanostructure and a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface below all of the first semiconductor nanostructure and the second semiconductor nanostructure. One example of a first transistor is the first transistor 103a of fig. 1O. One example of a first semiconductor nanostructure is the first semiconductor nanostructure 107a of fig. 1O. One example of a second transistor is the second transistor 103b of fig. 1O. One example of a second semiconductor nanostructure is the second semiconductor nanostructure 107b of fig. 1O. One example of an isolation structure is isolation structure 122a of fig. 1O. One example of a core dielectric layer is core dielectric layer 126 of fig. 1O. One example of a shell dielectric layer is shell dielectric layer 124 of fig. 1O. At 504, method 500 includes forming an interfacial gate dielectric layer in contact with the first semiconductor nanostructure and the second semiconductor nanostructure. One example of an interfacial gate dielectric is interfacial dielectric 162 of fig. 1O. At 506, method 500 includes forming a high-K gate dielectric layer in contact with sidewalls of the interfacial dielectric layer and the core dielectric layer. One example of a high-K gate dielectric layer is high-K gate dielectric layer 164 of fig. 1O.
Embodiments of the present invention reduce active area pitch and improve scaling of integrated circuit cell size (e.g., height). In some embodiments, isolation structures are formed between adjacent stacks of semiconductor nanostructures corresponding to channel regions of adjacent transistors. The isolation structure may have a shell dielectric layer and a core dielectric layer. Initially, the shell dielectric layer is in contact with the sides of the semiconductor nanostructure. However, the etching process completely removes the shell dielectric layer from between the core dielectric layer and the semiconductor nanostructure. Subsequently, a high-K gate dielectric layer is conformally deposited over the semiconductor nanostructure and the surface of the core dielectric layer. The result is that the high-K gate dielectric layer completely fills the space between the semiconductor nanostructure and the core dielectric layer. This helps control the profile of the subsequently deposited gate metal, preventing undesirable overlap between the gate metal and the source/drain regions. The result is an improved wafer yield and integrated circuits with improved performance.
In one embodiment, a device includes a semiconductor substrate, a first transistor including a plurality of first stacked channels over the semiconductor substrate, a second transistor including a plurality of second stacked channels over the semiconductor substrate, and an isolation structure including a core dielectric layer between the first stacked channels and the second stacked channels. The device includes a high-K gate dielectric layer on the channel of the first stack and the channel of the second stack and on sidewalls of the core dielectric layer between the channel of the first stack and the core dielectric layer and between the channel of the second stack and the core dielectric layer.
In some embodiments, the device includes an interfacial dielectric layer between the high-K gate dielectric layer and the first stacked channel, wherein the high-K gate dielectric layer and the interfacial dielectric layer completely fill a space between at least one of the first stacked channel and the core dielectric layer.
In some embodiments, the core dielectric layer extends vertically above all of the channels of the first stack and the channels of the second stack and below the top surface of the semiconductor substrate.
In some embodiments, the isolation structure includes a shell dielectric layer surrounding a lower portion of the core dielectric layer, wherein the shell dielectric layer does not extend as high as the core dielectric layer.
In some embodiments, the top surface of the shell dielectric layer is lower than the top surface of the semiconductor substrate.
In some embodiments, the high-K gate dielectric layer is in contact with a top surface of the shell dielectric layer.
In some embodiments, the device includes a gate metal over the channels of the first stack and the channels of the second stack and over the high-K gate dielectric layer over the channels of the first stack and the channels of the second stack, wherein the high-K gate dielectric layer forms corner portions adjacent to one of the channels of the first stack and the core dielectric layer, wherein the gate metal contacts corner portions of the high-K gate dielectric layer.
In some embodiments, the corner portions of the gate metal are located between at least one of the channels of the first stack and the core dielectric layer.
In some embodiments, the corner portions of the gate metal are at substantially the same vertical level as the top surfaces of the adjacent channels of the first stack.
In some embodiments, the interfacial dielectric layer has the same thickness on a first side of one of the channels of the first stack adjacent to the core dielectric layer as on a second side of the one of the channels of the first stack remote from the core dielectric layer.
In one embodiment, a method includes forming an isolation structure between a stacked first semiconductor nanostructure of a first transistor and a stacked second semiconductor nanostructure of a second transistor. The isolation structure includes a core dielectric layer having a top surface above all of the first and second semiconductor nanostructures and a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface below all of the first and second semiconductor nanostructures. The method includes forming a high-K gate dielectric layer in contact with sidewalls of the core dielectric layer.
In some embodiments, the method comprises: forming a shell dielectric layer on sidewalls of the first and second semiconductor nanostructures, and the shell dielectric layer having a top surface higher than all of the first and second semiconductor nanostructures; and etching the shell dielectric layer to remove the shell dielectric layer from the sidewalls of the first and second semiconductor nanostructures and recess a top surface of the shell dielectric layer to a level below all of the first and second semiconductor nanostructures.
In some embodiments, the method includes forming an interfacial dielectric layer in contact with the first semiconductor nanostructure and the second semiconductor nanostructure, wherein forming the high-K gate dielectric layer includes: a first portion of the high-K gate dielectric layer is deposited over the interfacial dielectric layer and a second portion of the high-K gate dielectric layer is deposited over the core dielectric layer at the location where the shell dielectric layer is removed.
In some embodiments, forming the high-K gate dielectric layer includes growing the high-K gate dielectric layer such that a first portion of the high-K gate dielectric layer merges with a second portion of the high-K gate dielectric layer.
In some embodiments, the method includes depositing a gate metal over and under the first semiconductor nanostructure and the second semiconductor nanostructure, and the gate metal is in contact with the first portion and the second portion of the high-K gate dielectric layer.
In some embodiments, the gate metal includes a corner portion in contact with the first portion and the second portion of the high-K gate dielectric layer at a corner region of the high-K gate dielectric layer, wherein the corner portion is at substantially the same level as a top surface of the uppermost first semiconductor nanostructure.
In some embodiments, the gate metal includes a corner portion in contact with the first portion and the second portion of the high-K gate dielectric layer at a corner region of the high-K gate dielectric layer, wherein the corner portion is below a top surface of the uppermost first semiconductor nanostructure.
In one embodiment, a device includes a semiconductor substrate, a first transistor including a plurality of stacked first semiconductor nanostructures over the semiconductor substrate corresponding to channel regions of the first transistor. The device includes a second transistor including a plurality of stacked second semiconductor nanostructures over the semiconductor substrate corresponding to channel regions of the second transistor. The device includes an isolation structure including a core dielectric layer between the first semiconductor nanostructure and the second semiconductor nanostructure, and the core dielectric layer has a top surface that is higher than all of the first semiconductor nanostructure and the second semiconductor nanostructure. The isolation structure includes a shell dielectric layer having a base portion surrounding a lower region of the core dielectric layer and having a top surface below all of the first and second semiconductor nanostructures, and a plurality of residue portions, each residue portion being located between the core dielectric layer and a respective one of the first and second semiconductor nanostructures.
In some embodiments, the shell dielectric layer includes a first shell dielectric layer directly on the core dielectric layer and a second shell dielectric layer directly on the first shell dielectric layer.
In some embodiments, the device includes a gate dielectric layer on the first semiconductor nanostructure and the second semiconductor nanostructure and on a top surface of the remainder of the shell dielectric layer.
The foregoing outlines features of a drop-on embodiment so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims (10)

1. A semiconductor device, comprising:
a semiconductor substrate;
a first transistor including a plurality of first stacked channels over the semiconductor substrate;
a second transistor including a plurality of second stacked channels over the semiconductor substrate;
An isolation structure comprising a core dielectric layer between the channels of the first stack and the channels of the second stack; and
a high-K gate dielectric layer on the first and second stacked channels and on sidewalls of the core dielectric layer between the first and second stacked channels and the core dielectric layer.
2. The semiconductor device of claim 1, comprising an interface dielectric layer between the high-K gate dielectric layer and the first stacked channel, wherein the high-K gate dielectric layer and the interface dielectric layer completely fill a space between at least one of the first stacked channel and the core dielectric layer.
3. The semiconductor device of claim 1, wherein the core dielectric layer extends vertically above all of the channels of the first stack and the channels of the second stack and below a top surface of the semiconductor substrate.
4. A semiconductor device according to claim 3, wherein the isolation structure comprises a shell dielectric layer surrounding a lower portion of the core dielectric layer, wherein the shell dielectric layer does not extend as high as the core dielectric layer.
5. The semiconductor device of claim 4, wherein a top surface of the shell dielectric layer is lower than a top surface of the semiconductor substrate.
6. The semiconductor device of claim 5, wherein the high-K gate dielectric layer is in contact with a top surface of the shell dielectric layer.
7. The semiconductor device of claim 1, comprising a gate metal over the first and second stacked channels and over the high-K gate dielectric layer under the first and second stacked channels, wherein the high-K gate dielectric layer forms a corner portion adjacent to one of the first stacked channels and the core dielectric layer, wherein the gate metal contacts the corner portion of the high-K gate dielectric layer.
8. The semiconductor device of claim 7, wherein the corner portion of the gate metal is located between at least one of the channels of the first stack and the core dielectric layer.
9. A method of forming a semiconductor device, comprising:
forming an isolation structure between a stacked first semiconductor nanostructure of a first transistor and a stacked second semiconductor nanostructure of a second transistor, the isolation structure comprising:
A core dielectric layer having a top surface above all of the first and second semiconductor nanostructures; and
a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface below all of the first and second semiconductor nanostructures; and
a high-K gate dielectric layer is formed in contact with sidewalls of the core dielectric layer.
10. A semiconductor device, comprising:
a semiconductor substrate;
a first transistor comprising a plurality of stacked first semiconductor nanostructures located over the semiconductor substrate corresponding to channel regions of the first transistor;
a second transistor comprising a plurality of stacked second semiconductor nanostructures located over the semiconductor substrate corresponding to channel regions of the second transistor;
an isolation structure comprising:
a core dielectric layer located between the first and second semiconductor nanostructures, and having a top surface higher than all of the first and second semiconductor nanostructures; and
a shell dielectric layer having:
a base portion surrounding a lower region of the core dielectric layer, and having a top surface below all of the first and second semiconductor nanostructures; and
A plurality of remnants, each remnants located between the core dielectric layer and a respective one of the first and second semiconductor nanostructures.
CN202310537785.5A 2022-05-13 2023-05-12 Semiconductor device and method of forming the same Pending CN116682823A (en)

Applications Claiming Priority (4)

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US63/342,008 2022-05-13
US63/415,561 2022-10-12
US18/165,853 US20230369396A1 (en) 2022-05-13 2023-02-07 Field effect transistor with dual layer isolation structure and method
US18/165,853 2023-02-07

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