CN117894350A - Boolean logic in-memory operation circuit based on 2T-2C ferroelectric memory cell - Google Patents

Abstract

The invention designs and provides an FRAM-based in-memory computing circuit, and belongs to the field of integrated circuits. A2T-2C-based FRAM in-memory computing circuit is designed, and OR Boolean logic operation can be realized in an FRAM cell. The invention also provides a 4T-2C structure which can realize OR operation in the 2T-2C FRAM storage unit. Based on the two structures, we can perform all boolean logic operations in FRAM, which is of great importance for breaking the "memory wall" and "power consumption wall" of von neumann architecture. The 2T-2C FRAM unit has the advantages of high reliability and radiation resistance, non-volatility, low power consumption, high reading and writing speed, compatibility with a CMOS process and the like, and is expected to be applied to brain-like chips, self intelligent chips and intelligent chips in the directions of military industry, aerospace and the like.

Description

Boolean logic in-memory operation circuit based on 2T-2C ferroelectric memory cell

Technical Field

The invention belongs to the field of integrated circuits, and relates to a Boolean logic in-memory operation circuit based on a 2T-2C ferroelectric memory cell.

Background

In recent years, with the continuous development of technologies such as artificial intelligence and the internet of things, various deep learning algorithms are layered, the demands on chip computing power are also continuously improved, and the traditional von neumann architecture cannot meet the increasingly huge data computing demands. In von neumann architecture, the storage and processing of data is separated, and the data is transferred between the memory and the processor through a data bus, which has several drawbacks. Firstly, the access speed of the memory is far less than the operation speed of the processor, so the operation speed of the whole system is limited by bandwidth, the actual calculation example of the processor is far lower than the theoretical calculation force, the requirements of the intelligent chip for quick calculation and accurate response are difficult to meet, and the problem is called as a memory wall problem. The speed of data transmission can be increased by increasing the bandwidth and clock frequency of the bus, thereby improving the performance of the processor to some extent, but at the same time, this results in large power consumption and integration cost, and the expandability thereof is also severely limited. Second, in von neumann architectures, where the memory module is separated from the computing module, data is frequently transferred between the memory module and the computing module, which can create significant transfer power consumption (70% of the overall power consumption), which is also known as a "power consumption wall" problem. For example, injeida's research report indicates that the power consumption for data transfer required for floating point operations is about 200 times the power consumption for data processing. The "memory wall" and "power consumption wall" problems described above are also referred to as bottlenecks of the von neumann architecture.

In order to break through the bottleneck of von neumann architecture, two new architectures of near-memory computing architecture and in-memory computing architecture are proposed, wherein the near-memory computing architecture increases the bandwidth of data through high-speed borrowing, three-dimensional stacking, on-chip cache increasing and other methods, and simultaneously reduces the distance between a processor and a memory to reduce power consumption. Two methods of adopting three-dimensional stacking technology and adding on-chip caching have been widely used in the industry. However, the near-memory architecture belongs to the von neumann architecture, the "memory wall" and the "power consumption wall" bottlenecks of the von neumann architecture can be relieved only by increasing the bandwidth and reducing the transmission distance between the memory module and the computing module, and the von neumann architecture bottlenecks cannot be fundamentally solved. Therefore, a brand new in-memory computing architecture is proposed in the industry, the in-memory computing architecture utilizes a memory to operate and process data, the data is not required to be called back and forth between a processor and the memory, the fusion of storage and computation is realized, and the bottleneck of a memory wall and a power consumption wall of the von Neumann architecture is hopefully broken through. The technology has wide application prospect in the intelligent chip because the in-memory calculation is expected to greatly improve the calculation speed and reduce the calculation power consumption.

Heretofore, various integrated memory architectures based on Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), flash memory (Flash), resistive random access memory (ReRAM), phase Change Memory (PCM), ferroelectric transistor (FeFET), magnetic memory (MRAM) have been developed, but they are still faced with various problems and challenges on an industrial scale. SRAM has the advantages of mature process and advanced process nodes, but belongs to volatile memories, and power failure can result in data loss. The memory and calculation integrated unit of the SRAM occupies larger area, which is unfavorable for the high integration and the memory and calculation chip with high calculation performance. DRAM is also a mature technology, and the memory cell area of DRAM is small, but it is a volatile memory like SRAM, and cannot save data in case of power failure. And because the DRAM adopts capacitance to store data, the DRAM needs to be refreshed periodically and has leakage phenomenon, and high-precision in-memory calculation is difficult to realize, the DRAM is widely applied to a three-dimensional stacked near-memory calculation architecture. The ReRAM has non-volatility, can save data under the condition of power failure, can realize a large-scale cross point array, and is one of potential chips for realizing the industrialization of an integrated chip in the future; however, the current ReRAM process is still not mature, and the ReRAM requires a larger programming voltage, so that advanced node manufacturing is difficult, the calculation accuracy in the multi-bit memory calculated in the ReRAM memory is poor (generally lower than 8 bits), and the robustness is poor. The phase change memory PCM is also a nonvolatile memory, and can realize a large-scale cross array, but PCM has large read-write power consumption, low read-write speed and poor durability. Fefets are non-volatile memories and can implement cross-point arrays, but the current technology is still not mature, and the data retention characteristics are poor, and the read-write endurance is poor. MRAM is a nonvolatile memory, and has advantages of high durability, high speed, low power consumption, etc., and the MRAM process is relatively mature and has good expansibility, but the ratio of the high resistance state and the low resistance state of MRAM is low (about 250%), and the reliability in multi-bit memory is low. Flash is a nonvolatile memory, the process is mature, the cost is low, and an in-memory computing chip for mass production is realized; however, flash still needs to be further improved in terms of scalability, and the programming time of Flash is long.

The invention provides an in-memory computing unit based on a 2T-2C ferroelectric memory (FRAM) unit for the first time, and designs a method and a time sequence for realizing Boolean logic operation in the FRAM in-memory computing unit. Compared with a DRAM and an SRAM, the FRAM is used as a nonvolatile memory, has the capability of storing data when power is lost, and is beneficial to low-power consumption design; moreover, the ferroelectric capacitor has no leakage problem, and compared with a DRAM, the FRAM in-memory calculation has better reliability. Compared with the rest nonvolatile memories used for in-memory calculation, the (ReRAM, PCM, MRAM, flash, feFET) FRAM memory has lower read-write power consumption than MRAM, flash and PCM, has faster read-write speed than flash, PCM, and has higher read-write times than flash, reRAM and PCM; besides, the FRAM based on the hafnium oxide film has the advantages of high compatibility with CMOS technology and high radiation resistance. Therefore, the 2T-2C ferroelectric unit in-memory computing structure provided by the invention has the advantages of high reliability, high tolerance, low power consumption and the like, and is expected to be applied to artificial intelligent chips and AI neural networks.

Disclosure of Invention

The invention designs and provides an in-memory computing unit architecture based on a capacitive ferroelectric memory cell FRAM, provides a method for realizing AND, OR and NOT Boolean logic operation in the FRAM in-memory computing unit, and carries out simulation verification on functions and time sequences of the method.

In order to realize high-reliability memory operation, the invention designs a 2T-2C-based FRAM memory operation unit which realizes non-volatile storage of data by using a ferroelectric capacitor. The ferroelectric memory internal operation structure is shown in figure 1, and consists of more than or equal to three 2T-2C FRAM units, wherein the units adopt ferroelectric capacitors with data complementation as reference units, and only one word line is activated at a time when the ferroelectric memory internal operation structure is used for storing; in doing in-memory computation, at least three word lines are activated at a time to add the data of the memory cells at BL (bit line) (as shown in FIG. 2). When writing data into a memory cell, the ferroelectric capacitor connected to the BLN (complementary bit line) is used as a reference cell, and the potential on the BLN is opposite to the potential of the BL, so that the value of the written reference cell is opposite to that of the calculated cell, the BLN is connected to one end of the latch-type sense amplifier as a reference voltage, and the BL is connected to the other end of the latch-type sense amplifier (the latch-type sense amplifier will compare the voltages at both ends, pull the voltage at one end of the high potential up to VDD, and pull the voltage at one end of the low potential down to 0). Taking three word lines as an example, as shown in fig. 2, W1, W2, W3 and three word lines are activated simultaneously during calculation, and a pulse is applied to the plate line PL to transfer all data stored in A1, B1 and C1 to BL, and all data stored in A2, B2 and C2 to BLN. Taking fig. 2 as an example, if the data 110 is written in A1, B1, C1, the data written in A2, B2, C2 is 001, the voltage at BL will be greater than the voltage at BLN after W1, W2, W3 is activated, the voltage on the BL bit line will be pulled up to VDD after amplification by the latch sense amplifier, the voltage at BLN will be pulled down to 0, and the BL result is VDD. It can be seen that for three inputs A, B, C, the output is 1 when there are 2 or 3 inputs of 1 and 0 when there are only 1 or 0 inputs of 1, since the complementary ferroelectric capacitors are used as references. Based on this, the expression of the arithmetic unit in the 2T-2C ferroelectric memory can be obtained:

Out＝A+B+C (1)

After simplification, can obtain

Thus, C corresponds to an enable signal that determines the type of operation, and by setting the value of C, we can implement or operation and AND operation. When C is 1, out=a+b; when C is 0, out=ab. Based on the FRAM in-memory operation unit shown in FIG. 1, the invention can realize Boolean logical OR and logical AND operation.

To implement all logic, no operation is required in addition to or and operations. In order to implement the non-operation in the FRAM in-memory operation unit, the present invention designs a 4T-2C unit as shown in FIG. 3. Two transistors and a word line WLN are added on the basis of a 2T-2C structure, and the ferroelectric capacitors originally connected with BL and BLN are respectively connected with BLN and BL through the two transistors controlled by the WLN, so that the non-logic of the calculation result can be written into the unit, and the non-operation is realized.

The structure of the complete FRAM in-memory computation unit, including NAND, NOR operations, is shown in FIG. 4, consisting of three 2T-2C units A, B, C and one 4T-2C unit D. Writing data to be calculated in AB and writing enabling signals for determining AB calculation type in C, then switching on all word lines WL1, WL2 and WL3 of the ABC unit, after calculation is completed on a bit line BL through a latch type sense amplifier, switching on a WLN word line of the 4T2C unit, connecting D1 to bit lines BLN and D2 to the bit line BL, and writing non-logic of an operation result into the 4T-2C unit by a matched plate line to realize non-or non-logic operation. When the data is to be read or the data is required to participate in operation, the word line WL is turned on to complete the calculation.

The number of FRAM in-memory computing units 2T-2C participating in the boolean logic computation may be plural, and is not limited to 3. A plurality of 2T-2C FRAM storage units can be mounted on a pair of BL, BLN, and the plurality of 2T-2C FRAM storage units can be called according to logic to be realized during calculation, and the structure and the operation flow for performing exclusive OR calculation are given below.

The structure of the exclusive nor calculation using FRAM is composed of 5 2T-2C units and 2 4T-2C units, and the calculation structure thereof is shown in fig. 5. The result of the exclusive nor calculation operates as: WL1 and WLN6 are first turned on and a and/> are written to the corresponding 2T-2C FRAM memory cells and 4T-2C FRAM memory cells, respectively

In the units, turning off WL1 and WLN6, turning on word lines WL2 and WLN7, writing B and into corresponding 2T-2C FRAM memory cells and 4T-2C FRAM memory cells respectively, turning off WL2 and WLN7, turning on WL3 and WL4, writing 0 in corresponding 2T-2C cells, turning off WL4, turning on WL5, writing 1 in corresponding 2T-2C cells, turning on WL1, WL2, WL3, calculating to obtain Z1=AB, turning off WL2 and WL3 after the signal on BL is stable, writing Z1 into the 2T-2C cells controlled by WL1, turning off WL1, turning on WL4, WL6, WL7, calculating to obtain/> to turn off WL6 and WL7, writing Z2 into the 2T-2C cells controlled by WL4,

And (3) turning off WL4, turning on WL1, WL4 and calculating WL5 to obtain so as to obtain a calculation result of A and B.

The result of the exclusive-or calculation operates as: firstly, opening WL1 and WLN6, writing A and/> into corresponding 2T-2C FRAM memory cells and 4T-2C FRAM memory cells respectively, closing WL1 and WLN6, opening word lines WL2 and WLN7, writing B and/> into corresponding 2T-2C FRAM memory cells and 4T-2CFRAM memory cells respectively, closing WL2 and WLN7, opening WL3 and WL4, writing 0 into corresponding 2T-2C cells, closing WL4, opening WL5, writing 1 into corresponding 2T-2C cells, opening WL1, WL3 and WL7, calculating to obtain/> , closing WL3 and WL7 after BL on-signal is stable, and writing Z1 into WL1

And in the 2T-2C unit controlled by the control method, WL1 is turned off, WL2, WL4 and WL6 are turned on, and then is calculated to obtain WL4 and WL6 which are turned off, Z2 is written into the 2T-2C unit controlled by the WL2, WL2 is turned off, WL1, WL2 and WL5 are turned on, and then is calculated to obtain the calculation result of A exclusive OR B.

The structure can realize AND or NOT basic operation, and can realize all Boolean logic operations including NAND, NOR, OR and XOR on the basis.

The invention has the beneficial effects that:

the invention designs and provides an FRAM-based in-memory computing unit, which can realize AND, OR and NOT logic operations and can realize all Boolean logic operations based on the AND, OR and NOT logic operations. Compared with other in-memory computing units, the FRAM in-memory computing unit provided by the invention has the advantages of high reliability, high tolerance, low power consumption and the like, and is expected to be applied to artificial intelligent chips and AI neural networks.

Drawings

Fig. 1 is a schematic diagram of a structure for implementing FRAM in-memory operations.

Fig. 2 is a schematic diagram of a FRAM cell architecture for implementing and, or in-memory, computation.

FIG. 3 is a schematic diagram of a 4T-2C cell architecture implementing non-logical operations.

Fig. 4 is a schematic diagram of a computational unit architecture in a FRAM memory for implementing nor, nand operations.

Fig. 5 is a FRAM in-memory operation structure implementing exclusive-nor logic.

Fig. 6 is a circuit diagram of the calculation base unit in FRAM memory for simulation of the first to sixth embodiments.

Fig. 7 is a waveform diagram of simulation results of the first embodiment.

Fig. 8 is a waveform diagram of simulation results of the second embodiment.

Fig. 9 is a waveform diagram of simulation results of the third embodiment.

Fig. 10 is a waveform diagram of simulation results of the fourth embodiment.

Fig. 11 is a waveform diagram of simulation results of the fifth embodiment.

Fig. 12 is a waveform diagram of simulation results of the sixth embodiment.

FIG. 13 is a circuit diagram of a 4T-2C FRAM non-logic operation unit.

Fig. 14 is a circuit diagram of a simulation performed in embodiment seven.

Fig. 15 is a waveform diagram of simulation results of embodiment seven.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following two specific experimental solutions will be used to further describe the beneficial effects of the present invention:

embodiment one:

Logic operations of "0" and "0" are performed in the FRAM in-memory computation unit. The circuit invokes three 2T-2C ferroelectric memory cells ABC and a latch-type sense amplifier as shown in fig. 6.

The specific operation flow is as follows: and respectively writing 000 into the A, B and C2T-2C ferroelectric units, simultaneously conducting the three word lines of A, B and C, applying a PL pulse signal to enable the three word lines to participate in calculation, then opening a sense amplifier enabling signal to obtain calculation results on BL and BLN, executing 'A and B' operation when C is 0, setting the calculated BL line to be low level, setting the calculated BLN to be high level, setting the calculation result to be 0, and setting the calculation result to be consistent with the theoretical result of '0 and 0' operation. The simulated waveforms are shown in fig. 7.

Embodiment two:

A logic operation of "0" or "0" is performed in the FRAM in-memory computing unit. The circuit invokes three 2T-2C ferroelectric memory cells ABC and a latch-type sense amplifier as shown in fig. 6.

The specific operation flow is as follows: and (3) respectively writing 001 into the A, B and C2T-2C ferroelectric units, conducting the A, B and C word lines simultaneously, applying a PL pulse signal to enable the A, B and C word lines to participate in calculation, then opening a sense amplifier enabling signal to obtain calculation results on BL and BLN, executing 'A or B' operation when C is 1, setting the calculated BL line to be low level, setting the BLN to be high level, and setting the calculation result to be 0 and conforming to the theoretical result of '0 or 0' operation. The simulated waveforms are shown in fig. 8.

Embodiment III:

Logic operations of "1" and "0" are performed in the FRAM in-memory computation unit. The circuit invokes three 2T-2C ferroelectric memory cells ABC and a latch-type sense amplifier as shown in fig. 6.

The specific operation flow is as follows: 100 is written into the three 2T-2C ferroelectric units A, B and C respectively, three word lines A, B and C are conducted simultaneously, PL pulse signals are applied to enable the three word lines A, B and C to participate in calculation, then sense amplifier enabling signals are turned on, calculation results are obtained on BL and BLN, when C is 0, the calculation of 'A and B' is executed, the calculated BL line is low level, the calculated BLN is high level, the calculation result is 0, and the theoretical result of the calculation of '1 and 0' is consistent. The simulated waveforms are shown in fig. 9.

Embodiment four:

A logic operation of "1" or "0" is performed in the FRAM in-memory computing unit. The circuit invokes three 2T-2C ferroelectric memory cells ABC and a latch-type sense amplifier as shown in fig. 6.

The specific operation flow is as follows: and writing 101 into the three 2T-2C ferroelectric units A, B and C respectively, conducting the three word lines A, B and C simultaneously, applying PL pulse signals to enable the three word lines A, B and C to participate in calculation, then opening sense amplifier enabling signals to obtain calculation results on BL and BLN, executing 'A or B' operation when C is 1, setting the calculated BL line to be high level, setting the BLN to be low level, and setting the calculation result to be 1 and conforming to the theoretical result of '1 or 0' operation. The simulated waveforms are shown in fig. 10.

Fifth embodiment:

Logic operations of "1" and "1" are performed in the FRAM in-memory computation unit. The circuit invokes three 2T-2C ferroelectric memory cells ABC and a latch-type sense amplifier as shown in fig. 6.

The specific operation flow is as follows: and respectively writing 110 into the A, B and C2T-2C ferroelectric units, simultaneously conducting the three word lines of A, B and C, applying a PL pulse signal to enable the word lines to participate in calculation, then opening a sense amplifier enabling signal to obtain calculation results on BL and BLN, executing 'A and B' operation when C is 0, setting the calculated BL line to be high level, setting the BLN to be low level, setting the calculation result to be 1, and setting the calculation result to be consistent with the theoretical result of '1 and 1' operation. The simulated waveform is shown in fig. 11.

Example six:

A logic operation of "1" or "1" is performed in the FRAM in-memory computing unit. The circuit invokes three 2T-2C ferroelectric memory cells ABC and a latch-type sense amplifier as shown in fig. 6.

The specific operation flow is as follows: and writing 111 into the three 2T-2C ferroelectric units A, B and C respectively, conducting the three word lines A, B and C simultaneously, applying PL pulse signals to enable the three word lines A, B and C to participate in calculation, then opening sense amplifier enabling signals to obtain calculation results on BL and BLN, executing 'A or B' operation when C is 1, setting high level on the calculated BL line, setting low level on BLN, setting the calculation result to be 1, and conforming to the theoretical result of '1 or 1' operation. The simulated waveform is shown in fig. 12.

Embodiment seven:

The nor gate operation is implemented in the FRAM in-memory computation unit ("0 or 0" negate). A circuit diagram of a 4T-2C FRAM computational cell implementing non-logic is shown in FIG. 13. The simulated FRAM or NOR (NAND) operation circuit diagram is shown in fig. 14, and three 2T-2C ferroelectric memory cells ABC, a 4T-2C non-logic operation unit and a latch type sense amplifier are called, so that the NOT, NOT and NAND logic operation can be realized.

The specific operation flow is as follows: 001 is written into ABC in three calculation units, then a corresponding word line of the ABC unit is opened, PL pulse signals are applied to read three data to calculate (the data written in C is 1, so that 0 or 0 calculation is performed), and after the data is amplified by a sense amplifier, BL is at a low potential, and BLN is at a high potential, so that a calculation result of 0 is obtained. And then opening a word line WLN of the 4T-2C unit, writing non-logic of a calculation result into the 4T-2C unit by a matched plate line, closing the WLN, then opening the word line WL, reading data in the 4T-2C unit by the matched plate line, amplifying the data by a sense amplifier, setting BL to be high potential, setting BLN to be low potential, obtaining data 1, realizing the calculation of '0' or '0' and then taking NOT by the operation, indicating that the 4T-2C unit has the function of taking NOT, realizing one-time or non-calculation by the simulation, and realizing the simulation result as shown in figure 15.

The examples described above represent only embodiments of the invention and are not to be understood as limiting the scope of the patent of the invention, it being pointed out that several variants and modifications may be made by those skilled in the art without departing from the concept of the invention, which fall within the scope of protection of the invention.

Claims (10)

1. An in-memory computing circuit based on ferroelectric memory (FRAM) 2T-2C units is characterized by comprising more than or equal to 3 2T-2C FRAM memory units, wherein at least three word lines of the 2T-2C units are activated simultaneously when logic operation is carried out, and the units participating in computation comprise 6 ferroelectric capacitors A1, A2, B1, B2, C1 and C2. One end of the 6 ferroelectric capacitors is connected with the plate line PL, the other end is connected with a pair of complementary bit lines BL, BLN through a switch transistor, the grid electrode of each switch transistor is connected with the word line WL, BL, BLN are respectively connected with two ends of the latch type sense amplifier, and the read-write operation of a group of 2T-2C ferroelectric capacitors is the same as the read-write operation of the FRAM 2T-2C ferroelectric capacitors.

2. The memory computing circuit based on FRAM 2T-2C units of claim 1, wherein a plurality of 2T-2C units can be mounted on a pair of bit lines BL, BLN, and different logic computations can be combined by calling different numbers of FRAM units.

3. The memory computation circuit of claim 1, wherein when writing data, the BL and BLN are opposite in potential, so that opposite data is written in two capacitors in the 2T-2C cell, the data written in the capacitor of one column is defined as the contrast data, and the data of the other column is defined as the storage/computation data.

4. The in-memory computing circuit based on FRAM 2T-2C cells of claim 1, wherein when three FRAM cells are called for in-memory computation, signals stored in C1, C2 are used as an enable signal, and when data stored in C1, C2 is 1, an a or B operation is performed; when the data stored in C1 and C2 is 0, the operation A and B is performed.

5. The FRAM 2T-2C cell based in-memory computational circuit of claim 1 wherein only one WL is activated at a time when reading data; when data is written, as long as the written data is the same, a plurality of WL (WL) can be activated simultaneously to write data into a plurality of 2T-2C units; in performing the calculations, a minimum of three WLs need to be activated simultaneously.

6. The invention discloses an in-memory computing circuit based on an FRAM 2T-2C unit, which is characterized in that a 4T-2C FRAM non-logic operation circuit is designed and comprises two ferroelectric capacitors A1 and A2 and four switching tubes, wherein one end of each of the A1 and A2 is connected with PL, and the other end of each of the A1 and A2 is connected with the sources of the two switching tubes. The grid electrode of one switching tube of A1 is connected with word line WL, the drain electrode is connected with BL, another switching tube grid electrode is connected with WLN, the drain electrode is connected with BLN; the grid electrode of one switching tube of A2 is connected with WL, the drain electrode is connected with BLN, the grid electrode of the other switching tube is connected with WLN, and the drain electrode is connected with BL.

7. The non-logic operation circuit based on the FRAM 4T-2C cell of claim 6, wherein the word line WLN of the word line 4T-2C cell is activated and the data on BL and BLN are written into the ferroelectric capacitors A1, A2 according to non-logic when the non-logic operation is performed; when data reading and writing and data calculation are performed, word lines WL of 4T-2C units are activated, and data is written into A1 and A2, data is read out or data is read out to participate in calculation.

8. The in-memory computing circuit based on the FRAM 2T-2C unit and the non-logic computing circuit based on the FRAM 4T-2C unit as claimed in claim 6 are characterized in that an in-memory computing unit of the FRAM for performing NAND or NOR is designed, and the unit needs to call 3 2T-2CFRAM units and 1 4T-2C units, so that the NAND or NOR computation of the FRAM can be realized.

9. The in-memory computing circuit based on the FRAM 2T-2C unit and the non-logic computing circuit based on the FRAM 4T-2C unit as claimed in claim 1 are characterized in that an in-memory computing unit for performing exclusive-OR and exclusive-OR is designed, and the in-memory computing unit needs to call 5 2T-2CFRAM units and 2 4T-2C units, so that the exclusive-OR and the exclusive-OR can be realized in the FRAM.

10. The FRAM 2T-2C cell-based in-memory computational circuit of claim 1 and the FRAM 4T-2C cell-based non-logic computational circuit of claim 6, wherein all boolean logic operations are implemented by combining the 2T-2C in-memory computational circuits and the 4T-2C non-logic computational circuits on a pair of bit lines with a corresponding timing scheme.