CN117881179A

CN117881179A - Semiconductor structure and forming method thereof

Info

Publication number: CN117881179A
Application number: CN202211216819.2A
Authority: CN
Inventors: 杨蒙蒙
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2024-04-12
Also published as: WO2024066450A1

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same, the method comprising: providing a laminated structure and an active region connected with the laminated structure; the active region divides the laminated structure into a first step region and a second step region arranged along a first direction; the first step region and the second step region comprise M initial step structures which are arranged at intervals along the first direction; sequentially etching the first i initial step structures far away from the active region in the first step region and the second step region simultaneously, and correspondingly forming M first step structures in the first step region and M first step structures in the second step region; the size of the first step structure in the third direction is sequentially reduced along the direction away from the active region; the size of the ith first step structure which is positioned in the first step region and the second step region and is far away from the active region is unequal in the third direction; i=1, 2 … M.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method of forming the same.

Background

Currently, a step (Staircase) structure is generally used to assist in realizing a stacking structure of a three-dimensional semiconductor device, so as to improve the integration level of the semiconductor device. However, for stacked three-dimensional semiconductor devices, both Bit Line (BL) and Word Line (WL) step structures face significant coupling problems.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

In a first aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, the method including:

providing a laminated structure and an active region connected with the laminated structure; the active region divides the laminated structure into a first step region and a second step region arranged along a first direction; the first step area and the second step area comprise M initial step structures which are arranged at intervals along the first direction;

sequentially etching the first i initial step structures far away from the active region in the first step region and the second step region simultaneously, and correspondingly forming M first step structures in the first step region and M first step structures in the second step region;

the size of the first step structure in the third direction is sequentially reduced along the direction away from the active region; the size of the ith first step structure, which is located in the first step region and the second step region and is far away from the active region, is unequal in the third direction; i=1, 2 … M; the first direction is parallel to the plane of the active region, and the third direction is perpendicular to the plane of the active region. In some embodiments, the method further comprises:

Etching the first step structures for multiple times along a second direction, and forming a plurality of second step structures which are stacked in sequence along the third direction in each first step structure; the size of the second step structure in the second direction sequentially increases from top to bottom along the third direction;

the second direction is parallel to the plane of the active region and intersects the first direction.

In some embodiments, the projected area of the laminated structure along the third direction is comb-shaped; the second step structures located at the connecting end part of each first step structure in the first step regions are interconnected along the projection region in the third direction and are connected with the active region; the second step structures located at the connecting end part of each first step structure in the second step region are interconnected along the projection region in the third direction and are connected with the active region; the laminated structure is formed by the following steps:

providing an initial laminated structure, wherein the initial laminated structure is positioned at two sides of the active area along the first direction;

forming a protective layer on the surface of the active region;

etching the initial laminated structure to form the initial step structure and an isolation groove which is positioned between two adjacent initial step structures and between the initial step structure and the active region; the isolation groove has an opening in the second direction.

In some embodiments, the method further comprises:

forming an isolation structure in the isolation groove;

and forming a barrier layer with a preset thickness on the surfaces of the M initial step structures and the isolation structures in the second step region.

In some embodiments, the first step structure is formed by:

forming a first photoresist layer on the surfaces of the first step region, the protective layer and the barrier layer;

etching part of the initial step structure, part of the barrier layer and part of the isolation structure for M times through the first photoresist layer, and forming M first step structures and etched isolation structures in the first step region and the second step region;

and trimming the first photoresist layer used in the i-1 th etching process before the i-th etching process, so that the first photoresist layer in the i-th etching process at least exposes the first i initial step structures in the first step region, the barrier layer on the surface of the i-th initial step structures in the second step region and the first i-1 initial step structures.

In some embodiments, etching a portion of the initial step structure and a portion of the barrier layer M times through the first photoresist layer, forming the M first step structures in both the first step region and the second step region, including:

and carrying out M-i+1 times of etching on the ith initial step structure far away from the active region in the first step region and the second step region along the direction close to the active region through the first photoresist layer, and forming M first step structures in the first step region and the second step region.

In some embodiments, the second step structure is formed by:

forming a second photoresist layer on the surfaces of the first step structure, the protective layer and the etched isolation structure;

etching the first step structure and the etched isolation structure for N-1 times through the second photoresist layer to form a second step structure and a residual isolation structure;

before the jth etching, trimming the second photoresist layer used in the jth etching process to enable the second photoresist layer in the jth etching process to at least expose the first j parts, far away from the connecting end parts, of each first step structure; j=1, 2 … N.

In some embodiments, the first step structure includes j parts sequentially arranged from right to left along the second direction, N-1 times of etching is performed on the first step structure through the second photoresist layer to form the second step structure, including:

and sequentially carrying out N-j times of etching on the j-th part far away from the connecting end part along the second direction to form the second step structure.

In some embodiments, after forming the second step structure, the method further comprises:

and removing the second photoresist layer and the protective layer.

In some embodiments, after removing the protective layer, the method further comprises:

forming a dielectric layer on the surfaces of the second step structure, the residual isolation structure and the active region;

etching the dielectric layer to form 2M x N etching holes; wherein each etching hole exposes one second step structure;

and forming a conductive column in the etching hole.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure comprising: a first step region, a second step region, and an active region located between the first step region and the second step region;

The first step area and the second step area comprise M first step structures which are sequentially arranged along a first direction, and the first step structures are connected with the active area;

the size of the first step structure in the third direction is sequentially reduced along the direction away from the active region; the size of the ith first step structure, which is located in the first step region and the second step region and is far away from the active region, is unequal in the third direction; i=1, 2 … M;

the first direction is parallel to any one direction in the plane of the active region, and the third direction is perpendicular to the intersecting plane of the active region.

In some embodiments, each of the first step structures includes N second step structures stacked in sequence along the third direction;

the size of the j-th second step structure in the third direction is equal to or different from the size of the j-th second step structure in the third direction;

the second direction is located in the plane of the active region and intersects the first direction.

In some embodiments, an ith one of the first step structures in the first step region includes (2 i-2) th to (2 i-1) th second step structures n+1 th second step structures; each second step structure has a preset size in the third direction;

the difference between the dimension in the third direction of the top surface of the ith first step structure, which is located in the first step region and is far away from the active region, and the dimension in the second step region and is far away from the active region, which is the dimension N times, is the preset dimension.

In some embodiments, the semiconductor structure further comprises an isolation structure;

the isolation structures are located between adjacent first step structures and between the first step structures and the active region.

In some embodiments, a projection area of the first step structure along the third direction is comb-shaped; the second step structures of the connecting end part of each first step structure in the first step region are interconnected along the projection region in the third direction and are connected with the active region; the second step structures of the connection end of each first step structure in the second step region are interconnected along the projection region in the third direction and connected with the active region.

In some embodiments, the semiconductor structure further comprises a dielectric layer and a conductive pillar;

the dielectric layer is positioned on the surfaces of the first step structure, the isolation structure and the active region;

the conductive posts are located in the dielectric layer and located on the surface of each second step structure.

According to the semiconductor structure and the forming method thereof, M first step structures are formed in the first step regions and the second step regions on two sides of the active region at intervals. Because M first step structures are arranged at intervals, the projection area of the whole formed step structure in the third direction can be reduced, so that the coupling effect between the step structures can be reduced, signal crosstalk is reduced, and the performance of the semiconductor structure is improved.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure;

FIGS. 2 a-2 l are schematic diagrams illustrating a semiconductor structure during formation according to embodiments of the present disclosure;

fig. 3 a-3 d are schematic views illustrating another semiconductor structure forming process according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Before describing the embodiments of the present disclosure, three directions describing the three-dimensional structure that may be used in the following embodiments are defined, and may include X-axis, Y-axis, and Z-axis directions, for example, in a cartesian coordinate system. The active region may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction of intersection (e.g., perpendicular) with the top and bottom surfaces of the active region is defined as a third direction, ignoring the flatness of the top and bottom surfaces. In the direction of the top surface and the bottom surface of the active region (i.e., the plane in which the active region is located), two directions intersecting each other (e.g., perpendicular to each other) are defined, for example, a direction in which the first step structures are arranged may be defined as a first direction, and the plane direction of the active region may be determined based on the second direction and the first direction. In the embodiment of the disclosure, the first direction, the second direction and the third direction may be perpendicular to each other, for example, the first direction may be defined as an X-axis direction, the second direction may be defined as a Y-axis direction, and the third direction may be defined as a Z-axis direction. In other embodiments, the first direction, the second direction, and the third direction may not be perpendicular.

An embodiment of the present disclosure provides a method for forming a semiconductor structure, and fig. 1 is a schematic flow chart of the method for forming a semiconductor structure provided in the embodiment of the present disclosure, as shown in fig. 1, the method for forming a semiconductor structure includes the following steps:

step S101, providing a laminated structure and an active area connected with the laminated structure; the active region divides the laminated structure into a first step region and a second step region arranged along a first direction; the first step region and the second step region each include M initial step structures arranged at intervals along the first direction.

In some embodiments, a memory cell array including a transistor structure, a capacitor structure, and the like is formed in an active region, a stacked structure is connected to the active region, and the stacked structure is used to form a word line step or a bit line step connected to the memory cell array. In the embodiment of the disclosure, the active region divides the stacked structure into a first step region and a second step region arranged along the first direction, wherein the areas of the first step region and the second step region may be equal in size, that is, the active region may divide the stacked structure into two equal areas. In other embodiments, the areas of the first step region and the second step region may also be unequal.

In the embodiment of the disclosure, the projection area of the laminated structure along the third direction is in a comb shape, the initial step structure forms a comb tooth part of the comb-shaped laminated structure, and the initial step structure extends along the second direction. The connection ends in the second direction of the M preliminary step structures located in the first step region are connected to each other, and the connection ends in the second direction of the M preliminary step structures located in the second step region are connected to each other. The connecting ends of the initial step structures in the first step region and the second step region are connected with the active region, and the connecting ends connected with the active region form the comb back part of the comb-shaped laminated structure.

The stacked structure (or the initial step structure) includes conductive layers and insulating layers alternately arranged in a third direction; the material of the conductive layer may be any one of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd), or may be any one of doped polysilicon, doped silicon, indium gallium zinc oxide and the like; the material of the insulating layer can be silicon oxide or silicon oxynitride. The insulating layer is used for isolating the adjacent conductive layers along the third direction and preventing electric leakage.

In embodiments of the present disclosure, each conductive layer in the stack structure may be connected to a column (or row) of word line structures (or gate structures) in the active region, forming a word line step. Alternatively, each conductive layer in the stacked structure may be connected to a row (or column) of bit line structures in the active region, forming a bit line step.

In an embodiment of the disclosure, the first step region includes M initial step structures arranged at intervals along the first direction, and the second step region includes M initial step structures arranged at intervals along the first direction; it should be noted that M may be determined according to the number of stacked memory cells in the semiconductor structure, where M may be any integer greater than 1, for example, M is 2, 3, or more.

Step S102, sequentially and simultaneously etching the first i initial step structures far away from the active region in the first step region and the second step region, and correspondingly forming M first step structures in the first step region and M first step structures in the second step region; the size of the first step structure in the third direction is sequentially reduced along the direction away from the active region; the i-th first step structure located in the first step region and the second step region away from the active region is not equal in size in the third direction.

In the embodiment of the present disclosure, sequentially etching the first i initial step structures far away from the active region in the first step region and the second step region at the same time refers to: and carrying out M-i+1 times of etching on the ith initial step structure far away from the active region in the first step region and the second step region along the direction close to the active region. i=1, 2 … M.

For example, when M is equal to 3, etching the 1 st initial step structure far from the active region in the first step region and the second step region for 3 times along the direction close to the active region, wherein the 1 st initial step structure is located at the outermost side of the first step region and the second step region; etching the 2 nd initial step structure far away from the active region in the first step region and the second step region for 2 times; and etching the 3 rd initial step structure far away from the active region in the first step region and the second step region for 1 time, wherein the 3 rd initial step structure is positioned at the innermost side of the first step region and the second step region.

In the embodiment of the disclosure, by sequentially and simultaneously etching the first i initial step structures far away from the active region in the first step region and the second step region, M first step structures located in the first step region and M first step structures located in the second step region are formed, and the sizes of the first step structures are sequentially reduced in the third direction along the direction far away from the active region. For example, when M is equal to 3, the sizes of the 3 first step structures located in the first step region sequentially decrease in the third direction in a direction away from the active region, and the sizes of the 3 first step structures located in the second step region sequentially decrease in the third direction.

In some embodiments, the top surface of the i-th first step structure located in the first step region away from the active region and the top surface of the i-th first step structure located in the second step region away from the active region are not equal in size in the third direction. For example, when M is equal to 3, the top surface of the 1 st first step structure located in the first step region away from the active region and the top surface of the 1 st first step structure located in the second step region away from the active region are not equal in size in the third direction; the top surface of the 3 rd first step structure located in the first step region and away from the active region is not equal to the top surface of the 3 rd first step structure located in the second step region and away from the active region.

According to the method for forming the semiconductor structure, the M first step structures which are arranged at intervals along the first direction are formed in the first step region and the second step region by etching the initial step structure in the laminated structure. Because M first step structures are arranged at intervals, the projection area of the whole formed step structure in the third direction can be reduced, so that the coupling effect between the step structures can be reduced, signal crosstalk is reduced, and the performance of the semiconductor structure is improved.

In addition, in the embodiment of the disclosure, the first step region and the second step region on both sides of the active region form a step structure, and the size of the ith first step structure, which is located away from the active region in the first step region and the second step region, in the third direction is not equal. Therefore, the wirings of adjacent layers can be arranged on both sides of the active region, so that the density of the wirings can be reduced, and the wiring arrangement of the semiconductor structure is simplified.

Fig. 2a to 2l are schematic structural views of a semiconductor structure forming process according to an embodiment of the present disclosure, and the forming process of the semiconductor structure according to the embodiment of the present disclosure is described in detail below with reference to fig. 2a to 2 l.

First, referring to fig. 2a to 2e, step S101 may be performed to provide a stacked structure and an active region connected to the stacked structure; the active region divides the laminated structure into a first step region and a second step region arranged along a first direction; the first step region and the second step region each include M initial step structures arranged at intervals along the first direction.

In some embodiments, the laminate structure may be formed by: providing an initial laminated structure, wherein the initial laminated structure is positioned at two sides of the active area along the first direction; forming a protective layer on the surface of the active region; etching the initial laminated structure to form an initial step structure and an isolation groove which is positioned between two adjacent initial step structures and between the initial step structure and the active region; the isolation groove has an opening in the second direction.

In the disclosed embodiments, the initial stack structure may be used to form a word line step or a bit line step.

As shown in fig. 2a, the initial stacked structure 11 is located at both sides of the active region 10 in the X-axis direction and is connected to the word line structure 101 (or gate structure) in the active region 10; the initial stacked structure 11 includes a plurality of steps 110 stacked in order in the Z-axis direction, the steps 110 including an insulating layer 112 and a conductive layer 111 on a surface of the insulating layer 112. The step 110 has a preset dimension L1 in the Z-axis direction.

As shown in fig. 2b, the initial stack structure 11 may also be connected to a bit line structure 102 in the active region 10.

Next, the embodiment of the present disclosure will be described with reference to a word line step as an example.

In some embodiments, the number of layers of the conductive layer 111 and the insulating layer 112 (or the step 110) in the initial stacked structure 11 may be set according to the number of layers of the memory cells in the semiconductor structure, and the word line structure 101 located in the same layer may draw out its signal through one conductive layer 111. In the embodiment of the present disclosure, the number of layers of the word line structure 101 in the active area 10 is 18 as an example.

With continued reference to fig. 2a and 2c, a dielectric material is deposited on the surface of the active region 10 to form a protective layer 12; the initial laminate structure 11 is etched using a dry etching technique to form a laminate structure 13. In practice, a mask layer (not shown) having a predetermined pattern is formed on the surface of the laminated structure, wherein the predetermined pattern exposes a portion of the initial laminated structure 11, and the exposed portion of the initial laminated structure 11 is etched through the mask layer to transfer the predetermined pattern into the initial laminated structure 11, thereby forming the laminated structure 13.

In embodiments of the present disclosure, the dielectric material may be any suitable inert material, such as photoresist, hard mask material. The protective layer 12 serves to protect the active region 10 from etching damage during subsequent formation of the word line step.

In the embodiment of the present disclosure, the stacked structure 13 includes 6 initial step structures 14 arranged in the X-axis direction and isolation grooves 15a between adjacent two of the initial step structures 14 and between the initial step structures 14 and the active region 10. The isolation groove 15a has one opening b in the Y-axis direction. The active region 10 divides the stacked structure 13 into a first step region a and a second step region B arranged in the X-axis direction, each of which includes 3 initial step structures 14, i.e., m=3 in the embodiment of the present disclosure.

It should be noted that, in the embodiment of the present disclosure, the number of layers of the word line structure 101 in the active area 10 is 18, and the total number of the initial step structures in the embodiment of the present disclosure is 2M, so that N (N is 18/2M) small step structures (corresponding to the second step structures formed subsequently) need to be formed in each subsequent initial step structure to electrically lead out each layer of the word line structure 101. Since M is 3, N is 3.

In the embodiment of the present disclosure, the connection ends c of the 3 initial step structures 14 located in the first step region a are connected to each other, the connection ends c of the 3 initial step structures 14 located in the second step region B are connected to each other, and each initial step structure 14 is connected to the active region 10 (i.e., the word line structure 101) through the connection ends c.

In some embodiments, after forming the initial step structure, the method of forming the semiconductor structure further comprises: forming an isolation structure in the isolation groove; and forming a barrier layer with a preset thickness on the surfaces of the M initial step structures and the isolation structures in the second step region.

As shown in fig. 2c and 2d, an isolation material is deposited in the isolation trench 15a, forming an isolation structure 15. The isolation material may be any insulating material, such as silicon oxide or silicon oxynitride. The isolation structure 15 may isolate adjacent initial step structures 14 to prevent leakage between the step structures.

It should be noted that, the isolation structures in the embodiments of the present disclosure are also formed outside the isolation grooves, only the isolation structures located in the isolation grooves are shown in the present disclosure, and the isolation structures outside the isolation grooves are not shown.

As shown in fig. 2e, a barrier layer material is deposited on the surfaces of the 3 initial step structures 14 in the second step region B and the isolation structures 15 located in the second step region B to form a barrier layer 16; the barrier material may be silicon oxide and the barrier layer 16 is used to achieve a certain level difference between the first step area a and the second step area B.

In the embodiment of the disclosure, the barrier layer 16 has a preset thickness L2, and when the etching selectivity of the barrier layer 16 with respect to the stacked structure 13 is equal to 1, the preset thickness L2 may be 3×l1 (i.e. n×l1).

In the embodiment of the disclosure, the barrier layer 16 is used to stop etching of the i-th first step structure located in the first step region a and away from the active region and the i-th first step structure located in the second step region B on different layers in the subsequent formation of the first step structure. And thus the size of the i-th first step structure far from the active region 10 in the Z-axis direction is not equal in the first step region a and the second step region B.

Next, referring to fig. 2f to 2l, step S102 may be performed to sequentially etch the first i initial step structures far from the active region in the first step region and the second step region simultaneously, and correspondingly form M first step structures in the first step region and M first step structures in the second step region.

In some embodiments, the first step structure is formed by: forming a first photoresist layer on the surfaces of the first step region, the protective layer and the barrier layer; etching part of the initial step structure, part of the barrier layer and part of the isolation structure for M times through the first photoresist layer, and forming M first step structures and etched isolation structures in the first step region and the second step region; and trimming the first photoresist layer used in the i-1 th etching process before the i-th etching process, so that the first photoresist layer in the i-th etching process at least exposes the first i initial step structures in the first step region, the barrier layer on the surface of the i initial step structures in the second step region and the first i-1 initial step structures.

In the embodiment of the disclosure, the first step region a and the second step region B each include 3 initial step structures 14 (i.e., m=3), and thus, a total of 3 etches are required to form 3 first step structures in the first step region and 3 first step structures in the second step region.

First, referring to fig. 2f and 2g, a 1 st longitudinal etching process is performed to form a first photoresist layer 17a on the surfaces of the first step region a, the protective layer 12 and the barrier layer 16. The surfaces of the first photoresist layer 17a in different regions may be in the same plane or different planes, and the thickness of the first photoresist layer 17a satisfies the thickness required for a plurality of longitudinal etching processes. The first photoresist layer 17a exposes the 1 st preliminary step structure 14 and the 1 st isolation structure 15 located in the first step region a, which are away from the active region 10, and exposes the barrier layer 16 located on the 1 st preliminary step structure 14 surface, which is away from the active region 10, and the barrier layer 16 located on the 1 st isolation structure 15 surface in the second step region B, and the exposed preliminary step structure 14, isolation structure 15, and barrier layer 16 are subjected to 1 st etching to form a first etched structure 14a located in the first step region a, and a first etched structure 14a located in the second step region B. Wherein, the first etched structure 14a in the first step region a includes an initial step structure 14 after the 1 st etching and an isolation structure 15 after the 1 st etching; the first etched structure 14a located in the second step region B includes an initial step structure 14 after the 1 st etching and an isolation structure 15 after the 1 st etching.

The etching depth of the 1 st longitudinal etching is 6×l1 (i.e., 2N steps). Since the etching selectivity of the barrier layer 16 with respect to the stacked structure 13 is equal to 1, l2=nl1=3×l1; therefore, at the time of the 1 st longitudinal etching, the size of the first etched structure 14a in the Z-axis direction is 3×l1 lower than the size of the first etched structure 14a in the second step region B in the Z-axis direction; that is, the first etched structure 14a located in the first step region a is 3 steps lower than the first etched structure 14a located in the second step region B.

Next, referring to fig. 2h, a 2 nd longitudinal etching process is performed, and before the 2 nd longitudinal etching process, the first photoresist layer 17a used in the 1 st longitudinal etching process is trimmed along a direction approaching the active region 10 to form a first photoresist layer 17b; so that the first photoresist layer 17B during the 2 nd longitudinal etching exposes the first etched structure 14a in the first step region a, and the 2 nd initial step structure 14 and the 2 nd isolation structure 15 away from the active region 10, and exposes the first etched structure 14a in the second step region B, the barrier layer 16 located on the surface of the 2 nd initial step structure 14 away from the active region 10, and the barrier layer 16 located on the surface of the 2 nd isolation structure 15; performing 2 nd longitudinal etching on the exposed first etched structure 14a, the initial step structure 14, the isolation structure 15 and the barrier layer 16; a second etched structure 14B in the first step region a is formed, and a second etched structure 14B in the second step region B is formed. The second etched structure 14b located in the first step area a includes 2 initial step structures located after the 2 nd etching and 2 isolation structures located after the 2 nd etching; the second etched structure 14B located in the second step region B includes 2 initial step structures after the 2 nd etching and 2 isolation structures after the 1 st etching.

In this embodiment, the etching depth of the 2 nd longitudinal etching is 6×l1 (i.e. 2N steps), and l2=nl1=3×l1, so that, during the 2 nd longitudinal etching, the dimension of the second etched structure 14B in the first step region a in the Z-axis direction is 3×l1 lower than the dimension of the second etched structure 14B in the second step region B in the Z-axis direction; that is, the second etched structure 14B located in the first step region a is 3 steps lower than the second etched structure 14B located in the second step region B.

Finally, performing a 3 rd longitudinal etching process, referring to fig. 2i, before the 3 rd longitudinal etching process, trimming the first photoresist layer 17b used in the 2 nd longitudinal etching process along a direction close to the active region 10 to form a first photoresist layer 17c, so that the first photoresist layer 17c in the 3 rd longitudinal etching process exposes the second etched structure 14b in the first step region a, and the 3 rd initial step structure 14 and the 3 rd isolation structure 15 far from the active region 10; and exposing the second etched structure 14b in the second step region, and a barrier layer 16 on the surface of the 3 rd initial step structure 14 remote from the active region 10 and a barrier layer 16 on the surface of the 3 rd isolation structure 15; and etching the exposed second etched structure 14B, the initial step structure 14, the isolation structure 15 and the barrier layer 16 for the 3 rd time to form a first step structure 18 and an etched isolation structure 19 which are alternately arranged in the first step region a in a direction away from the active region 10, and a first step structure 18 and an etched isolation structure 19 which are alternately arranged in the second step region B in a direction away from the active region 10.

In this embodiment, the etching depth of the 3 rd longitudinal etching is 3×l1 (i.e. N steps), and l2=3×l1; thus, after the 3 rd longitudinal etching, the difference in dimensions in the third direction between the top surface of the i-th first step structure 18 located in the first step region a away from the active region 10 and the top surface of the i-th first step structure 18 located in the second step region B away from the active region 10 is 3×l1, where i=1, 2, 3. That is, the i-th first step structure 18 located in the first step region a away from the active region 10 is 3 steps lower than the i-th first step structure 18 located in the second step region B away from the active region 10.

It should be noted that, since each layer of the word line structure needs to be connected through the step structure, the maximum layer number of the steps in the first step structure 18 needs to be equal to the layer number of the word line structure. Since the height of the ith first step structure 18 in the second step region B is greater than the height of the ith first step structure 18 in the first step region a, in the 3 rd process, the 3 rd initial step structure 14 far from the active region 10 in the second step region B is not required to be etched, and only the barrier layer 16 on the surface of the initial step structure 14 is required to be removed, so that the depth of the 3 rd etching process is n×l1 of the thickness of the barrier layer.

In some embodiments, after forming the first step structure, the method of forming a semiconductor structure further includes: the first photoresist layer 17c is removed. In the disclosed embodiment, the first photoresist layer 17c may be removed by a wet process (e.g., a strong acid etching using concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or a dry etching technique.

In some embodiments, after removing the first photoresist layer 17c, the method of forming a semiconductor structure further includes: etching the first step structures for multiple times along the second direction, and forming a plurality of second step structures which are stacked in sequence along the third direction in each first step structure; the second step structures sequentially increase in size in the second direction from top to bottom in the third direction.

In some embodiments, the second step structure is formed by: forming a second photoresist layer on the surfaces of the first step structure, the protective layer and the etched isolation structure; etching the first step structure and the etched isolation structure for N-1 times through the second photoresist layer to form a second step structure and a residual isolation structure; before the jth etching, trimming the second photoresist layer used in the jth etching process to enable the second photoresist layer in the jth etching process to at least expose the first j parts, far away from the connecting end parts, of each first step structure; j=1, 2 … N.

Referring to fig. 2j, the first step structure 18 includes 3 portions, d, e, f (portions divided by dotted lines in fig. 2 j) sequentially arranged from right to left in the Y-axis direction, and thus, 2 times of etching are required in total to form 3 second step structures corresponding to each of the first step structures.

Firstly, please continue with reference to fig. 2j, a 1 st lateral etching process is performed, and a second photoresist layer 20a is formed on the surfaces of the first step structure 18 and the etched isolation structure 19, wherein the second photoresist layer 20a exposes a first portion d far from the connection end portion; the exposed first portion d is subjected to a 1 st lateral etching to form a first sub-step structure 18a and a first sub-isolation structure 19a. Wherein, the etching depth of the 1 st lateral etching is L1 (i.e. 1 step).

Next, referring to fig. 2j to 2l, a 2 nd lateral etching process is performed, and before the 2 nd lateral etching, the second photoresist layer 20a used in the 1 st lateral etching process is trimmed along a direction near the connection end in the Y-axis direction, so as to form a second photoresist layer 20b; so that the second photoresist layer 20b during the 2 nd etching exposes the first sub-step structure 18a, the first sub-isolation structure 19a and the second portion e; the exposed first sub-step structure 18a, first sub-isolation structure 19a and second portion e are subjected to a 2 nd lateral etch and the second photoresist layer 20b is removed, forming a second step structure 181 and a remaining isolation structure 191. The etching depth of the 2 nd transverse etching is L1 (namely 1 step).

In the embodiment of the disclosure, the size of the j-th second step structure 181 in the Z-axis direction in the first step area a is equal to the size of the j-th second step structure 181 in the Y-axis direction in the Z-axis direction in the second step area B. For example, the 2 nd second step structure 181 located in the first step region a from bottom to top in the Z-axis direction is equal in size to the 2 nd second step structure 181 located in the second step region B from bottom to top in the Y-axis direction.

As shown in fig. 2l, after forming the second step structure 181, the method for forming a semiconductor structure further includes: the protective layer 12 is removed.

In the embodiment of the present disclosure, the second photoresist layer 20b and the protective layer 12 may be sequentially removed by a wet process (e.g., a strong acid etching using concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or a dry etching technique.

With continued reference to fig. 2l, after removing the protective layer 12, the method for forming a semiconductor structure further includes: depositing a dielectric layer material on the surfaces of the second step structure 181, the remaining isolation structures 191 and the active region 10 to form a dielectric layer 22; etching the dielectric layer 22 to form 2m×n etching holes (not shown); wherein, each etching hole exposes one second step structure 181; the conductive material is filled in the etching holes to form conductive pillars 21.

In the embodiment of the disclosure, the dielectric layer material may be any insulating material, for example, silicon oxide or silicon oxynitride. The conductive material may be any suitable metal material, for example tungsten, cobalt, copper, etc.

In the embodiment of the disclosure, the first step region and the second step region at two sides of the active region form a step structure, and the i-th first step structure located in the first step region and the second step region and far from the active region is unequal in size in the third direction, so that the j-th second step structure is different in height in the third direction from bottom to top along the third direction. Therefore, the wirings of adjacent layers can be arranged on both sides of the active region, so that the density of the wirings can be reduced, and the wiring arrangement of the semiconductor structure is simplified.

Fig. 3a to 3c are schematic structural views of another semiconductor structure forming process according to an embodiment of the present disclosure, and the semiconductor structure forming process according to the embodiment of the present disclosure is described in detail below with reference to fig. 3a to 3 c.

In some embodiments, after forming the structure as shown in fig. 2i, the method of forming a semiconductor structure may further include: the first step structure comprises j parts which are sequentially arranged from right to left along the second direction; and sequentially carrying out N-j times of etching on the j-th part far away from the connecting end part along the second direction to form a second step structure.

As shown in fig. 2i and 3a, the first step structure 18 includes 3 parts from right to left along the Y-axis direction, namely, a first part d, a second part e, and a third part f (as the part divided by the dotted line in fig. 3 a), and thus, a total of 2 times of etching is required to form 3 second step structures corresponding to each first step structure. Wherein the third portion f located in the first step region a and the third portion f located in the second step region B are not equal in size in the Y-axis direction; the first portion d located in the first step region a is not equal in size to the first portion d located in the second step region B in the Y-axis direction.

First, referring to fig. 3a, a 1 st lateral etching process is performed to form a third photoresist layer 23a on the surfaces of the first step structure 18 and the etched isolation structure 19, wherein a size of a portion of the third photoresist layer 23a located in the first step region a in the Y-axis direction is smaller than a size of a portion of the third photoresist layer 23a located in the second step region B in the Y-axis direction, such that the third photoresist layer 23a exposes a first portion d located in the first step region a having a size L3 greater than a size L4 of the first portion d located in the second step region B; the exposed first portion d is subjected to a 1 st lateral etching to form a second sub-step structure 18b and a second sub-isolation structure 19b. Wherein, the etching depth of the 1 st lateral etching is L1 (i.e. 1 step).

Next, referring to fig. 3B and 3c, a 2 nd lateral etching process is performed, before the 2 nd lateral etching process, the third photoresist layer 23a used in the 1 st etching process is trimmed in a direction close to the connection end (Y-axis direction) to form a trimmed third photoresist layer 23B, wherein a size of a portion of the third photoresist layer 23B located in the first step region a in the Y-axis direction is smaller than a size of a portion of the third photoresist layer 23B located in the second step region B in the Y-axis direction, such that the third photoresist layer 23B in the 2 nd lateral etching process exposes the second sub-step structure 18B, the second sub-isolation structure 19B, and the second portion e, in the disclosed embodiment, a size L5 of the second portion e located in the first step region a in the Y-axis direction and a size L6 of the second portion e located in the second step region B in the Y-axis direction are equal, and in other embodiments, the size of the second portion e located in the first step region a and the second step region B in the Y-axis direction may not be equal. The exposed second sub-step structure 18b, second sub-isolation structure 19b and second portion e are subjected to a 2 nd lateral etch and the third photoresist layer 23b is removed, forming a second step structure 181 and a remaining isolation structure 191. The etching depth of the 2 nd transverse etching is L1 (namely 1 step).

It should be noted that, as the trimming number of the third photoresist layer increases, the area of the third photoresist layer gradually decreases, and the area of the third photoresist layer exposed along the X-axis in the first step area a gradually increases (please refer to fig. 3a and 3 b), limited by the area of the active region 10, the area of the third photoresist layer exposed along the X-axis in the first step area a cannot exceed the area of the active region 10.

In the embodiment of the disclosure, please continue to refer to fig. 3c, the dimensions of the second step structure 181 in the first step region a and the second step region B in the Z-axis direction from bottom to top 1 st are not equal in the Y-axis direction, and the dimensions of the second step structure 181 in the first step region a and the second step region B in the Z-axis direction from bottom to top 3 rd are not equal in the Y-axis direction. Accordingly, the j-th second step structure 181 located in the first step region a from bottom to top in the Z-axis direction and the j-th second step structure 181 located in the second step region B from bottom to top in the Z-axis direction are distributed in a staggered manner in the X-axis direction.

As shown in fig. 3c, after forming the second step structure 181, the method for forming a semiconductor structure further includes: the protective layer 12 is removed. As shown in fig. 3d, after removing the protective layer 12, the method for forming a semiconductor structure further includes: depositing a dielectric layer material on the surfaces of the second step structure 181, the remaining isolation structures 191 and the active region 10 to form a dielectric layer 22; etching the dielectric layer 22 to form 2m×n etching holes (not shown); wherein, each etching hole exposes one second step structure 181; the conductive material is filled in the etching holes to form conductive pillars 21.

The method for forming a semiconductor structure provided in the embodiments of the present disclosure is similar to the method for forming a semiconductor structure in the above embodiments, and for technical features that are not disclosed in detail in the embodiments of the present disclosure, please refer to the above embodiments for understanding, and details are not repeated here.

By the method for forming the semiconductor structure provided by the embodiment of the disclosure, the j-th second step structure 181 located in the first step region a from bottom to top along the Z-axis direction and the j-th second step structure 181 located in the second step region B from bottom to top along the Z-axis direction are formed to be distributed in a staggered manner along the X-axis direction, so that the formed conductive pillars located in the first step region a and the second step region B are distributed in a staggered manner along the X-axis direction, the wiring density is reduced, and the wiring arrangement of the semiconductor structure is simplified.

The embodiment of the disclosure further provides a semiconductor structure formed by the method for forming a semiconductor structure in the above embodiment, please continue to refer to fig. 2l, the semiconductor structure includes: a first step region a, a second step region B, and an active region 10 located between the first step region a and the second step region B.

In some embodiments, a word line structure, a bit line structure, a gate structure, and the like are formed in the active region, and the first and second step regions a and B are connected to the active region 10.

With continued reference to fig. 2l, the first and second step regions a and B are connected to the word line structure 101 in the active region 10, and in other embodiments, the first and second step regions a and B are connected to the bit line structure in the active region 10.

With continued reference to fig. 2l, the areas of the first step area a and the second step area B may be equal in size. In other embodiments, the areas of the first step region and the second step region may also be unequal.

In some embodiments, please continue with fig. 2l, the first step region a and the second step region B each include M (e.g., M is 3) first step structures 18 sequentially arranged along the X-axis direction, and the first step structures 18 are connected to the active region 10; the first step structure 18 sequentially decreases in size in the Z-axis direction in a direction away from the active region 10.

In some embodiments, the i-th first step structure located in the first step region a and the second step region B away from the active region 10 is not equal in size in the third direction; i=1, 2 … M. For example, the 1 st first step structure 18 located away from the active region 10 in the first step region a and the second step region B are not equal in size in the Z-axis direction.

In the embodiment of the present disclosure, the first step structure 18 includes steps (not shown) stacked in sequence in the Z-axis direction, each of which includes a conductive layer (not shown) and an insulating layer (not shown) arranged in sequence in the Z-axis direction. The insulating layer is used for isolating the adjacent conductive layers along the third direction and preventing electric leakage.

In some embodiments, referring to fig. 2l, the first step structure 18 includes N (e.g., N is 3) second step structures 181 stacked sequentially along the Z-axis direction; the size of the j-th second step structure in the Z-axis direction is equal to that of the j-th second step structure in the Y-axis direction in the third direction. For example, the size of the 2 nd second step structure located in the first step region a from bottom to top in the Z-axis direction is equal to the size of the 2 nd second step structure located in the second step region from bottom to top in the third direction in the Y-axis direction.

In some embodiments, the i-th first step structure 18 in the first step region a includes (2 i-2) -th n+1 (e.g., N is 3) -th second step structure 181 to (2 i-1) -th N (e.g., N is 3) -th second step structure 181; each of the second step structures 181 has a preset dimension L1 in the Z-axis direction; the difference in dimension in the Z-axis direction between the top surface of the i-th first step structure 18 located in the first step region a away from the active region 10 and the top surface of the i-th first step structure 18 located in the second step region B away from the active region is 3 times a preset dimension L1; for example, the difference in size in the third direction between the top surface of the 1 st first step structure 18 located in the first step region a away from the active region 10 and the top surface of the 1 st first step structure 18 located in the second step region B away from the active region is 3 times the preset size L1.

In some embodiments, please continue to refer to fig. 2l, the semiconductor structure further includes an isolation structure (corresponding to the isolation structure 191 remaining in the above embodiments); isolation structures are located between adjacent first step structures 18, and between the first step structures 18 and the active region 10. The isolation structure may isolate adjacent first step structures 18, preventing leakage between the step structures.

In some embodiments, please continue to refer to fig. 2l, a projection area of the first step structure 18 along the Z-axis direction is comb-shaped; the second step structure 181 of the connection end c of each first step structure 18 in the first step region a is interconnected along the projection region in the Z-axis direction and connected with the active region 10; the second step structure 181 of the connection end portion c of each of the first step structures 18 in the second step region B is interconnected along the projection region in the Z-axis direction and is connected with the active region 10.

In some embodiments, referring to fig. 2l, the semiconductor structure further includes a dielectric layer 22 and a conductive pillar 21; dielectric layer 22 is located on the surfaces of first step structure 18, isolation structure and active region 10; the conductive pillars 21 are located in the dielectric layer 22 and on a surface of each second step structure 181.

The embodiment of the disclosure provides a semiconductor structure, wherein each of a first step region and a second step region comprises M first step structures which are arranged at intervals along a first direction. Because M first step structures are arranged at intervals, the projection area of the whole formed step structure in the third direction can be reduced, so that the coupling effect between the step structures can be reduced, signal crosstalk is reduced, and the performance of the semiconductor structure is improved.

In addition, in the embodiment of the disclosure, the dimensions of the ith first step structure located away from the active region in the first step region and the second step region are not equal in the third direction. Therefore, the wirings of adjacent layers can be arranged on both sides of the active region, so that the density of the wirings can be reduced, and the wiring arrangement of the semiconductor structure is simplified.

The embodiment of the disclosure further provides a semiconductor structure formed by the method for forming a semiconductor structure in the above embodiment, please continue with reference to fig. 3c, in which the first step structure 18 includes N (for example, N is 3) second step structures 181 stacked in sequence along the Z-axis direction; the size of the second step structure 181 in the Y-axis direction is not equal from bottom to top in the Z-axis direction in the first step region a and in the second step region B; the size of the second step structure 181 in the Y-axis direction of the 3 rd one from bottom to top in the Z-axis direction in the first step region a and the second step region B is not equal; the second step structure 181 of the 2 nd from bottom to top in the Z-axis direction in the first step region a and the second step region B are equal in size in the Y-axis direction.

Since the sizes of the second step structures 181 in the Y-axis direction of the ith from bottom to top in the Z-axis direction in the first step region a and the second step structures 181 in the second step region B are not equal in part, the second step structures 181 in the jth from bottom to top in the Z-axis direction in the first step region a and the jth second step structures 181 in the second step region B from bottom to top in the Z-axis direction are distributed in a staggered manner in the X-axis direction.

The semiconductor structure provided in the embodiments of the present disclosure is similar to the semiconductor structure in the above embodiments, and for technical features that are not fully disclosed in the embodiments of the present disclosure, reference is made to the above embodiments for understanding, and details are not repeated here.

The embodiment of the disclosure provides a semiconductor structure, which comprises a j-th second step structure located in a first step region from bottom to top along a Z-axis direction and a j-th second step structure located in a second step region from bottom to top along the Z-axis direction, wherein the j-th second step structure is distributed in a staggered manner along an X-axis direction, so that formed conductive columns located in the first step region and the second step region are distributed in a staggered manner along the X-axis direction, the wiring density can be reduced, and the wiring arrangement of the semiconductor structure is simplified.

In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.

The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of forming a semiconductor structure, the method comprising:

The size of the first step structure in the third direction is sequentially reduced along the direction away from the active region; the size of the ith first step structure, which is located in the first step region and the second step region and is far away from the active region, is unequal in the third direction; i=1, 2 … M; the first direction is parallel to the plane of the active region, and the third direction is perpendicular to the plane of the active region.

2. The method according to claim 1, wherein the method further comprises:

3. The method of claim 2, wherein a projected area of the laminate structure along the third direction is comb-shaped; the second step structures located at the connecting end part of each first step structure in the first step regions are interconnected along the projection region in the third direction and are connected with the active region; the second step structures located at the connecting end part of each first step structure in the second step region are interconnected along the projection region in the third direction and are connected with the active region; the laminated structure is formed by the following steps:

forming a protective layer on the surface of the active region;

4. A method according to claim 3, characterized in that the method further comprises:

forming an isolation structure in the isolation groove;

5. The method of claim 4, wherein the first step structure is formed by:

6. The method of claim 5, wherein etching a portion of the initial step structure and a portion of the barrier layer M times through the first photoresist layer, the M first step structures being formed in both the first step region and the second step region, comprising:

7. A method according to claim 3, wherein the second step structure is formed by:

8. The method of claim 7, wherein the first step structure comprises j portions arranged in sequence from right to left along the second direction, the first step structure is etched N-1 times through the second photoresist layer to form the second step structure, comprising:

9. The method of claim 8, wherein after forming the second step structure, the method further comprises:

And removing the second photoresist layer and the protective layer.

10. The method according to any one of claims 7 to 9, wherein after removing the protective layer, the method further comprises:

and forming a conductive column in the etching hole.

11. A semiconductor structure, comprising: a first step region, a second step region, and an active region located between the first step region and the second step region;

12. The semiconductor structure of claim 11, wherein each of the first step structures comprises N second step structures stacked in sequence along the third direction;

the size of the j-th second step structure in the third direction in the first step region is equal to or different from the size of the j-th second step structure in the second direction in the third direction in the second step region;

13. The semiconductor structure of claim 12, wherein an ith of the first step structures in the first step region comprises (2 i-2) th to (2 i-1) th second step structures; each second step structure has a preset size in the third direction;

14. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises an isolation structure;

15. The semiconductor structure of claim 14, wherein a projected area of the first step structure along the third direction is comb-shaped; the second step structures of the connecting end part of each first step structure in the first step region are interconnected along the projection region in the third direction and are connected with the active region; the second step structures of the connection end of each first step structure in the second step region are interconnected along the projection region in the third direction and connected with the active region.

16. The semiconductor structure of claim 15, further comprising a dielectric layer and a conductive pillar;