CN114613838A - Three-dimensional memory device, manufacturing method thereof and memory system - Google Patents

Three-dimensional memory device, manufacturing method thereof and memory system Download PDF

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Publication number
CN114613838A
CN114613838A CN202210190892.0A CN202210190892A CN114613838A CN 114613838 A CN114613838 A CN 114613838A CN 202210190892 A CN202210190892 A CN 202210190892A CN 114613838 A CN114613838 A CN 114613838A
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gate line
isolation
sub
line slit
forming
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许波
徐伟
刘思敏
郭亚丽
陈斌
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The application provides a three-dimensional memory device, a manufacturing method thereof and a memory system. The three-dimensional memory device includes: a stacked structure having a stacking direction and a first extending direction perpendicular to the stacking direction; an isolation pillar extending in the stacked structure along the stacking direction; and the first grid line gap structure penetrates through the laminated structure along the stacking direction and extends along the first extending direction, and comprises a plurality of sub-grid line gap structures arranged at intervals along the first extending direction, wherein one part of each sub-grid line gap structure extends into the isolation column.

Description

Three-dimensional memory device, manufacturing method thereof and memory system
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a three-dimensional memory device, a method for manufacturing the same, and a memory system.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.
In the 3D memory device of the NAND structure, the conductor layers of the selection transistor and the memory cell are provided in a stacked structure, and the memory cell is connected to the source electrode via the gate line slit structure. As the number of layers of the laminated structure is increased, the thickness of the laminated structure is increased, and the laminated structure has a larger aspect ratio. There are many process difficulties in replacing the gate of the stacked structure with a large aspect ratio.
Disclosure of Invention
Embodiments of the present application provide a three-dimensional memory device, including: a stacked structure having a stacking direction and a first extending direction perpendicular to the stacking direction; an isolation pillar extending in the stacked structure along the stacking direction; and the first grid line gap structure penetrates through the laminated structure along the stacking direction and extends along the first extending direction, and comprises a plurality of sub-grid line gap structures arranged at intervals along the first extending direction, wherein one part of each sub-grid line gap structure extends into the isolation column.
In some embodiments, the three-dimensional memory device includes at least two of the isolation pillars disposed at intervals along the first extending direction; and the two ends of the sub-grid line gap structure in the first extending direction respectively extend into the isolation columns.
In some embodiments, the stacked structure includes gate layers and insulating layers stacked alternately, the isolation pillar is made of an insulating material, and the three-dimensional memory device further includes a residual gate disposed between the isolation pillar and the sub-gate line gap structure, the gate layers and the residual gate being electrically isolated by the isolation pillar and the sub-gate line gap structure.
In some embodiments, the stacked structure has a first side and a second side along the stacking direction; the isolation column penetrates through at least one part of the laminated structure from the first side; the end surface area of the first grid line gap structure on the first side is smaller than that of the first grid line gap structure on the second side.
In some embodiments, the isolation pillars extend through the stacked structure.
In some embodiments, a dimension of the isolation pillar is greater than a dimension of the portion of the sub-gate line slit structure along a second extending direction perpendicular to the stacking direction and the first extending direction, and a maximum dimension of the portion of the sub-gate line slit structure along the second extending direction is greater than or equal to 150 nm.
In some embodiments, the three-dimensional memory device further includes at least two second gate line slit structures extending through the stacked structure and along the first extending direction, wherein the first gate line slit structure is located between the two second gate line slit structures.
In some embodiments, two isolation pillars are disposed between two adjacent sub-gate line gap structures.
In a second aspect, embodiments of the present application provide a method of fabricating a three-dimensional memory device. The manufacturing method comprises the following steps: stacking in a stacking direction to form a pre-fabricated stack structure, wherein the pre-fabricated stack comprises a first extension direction perpendicular to the stacking direction; forming an isolation pillar extending in the pre-fabricated laminate structure along the stacking direction; and forming a first gate line slit structure, wherein the first gate line slit structure includes a plurality of sub-gate line slit structures arranged at intervals along the first extending direction, and a portion of the sub-gate line slit structure extends into the isolation pillar.
In some embodiments, the step of forming the first gate line slit structure includes: forming a first gate line gap penetrating through the prefabricated laminated structure, wherein the first gate line gap comprises a plurality of sub-gate line gaps arranged at intervals along the first extending direction, and the sub-gate line gap comprises an isolation column groove formed by removing part of the isolation column; and forming the first gate line slit structure in the first gate line slit.
In some embodiments, the step of forming the pre-fabricated laminate structure comprises: alternately stacking a sacrificial layer and an insulating layer; the step of forming the isolation pillars includes: forming the isolation pillars by using an insulating material; the method further comprises the following steps after the step of forming the isolation column groove: replacing the sacrificial layer with a gate layer to form the prefabricated laminated structure into a laminated structure, and removing the gate material in the first gate line gap, wherein a residual gate is formed in the isolation column groove; in the step of forming the first gate line gap structure, the residual gate electrode and the laminated structure are electrically isolated by the isolation pillar and the first gate line gap structure.
In some embodiments, the step of forming the pre-fabricated laminate structure comprises: forming a first prefabricated laminated structure; and forming a second pre-fabricated laminate structure on one side of the first pre-fabricated laminate structure in the stacking direction; before the second prefabricated laminated structure is formed, forming a plurality of isolation columns, wherein the isolation columns penetrate through the first prefabricated laminated structure; and after the second prefabricated laminated structure is formed, forming the first grid line gap structure, wherein the area of the end face of the first grid line gap structure in the first prefabricated laminated structure is smaller than that of the end face of the first grid line gap structure in the second prefabricated laminated structure.
In some embodiments, the spacer pillars extend through the pre-fabricated laminate structure.
In some embodiments, a dimension of the isolation pillar is greater than a dimension of the portion of the sub-gate line slit structure along a second extending direction perpendicular to the stacking direction and the first extending direction, and a maximum dimension of the portion of the sub-gate line slit structure along the second extending direction is greater than or equal to 150 nm.
In some embodiments, the method further comprises forming a second gate line slit structure, wherein the second gate line slit structure extends along the first extending direction, and the first gate line slit structure is located between two of the second gate line slit structures.
In some embodiments, the method comprises: forming at least two isolation columns arranged at intervals along the first extending direction; the step of forming the plurality of sub-gate line slit structures includes: and separating the two isolation columns to form two adjacent sub-grid line gap structures.
The third aspect of the present application also provides a storage system including the aforementioned three-dimensional storage device; and the controller is electrically connected with the three-dimensional storage device and used for controlling the storage.
According to the three-dimensional memory device and the manufacturing method thereof provided by the embodiment of the application, by arranging the partial grid line gap structures into discontinuous multiple sections, the probability of distortion of the bottoms of the deep grooves of the grid line gap structures is reduced, and the stability of the whole laminated structure in the manufacturing process and the stability of the whole laminated structure in the formed three-dimensional memory device are ensured.
In some embodiments of the present application, the critical dimension at the discontinuous grid line slot structure joint is small. Particularly, the isolation holes are formed in the joints of the discontinuous grid line gap structures, and the isolation materials are filled in the isolation holes, so that the problem of interlayer electric leakage caused by the fact that the bottoms of the joints of the grid line gap structures are sharpened is solved, and the yield and the reliability of the three-dimensional storage device are improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic structural view of a three-dimensional memory device according to the related art;
FIG. 2 is a schematic cross-sectional view taken at A-A of FIG. 1;
FIG. 3 is a schematic cross-sectional view taken at B-B of FIG. 1;
FIG. 4 is a schematic flow chart diagram of a method of fabricating a three-dimensional memory device according to an embodiment of the present application;
fig. 5 to 12 are process diagrams of a method of manufacturing a three-dimensional memory device according to an embodiment of the present application;
fig. 13 is a schematic view of a semiconductor structure after forming a first gate line slit according to a method of manufacturing an exemplary embodiment of the present application;
fig. 14 is a schematic view of the semiconductor structure after forming a first gate line slit structure according to fig. 13;
FIG. 15 is a block diagram of a three-dimensional memory device according to an exemplary embodiment of the present application;
FIG. 16 is a block diagram of a three-dimensional memory device according to an exemplary embodiment of the present application; and
fig. 17 is a structural diagram of a storage system according to an exemplary embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.
It should be noted that in this specification, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not represent any limitation on the features. Accordingly, the first gate line slit structure discussed below may also be referred to as a second gate line slit structure without departing from the teachings of the present application. And vice versa.
In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, the size of the isolation pillars and the width of the gate line slit structure are not in proportion to actual production. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In one embodiment, in a manufacturing process of a three-dimensional NAND memory, a substrate is provided and a stacked structure is formed on the substrate, then a Channel Hole (CH) is formed in the stacked structure, and a Gate Line Slit (GLS) is formed after the Channel hole is formed, so as to form a Word-line (WL) opening by removing a sacrificial layer in the stacked structure through the Gate line slit, and then a Gate metal is filled in the Word-line opening to form a Gate layer. Manufacturers will strive to make the dimensions of three-dimensional memory devices smaller while memory capacity can be maintained or even increased.
Fig. 1 to 3 are schematic structural views of a three-dimensional memory device. As shown in fig. 1, the first gate line slit structure 3 includes a plurality of sub-gate line slit structures 4. The top feature size at the joint of the sub-gate line slit structure 4 is small, and the channel structures 7 on two sides can be arranged more densely under the condition of preventing the common source line 5 at the top of the laminated structure 2 from pressing the gap insulating layer 6 to be close to or even contact with the channel structures 7.
However, in some cases, as shown in fig. 2 and 3, the profile (profile) of the gate line slit structure 3 at the bottom of the stacked structure 2 may be tapered, so that the tapered portion of the gate line slit structure 3 may generate metal aggregation during the metal gate line replacement process to form a residual gate 10, which may result in a short circuit between two adjacent gate electrode layers 8 across the insulating layer 9 or even a failure of the three-dimensional memory device.
Fig. 4 shows a flow diagram of a method of fabricating a three-dimensional memory device according to an embodiment of the present application. As shown in fig. 4, the method 1000 for manufacturing a three-dimensional memory device may include at least the following steps S100, S200, and S300.
Step S100: and stacking along the stacking direction to form a prefabricated laminated structure. The prefabricated stacked structure has a first side and a second side opposite in the stacking direction, and the prefabricated stacked structure is extensible in a first extension direction and a second extension direction. The first and second extension directions may be perpendicular to each other. The first and second extension directions may be staggered with respect to the stacking direction, e.g. may be perpendicular.
Step S200: and forming the isolation columns. Illustratively, a plurality of isolation pillars may be formed. Specifically, the isolation pillars are arranged at intervals along the first extending direction. The spacers extend in the stacking direction in the prefabricated laminated structure. Exemplarily, the spacer columns extend from the first side to the second side, even throughout the pre-fabricated laminate structure from the first side to the second side.
Step S300: and forming a first grid line gap structure penetrating through the prefabricated laminated structure. Illustratively, the first gate line slit structure extends through the pre-fabricated laminate structure from the second side to the first side, i.e. in the stacking direction. The first gate line slit structure may include a plurality of sub-gate line slit structures disposed at intervals along the first extending direction. The sub-grid line gap structure is positioned between the corresponding pair of isolation columns, and two ends of the sub-grid line gap structure can respectively extend into one part of the isolation column. The position of the isolation pillar may be preset based on the position of the sub-gate line slit structure to be formed.
Illustratively, the manufacturing method 1000 may further include: a step S400 of forming a plurality of channel structures and the channel structures extending through the first pre-fabricated stack structure. Illustratively, step S400 may be performed before step S200.
According to some embodiments of the present application, the above-mentioned manufacturing method 1000 further includes a step of forming a step structure before forming the plurality of channel structures, and includes a step S500 of performing gate replacement. Step S500 may be performed after step S200 and before step S300. In this embodiment, the gate replacement is performed after the channel structure is formed.
The respective steps will be further described below based on the specific embodiments of the present application.
Implementation mode one
A specific process for performing the above-described manufacturing method 1000 according to the first embodiment is as follows.
S100
A first pre-fabricated laminate structure 20 may be formed on the substrate 10. As shown in fig. 5, a first pre-fabricated stacked structure 20 is disposed on a substrate 10 and includes sacrificial layers 21 and insulating layers 22 alternately stacked. In this embodiment, the number of layers that can be set is, for example, 32, 64, 96, 128 or more layers according to design requirements. Further, other numbers of sacrificial layers 21 and insulating layers 22 may also be stacked according to design requirements. In this embodiment, a 32-layer first preformed stack 20 may be formed, while in other embodiments 8, 16, or any no more than 32 layers of the first preformed stack 20 may be formed on the substrate 10 prior to forming a subsequent preformed stack on the first preformed stack 20.
In this embodiment, the substrate 10 may be a semiconductor substrate. For example, the substrate 10 may be a single crystal Silicon (Si) substrate, a single crystal Germanium (Ge) substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like. The substrate 10 may also be a P-type doped substrate or an N-type doped substrate. In other embodiments, the material of the substrate 10 may also be a semiconductor or a compound including other elements. For example, the substrate 10 may be a gallium arsenide (GaAs) substrate, an Indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like. It should be understood that suitable materials can be selected as the substrate 10 according to actual requirements, and the present application is not limited thereto.
The first pre-fabricated stacked structure 20 may be formed by deposition to form alternating sacrificial layers 21 and insulating layers 22. The deposition method of the sacrificial layer 21 and the insulating layer 22 may be Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Sputtering (Sputtering), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and the like. The deposition method may be selected according to actual requirements to form the first pre-fabricated stacked structure 20. For example, in the prefabricated stacked structure 20, the thicknesses of the plurality of sacrificial layers 21 may be the same or different, and the thicknesses of the plurality of insulating layers 22 may be the same or different, and the specific thicknesses may be set according to specific process requirements.
The sacrificial layer 21 and the insulating layer 22 have different etching selectivity, for example, the material of the insulating layer 22 may be an insulating dielectric material such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide, and the material of the sacrificial layer 21 may be silicon nitride. Furthermore, the first pre-fabricated stacked structure 20 may be a pre-fabricated stacked structure, which is subsequently subjected to a gate replacement process.
In fig. 5, the Z direction is the stacking direction, and the X direction is the first extending direction. The first pre-fabricated stacked structure 20 comprises a storage region and a plateau region (not shown). Illustratively, the present embodiment includes forming a step structure (not shown) based on the first pre-fabricated laminate structure 20 in the step region.
S200
A plurality of pillars 30 penetrating the first pre-laminated structure 20 are formed in step S200 (fig. 6). Taking the lower side as the first side and the upper side as the second side in fig. 6, the spacer pillars 30 may extend through the first pre-fabricated laminated structure 20 in the stacking direction or from the second side to the first side. Specifically, isolation holes (not shown) penetrating the first pre-fabricated laminated structure 20 may be formed in the first pre-fabricated laminated structure 20, and then the isolation holes may be filled with an insulating material to form the isolation pillars 30.
According to this embodiment, a patterned first mask layer (not shown) may be formed on the surface of the first pre-fabricated stacked structure 20 facing away from the substrate 10. The patterned first mask layer includes a first opening (not shown) therein corresponding to the isolation hole. In some embodiments, the first mask layer further comprises a second opening for etching a virtual channel hole (not shown). The positions of the isolation hole and the first opening etched by the subsequent etching process are determined by the design of the whole layout. Virtual channel structures can be formed in the virtual channel holes, and the positions of the virtual channel structures are arranged according to requirements. The dummy channel structure is used to support the insulating layer 22 during the gate replacement process to ensure that the first pre-fabricated stack 20 does not collapse during gate replacement. As an example, the position of the first opening may be made to correspond to the position of the first gate line slit structure 40 (fig. 11) to be formed.
Specifically, after the first opening exposes the first pre-fabricated stacked structure 20, the isolation hole is formed by removing a portion of the first pre-fabricated stacked structure 20 exposed by the first opening through a suitable etching process, such as dry etching or wet etching. Illustratively, a portion of the isolation hole is located in the substrate 10, but does not penetrate the substrate 10. The first mask layer may be removed after the isolation hole is formed. In this step, a plurality of isolation holes may be formed simultaneously, that is, the first mask layer may form a plurality of first openings, and the positions of the plurality of first openings respectively correspond to the positions of a plurality of subsequently formed isolation holes.
In one embodiment, the cross-sectional configuration of the isolation hole in the stacking direction may be circular or square.
After the isolation hole is formed, an insulating material is filled in the isolation hole to form the isolation pillar 30. The filled insulating material may include a dielectric layer of oxide, such as silicon oxide or the like.
In an exemplary embodiment, as shown in fig. 7 and 8, where fig. 8 is a cross-sectional view at C-C in fig. 7, the XY plane may be an extension plane of the first pre-fabricated stacked structure 20. The X direction shown in fig. 7 is the first extending direction, and the Y direction in fig. 8 is the second extending direction. Further, the extended face of the first preform stack 20 may not be planar, and may be a continuous face with undulations. The dimension d of the pillar 30 in the second extending direction is set to be greater than or equal to the width of the first gate line slit 400 to be formed, that is, greater than or equal to the width of the first gate line slit structure 40 (fig. 12) to be formed, so that the arrangement can ensure that the bottom-tapered portion of the sub-gate line slit structure 41 (fig. 12) can extend into the pillar 30.
S300
In this step, a first gate line slit structure 40 is formed in the first pre-fabricated laminate structure 20 therethrough. Illustratively, in the step of forming the first gate line slit structure 40, a first gate line slit 400 penetrating the first pre-fabricated stacked structure 20 along the Z-direction is formed first, and then the first gate line slit structure 40 may be formed in the first gate line slit 400.
Although the isolation pillars 30 are provided to prevent the residual drain gate 24 from contacting the first pre-fabricated stack structure 20, it is not excluded that the residual gate 24 is just removed in the individual product. Regardless of the residual gate electrode 24, in the present embodiment, a portion of the first gate line slit 400 extends into the isolation pillar 30, and then it is necessary to ensure that a portion of the first gate line slit structure 40 extends into the isolation pillar 30.
In the step of forming the isolation hole and the first gate line slit 400, the first pre-fabricated stacked structure 20 may be etched using a mask. The pattern of the mask forming the isolation hole and the pattern of the mask forming the first gate line slit 400 are determined according to the set position, and then the overlay accuracy of the two masks needs to be ensured. Referring to fig. 8, the first sub gate line slit 401 and the second sub gate line slit 402 are disposed at intervals, and two spacers 30 may be disposed therebetween. The two spacers 30 may have a space therebetween to ensure that the first pre-fabricated laminated structure 20 is integrally connected in the Y-direction.
Illustratively, the gap insulating layer 43 and the common source line 42 are sequentially formed in the first gate line slit 400. In other embodiments, the first gate line slit structure 400 may be obtained by filling the first gate line slit 400 with an oxide. The first gate line slit structure 40 may be designed as various composite structures as required, and may be connected to the substrate 10.
Referring first to fig. 11 and 12, as shown in fig. 11 and 12 (where fig. 12 is a schematic cross-sectional view at D-D in fig. 11), the first gate line slit structure 40 includes a plurality of sub-gate line slit structures 41 arranged at intervals in the X direction, wherein each sub-gate line slit structure 41 penetrates the first stacked structure 20A in the Z direction and extends into the isolation pillar 30 in the X direction. The remaining gates 24 in the first isolation pillar recesses 4011 are covered by the corresponding isolation pillars 30 and sub-gate line gap structures 41, and the other remaining gates 24 in the second isolation pillar recesses 4021 are covered by another pair of isolation pillars 30 and sub-gate line gap structures 41 and electrically isolated from the gate layer 23 of the first stacked structure 20A.
S400
In this step a plurality of channel structures 50 (fig. 8) are formed through the first pre-fabricated stack structure 20, for example a channel hole may first be formed through the first pre-fabricated stack structure 20 and then the channel structure 50 may be formed in the channel hole. The channel structure 50 may, for example, extend into the substrate 10. This step S400 may be performed before step S200.
The channel structure 50 may include a blocking layer, a memory layer, a tunneling layer, a channel layer, and an insulating fill layer (not shown) sequentially formed on sidewalls of the channel hole. It is understood that the insulating fill layer may serve as a core of the channel structure 50, while the channel layer, tunneling layer, memory layer, and barrier layer, in turn, form an annular layer structure surrounding the core.
Illustratively, a plurality of dummy channel structures (not shown) may also be formed in the first pre-fabricated stack structure 20. The dummy channel structure may have the same layer structure as the channel structure 50, or may be filled with an insulating material for supporting the first pre-fabricated stacked structure 20 to increase its strength. Illustratively, the dummy channel structure may be located at a step region (not shown) of the first pre-fabricated stacked structure 20.
S500
In this step S500, gate replacement is performed. Specifically, the first gate line slit 400 and the second gate line slit (not shown) may be formed first, and then the sacrificial interval between any adjacent two insulating layers 22 may be formed by removing the sacrificial layer 21 through the first gate line slit 400 and the second gate line slit, and then the gate layer 23 may be formed in the sacrificial interval through the first gate line slit 400 and the second gate line slit. The gate layer 23 is located between two adjacent insulating layers 22, and the pre-fabricated stacked structure may be formed into a stacked structure after gate replacement, where the stacked structure includes the insulating layers 22 and the gate layer 23 stacked alternately.
The step S500 may be performed after the first gate line slit 400 is formed and before the first gate line slit structure 40 is formed. When the material of the gate layer 23 is deposited after the sacrificial layer 21 is removed, a lot of material is also deposited in the first gate line slit 400, and then the material in the first gate line slit 400 needs to be removed. However, referring to fig. 7 and 8, when the first gate line slit 400 is formed by, for example, etching, the smaller the area of the cross section at a lower position in the Z direction, the narrower the notches of the first and second stud recesses 4011 and 4021. When removing material using, for example, a wet process, the material in the narrow area may not be cleaned and conductive material remains, i.e., the gate 24 remains as shown in fig. 9 and 10.
As shown in fig. 9, the residual gate 24 is completely located in the first spacer groove 4011 or the second spacer groove 4021 without protruding from the notch in the X direction. Then, a portion of the first gate line slit structure 40 to be formed may extend into the pillar 30.
Illustratively, referring to fig. 9 and 10, in any cross section of the spacer 30 in the Z direction, the opening dimension, i.e., the maximum dimension a, of the first spacer recesses 4011 or the second spacer recesses 4021 in the Y direction is greater than or equal to 150 nm. Illustratively, a may be greater than 200nm, further, greater than 230 nm. Specifically, it is ensured that the maximum dimension a of the first spacer recesses 4011 or the second spacer recesses 4021 in the Y direction at the cross section at the lowermost position satisfies the condition to ensure that at least a portion of the conductive material in the first spacer recesses 4011 or the second spacer recesses 4021 can also be removed.
In step S300, a gap dielectric material, such as oxide, may be selected to fill the first gate line gap 400 and the second gate line gap (not shown) to form the gap insulating layer 43. Specifically, the same material as the insulating layer 22 may be selected for filling. As an example, the remaining gate electrode 24 within the column recess 4011 may be encapsulated, i.e., isolated from the gate line layer 23, while the gap insulating layer 43 is filled into the first gate line slit 400 and the second gate line slit (not shown).
As shown in fig. 8, the first gate line slit 400 extends in the first extending direction, and includes a plurality of sub gate line slits 401/402 spaced apart in the first extending direction. Each sub-grid line slit structure 401/402 is disposed between a pair of the pillars 30, and a portion of the first pre-fabricated laminate structure 20 between two pairs of the pillars 30 is retained.
In fig. 8, the left-hand separator column 30 belongs to the left-hand pair of separator columns (not all shown), and the right-hand separator column belongs to the right-hand pair of separator columns (not all shown). The joint of the first sub-gate line slit 401 extends into the right spacer 30, and specifically, a portion of the right spacer 30 is removed during the formation of the gate line slit 400 to form a first spacer groove 4011. Similarly, the second sub gate line slit 402 includes a second spacer groove 4021.
In this embodiment, before the first pre-fabricated stacked structure 20 is etched to form the first gate line slit 400 penetrating through the first pre-fabricated stacked structure 20, a patterned second mask layer (not shown) may be formed on a surface of the first pre-fabricated stacked structure 20 facing away from the substrate 10, where the patterned second mask layer includes a second opening corresponding to the first gate line slit 400, and a vertical projection of the second opening on the first pre-fabricated stacked structure 20 overlaps with a position of the first gate line slit 400.
Illustratively, the second mask layer further includes a third opening having substantially the same shape and position as the second gate line slit (not shown) to be formed. The second gate line gaps extend along the first extending direction, and the first gate line gap is located between the two second gate line gaps in the second extending direction.
Specifically, the first gate line slit 400 is formed by performing a suitable etching process, such as dry etching or wet etching, on the second opening to remove a portion of the first pre-fabricated stacked structure 20 exposed by the second opening, and the first gate line slit structure 40 formed by etching exposes the substrate 10. Illustratively, the second gate line slit and the first gate line slit 400 divide a storage region of the three-dimensional memory device into a plurality of block storage regions and finger storage regions, and the second mask layer may be removed after the first gate line slit structure 400 is formed.
Next, the sacrificial layer 21 may be removed through the first gate line slit 400 and the second gate line slit to form a sacrificial space between the adjacent insulating layers 22. Illustratively, the sacrificial layer 21 and the insulating layer 22 include silicon nitride and silicon oxide, respectively, a phosphoric acid solution may be used as an etchant in the wet etching, and an etchant in the isotropic dry etching includes one or more of CF4, CHF3, C4F8, C4F6, and CH2F 2. In the etching step, the first gate line slit 400 and the second gate line slit are filled with an etchant. The sacrificial layer 21 is exposed to the first gate line slit 400 and the second gate line slit and is contacted to an etchant. Due to the selectivity of the etchant, the etching process removes the sacrificial layer 21 relative to the insulating layer 22 to form sacrificial spacers.
Then, a conductive material may be filled in the sacrificial gap through the first gate line slit 400 and the second gate line slit to form the gate layer 23. The gate layer 23 may be formed in the sacrificial spacer using a deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the gate layer 23 may be tungsten, cobalt, copper, aluminum, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof, which may be selected according to the actual situation.
Reference is made to fig. 11 and 12, wherein fig. 12 is a schematic cross-sectional view at D-D in fig. 11. The sidewalls of the first gate line slit 400 may also be hung with some conductive material during the formation of the gate layer 23. After the gate layer 23 is formed, the conductive material on the sidewall of the first gate line slit 400 needs to be removed. Since the sub-gate line slit 401/402 is too narrow at the junction at the deeper position, some conductive material in the pillar trench 4011/4021 is difficult to remove cleanly, and a residual gate 24 is formed. At the shallower locations of sub-gate line gaps 401/402, there may be no residual conductive material, i.e., residual gate 24 may extend a distance from the lower side to the upper side. However, at any cross section in the Z direction, a portion of the sub-gate line slit structure 41 extends into the isolation pillar 30.
In some embodiments, as shown in fig. 13, the first/second sub-gate line slits 401/402 have upper ends extending deeper into the pillars 30 and lower ends extending shallower into the pillars 30 in the X direction. Illustratively, it is required to ensure that the maximum dimension of the lower ends of the first spacer grooves 4011/the second spacer grooves 4021 in the Y direction is not less than 150 nm. In other words, due to the characteristics of the etching process, taking the XY plane as the projection plane, the area of the opening at the upper end of the first grating sub-line slit 401/the second grating sub-line slit 402 is larger than the area S1 at the bottom end, that is, the area of the opening at the upper end of the first grating sub-line slit 400 is larger than the area at the bottom end thereof.
Based on the semiconductor structure shown in fig. 13, after the first pre-fabricated stacked structure 20 is formed into the stacked structure 20A, the first gate line slit structure 40 is formed in the first gate line slit 400. As shown in fig. 14, the size of the whole upper end of the first gate line slit structure 40 in the Y direction is large, and the gate material is removed cleanly. Further, the area S2 of the end of the sub-gate line slit structure away from the substrate 10 is approximately equal to the top opening of the original first/second sub-gate line slits 401/402, which is mainly to trim the top end of the first gate line slit structure 40 by using a chemical mechanical polishing process after it is formed. The area of one end of each sub-gate line slit structure near the substrate may be slightly smaller than the area S1 of the bottom end of the original first/second sub-gate line slits 401/402, which is occupied by the possible residual gate. In summary, after the semiconductor structure shown in fig. 14 is formed from the semiconductor structure shown in fig. 13, the first gate line slit structure 40 in fig. 14 has a smaller end surface area on the first side than on the second side, wherein the first side refers to the lower side shown in fig. 13 and the second side refers to the upper side shown in fig. 13.
In the embodiment, the isolation pillar 30 is arranged in advance, so that the joint of the sub-gate line gap structure 41 and the gate layer 23 of the first prefabricated stacked structure 20 are completely isolated by the isolation pillar 30. And then the residual gate 24 possibly remained at the sub-gate line gap structure 41 cannot contact the gate layer 23, so that the leakage between the stacked gate layers 23 through the residual gate 24 is avoided.
Second embodiment
In the manufacturing method for a three-dimensional memory according to the second embodiment, a first pre-fabricated stacked structure 20 is first formed on a substrate 10, and a second pre-fabricated stacked structure is formed on the first pre-fabricated stacked structure 20 in step S100. Illustratively, a step structure (not shown) is formed in the step region based on the first and second pre-fabricated laminate structures 20 and 20.
Next, a plurality of isolation pillars 30 are formed and the isolation pillars 30 penetrate the first and second pre-fabricated laminated structures 20 and 200. Illustratively, the isolation hole may be formed after the second pre-fabricated laminate structure is formed and the isolation pillar 30 may be formed in the isolation hole. For example, a lower spacer column may be formed through the first pre-fabricated laminate structure 20 in the stacking direction after forming the same, and then an upper spacer column may be formed through the second pre-fabricated laminate structure after forming the second pre-fabricated laminate structure. The upper and lower spacers have the same position in the cross section in the stacking direction, and are connected to form the spacer 30.
Illustratively, the manufacturing method may further comprise the step of forming a plurality of channel structures, wherein the formed channel structures extend through the first pre-fabricated laminate structure 20 and the second pre-fabricated laminate structure. In some embodiments, after forming the first prefabricated laminated structure 20, a lower channel hole penetrating the first prefabricated laminated structure 20 in the stacking direction may be formed and a sacrificial material may be filled in the lower channel hole; then after a second prefabricated laminated structure is formed, forming an upper channel hole penetrating through the second prefabricated laminated structure along the stacking direction; and removing the sacrificial material in the lower channel hole through the upper channel hole to enable the upper channel hole to be communicated with the lower channel hole, and further forming a channel structure in the upper channel hole.
The first and second pre-fabricated stacked structures are gate-replaced by a first gate line slit (not shown) to obtain a first stacked structure 20A and a second stacked structure 60A, and a first gate line slit structure 40 penetrating the first and second stacked structures 20A and 60A is formed in the first gate line slit in step S300. The first gate line slit structure 40 includes a plurality of sub-gate line slit structures 41 arranged at intervals in the X direction. The finger slit structure 41 is located between a pair of the pillars 30 and extends into the pillars 30. Exemplarily, in the step S300, a second gate line slit structure (not shown) penetrating the first and second stacked structures 20A and 60A may be further formed in the second gate line slit. The second gate line slit structures extend along the first extension direction, and in the Y direction, the first gate line slit structure 40 is located between two second gate line slit structures.
Fig. 15 shows a three-dimensional memory device formed according to the above-described method of the second embodiment. As shown, the three-dimensional memory device may include: the gate line structure includes a substrate 10, a first stacked structure 20A, a second stacked structure 60A, a pillar 30, and a first gate line slit structure 40. The substrate 10 is a semiconductor substrate. The substrate 10 can be formed by selecting suitable materials according to actual requirements, which will not be described in detail herein.
The first stacked structure 20A includes a first gate layer 23 and a first insulating layer 22 which are alternately stacked. The second stacked layer structure 60A is located on the first stacked layer structure 20A, and the second stacked layer structure 60A includes a second gate layer 63 and a second insulating layer 62 alternately stacked. The first stacked structure 20A and the second stacked structure 60A may be regarded as one composite stacked structure as a whole, which includes the gate electrode layer 23/63 and the insulating layer 22/62 alternately stacked.
The first gate line slit structure 40 extends in the left-right direction as shown in the drawing and includes a plurality of sub-gate line slit structures 41 arranged at intervals in the extending direction, and the first gate line slit structure 40 penetrates through the composite laminated structure and may extend to the substrate 10. Isolation pillars 30 are provided at both ends of each sub-gate line slit structure 41 in the left-right direction, wherein the isolation pillars 30 penetrate the composite laminated structure. A portion of the sub-gate line slit structure 41 extends into the spacer 30, and the spacer 30 and the sub-gate line slit structure 41 wrap the remaining gate 24 in the spacer 30.
In an exemplary embodiment, the material of the isolation pillar 30 is an insulating material, such as silicon oxide. In an exemplary embodiment, the cross section of the isolation pillars 30, i.e., the section parallel to the substrate 10, is circular or square. In an exemplary embodiment, the gate layer is isolated from the first gate line slit structure 40 by the isolation pillar 30 in an extending direction of the first gate line slit structure 40.
Third embodiment
In the manufacturing method for a three-dimensional memory device according to the third embodiment, the first pre-fabricated stacked structure 20 is first formed on the substrate 10 in step S100. Next, a plurality of pillars 30 penetrating the first pre-laminated structure 20 in the stacking direction are formed in step S200. Illustratively, this embodiment provides a manufacturing method further comprising the steps of forming a second pre-fabricated laminate structure on the first pre-fabricated laminate structure 20, and forming a stair structure (not shown) based on the first pre-fabricated laminate structure 20 and the second pre-fabricated laminate structure in the stair step region. After the step structure is formed, a plurality of dummy channel structures may be further formed to penetrate the step structure.
Illustratively, the method of manufacturing may include the step of forming a channel structure. This step can be referred to as the step of forming a channel structure in the second embodiment.
Next, in step S300, a gate replacement is performed through a first gate line slit (not shown) and a second gate line slit (not shown) to form a first stacked structure 20A and a second stacked structure 60A, and a first gate line slit structure 40 and a second gate line slit structure (not shown) penetrating the first stacked structure 20A and the second stacked structure 60A are formed in the first gate line slit and the second gate line slit, respectively. The first gate line slit structure 40 includes a plurality of sub-gate line slit structures 41 arranged at intervals in parallel to the first extending direction of the substrate 10. The sub-gate line slit structure 41 is located between a corresponding pair of the isolation pillars 30 and extends to the isolation pillars 30.
Fig. 16 shows a three-dimensional memory device formed according to the above-described method of the third embodiment. The three-dimensional memory device may include: the gate line structure includes a substrate 10, a first stacked structure 20A, a second stacked structure 60A, a spacer pillar 30, and a first gate line slit structure 40.
The substrate 10 may be a semiconductor substrate. The substrate 10 can be formed by selecting suitable materials according to actual requirements, and will not be described in detail.
The first stacked layer structure 20A includes first gate layers 23 and first insulating layers 22 alternately stacked. The second stacked layer structure 60A is located on the first stacked layer structure 20A, and the second stacked layer structure 60A also includes a second gate layer 63 and a second insulating layer 62 which are alternately stacked. The first stack structure 20A and the second stack structure 60A may be regarded as one composite stack structure as a whole, which includes the gate electrode layer 23/63 and the insulating layer 22/62 alternately stacked.
The first gate line slit structure 40 extends in the left-right direction and includes a plurality of sub-gate line slit structures 41 arranged at intervals in the extending direction, and the first gate line slit structure 40 penetrates through the composite laminated structure and may extend to the substrate 10. Isolation pillars 30 are provided at both ends of each sub-gate line slit structure 41 in the left-right direction, wherein the isolation pillars 30 penetrate at least the first stacked structure 20A located closer to the substrate 10.
In the stacking direction, the area of the upper end face of the sub-gate slit structure 41, i.e., the end face on the side of the second stacked structure 60A, is larger than the area of the lower end face thereof, i.e., the end face on the side of the first stacked structure 20A. The large upper end and small lower end of the sub-gate line slit structure 41 result from the etched form of the sub-gate line slit, and the conductive material is not easily remained at the end of the second stacked structure 60A along the X direction due to the form of the sub-gate line slit. Therefore, the isolation pillar 30 disposed at the first stacked structure 20A can protect the first gate layer 23 in the first stacked structure 20A, so that the first gate layer 23 is electrically isolated from the residual gate 24. The thus arranged separation column 30 is shorter and the manufacturing process thereof is simpler.
As shown in fig. 16, the dashed lines therein identify the boundaries of the isolation pillars 30 in the X direction, and the isolation pillars 30 are staggered with respect to the sub-gate line slit structures 41. A portion of the sub-gate line slit structure 41 extends into the isolation pillar 30, so that the isolation pillar 30 and the sub-gate line slit structure 41 wrap around the residual gate electrode 24 located in the isolation pillar 30, and help to separate the residual gate electrode 24 from the first gate layer 23.
The three-dimensional memory may further include a second gate line slit structure (not shown). The second gate line slit structure penetrates the first stacked structure 20A and extends in a first extending direction parallel to the substrate 10. In an exemplary embodiment, the first gate line slit structure 40 is positioned between two second gate line slit structures.
The channel structure 50 extends through the composite laminate structure. A plurality of channel structures 50 are disposed between two second gate line slit structures, and the first gate line slit structure 40 may separate the channel structures 50.
According to the manufacturing method of the three-dimensional memory device, the isolation pillars are additionally arranged at two ends of each sub-gate line gap structure, and the isolation pillars can be only arranged at the position where the bottom of each sub-gate line gap structure is pointed, namely only penetrate through one part of the composite laminated structure. The arrangement avoids the problem of leakage current caused by the subsequent process of filling the grid metal in the word line opening, improves the electrical performance of the three-dimensional memory device and the yield of the three-dimensional memory device, and the manufacturing process of the isolation column is simpler.
As shown in fig. 17, the present disclosure also provides a storage system 8 comprising at least one three-dimensional storage device 81, a controller 82, and a connector 83. The connector 83 is used to couple the storage system 8 with an external device.
Illustratively, the three-dimensional memory device 81 provided by the present disclosure includes the aforementioned stacked structure, and further includes a peripheral circuit. Illustratively, the stacked structure and the peripheral circuit may be disposed in parallel and electrically connected; the stacked structure and the peripheral circuit may also be stacked and electrically connected by bonding. Peripheral circuitry is electrically connected to the stacked structure to facilitate the stacked structure to perform a function in the circuit, the peripheral circuitry may include, for example: page buffers/sense amplifiers, column decoders/Bit Line (BL) drivers, row decoders/Word Line (WL) drivers, voltage generators, control logic units, registers, interfaces, and data buses.
Illustratively, the controller 82 and the at least one three-dimensional memory device 81 may be integrated into a memory card. The memory card may include a PC card (PCMCIA, personal computer memory card international association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), and the like. Illustratively, the controller 82 and the at least one three-dimensional storage device 81 may be integrated into a Solid State Drive (SSD).
The memory or the storage system provided by the disclosure has the advantages that the form of the three-dimensional storage structure is good, the manufacturing yield is high, and good storage capacity can be stably and permanently provided.
The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of protection covered by this application is not limited to the embodiments with a specific combination of features described above, but also covers other embodiments with any combination of features described above or their equivalents without departing from the technical idea described. For example, the above features and (but not limited to) features having similar functions in this application are mutually replaced to form the technical solution.

Claims (17)

1. A three-dimensional memory device, comprising:
a stacked structure having a stacking direction and a first extending direction perpendicular to the stacking direction;
an isolation pillar extending in the stacked structure along the stacking direction; and
the first grid line gap structure penetrates through the laminated structure along the stacking direction and extends along the first extending direction, and comprises a plurality of sub-grid line gap structures arranged at intervals along the first extending direction, wherein a part of the sub-grid line gap structures extends into the isolation column.
2. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device comprises at least two of the pillars disposed at intervals along the first extending direction;
and the two ends of the sub-grid line gap structure in the first extending direction respectively extend into the isolation columns.
3. The three-dimensional memory device of claim 1, wherein the stacked structure comprises alternately stacked gate layers and insulating layers, the material of the isolation pillar is an insulating material, and
the three-dimensional memory device further comprises a residual grid, the residual grid is arranged between the isolation column and the sub-grid line gap structure, and the grid layer and the residual grid are electrically isolated by the isolation column and the sub-grid line gap structure.
4. The three-dimensional memory device of claim 1, wherein the stacked structure has a first side and a second side along the stacking direction;
the isolation column penetrates through at least one part of the laminated structure from the first side;
the end surface area of the first grid line gap structure on the first side is smaller than that of the first grid line gap structure on the second side.
5. The three-dimensional memory device of claim 4, wherein the isolation pillars extend through the stacked structure.
6. The three-dimensional memory device of claim 1, wherein a dimension of the isolation pillar is greater than a dimension of the portion of the sub-gate line slit structure in a second extending direction perpendicular to the stacking direction and the first extending direction, and
the maximum dimension of the portion of the sub-grid line slit structure along the second extension direction is greater than or equal to 150 nm.
7. The three-dimensional memory device of claim 1, further comprising at least two second gate line slit structures extending through the stacked structure and along the first extending direction, wherein the first gate line slit structure is located between the two second gate line slit structures.
8. The three-dimensional memory device of claim 1, wherein two of the isolation pillars are disposed between two adjacent sub-gate line slit structures.
9. A method of fabricating a three-dimensional memory device, comprising:
stacking in a stacking direction to form a pre-fabricated stack structure, wherein the pre-fabricated stack comprises a first extension direction perpendicular to the stacking direction;
forming an isolation pillar extending in the stacking direction in the pre-fabricated laminate structure; and
and forming a first gate line slit structure, wherein the first gate line slit structure comprises a plurality of sub-gate line slit structures arranged at intervals along the first extending direction, and a part of the sub-gate line slit structures extends into the isolation column.
10. The method of manufacturing of claim 9, wherein forming the first gate line slit structure comprises:
forming a first gate line gap penetrating through the prefabricated laminated structure, wherein the first gate line gap comprises a plurality of sub-gate line gaps arranged at intervals along the first extending direction, and the sub-gate line gap comprises an isolation column groove formed by removing part of the isolation column; and
forming the first gate line slit structure in the first gate line slit.
11. The manufacturing method according to claim 10,
the step of forming the pre-fabricated laminate structure comprises: alternately stacking sacrificial layers and insulating layers;
the step of forming the isolation column includes: forming the isolation column by using an insulating material;
the method further comprises the following steps after the step of forming the isolation column groove:
replacing the sacrificial layer with a gate layer to form the prefabricated laminated structure into a laminated structure, and removing the gate material in the first gate line gap, wherein a residual gate is formed in the isolation column groove;
in the step of forming the first gate line gap structure, the residual gate and the stacked structure are electrically isolated by the isolation pillar and the first gate line gap structure.
12. The manufacturing method of claim 9, wherein the step of forming the pre-fabricated laminate structure comprises:
forming a first prefabricated laminated structure; and
forming a second pre-fabricated laminate structure on one side of the first pre-fabricated laminate structure in the stacking direction;
before the second prefabricated laminated structure is formed, forming a plurality of isolation columns, wherein the isolation columns penetrate through the first prefabricated laminated structure;
and after the second prefabricated laminated structure is formed, forming the first grid line gap structure, wherein the area of the end face of the first grid line gap structure in the first prefabricated laminated structure is smaller than that of the end face of the first grid line gap structure in the second prefabricated laminated structure.
13. The manufacturing method according to claim 9, wherein the spacer pillars penetrate the pre-fabricated laminate structure.
14. The method of manufacturing of claim 9, wherein a dimension of the isolation pillar is greater than a dimension of the portion of the sub-gate line slit structure in a second extending direction perpendicular to the stacking direction and the first extending direction, and
the maximum dimension of the portion of the sub-grid line slit structure along the second extension direction is greater than or equal to 150 nm.
15. The method of manufacturing of claim 9, further comprising forming a second gate line slit structure, wherein the second gate line slit structure extends along the first extending direction, and wherein the first gate line slit structure is located between two of the second gate line slit structures.
16. The manufacturing method according to claim 9, wherein the method includes:
forming at least two isolation columns arranged at intervals along the first extending direction;
the step of forming the plurality of sub-gate line slit structures includes:
and separating two isolation columns to form two adjacent sub-grid line gap structures.
17. A storage system, comprising:
the three-dimensional memory device of any one of claims 1-8; and
and the controller is electrically connected with the three-dimensional storage device and used for controlling the storage.
CN202210190892.0A 2022-02-24 2022-02-24 Three-dimensional memory device, manufacturing method thereof and memory system Pending CN114613838A (en)

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CN202210190892.0A CN114613838A (en) 2022-02-24 2022-02-24 Three-dimensional memory device, manufacturing method thereof and memory system

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Application Number Priority Date Filing Date Title
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