CN117881046A - Circuit for improving problem of easy flashing frequency of LED digital deep dimming - Google Patents
Circuit for improving problem of easy flashing frequency of LED digital deep dimming Download PDFInfo
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- CN117881046A CN117881046A CN202410167730.4A CN202410167730A CN117881046A CN 117881046 A CN117881046 A CN 117881046A CN 202410167730 A CN202410167730 A CN 202410167730A CN 117881046 A CN117881046 A CN 117881046A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
- H05B45/59—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits for reducing or suppressing flicker or glow effects
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/32—Pulse-control circuits
- H05B45/325—Pulse-width modulation [PWM]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/37—Converter circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/16—Controlling the light source by timing means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a circuit for improving the problem of easy flashing frequency of LED digital deep dimming, which consists of a connected microcontroller and an improved DC-DC LED driver, wherein the improved DC-DC LED driver comprises: the device comprises a Dithering clock state latch circuit, a traditional Dithering frequency dimming control Osc oscillator circuit, a dimming signal PWMI rising edge extraction circuit, a PWM generating circuit, a driver and a power switch tube, wherein the Dithering frequency clock state latch circuit and the dimming signal PWMI rising edge extraction circuit are connected with the traditional Dithering frequency dimming control Osc oscillator circuit, the output end of the traditional Dithering frequency dimming control Osc oscillator circuit is connected with the input end of the PWM generating circuit, the output end of the PWM generating circuit is connected with the input end of the driver, the output end of the driver is connected with the grid electrode of the power switch tube, the source electrode of the power switch tube is grounded, and the drain electrode of the power switch tube is connected with an external LED through an inductor. The invention avoids the occurrence of the frequency flashing phenomenon, increases the light adjustable range of the LED and improves the illumination use experience of customers.
Description
Technical Field
The invention relates to the technical field of semiconductor LED driving, in particular to a circuit for improving the problem of easy flashing of LED digital deep dimming.
Background
In various driving modes of the LED, the DC-DC is controlled by switching conversion, so that the energy loss of the DC-DC is low, and the LED is particularly suitable for various high-efficiency applications. When the LED is driven, brightness adjustment is often performed according to customer requirements and different scenes, so that dimming operation is required. The dimming mode is usually PWM digital dimming, analog dimming, and the like, wherein PWM digital dimming has advantages of almost no color shift, wide brightness adjustment range, easy system control, and the like, and is favored.
FIG. 1 is a schematic diagram of a typical LED drive employing PWM digital dimming, consisting of a microcontroller and a DC-DC LED driver, the microcontroller emitting PWMI dimming signals of corresponding duty cycle according to system brightness requirements; the DC-DC LED driver contains an Osc oscillator to generate switching frequency, the switching frequency is sent to an internal PWM generating circuit, and then a power switch tube is driven by the driver to supply energy for an external LED string. In addition, because the DC-DC LED driver can generate a large amount of electromagnetic interference, frequency-jittering control is usually added to the Osc oscillator to meet the EMC requirement of electromagnetic compatibility.
Fig. 2 is a schematic diagram of an Osc oscillator circuit incorporating conventional dither control, comprising: the triangular wave frequency-jittering clock generation circuit and the triangular wave frequency-jittering current generation circuit are used for charging and discharging a capacitor together after superposition of an NM1 position and an internal original bias current Ib, comparing the capacitor with Vref to generate sawtooth waves, integrating the sawtooth waves through digital logic, and outputting an internal clock signal used by a PWM generator in a chip. Fig. 3 shows a conventional triangular wave jitter clock generating circuit, in which CLK frequency signals are sent in, four continuously high and low varying signals are generated a, b, c, D by D flip-flops with a zero clearing function, and triangular wave step control signals 0000,0001,0010, etc. are generated by combining, after one period is full to 1111, zero clearing is triggered by and gate and nand gate combination logic, so that all D flip-flops are zero cleared, reset and return to the 0000 starting point. Under the continuous excitation of the CLK frequency signal, the next cycle of cyclic reciprocation is entered, and finally the triangular wave jitter frequency control clock signal is generated.
The PWM digital dimming process of the Osc oscillator circuit added with the traditional Dithering frequency dimming control comprises the following steps: when the PWMI dimming signal sent from the outside is at a low level, the power switch tube does not conduct switch operation, and the current flowing through the LED is 0; when the PWMI dimming signal is at a high level, the power switch tube outputs a set current to the LED according to the frequency generated by the Osc oscillator controlled by the traditional frequency Dithering. When the LED needs high brightness, only the duty ratio of the PWMI dimming signal is required to be improved, and more energy is output to the LED; when the LED needs low brightness, the duty ratio is reduced. PWM dimming frequencies are typically several hundred to several khz, and when dimming is performed with a small duty cycle, such as a deep dimming of 1000:1, or deeper, the PWMI dimming signal has a high level time of only several μs to several tens of μs, the power tube is turned on easily, the number of periods is different, and serious flashing problems occur, specifically, as shown in fig. 4, each time the PWMI dimming signal has a high level rising edge, the internal clk may be in a low level state or may be in a high level, and even if the PWMI dimming signal is in a high level or a low level, the internal clk may not be in the same position in the internal clk period; and because of the existence of the triangular wave jitter frequency, the internal clk frequency is different every time the PWMI dimming signal is in a high level period, so that the clock signal finally sent to the power switch tube shows random change, and the energy for driving the LED is also changed randomly. When the dimming PWMI dimming signal is of a large duty ratio, the random differences are not easy to distinguish by naked eyes on the change of the brightness of the LED, and the influence is small; however, when the dimming PWMI dimming signal is used for deep dimming with a small duty ratio, these random energy differences can have a serious effect on the brightness of the LED, and the LED is suddenly and suddenly dimmed, and a flicker phenomenon occurs. Therefore, when the traditional DC-DC LED driver adopting the digital PWMI dimming mode is used for deep dimming with a small duty ratio, the flash frequency is very easy to occur, the dimming range of the LEDs is limited, and the use experience of customers is seriously affected.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a circuit for improving the problem of easy frequency flashing of LED digital deep dimming, which avoids the occurrence of frequency flashing, increases the dimming range of LEDs and improves the lighting use experience of customers.
In order to achieve the technical purpose, the invention adopts the following technical scheme: a circuit for improving the problem of easy flashing of digital deep dimming of LED, is made up of microcontroller and improved DC-DC LED driver connected, the said microcontroller provides PWMI dimming signal for improved DC-DC LED driver; the improved DC-DC LED driver comprises: the device comprises a Dithering clock state latch circuit, a traditional Dithering frequency dimming control Osc oscillator circuit, a dimming signal PWMI rising edge extraction circuit, a PWM generation circuit, a driver and a power switch tube, wherein the Dithering frequency clock state latch circuit and the dimming signal PWMI rising edge extraction circuit are connected with the traditional Dithering frequency dimming control Osc oscillator circuit, the output end of the traditional Dithering frequency dimming control Osc oscillator circuit is connected with the input end of the PWM generation circuit, the output end of the PWM generation circuit is connected with the input end of the driver, the output end of the driver is connected with the grid electrode of the power switch tube, the source electrode of the power switch tube is grounded, and the drain electrode of the power switch tube is connected with an external LED through an inductor;
the jitter clock state latch circuit is used for keeping the starting point of jitter frequency consistent when the rising edge of the PWMI dimming signal arrives;
the dimming signal PWMI rising edge extraction circuit is used for extracting the PWMI dimming signal rising edge time and resetting the Osc oscillator circuit controlled by the traditional Dithering frequency dimming.
Further, the input end of the jitter clock state latch circuit and the input end of the dimming signal PWMI rising edge extraction circuit are connected with the PWMI dimming signal sent by the microcontroller.
Further, the jitter clock state latch circuit includes: the output end of the first inverter Inv1 is connected with the first input end of the AND gate And2, the output end of the first Nor gate Nor4 is connected with the second input end of the AND gate And2, the output end of the AND gate And2 is connected with the second input end of the OR gate Or2, the first input end of the OR gate Or2 is connected with the input clock CLK, and the output end of the OR gate Or2 is connected with the input end of the Osc oscillator circuit controlled by the traditional frequency-jittering.
Further, the input end of the first inverter Inv1 is connected with a PWMI dimming signal sent by the microcontroller, and the input end of the first Nor gate Nor4 is connected with an Osc oscillator circuit controlled by conventional dither frequency dimming.
Further, the Osc oscillator circuit controlled by the conventional dither frequency dither includes: the device comprises a triangular wave frequency-jittering clock generation circuit, a triangular wave frequency-jittering current generation circuit, a sawtooth wave generator, a first NMOS switching tube NM5, a capacitor C, a comparator and a digital logic circuit, wherein the output end of the triangular wave frequency-jittering clock generation circuit is connected with the input end of the triangular wave frequency-jittering current generation circuit, the output end of the triangular wave frequency-jittering current generation circuit is connected with the input end of the sawtooth wave generator, the output end of the sawtooth wave generator is respectively connected with one end of the capacitor C, the drain electrode of the first NMOS switching tube NM5 and the first input end of the comparator, the other end of the capacitor C is grounded, the source electrode of the first NMOS switching tube NM5 is grounded, the grid electrode of the first NMOS switching tube NM5 is respectively connected with the output end of the comparator and the input end of the digital logic circuit, and the output end of the digital logic circuit is connected with the input end of the PWM generating circuit.
Further, the triangular wave frequency-jittering clock generation circuit consists of four D flip-flops with zero clearing function, and the D port of each D flip-flop with zero clearing function is connected with the D port of each D flip-flopThe port is connected, and the Reset port of each D trigger with the zero clearing function is connected with a Reset signal rst; the Q ports of the first three D triggers with the zero clearing function are connected with the Clk ports of the next D trigger with the zero clearing function.
Further, the Clk port of the first D flip-flop with the zero clearing function is connected to the output end of the Or gate Or2, the Q ports of the four D flip-flops with the zero clearing function are respectively and correspondingly connected to the four input ports of the Nor gate Nor4, and the Q port of the fourth D flip-flop with the zero clearing function is also connected to the input end of the triangular wave jitter frequency current generating circuit.
Further, the dimming signal PWMI rising edge extraction circuit includes: the Delay unit Delay, the second inverter I1 and the second NOR gate N2, the PWMI dimming signal that microcontroller sent is connected with Delay unit Delay's input, second inverter I1's input respectively, delay unit Delay's output is connected with second NOR gate N2's first input, second inverter I1's output is connected with second NOR gate N2's second input, second NOR gate N2's output is connected with digital logic circuit's reset terminal, first NMOS switch tube NM 5's grid, comparator's output, digital logic circuit's input respectively.
Further, when PWMI is low, the first inverter Inv1 turns to high, enabling the And gate nd2, and the four D flip-flops with the zero clearing function in the triangular wave frequency-jittering clock generating circuit follow the input clock CLK until the four D flip-flops with the zero clearing function generate the latched signal, and the And gate nd2 outputs 1, locks Or gate Or2, and no longer receives the input clock CLK, at this time, the frequency-jittering clock state latching circuit is latched in the set latched signal.
Further, when PWMI goes high, delay unit Delay of the dimming signal PWMI rising edge extraction circuit captures rising edge, generates a narrow pulse of 10-20ns, resets the sawtooth wave generator, and resets the digital logic circuit, aligning the rising edge of the digital logic circuit output with the rising edge of the digital dimming signal PWMI, at this time, the output of the first inverter Inv1 becomes 0, the output of the And gate And2 is 0, the Or gate Or2 is unlocked, the dither clock state latch circuit is started to receive the input clock CLK, and the four D flip-flops with clear function start to modulate the sawtooth wave frequency along the latched signal.
Compared with the prior art, the invention has the following beneficial effects: the invention relates to a circuit for improving the problem of easy flashing of LED digital deep dimming, which is characterized in that a Dithering clock state latch circuit and a dimming signal PWMI rising edge extraction circuit are added on the basis of a traditional Dithering frequency dimming control Osc oscillator circuit, the Dithering frequency clock state latch circuit sets and latches a certain specific state of a Dithering frequency clock in a plurality of triangular wave clock states in a period that PWMI is low level, and then triangular wave modulation starts along the same state starting point every time the PWMI is converted into high level to start dimming; the dimming signal PWMI rising edge extraction circuit is used for extracting PWMI rising edge time, resetting the sawtooth wave generator and resetting the digital logic. The invention ensures that when the PWMI dimming signal has a small duty ratio, the internal clock of the power switch tube which is transmitted to the DC-DC LED driver in a high level period has the same period starting point, and the period frequencies and the time lengths of the clocks in the period are consistent, thereby thoroughly solving the problem that the digital deep dimming with the small duty ratio is easy to flash, widening the digital dimming range of the LED and improving the use experience of customer illumination.
Drawings
FIG. 1 is a schematic diagram of an LED drive employing PWM digital dimming;
FIG. 2 is a schematic diagram of a conventional Osc oscillator circuit controlled by dither frequency Dither;
FIG. 3 is a schematic diagram of a conventional triangular wave jitter clock generation circuit;
FIG. 4 is a schematic diagram of the conventional PWM digital dimming flashing problem;
FIG. 5 is a schematic circuit diagram illustrating an improvement of the LED digital deep dimming flash problem according to the present invention;
FIG. 6 is an effect diagram of the invention to solve the LED small duty cycle deep dimming flashing problem;
FIG. 7 is a diagram of an embodiment of the present invention for solving the LED small duty cycle deep dimming flashing problem;
FIG. 8 is a schematic diagram of a jitter clock status frequency locking circuit according to the present invention.
Detailed Description
The technical scheme of the invention is further explained below with reference to the accompanying drawings.
As shown in fig. 5, the present invention provides a circuit for improving the problem of LED digital deep dimming flash frequency, which consists of a connected microcontroller and an improved DC-DC LED driver, wherein the microcontroller provides PWMI dimming signals for the improved DC-DC LED driver; the improved DC-DC LED driver comprises: the device comprises a Dithering clock state latch circuit, a traditional Dithering frequency dimming control Osc oscillator circuit, a dimming signal PWMI rising edge extraction circuit, a PWM generating circuit, a driver and a power switch tube, wherein the Dithering frequency clock state latch circuit and the dimming signal PWMI rising edge extraction circuit are connected with the traditional Dithering frequency dimming control Osc oscillator circuit, the output end of the traditional Dithering frequency dimming control Osc oscillator circuit is connected with the input end of the PWM generating circuit, the output end of the PWM generating circuit is connected with the input end of the driver, the output end of the driver is connected with the grid electrode of the power switch tube, the source electrode of the power switch tube is grounded, and the drain electrode of the power switch tube is connected with an external LED through an inductor; the input end of the jitter frequency clock state latch circuit and the input end of the dimming signal PWMI rising edge extraction circuit are connected with the PWMI dimming signal sent by the microcontroller; the jitter clock state latch circuit is used for keeping the starting point of jitter frequency consistent when the rising edge of the PWMI dimming signal arrives; the dimming signal PWMI rising edge extraction circuit is used for extracting the rising edge moment of the PWMI dimming signal and resetting the Osc oscillator circuit controlled by the traditional Dithering frequency dimming. Setting and latching a certain specific state of a jitter clock in a plurality of clock states of triangular waves in a period that a PWMI dimming signal is in a low level through a jitter clock state latching circuit, and then, when the PWMI dimming signal is converted into a high level to start dimming each time, starting the triangular wave modulation along the same state, and cycling the next triangular wave state; the dimming signal PWMI rising edge extraction circuit is used for extracting the rising edge moment of the PWMI dimming signal, resetting the sawtooth oscillator and the digital logic, so that when the PWMI dimming signal has a small duty ratio, the internal clock of the power switch tube which is transmitted to the DC-DC LED driver in a high level period has the same period starting point, and the period frequencies and the time lengths of a plurality of clocks in the period are consistent, thereby thoroughly solving the problem of easy flashing of the digital deep dimming with the small duty ratio.
As shown in fig. 2, the Osc oscillator circuit controlled by the conventional dither frequency Dithering includes: the device comprises a triangular wave frequency-jittering clock generation circuit, a triangular wave frequency-jittering current generation circuit, a sawtooth wave generator, a first NMOS switching tube NM5, a capacitor C, a comparator and a digital logic circuit, wherein the output end of the triangular wave frequency-jittering clock generation circuit is connected with the input end of the triangular wave frequency-jittering current generation circuit, the output end of the triangular wave frequency-jittering current generation circuit is connected with the input end of the sawtooth wave generator, the output end of the sawtooth wave generator is respectively connected with one end of the capacitor C, the drain electrode of the first NMOS switching tube NM5 and the first input end of the comparator, the other end of the capacitor C is grounded, the source electrode of the first NMOS switching tube NM5 is respectively connected with the output end of the comparator and the input end of the digital logic circuit, and the output end of the digital logic circuit is connected with the input end of the PWM generating circuit.
The sawtooth wave generator includes: the first NMOS current mirror NM1, the second NMOS current mirror NM2, the third NMOS current mirror NM3, the fourth NMOS current mirror, the first PMOS current mirror PM1, the second POMS current mirror PM2, the third PMOS current mirror PM3, the fourth PMOS current mirror PM4 and the bias current Ib, wherein the triangular wave dithering frequency current generation current is respectively connected with the source electrode of the third NMOS current mirror NM3, the grid electrode of the first NMOS current mirror NM1, the drain electrode of the first NMOS current mirror NM1 and the grid electrode of the second NMOS current mirror NM2, and the source electrode of the first NMOS current mirror NM1 and the source electrode of the second NMOS current mirror NM2 are grounded; the drain electrode of the second NMOS current mirror NM2 is connected with the source electrode of a fourth NMOS current mirror NM4, the grid electrode of the fourth NMOS current mirror NM4 is respectively connected with the grid electrode of a third NMOS current mirror NM3, the drain electrode of the third NMOS current mirror NM3 and the output end of bias current Ib, and the input end of the bias current Ib is connected with access voltage VCC; the drain electrode of the fourth NMOS current mirror NM4 is respectively connected with the drain electrode of the first PMOS current mirror PM1, the grid electrode of the first PMOS current mirror PM1 and the grid electrode of the second PMOS current mirror PM2, the source electrode of the first PMOS current mirror PM1 is respectively connected with the drain electrode of the third PMOS current mirror PM3, the grid electrode of the third PMOS current mirror PM3 and the grid electrode of the fourth PMOS current mirror PM4, the source electrode of the third PMOS current mirror PM3 and the source electrode of the fourth PMOS current mirror PM4 are respectively connected with the access voltage VCC, the drain electrode of the fourth PMOS current mirror PM4 is connected with the source electrode of the second PMOS current mirror PM2, and the drain electrode of the second PMOS current mirror PM2 is respectively connected with one end of the capacitor C, the drain electrode of the first NMOS switch tube NM5 and the first input end of the comparator.
As shown in fig. 3, the triangular wave jitter clock generating circuit is composed of four D flip-flops with zero clearing function, the D port of each D flip-flop with zero clearing function is connected with the respective D portThe port is connected, and the Reset port of each D trigger with the zero clearing function is connected with a Reset signal rst; q ports of the first three D triggers with zero clearing function are all connected with the next D trigger with zero clearing functionThe Clk port of the device is connected. The reset signal rst is that the Q port of the D trigger with the zero clearing function is respectively connected with two parallel AND gates, the output ends of the two parallel AND gates are connected with the other AND gate, and the output end signal of the other AND gate is the reset signal rst.
As shown in fig. 8, the dither clock state latch circuit includes: the input end of the first inverter Inv1 is connected with a PWMI dimming signal sent by the microcontroller, the output end of the first inverter Inv1 is connected with the first input end of the AND gate And2, the output end of the first NOR gate Nor4 is connected with the second input end of the AND gate And2, the output end of the AND gate And2 is connected with the second input end of the OR gate Or2, the first input end of the OR gate Or2 is connected with an input clock CLK, the output end of the OR gate Or2 is connected with the input end of an Osc oscillator circuit controlled by traditional Dithering frequency, the input end of the first NOR gate Nor4 is connected with the Osc oscillator circuit controlled by traditional Dithering frequency, specifically, the Clk port of a D trigger with a zero clearing function is connected with the output end of the OR gate Or2, the Q ports of four D triggers with zero clearing function are respectively connected with the four input ports of the OR gate Or2, the four input ports of the OR gate Or2 are respectively, and the four input ports of the D triggers with zero clearing function are enabled to be different from the triangle-shaped end of the PWMI, so that the PWMI current is enabled to be more uniform when the PWMI is enabled to be more uniform.
As shown in fig. 7, the dimming signal PWMI rising edge extraction circuit includes: the Delay unit Delay, the second inverter I1 and the second NOR gate N2, the PWMI dimming signal that the microcontroller sent is connected with the input of Delay unit Delay, the input of second inverter I1 respectively, the output of Delay unit Delay is connected with the first input of second NOR gate N2, the output of second inverter I1 is connected with the second input of second NOR gate N2, the output of second NOR gate N2 is connected with the reset terminal of digital logic circuit, the grid of first NMOS switch tube NM5, the output of comparator, the input of digital logic circuit respectively. The time from the rising edge of PWMI is extracted by the rising edge extracting circuit of the dimming signal PWMI, thereby resetting the sawtooth wave generator and resetting the digital logic circuit.
When PWMI is low, the first inverter Inv1 turns to high level to enable the AND gate And2, so long as the output signals of Q ports of the four D flip-flops with zero clearing function are not latched signals, the four D flip-flops with zero clearing function in the triangular wave frequency-jittering clock generating circuit can quickly change along with the input clock CLK until the four D flip-flops with zero clearing function generate the latched signals, the AND gate And2 outputs 1 to lock the OR gate Or2 And no longer receives the input clock CLK, and at the moment, the frequency-jittering clock state latching circuit is latched at the set latched signals.
When PWMI goes high, delay unit Delay of the dimming signal PWMI rising edge extraction circuit captures rising edge, generates a narrow pulse of 10-20ns, resets the sawtooth wave generator, and resets the digital logic circuit, aligning the rising edge of the digital logic circuit output with the rising edge of the digital dimming signal PWMI, at this time, the first inverter Inv1 output becomes 0, the output of the And gate And2 is 0, unlock Or gate Or2, the dither clock state latch circuit is started to receive the input clock CLK, and four D flip-flops with zero clearing function start modulating the sawtooth wave frequency along the latched signal, so that the start point of sawtooth wave dither frequency is the same each time the PWMI dimming signal rising edge comes.
As shown in fig. 6, in the dimming process, the circuit for improving the problem of easy flashing of digital deep dimming of an LED according to the present invention continuously detects the rising edge of the digital dimming signal PWMI, so that the rising edge of the digital dimming signal PWMI is aligned with the rising edge of the internal clock, and the period of the internal clk period frequency transmitted to the power tube during the high level period of the small duty cycle signal is consistent with the starting point and the variation trend of the dithering frequency modulation, the number of periods is the same, thereby thoroughly solving the problem of flashing caused by random variation of the driving energy of the LED during the digital deep dimming of the small duty cycle from the root, widening the digital dimming range of the LED, and improving the illumination use experience of customers.
The above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, and all technical solutions belonging to the concept of the present invention are within the scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (10)
1. A circuit for improving the problem of easy flashing of digital deep dimming of an LED, which is characterized by comprising a microcontroller and an improved DC-DC LED driver which are connected, wherein the microcontroller provides PWMI dimming signals for the improved DC-DC LED driver; the improved DC-DC LED driver comprises: the device comprises a Dithering clock state latch circuit, a traditional Dithering frequency dimming control Osc oscillator circuit, a dimming signal PWMI rising edge extraction circuit, a PWM generation circuit, a driver and a power switch tube, wherein the Dithering frequency clock state latch circuit and the dimming signal PWMI rising edge extraction circuit are connected with the traditional Dithering frequency dimming control Osc oscillator circuit, the output end of the traditional Dithering frequency dimming control Osc oscillator circuit is connected with the input end of the PWM generation circuit, the output end of the PWM generation circuit is connected with the input end of the driver, the output end of the driver is connected with the grid electrode of the power switch tube, the source electrode of the power switch tube is grounded, and the drain electrode of the power switch tube is connected with an external LED through an inductor;
the jitter clock state latch circuit is used for keeping the starting point of jitter frequency consistent when the rising edge of the PWMI dimming signal arrives;
the dimming signal PWMI rising edge extraction circuit is used for extracting the PWMI dimming signal rising edge time and resetting the Osc oscillator circuit controlled by the traditional Dithering frequency dimming.
2. The circuit for improving the problem of easy flashing of digital deep dimming of an LED of claim 1, wherein the input of the jitter clock state latch circuit and the input of the dimming signal PWMI rising edge extraction circuit are both connected to the PWMI dimming signal sent by the microcontroller.
3. A circuit for improving the LED digital deep dimming flash frequency problem as recited in claim 2, wherein the dither clock state latch circuit comprises: the output end of the first inverter Inv1 is connected with the first input end of the AND gate And2, the output end of the first Nor gate Nor4 is connected with the second input end of the AND gate And2, the output end of the AND gate And2 is connected with the second input end of the OR gate Or2, the first input end of the OR gate Or2 is connected with the input clock CLK, and the output end of the OR gate Or2 is connected with the input end of the Osc oscillator circuit controlled by the traditional frequency-jittering.
4. A circuit for improving LED digital deep dimming susceptibility to flicker as claimed in claim 3, wherein the input of the first inverter Inv1 is connected to a PWMI dimming signal from the microcontroller, and the input of the first Nor gate Nor4 is connected to a conventional dither-controlled Osc oscillator circuit.
5. The circuit for improving LED digital deep dimming flash frequency as recited in claim 4, wherein the conventional dither-controlled Osc oscillator circuit comprises: the device comprises a triangular wave frequency-jittering clock generation circuit, a triangular wave frequency-jittering current generation circuit, a sawtooth wave generator, a first NMOS switching tube NM5, a capacitor C, a comparator and a digital logic circuit, wherein the output end of the triangular wave frequency-jittering clock generation circuit is connected with the input end of the triangular wave frequency-jittering current generation circuit, the output end of the triangular wave frequency-jittering current generation circuit is connected with the input end of the sawtooth wave generator, the output end of the sawtooth wave generator is respectively connected with one end of the capacitor C, the drain electrode of the first NMOS switching tube NM5 and the first input end of the comparator, the other end of the capacitor C is grounded, the source electrode of the first NMOS switching tube NM5 is grounded, the grid electrode of the first NMOS switching tube NM5 is respectively connected with the output end of the comparator and the input end of the digital logic circuit, and the output end of the digital logic circuit is connected with the input end of the PWM generating circuit.
6. An improved LED digital deep dimming as recited in claim 5The circuit for easily flashing frequency problem is characterized in that the triangular wave frequency-jittering clock generating circuit consists of four D flip-flops with zero clearing function, and the D port of each D flip-flop with zero clearing function is connected with the respective D portThe port is connected, and the Reset port of each D trigger with the zero clearing function is connected with a Reset signal rst; the Q ports of the first three D triggers with the zero clearing function are connected with the Clk ports of the next D trigger with the zero clearing function.
7. The circuit for improving the problem of easy frequency flashing of LED digital deep dimming according to claim 6, wherein the Clk port of the first D flip-flop with zero clearing function is connected with the output end of OR gate Or2, the Q ports of the four D flip-flops with zero clearing function are respectively and correspondingly connected with the four input ports of Nor gate Nor4, and the Q port of the fourth D flip-flop with zero clearing function is also connected with the input end of the triangular wave frequency-jittering current generating circuit.
8. The circuit for improving the LED digital deep dimming flash problem of claim 7, wherein the dimming signal PWMI rising edge extraction circuit comprises: the Delay unit Delay, the second inverter I1 and the second NOR gate N2, the PWMI dimming signal that microcontroller sent is connected with Delay unit Delay's input, second inverter I1's input respectively, delay unit Delay's output is connected with second NOR gate N2's first input, second inverter I1's output is connected with second NOR gate N2's second input, second NOR gate N2's output is connected with digital logic circuit's reset terminal, first NMOS switch tube NM 5's grid, comparator's output, digital logic circuit's input respectively.
9. The circuit for improving the problem of LED digital deep dimming with easy flashing according to claim 8, wherein the set dither clock state latch circuit is latched with the input clock CLK when PWMI is low, the first inverter Inv1 is turned high, the And gate And2 is enabled, the four D flip-flops with clear function in the triangular dither clock generating circuit follow the input clock CLK until the four D flip-flops with clear function generate the latched signal, and the And gate And2 outputs 1, latches Or gate Or2, no longer receives the input clock CLK, at which time the dither clock state latch circuit is latched with the set latched signal.
10. The circuit for improving the LED digital deep dimming susceptibility to flicker as claimed in claim 8, wherein when PWMI goes high, delay unit Delay of the rising edge extraction circuit of dimming signal PWMI captures rising edge, generates a narrow pulse of 10-20ns, resets sawtooth generator, and resets digital logic circuit, align rising edge of digital logic circuit output with rising edge of digital dimming signal PWMI, at this time, first inverter Inv1 output becomes 0, output of And gate And2 is 0, unlock Or gate Or2, and dither clock state latch circuit is started to receive input clock CLK, and four D flip-flops with zero clearing function start modulating sawtooth frequency along latched signal.
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Citations (5)
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| JPH04296115A (en) * | 1991-03-26 | 1992-10-20 | Matsushita Electric Works Ltd | Pwm waveform generating circuit |
| US20120194227A1 (en) * | 2011-02-01 | 2012-08-02 | Richpower Microelectronics Corporation | Jittering frequency control circuit and method for a switching mode power supply |
| CN103781240A (en) * | 2012-10-19 | 2014-05-07 | 凌力尔特公司 | LED driver and control method thereof |
| CN115149928A (en) * | 2022-07-29 | 2022-10-04 | 无锡格兰德微电子科技有限公司 | Voltage-insensitive high-precision oscillator circuit of process thermometer |
| CN116247921A (en) * | 2022-12-02 | 2023-06-09 | 深圳南云微电子有限公司 | Frequency-jittering control circuit, control chip and switching power supply |
-
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- 2024-02-06 CN CN202410167730.4A patent/CN117881046B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04296115A (en) * | 1991-03-26 | 1992-10-20 | Matsushita Electric Works Ltd | Pwm waveform generating circuit |
| US20120194227A1 (en) * | 2011-02-01 | 2012-08-02 | Richpower Microelectronics Corporation | Jittering frequency control circuit and method for a switching mode power supply |
| CN103781240A (en) * | 2012-10-19 | 2014-05-07 | 凌力尔特公司 | LED driver and control method thereof |
| CN115149928A (en) * | 2022-07-29 | 2022-10-04 | 无锡格兰德微电子科技有限公司 | Voltage-insensitive high-precision oscillator circuit of process thermometer |
| CN116247921A (en) * | 2022-12-02 | 2023-06-09 | 深圳南云微电子有限公司 | Frequency-jittering control circuit, control chip and switching power supply |
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