CN117879766A - Novel physical layer design scheme based on Turbo-FSK-QPSK technology - Google Patents

Abstract

The invention discloses a design scheme of a novel physical layer on the basis of a low-power-consumption wide area network, so that loss of a terminal in the Internet of things in communication with a base station is reduced. The invention can realize the principle by using a scheme with low frequency spectrum efficiency based on low sensitivity level, takes FSK signals as code words, combines FSK code words of a receiving end into a Turbo-FSK technology by adopting a Turbo decoding mode, combines QPSK on the basis, provides the Turbo-FSK-QPSK technology and provides structures of a transmitting end and a receiving end of the Turbo-FSK-QPSK technology. The present invention combines quadrature modulation and coding and is associated with an iterative receiver. The physical layer design obtained based on the method improves energy efficiency and spectrum efficiency, simultaneously maintains the characteristic of low complexity of the original Turbo-FSK technology, and better adapts to the requirement of a low-power consumption wide area network.

Description

Novel physical layer design scheme based on Turbo-FSK-QPSK technology

Technical Field

The invention relates to the technical field of wireless communication, in particular to a design of a low-power physical layer under a low-power wide area network, and provides a Turbo-FSK-QPSK scheme and structures of a transmitter and a receiver.

Background

Turbo codes have proven to be close to channel capacity and are considered a major breakthrough in channel coding, which concept relies on the parallel connection of two recursive systematic convolutional code (RSC) encoders separated by an interleaver, by using an interleaver, both encoders operate on the same set of information bits but with different input sequences, and thus different output sequences. One of the main advantages of Frequency Shift Keying (FSK) quadrature modulation is its constant envelope modulation. The use of this type of modulation can release the constraints of the Power Amplifier (PA), increase its efficiency and reduce its cost. Furthermore, FSK is a well known technique, which may be very attractive due to the availability of a variety of off-the-shelf solutions, and FSK modulation may be implemented by Orthogonal Frequency Division Multiplexing (OFDM) transceivers.

In recent years, the physical layer design of a new low-power wide area network is a key problem of a new generation of internet of things network, because a large number of connection devices are expected to need the connection solution in the coming years, while the existing industrial-level solution can only give a fixed solution for a specific scene and cannot balance the spectrum efficiency and the energy efficiency, the new physical layer solution can be designed to effectively solve the contradiction, thereby achieving the requirement of low power consumption, and having very profound significance, important theoretical research value and application prospect.

The present invention has been made in view of this.

Disclosure of Invention

The invention aims at providing a new physical layer design scheme aiming at a low-power consumption wide area network system so as to effectively reduce the power during transmission.

The invention adopts the following technical scheme for solving the technical problems: a new physical layer design scheme and a transmitting end and receiving end structure thereof are provided, which comprises:

considering that in the cascade scheme, the transmitter uses orthogonal FSK waveforms as code words, and transmits the input signals after interleaving into a parity check accumulation encoder;

decoding mode of posterior probability logarithmic ratio (log-APP) is utilized, which is related to channel observation value, and DFT is executed to received sequence by front end to calculate;

as an embodiment, consider that in a concatenated scheme, a transmitter interleaves an input signal with orthogonal FSK waveforms as codewords and sends the interleaved signal to a parity check accumulation encoder, comprising:

step 11, let Q be the information block matrix, the size is Q' ×N _q′ Thus N _q′ =q/Q ', i.e. the number of secondary words of length Q' in the information block. It has N _q′ A row vector b= { b _n } _{n∈{0,…,q′-1}} The Turbo-FSK-QPSK transmitter consists of a lambda-level parallel structure;

each row b of the input parity accumulation encoder is processed sequentially, step 12. The q' bit is calculated and the modulo-2 addition of the memory is performed and the memory is updated with the result. This process may be interpreted as applying an accumulator over the parity of the q' information bits. The encoder generates a word of length q '+1 bits, including a q' input bit and the output of the accumulator;

conventionally, the initial state of the memory is set to 0 and the final state is forced to 0 by adding an extra information word. Since the value of this word depends on the previous N _q′ Individual words, must be calculated during the encoding process. Finally, the encoder generates N of size m '=q' +1 _q′ +1 coding words;

step 13, combining these N _q′ The +1 binary words are fed to an FSK mapping block, which combines the m' bits with the alphabet4 m=2 of (2) ^m′ One of the codewords is associated. For executing FSK signals, ++>Constructed from hermite transposed Discrete Fourier Transform (DFT) matrix (or Inverse Discrete Fourier Transform (IDFT)), where +.>And: />

Wherein the method comprises the steps ofIs the M root of the unit. Thus, the output codeword is a row vector of 4M chips and each element is a complex number. The output size of stage l (l.epsilon. {0, …, lambda-1 }) is 4M× (N _q′ +1) matrixS ^(l) A representation;

step 14, the output of each stage is then connected to a signal x containing λ× (N _q′ +1) FSK codeword.

As an embodiment, the decoding method using a log-APP (log-APP) is related to a channel observation value, and may be calculated by performing DFT on a received sequence by a front end, and includes:

step 21, calculating p according to likelihood value given by detector and prior probability given by other decoderIs a product of (2);

step 22, for each conversion s'. Fwdarw.s, use formulaCalculation of gamma _t A value of (s', s);

step 23, under initialization condition α ₀ (0) =1 andcalculating the alpha and beta values of all t;

step 24, log-APP formulaCalculating;

since one interleaver step separates each encoder, the a priori information needs to be correctly deinterleaved at decoding. The same process is repeated for all decoders. An iteration refers to performing the aforementioned 4 steps, which may be repeated. At the end of the iteration, a matrix L of size a q' contains the log-APP of all decoders. By taking the sign of each log-APP of the q' bits, L can make a hard decision.

Compared with the prior art, the technical scheme provided by the invention has the following technical effects:

the novel physical layer design scheme based on the Turbo-FSK-QPSK technology has better performance than the existing industrial-level solution, the calculation complexity is obviously lower than that of the existing industrial-level solution, the limitation of channel capacity can be approximated, the good compromise of the performance and the complexity is realized, the spectrum efficiency and the energy efficiency are simultaneously considered, and the communication requirement of the low-power-consumption Internet of things can be realized.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention.

In the drawings:

fig. 1 is a diagram of a transmitter structure of the present invention;

fig. 2 is a block diagram of a receiver according to the present invention;

fig. 3 is a block diagram of a detector in a receiver according to the present invention.

Detailed Description

The present invention is further illustrated in the accompanying drawings and detailed description which are to be understood as being merely illustrative of the invention and not limiting of its scope, and various modifications of the invention, which are equivalent to those skilled in the art upon reading the invention, will fall within the scope of the invention as defined in the appended claims.

The new physical layer design scheme based on the Turbo-FSK-QPSK technology comprises the following steps: the signal of the transmitting end is added with parity check through a parity check accumulation encoder, then reaches the receiving end through a channel, and the receiving end carries out DFT calculation through a log-APP decoding mode to obtain a final result.

As an embodiment, the method comprises: considering that in the cascade scheme, the transmitter uses orthogonal FSK waveforms as code words, and transmits the input signals after interleaving into a parity check accumulation encoder; decoding means using a log-APP (posterior probability) ratio, which is related to the channel observations, can be calculated by performing DFT on the received sequence by the front end.

First step: let Q be the information block matrix, the size is Q'. Times.N _q′ Thus N _q ' Q/Q ', i.e. the number of secondary words of length Q ' in the information block. It has N _q′ A row vector b= { b _n } _n∈{ 0 _{，...，g′-1}} The Turbo-FSK-QPSK transmitter consists of a lambda-level parallel structure;

and a second step of: each row b of the input parity accumulation encoder is processed sequentially. The q' bit is calculated and the modulo-2 addition of the memory is performed and the memory is updated with the result. This process may be interpreted as applying an accumulator over the parity of the q' information bits. The encoder produces words of length q '+1 bits, including the q' input bits and the output of the accumulator.

Conventionally, the initial state of the memory is set to 0 and the final state is forced to 0 by adding an extra information word. Since the value of this word depends on the previous N _q′ Individual words, must be calculated during the encoding process. Finally, the encoder generates N of size m '=q' +1 _q′ +1 coding words;

and a third step of: these N are added to _q′ The +1 binary words are fed to an FSK mapping block, which combines the m' bits with the alphabet4 m=2 of (2) ^m′ One of the codewords is associated. For executing FSK signals, ++>Constructed from hermite transposed Discrete Fourier Transform (DFT) matrix (or Inverse Discrete Fourier Transform (IDFT)), where +.>And: />

Wherein the method comprises the steps ofIs the M root of the unit. Thus, the output codeword is a row vector of 4M chips and each element is a complex number. The output size of stage l (l.epsilon. {0, …, lambda-1 }) is 4M× (N _q′ +1) matrix S ^(l) A representation;

fourth step: the output of each stage is then connected to a signal x comprising lambda x (N _q′ +1) FSK codeword.

Fifth step: calculating p based on likelihood values given by the detector and prior probabilities given by other decodersIs a product of (2);

sixth step: for each transition s'. Fwdarw.s, formula is usedCalculation of gamma _t A value of (s', s);

seventh step: in the initialization condition alpha ₀ (0) =1 andcalculating the alpha and beta values of all t;

eighth step: log-APP formulaAnd (5) calculating.

Since one interleaver step separates each encoder, the a priori information needs to be correctly deinterleaved at decoding. The same process is repeated for all decoders. An iteration refers to performing the aforementioned 4 steps, which may be repeated. At the end of the iteration, a matrix L of size a q' contains the log-APP of all decoders. By taking the sign of each log-APP of the q' bits, L can make a hard decision.

The novel physical layer design scheme based on the Turbo-FSK-QPSK technology has better performance than the existing industrial-level solution, the calculation complexity is obviously lower than the former, the limitation of channel capacity can be approximated, the good compromise of the performance and the complexity is realized, the spectrum efficiency and the energy efficiency are simultaneously considered, and the communication requirement of the low-power-consumption Internet of things can be realized.

Claims (2)

1. The novel physical layer design scheme based on the Turbo-FSK-QPSK technology is characterized by comprising the following steps:

consider that in a concatenated scheme, the transmitter interleaves the input signal with orthogonal FSK waveforms as codewords and sends the interleaved signals to the parity-check accumulation encoder;

decoding mode of posterior probability logarithmic ratio (log-APP) is utilized, which is related to channel observation value, and DFT is executed to received sequence by front end to calculate;

the transmitter takes orthogonal FSK waveforms as code words in a cascading scheme, and transmits the input signals after interleaving into a parity check accumulation encoder; comprising:

step 11, let Q be the information block matrix, the size is Q' ×N _q′ Thus N _q′ =q/Q ', i.e. the number of secondary words of length Q' in the information block. It has N _q′ A row vector b= { b _n } _{n∈{0，...，q′-1}} The Turbo-FSK-QPSK transmitter consists of a lambda-level parallel structure;

each row b of the input parity accumulation encoder is processed sequentially, step 12. The q' bit is calculated and the modulo-2 addition of the memory is performed and the memory is updated with the result. This process may be interpreted as applying an accumulator over the parity of the q' information bits. The encoder generates a word of length q '+1 bits, including a q' input bit and the output of the accumulator;

conventionally, the initial state of the memory is set to 0 and the final state is forced to 0 by adding an extra information word. Since the value of this word depends on the previous N _q′ Individual words, must be calculated during the encoding process. Finally, the encoder generates N of size m '=q' +1 _q′ +1 coding words;

step 13, combining these N _q′ +1 twoThe binary words are fed to an FSK mapping block which combines the m' bits with the alphabet4 m=2 of (2) ^m′ One of the codewords is associated. For executing FSK signals, ++>Constructed from hermite transposed Discrete Fourier Transform (DFT) matrix (or Inverse Discrete Fourier Transform (IDFT)), where +.>And: />

Wherein the method comprises the steps ofIs the M root of the unit. Thus, the output codeword is a row vector of 4M chips and each element is a complex number. Stage l (1 e { 0..lambda. -1 }) output size is 4M× (N _q′ +1) matrix S ⁽¹⁾ A representation;

step 14, the output of each stage is then connected to a signal x containing λ× (N _q′ +1) FSK codeword.

2. The method of claim 1, wherein the decoding method using a log-APP (log-APP) is related to a channel observation, and can be calculated by performing DFT on a received sequence by a front end, and comprises:

step 21, calculating p according to likelihood value given by detector and prior probability given by other decoderIs a product of (2);

step 22, for each conversion s'. Fwdarw.s, use formulaCalculation of gamma _t A value of (s', s);

step 23, under initialization condition α ₀ (0) =1 andcalculating the alpha and beta values of all t;

step 24, log-APP formulaCalculating;

since one interleaver step separates each encoder, the a priori information needs to be correctly deinterleaved at decoding. The same process is repeated for all decoders. An iteration refers to performing the aforementioned 4 steps, which may be repeated. At the end of the iteration, a matrix L of size a q' contains the log-APP of all decoders. By taking the sign of each log-APP of the q' bits, L can make a hard decision.