CN117877996A - Nano laminated Cu-Sn low-temperature solid diffusion bonding process method - Google Patents
Nano laminated Cu-Sn low-temperature solid diffusion bonding process method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 86
- 230000008569 process Effects 0.000 title claims abstract description 53
- 238000009792 diffusion process Methods 0.000 title claims abstract description 27
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 title claims abstract description 19
- 239000007787 solid Substances 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 121
- 238000007747 plating Methods 0.000 claims description 25
- 238000009713 electroplating Methods 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 239000002094 self assembled monolayer Substances 0.000 claims description 16
- 239000013545 self-assembled monolayer Substances 0.000 claims description 16
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 14
- 238000004140 cleaning Methods 0.000 claims description 13
- 229910017755 Cu-Sn Inorganic materials 0.000 claims description 11
- 229910017927 Cu—Sn Inorganic materials 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 238000007781 pre-processing Methods 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000012790 adhesive layer Substances 0.000 claims description 2
- 239000007888 film coating Substances 0.000 claims description 2
- 238000009501 film coating Methods 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000007731 hot pressing Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000010926 purge Methods 0.000 claims 1
- 238000005406 washing Methods 0.000 claims 1
- 229910052718 tin Inorganic materials 0.000 abstract description 22
- 229910052802 copper Inorganic materials 0.000 abstract description 18
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 238000001179 sorption measurement Methods 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229910020888 Sn-Cu Inorganic materials 0.000 abstract description 2
- 229910019204 Sn—Cu Inorganic materials 0.000 abstract description 2
- 230000006378 damage Effects 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 230000009467 reduction Effects 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract description 2
- 230000005476 size effect Effects 0.000 abstract description 2
- 239000010949 copper Substances 0.000 description 98
- 238000010586 diagram Methods 0.000 description 16
- 229910000765 intermetallic Inorganic materials 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000005496 eutectics Effects 0.000 description 4
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000003795 desorption Methods 0.000 description 3
- 125000000524 functional group Chemical group 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000002791 soaking Methods 0.000 description 3
- 229910052717 sulfur Inorganic materials 0.000 description 3
- 239000011593 sulfur Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000012864 cross contamination Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 150000003573 thiols Chemical class 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductor packaging, in particular to a nano laminated Cu-Sn low-temperature solid diffusion bonding process method. According to the invention, by manufacturing the micro-salient points of the Cu/Sn/Cu/Sn/Cu/Sn/Cu laminated structure, the bonding temperature is reduced, the Sn-Cu interface diffusion distance is shortened, the atomic diffusion and the reaction rate are promoted, and the formation of the IMC is rapidly and accurately controlled by utilizing the melting point reduction effect and the size effect of the nano metal. The nano metal layer can be deposited to obtain a pollution-free and high-activity surface, so that the atomic diffusion rate between metal bonding layers is improved, the bonding with high speed, low temperature and low damage is realized, the surface of the micro bump is pretreated, the pollution of the Cu and Sn surfaces caused by adsorption is prevented, and the bonding quality is improved. The process method can rapidly complete bonding in a low-temperature environment, has the advantages of obviously shortening bonding time, being beneficial to improving production efficiency and further reducing production cost.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a nano laminated Cu-Sn low-temperature solid diffusion bonding process method.
Background
Package bonding techniques applied to semiconductor packages, die attach, fine pitch interconnects, and 3D stacking based on Through Silicon Vias (TSVs) are strongly demanded for low temperature, short time interconnects. The low-temperature bonding process commonly used at present mainly comprises the following steps: wafer direct bonding, thermocompression bonding, surface activation bonding, adhesive bonding, eutectic bonding, and the like. The wafer direct bonding technology has extremely high requirements on the cleanliness and flatness of bonding surfaces, and meanwhile, longer annealing time is needed>120 min) and a higher annealing temperature to increase the strength of the bonding interface; thermal compression bonding is as high as conventional Cu-Cu thermal compression bonding>Bonding time at 350 DEG C>30min, then need>A heat treatment process for 30 min; in general, the eutectic bonding time needs to be long enough to ensure that the diffusion reaction can proceed sufficiently to achieve good bond strength. Eutectic bonding includes solid-liquid interdiffusion bonding and solid-state diffusion bonding, such as conventional Cu/Sn/Cu solid-liquid interdiffusion bonding, which generates all Cu at 300 DEG C 3 The time of the Sn intermetallic compound (IMC) is 360min, and the bonding time is relatively long; the bonding time for forming stable intermetallic compound (IMC) by traditional Cu/Sn/Cu solid diffusion bonding is relatively long, generally about 15min, and the long-time high-temperature environment is easy to cause thermal damage to certain parts of the chip.
In recent years, bonding has been advanced to a low temperature (100 ℃ to 300 ℃) and a short time (3 to 60 minutes), and under the driving of this goal, transient liquid phase diffusion (TLP) bonding, solid-liquid interdiffusion (SLID) low temperature bonding, and the like, which are mainly focused in the eutectic bonding, have been intensively studied on influencing factors of the grain orientation and the growth kinetics of IMCs. However, the preparation of high integrity IMCs using these traditional bonding methods has the problems of long bonding times (over several hundred minutes), high temperatures (> 260 ℃), and the like. Therefore, how to quickly and efficiently prepare IMCs with high reliability and high integrity is still one of the problems to be solved in the low-temperature bonding process.
The invention disclosed in the invention patent CN105679683a discloses a copper-tin-copper bonding process and structure based on copper nanorods, which are simple and controllable, have good repeatability, but have high bonding temperature (< 400 ℃) and relatively long bonding time (about 60 min).
The invention patent of China disclosed as CN111916344A discloses a copper-copper low-temperature bonding method based on graphene/tin modified copper nano particles, which can greatly reduce sintering temperature (200-300 ℃) and sintering time (15-30 min) and inhibit the formation of Cu-Sn IMCs, but has the problems of poor thermal stability, extremely easy oxidation and the like.
The invention patent of China disclosed as CN107195559A discloses a method for bonding tin-coated nano porous copper at low temperature, which solves the problems of easy oxidation of Cu, insignificant nano-size effect and the like, but the quality of the coated Sn is difficult to ensure by long-time heat treatment (200-250 ℃ for 2-3 h).
Disclosure of Invention
The invention aims at solving at least one of the technical problems existing in the prior art, and therefore, one aspect of the invention aims at providing a nano-laminated Cu-Sn low-temperature solid diffusion bonding process method, which comprises the following specific steps:
s1, preparing a single-polished oxide wafer, performing improved RCA cleaning, depositing a patterned Al wiring layer on the bonding surface of a top chip and a bottom chip by using a negative photoresist photoetching and coating process, and stripping a photoresist mask layer and an attached Al wiring layer; depositing a graphical Ti adhesion layer and a Cu seed layer on the bonding surface of the top chip and the bottom chip by using a negative photoresist photoetching and coating process;
s2, a Cu/Sn micro-bump is obtained on the surface of the Cu seed layer of the top chip by an electroplating process; a continuous alternate electroplating process is used for obtaining micro-salient points of a Cu/Sn/Cu/Sn/Cu/Sn/Cu laminated structure on the surface of a Cu seed layer of the bottom chip;
s3, forming a patterned nano metal layer on the bonding surface of the top chip and the bottom chip, depositing an inert nano metal layer on the surface of the micro-salient point by using a novel film coating process-femtosecond pulse laser system, and stripping the photoresist mask layer and the attached Ti adhesive layer, cu seed layer and nano metal layer;
s4, preprocessing the bonding surface of the micro-bump by utilizing a novel surface preprocessing method compounded by an Ar plasma preprocessing method and a self-assembled monolayer (SAM) preprocessing method;
s5, aligning and bonding the micro-bumps of the top chip Cu/Sn/Au and the micro-bumps of the bottom chip Cu/Sn/Cu/Sn/Cu/Sn/Cu/Au lamination structure by using a hot pressing mode.
Preferably, the Al wiring layer, the Ti adhesion layer and the Cu seed layer on the top chip and the bottom chip in S1 need to be patterned by using a negative photoresist lithography, a plating process and a lift-off process, and the Al wiring layer, the Ti adhesion layer and the Cu seed layer are one of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) plating processes.
Preferably, the thickness of the deposited Al wiring layer in the step S1 is 1um; the Ti adhesion layer has a thickness of 50nm and the Cu seed layer has a thickness of 100nm.
Preferably, in the step S2, the Cu micro-bump is firstly electroplated on the surface of the Cu seed layer of the top chip, then replaced by Sn plating solution, and the Sn micro-bump is rapidly and directly electroplated on the surface of the Cu micro-bump after being cleaned by simple DI water, so as to obtain the Cu/Sn micro-bump. Wherein, the plating solution can be Cu bump plating solution of Anmeite and Sn bump plating solution of Xinyang, and the plating current density is 3ASD; according to complete conversion to Cu 3 The thickness ratio of the Cu and Sn micro-bumps consumed by the Sn IMC phase is not lower than 1.32, and the thicknesses of the corresponding Cu and Sn micro-bumps are determined; the parameter current density of the selected Cu and Sn micro-bumps is 20mA/cm respectively 2 、30mA/cm 2 。
Preferably, in the step S2, a first layer of Cu micro-bump is electroplated on the surface of the Cu seed layer of the bottom chip, DI water is used for cleaning the Cu micro-bump, the Sn micro-bump is replaced by Sn plating solution, the Sn micro-bump is electroplated on the surface of the first layer of Cu micro-bump, DI water is used for cleaning the Sn micro-bump, the Cu micro-bump is replaced by Cu plating solution, a second layer of Cu micro-bump is continuously electroplated on the surface of the Sn micro-bump, the DI water is used for cleaning the Cu micro-bump, the Sn micro-bump is replaced by Sn plating solution, the Sn micro-bump is electroplated on the surface of the second layer of Cu micro-bump, and the steps are repeated, and the third layer of Cu micro-bump, the Sn micro-bump and the fourth layer of Cu micro-bump are continuously and alternately electroplated, so as to obtain the micro-bump with a Cu/Sn/Cu laminated structure. Wherein, the alternating electroplating times of the laminated Sn micro-bumps and Cu micro-bumps are determined according to the respective target thickness, and the thickness requirement is less than 1um; to avoid cross-contamination between Sn and Cu solutions, the cathode plate must be rinsed with DI water after each plating step.
Preferably, the thickness of the inert nano metal layer in the S3 is 3nm-5nm.
Preferably, the inert nano metal in the S3 is Au, ag, pt or Pd, so that a bonding surface with no pollution and high activity is obtained.
Preferably, ar plasma in the S4 pretreats the surfaces of the Sn micro-convex points of the top chip and the Cu micro-convex points of the bottom chip, and the working atmosphere is selected to mix 5%H in Ar 2 The method comprises the steps of carrying out a first treatment on the surface of the The output frequency and the maximum power are 13.56MHz and 600W; the gas flow is 200sccm, and the cleaning time is 30s, 60s or 90s; the pretreatment conditions can not only remove the pollution generated by adsorption on the surfaces of the micro-bumps, but also activate the surfaces of the Cu micro-bumps and the Sn micro-bumps.
Preferably, the self-assembled monolayer (SAM) pretreatment in S4 temporarily passivates the surface of the micro-bump, and the formation thereof is mainly determined by the interaction between the sulfur-based functional group and the metal atom, and by temporarily adsorbing a protective film on the surface of the micro-bump, the secondary oxidation and pollution of the surface of the Cu and Sn micro-bump can be effectively reduced or completely avoided, and the bonding process is removed from the surface of the micro-bump by thermal desorption.
Preferably, the bonding atmosphere in the step S5 is inert gas or vacuum, the bonding temperature is controlled to be 150-220 ℃, the bonding time is controlled to be 2-5 min, and the bonding pressure is controlled to be 5-10 MPa.
The invention has the following beneficial effects:
the invention designs a nano laminated Cu-Sn low-temperature solid diffusion bonding process method. According to the invention, by manufacturing the micro-salient points of the Cu/Sn/Cu/Sn/Cu/Sn/Cu laminated structure, the bonding temperature is reduced, the Sn-Cu interface diffusion distance is shortened, the atomic diffusion and the reaction rate are promoted, and the formation of the IMC is rapidly and accurately controlled by utilizing the melting point reduction effect and the size effect of the nano metal. The nano metal layer can be deposited to obtain a pollution-free and high-activity surface, and the atomic diffusion rate between metal bonding layers is improved, so that the bonding with high speed, low temperature and low damage is realized. And meanwhile, the surface of the micro-bump is pretreated by utilizing plasma and a self-assembled monolayer, so that pollution caused by adsorption on the surfaces of Cu and Sn is prevented, and the bonding quality is improved. The nano laminated Cu-Sn low-temperature solid diffusion bonding process method can rapidly finish bonding in a low-temperature environment, and has the advantages of remarkably shortening bonding time, being beneficial to improving production efficiency and further reducing production cost.
Additional aspects and advantages of the invention will become apparent in the following description or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic flow chart of an embodiment of the present invention;
FIG. 2 is a schematic diagram of the bottom chip and the top chip structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a photoresist mask layer for fabricating an Al wiring layer by using a photolithography process according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure of an Al wiring layer sputtered by a magnetron sputtering process according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a photoresist mask layer removal process according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a patterned mask layer for fabricating a Ti adhesion layer and a Cu seed layer using a photolithographic process in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure of a Ti adhesion layer and a Cu seed layer sputtered by a magnetron sputtering process according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a micro bump structure fabricated on a top chip using an electroplating process according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a stacked micro-bump structure fabricated on a bottom chip using an electroplating process in accordance with an embodiment of the present invention;
FIG. 10 is a schematic diagram of a nano-metal thin layer structure fabricated on a top chip using a femtosecond laser deposition process according to an embodiment of the invention;
FIG. 11 is a schematic diagram of a nano-metal thin layer structure fabricated on a bottom chip using a femtosecond laser deposition process according to an embodiment of the invention;
FIG. 12 is a schematic diagram of a structure for removing a photoresist mask layer on a top chip using a lift-off process according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of a process for removing a photoresist mask layer on a bottom chip using a lift-off process in accordance with an embodiment of the present invention;
FIG. 14 is a schematic diagram of a top chip micro-bump surface pre-treatment using a plasma process in accordance with an embodiment of the present invention;
FIG. 15 is a schematic diagram of a surface of a micro bump on a substrate chip pretreated by a plasma process in accordance with an embodiment of the present invention;
FIG. 16 is a schematic illustration of a top chip micro bump surface pretreatment using a self-assembled monolayer process in accordance with an embodiment of the present invention;
FIG. 17 is a schematic diagram of a self-assembled monolayer process for pre-treating the surface of a micro bump on a substrate chip according to an embodiment of the present invention;
FIG. 18 is a schematic diagram illustrating the bonding process according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced otherwise than as described, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
FIG. 1 is a flow chart showing the steps of the present embodiment, wherein an Al wiring layer, a Ti adhesion layer and a Cu seed layer are deposited on the bonding surface of the top chip and the bottom chip by photolithography, magnetron sputtering, lift-off and other processes, and then micro-bumps of a Cu/Sn/Cu/Sn/Cu/Sn/Cu laminated structure are prepared on the seed layer by using a continuous alternate electroplating process, and simultaneously nano-metal layers are deposited on the Cu and Sn surfaces by using a femtosecond laser deposition system, parameters of a plasma cleaner are adjusted to activate the Cu and Sn micro-bump surfaces, the processed sample is placed in a thiol organic solution to complete monolayer self-assembly, and finally, direct bonding of the low-temperature Cu-Sn nano-laminated layer is realized in a bonding machine.
As shown in fig. 2, a wafer (single polished oxide wafer) was prepared, modified RCA clean;
as shown in fig. 3, spin-coating negative photoresist NR9-3000PY on the bonding interface of the top chip and the bottom chip, exposing and developing to form a patterned mask layer;
as shown in fig. 4, an Al wiring layer is deposited to a thickness of 1um, and in the drawings of this embodiment, the Al wiring layer is sputtered only by using a magnetron sputtering process;
as shown in fig. 5, stripping, removing the photoresist of the mask layer and the Al wiring layer attached to the mask layer, and in the embodiment, only using an acetone solution soaking mode in the drawing;
as shown in fig. 6, spin-coating negative photoresist NR9-3000PY on the bonding interface between the top chip and the bottom chip, exposing and developing to form a patterned mask layer;
as shown in fig. 7, a Ti adhesion layer and a Cu seed layer are sequentially deposited on the surface of the Al wiring layer, wherein the thickness of the Ti adhesion layer is 50nm, and the thickness of the Cu seed layer is 100nm, and in the embodiment, the Ti adhesion layer and the Cu seed layer are sputtered only by using a magnetron sputtering process in the drawing;
as shown in fig. 8, the surface of the Cu seed layer of the top chip is firstly electroplated with the Cu micro-bump, then replaced with the Sn plating solution, and after being cleaned by simple DI water, the surface of the Cu micro-bump is rapidly and directly electroplated with the Sn micro-bump; wherein, the plating solution can be Cu bump plating solution of Anmeite and Sn bump plating solution of Xinyang, and the plating current density is 3ASD; according to complete conversion to Cu 3 The thickness ratio of the Cu and Sn micro-bumps consumed by the Sn IMC phase is not lower than 1.32, and the thicknesses of the corresponding Cu and Sn micro-bumps are determined; the parameter current density of the selected Cu and Sn micro-bumps is 20mA/cm respectively 2 、30mA/cm 2 Calculating the required electroplating time according to the target thickness and the electroplating rate of electroplating;
as shown in fig. 9, a first layer of Cu micro-bumps is electroplated on the surface of a Cu seed layer of the bottom chip, DI water is used for cleaning the Cu micro-bumps, the Sn micro-bumps are replaced by Sn plating solution, the Sn micro-bumps are electroplated on the surface of the first layer of Cu micro-bumps, DI water is used for cleaning the Sn micro-bumps, the Cu plating solution is replaced by Cu plating solution, a second layer of Cu micro-bumps is continuously electroplated on the surface of the Sn micro-bumps, DI water is used for cleaning the Cu micro-bumps, the Sn micro-bumps are replaced by Sn plating solution, the Sn micro-bumps are electroplated on the surface of the second layer of Cu micro-bumps, and the steps are repeated, so that a third layer of Cu micro-bumps, a Sn micro-bumps and a fourth layer of Cu micro-bumps are continuously and alternately electroplated; wherein, the alternating electroplating times of the laminated Sn micro-bumps and Cu micro-bumps are determined according to the respective target thickness, and the thickness requirement is less than 1um; to avoid cross-contamination between Sn and Cu solutions, the cathode plate must be rinsed with DI water after each plating step;
as shown in fig. 10, a thin inert metal layer of 3-5nm is deposited on the surface of the Sn micro-bump of the top chip by a femtosecond laser deposition system, and in the embodiment, only inert metal Au is used as the deposited nano metal layer in the drawing;
as shown in fig. 11, a thin inert metal layer of 3-5nm is deposited on the surface of the bottom chip Cu micro-bump by a femtosecond laser deposition system, and in the embodiment, only inert metal Au is used as the deposited nano metal layer in the drawing;
as shown in fig. 12, stripping is performed to remove the photoresist of the mask layer of the top chip and the Ti adhesion layer, the Cu seed layer and the nano metal layer attached to the mask layer, and only an acetone solution soaking mode is used in the embodiment of the drawing;
as shown in fig. 13, stripping is performed to remove the photoresist of the mask layer of the bottom chip and the Ti adhesion layer, the Cu seed layer and the nano metal layer attached to the mask layer, and only an acetone solution soaking mode is used in the embodiment of the drawing;
as shown in FIG. 14, the surface of the Sn micro-bump of the top chip is pretreated by plasma, and 5%H is mixed into Ar in the working atmosphere 2 The method comprises the steps of carrying out a first treatment on the surface of the The output frequency and the maximum power are 13.56MHz and 600W; the flow rate of the used gas is 200sccm; the cleaning time can be one of 30s, 60s, 90s, etc.; the pretreatment conditions can not only remove the pollution generated by adsorption on the surfaces of the micro-bumps, but also activate the surfaces of the Cu micro-bumps and the Sn micro-bumps;
as shown in FIG. 15, the surface of the Cu micro-bump of the bottom chip is pretreated by plasma, and 5%H is mixed in Ar in the working atmosphere 2 The method comprises the steps of carrying out a first treatment on the surface of the The output frequency and the maximum power are 13.56MHz and 600W; the flow rate of the used gas is 200sccm; cleaningThe time may be one of 30s, 60s, 90s, etc.; the pretreatment conditions can not only remove the pollution generated by adsorption on the surfaces of the micro-bumps, but also activate the surfaces of the Cu micro-bumps and the Sn micro-bumps;
as shown in fig. 16, a self-assembled monolayer (SAM) temporarily passivates the surface of the Sn micro-bump of the top chip, the formation of the SAM mainly depends on the interaction between the sulfur-based functional group and the metal atom, and by temporarily adsorbing a layer of protective film on the surface of the micro-bump, secondary oxidation and pollution of Cu and Sn micro-bump surfaces can be effectively reduced or completely avoided, and the bonding process is removed from the surface of the micro-bump by thermal desorption;
as shown in fig. 17, a self-assembled monolayer (SAM) temporarily passivates the surface of the fourth layer of Cu micro-bump of the bottom chip, and the formation of the SAM is mainly dependent on the interaction between the sulfur-based functional group and the metal atom, so that secondary oxidation and pollution of the surface of the Cu and Sn micro-bump can be effectively reduced or completely avoided by temporarily adsorbing a layer of protective film on the surface of the micro-bump, and the bonding process is removed from the surface of the micro-bump by thermal desorption;
as shown in FIG. 18, the bonding equipment is an FC150 type chip-level bonding machine, the bonding environment atmosphere is inert gas or vacuum, the bonding temperature is controlled at 150-220 ℃, the bonding time is controlled at 2-5 min, the bonding pressure is controlled at 5-10 MPa, and the surfaces of the bonding structures are fully contacted by adjusting manual or automatic calibration to realize final bonding.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A nano laminated Cu-Sn low-temperature solid diffusion bonding process method is characterized in that: the specific steps of the process method are as follows:
s1, preparing a single-polished oxide wafer, performing improved RCA cleaning, depositing a patterned Al wiring layer on the bonding surface of a top chip and a bottom chip by using a negative photoresist photoetching and coating process, and stripping a photoresist mask layer and an attached Al wiring layer; depositing a graphical Ti adhesion layer and a Cu seed layer on the bonding surface of the top chip and the bottom chip by using a negative photoresist photoetching and coating process;
s2, a Cu/Sn micro-bump is obtained on the surface of the Cu seed layer of the top chip by an electroplating process; a continuous alternate electroplating process is used for obtaining micro-salient points of a Cu/Sn/Cu/Sn/Cu/Sn/Cu laminated structure on the surface of a Cu seed layer of the bottom chip;
s3, forming a patterned nano metal layer on the bonding surface of the top chip and the bottom chip, depositing an inert nano metal layer on the surface of the micro-salient point by using a novel film coating process-femtosecond pulse laser system, and stripping the photoresist mask layer and the attached Ti adhesive layer, cu seed layer and nano metal layer;
s4, preprocessing the bonding surface of the micro-bump by using a novel surface preprocessing method compounded by an Ar plasma preprocessing method and a self-assembled monolayer preprocessing method;
s5, aligning and bonding the micro-bumps of the top chip Cu/Sn/Au and the micro-bumps of the bottom chip Cu/Sn/Cu/Sn/Cu/Sn/Cu/Au lamination structure by using a hot pressing mode.
2. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: the Al wiring layer, the Ti adhesion layer and the Cu seed layer on the top chip and the bottom chip in the S1 are required to be patterned by utilizing negative photoresist photoetching, coating and stripping processes, and the Al wiring layer, the Ti adhesion layer and the Cu seed layer are one of physical vapor deposition, chemical vapor deposition and atomic layer deposition coating processes.
3. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: the thickness of the deposited Al wiring layer in the S1 is 1um; the Ti adhesion layer has a thickness of 50nm and the Cu seed layer has a thickness of 100nm.
4. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: in the step S2, firstly electroplating a Cu micro-bump on the surface of a Cu seed layer of a top chip, then replacing the Cu seed layer with Sn plating solution, and rapidly and directly electroplating the Sn micro-bump on the surface of the Cu micro-bump after washing with simple DI water to obtain the Cu/Sn micro-bump.
5. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: and in the step S2, electroplating a first layer of Cu micro-bumps on the surface of a Cu seed layer of the bottom chip, cleaning the Cu micro-bumps by DI water, replacing the Cu micro-bumps with Sn plating solution, electroplating the Sn micro-bumps on the surface of the first layer of Cu micro-bumps, cleaning the Sn micro-bumps by DI water, replacing the Sn micro-bumps with Cu plating solution, continuously electroplating a second layer of Cu micro-bumps on the surface of the Sn micro-bumps, cleaning the Cu micro-bumps by DI water, replacing the Sn plating solution, electroplating the Sn micro-bumps on the surface of the second layer of Cu micro-bumps, repeating the steps, and continuously and alternately electroplating a third layer of Cu micro-bumps, the Sn micro-bumps and a fourth layer of Cu micro-bumps to obtain the micro-bumps with a Cu/Sn/Cu/Sn/Cu laminated structure.
6. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: the thickness of the inert nano metal layer in the step S3 is 3nm-5nm.
7. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: the inert nano metal in the S3 is Au, ag, pt or Pd.
8. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: ar plasma in the S4 is used for preprocessing the surfaces of the Sn micro-bumps of the top chip and the Cu micro-bumps of the bottom chip, and the Ar is selected to be mixed with 5%H 2 The method comprises the steps of carrying out a first treatment on the surface of the The output frequency and the maximum power are 13.56MHz and 600W; the purge time was 30s, 60s or 90s using a gas flow of 200 sccm.
9. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: and S4, performing self-assembled monolayer (SAM) pretreatment to temporarily passivate the surface of the micro-bump.
10. The method for nano-stack Cu-Sn low temperature solid state diffusion bonding process of claim 1, wherein: and (5) selecting inert gas or vacuum in the bonding atmosphere in the step (S5), wherein the bonding temperature is controlled to be 150-220 ℃, the bonding time is controlled to be 2-5 min, and the bonding pressure is controlled to be 5-10 MPa.
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