CN117875261A - Verification method and device for rectangular inclusion rule in integrated circuit layout verification - Google Patents
Verification method and device for rectangular inclusion rule in integrated circuit layout verification Download PDFInfo
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Abstract
The application discloses a verification method and device for rectangular inclusion rules in integrated circuit layout verification, comprising the steps of moving edges of a polygon to be verified in a first preset direction to a second preset direction by the width of a preset matrix, scanning a determined graph block by utilizing a scanning line, and indicating that the polygon to be verified can contain the preset rectangle if the graph block with the upper and lower spans being greater than or equal to the length of the rectangle to be verified exists, wherein the graph block is more than one graph block with the positive number such as 1 and formed by the surrounding number of the moved edges and the remaining edges of the polygon. By the verification method for the rectangle inclusion rule in the integrated circuit layout verification, the rectangle inclusion rule verification is rapidly and effectively realized.
Description
Technical Field
The present invention relates to, but not limited to, semiconductor integrated circuit technology, and more particularly, to a method and apparatus for verifying rectangular inclusion rules in integrated circuit layout verification.
Background
In DRC verification of an integrated circuit layout, a rectangle-containing rule refers to a pattern for a layer in the integrated circuit layout that verifies whether it can contain a rectangle of a given length and width, wherein the manner in which the rectangle is contained is defined as three types of horizontal inclusion, 45 degree inclusion, or 135 degree inclusion.
Along with the smaller and smaller feature sizes of chips, the integration level of a single chip is higher and higher, and how to quickly and effectively realize rectangular inclusion rule verification in large-scale integrated circuit layout verification is a technical problem to be solved.
Disclosure of Invention
The invention provides a verification method and device for rectangular inclusion rules in integrated circuit layout verification, which can quickly and effectively realize rectangular inclusion rule verification.
The embodiment of the invention provides a verification method for rectangular inclusion rules in integrated circuit layout verification, which comprises the following steps:
moving the edge of the polygon to be verified in the first preset direction to the width of a preset matrix in the second preset direction; the polygon to be verified is a graph of a certain layer in the integrated circuit layout, and the direction of the outer contour edge of the polygon to be verified is opposite to the direction of the inner contour edge of the polygon to be verified; the angle of the polygon to be verified is consistent with the angle of the preset rectangle;
determining more than one graph blocks with positive surrounding numbers formed by the moved edges and the polygonal residual edges;
and scanning the determined graph blocks by using a scanning line, and if the graph blocks with the upper and lower spans being larger than or equal to the length of the rectangle to be verified exist, indicating that the polygon to be verified can contain the preset rectangle.
In an exemplary embodiment, the moving the sides of the first preset direction of the polygon to be verified to the second preset direction by the width of the preset matrix includes:
and acquiring all y coordinates of the polygon to be verified, initializing a first edge table and a first movable edge table by using a scanning line algorithm, and translating the edge in the first preset direction to the distance of the width of the preset rectangle in the second preset direction for the edge in the first preset direction.
In one exemplary embodiment, the determining the more than one graphics blocks with positive numbers of circles formed by the moved edges and the polygon surplus edges includes:
and updating the first movable edge table by utilizing scanning line scanning, continuously obtaining the graph blocks with the surrounding number equal to 1, and obtaining more than one graph block after the scanning is completed.
In an exemplary embodiment, the indicating that the polygon to be verified can include a preset rectangle includes:
acquiring all x coordinates of the graph block, and initializing a second edge table and a second movable edge table by using a scanning line algorithm;
updating a second movable edge table by scanning a scanning line, and acquiring the y coordinate of each intersection point of the scanning line and the edge forming the graph block to obtain the up-down span of the graph block;
and if the length of the upper span and the lower span which are larger than or equal to the preset rectangle exists in the scanning process, indicating that the polygon to be verified contains the preset rectangle.
In an exemplary example, the first preset direction edge may be an upward edge; the second preset direction is a horizontal direction.
The embodiment of the application also provides a computer readable storage medium, which stores computer executable instructions for executing the verification method of the rectangle containing rule in the integrated circuit layout verification.
Embodiments of the present application further provide a computer device comprising a memory and a processor, wherein the memory stores instructions executable by the processor to: a step of executing the verification method of rectangle containing rule in integrated circuit layout verification according to any one of the above.
The embodiment of the application also provides a verification device for rectangular inclusion rule in integrated circuit layout verification, comprising: the device comprises a processing module, a determining module and a verifying module; wherein,
the processing module is used for moving the edge of the polygon to be verified in the first preset direction to the width of the preset matrix in the second preset direction; the polygon to be verified is a graph of a certain layer in the integrated circuit layout, and the direction of the outer contour edge of the polygon to be verified is opposite to the direction of the inner contour edge of the polygon to be verified; the angle of the polygon to be verified is consistent with the angle of the preset rectangle;
the determining module is used for determining more than one graph blocks with positive surrounding numbers formed by the moved edges and the polygonal residual edges;
and the verification module is used for scanning the determined graphic blocks by using the scanning lines, and if the graphic blocks with the upper and lower spans being greater than or equal to the length of the rectangle to be verified exist, the polygon to be verified can contain the preset rectangle.
In one illustrative example, the processing module is to:
and acquiring all y coordinates of the polygon to be verified, initializing a first edge table and a first movable edge table by using a scanning line algorithm, and translating the edge in the first preset direction to the distance of the width of the preset rectangle in the second preset direction for the edge in the first preset direction.
In one illustrative example, the determination module is to:
and updating the first movable edge table by utilizing scanning line scanning, continuously obtaining the graph blocks with the surrounding number equal to 1, and obtaining more than one graph block after the scanning is completed.
In one illustrative example, the verification module is to:
acquiring all x coordinates of the graph block, and initializing a second edge table and a second movable edge table by using a scanning line algorithm;
updating a second movable edge table by scanning a scanning line, and acquiring the y coordinate of each intersection point of the scanning line and the edge forming the graph block to obtain the up-down span of the graph block;
and if the length of the upper span and the lower span which are larger than or equal to the preset rectangle exists in the scanning process, indicating that the polygon to be verified contains the preset rectangle.
The verification method for the rectangle inclusion rule in the integrated circuit layout verification provided by the embodiment of the application comprises the steps of moving the edge of the polygon to be verified in the first preset direction to the second preset direction by the width of a preset matrix, scanning the determined graph blocks by utilizing a scanning line, and if the graph blocks with the upper span and the lower span being greater than or equal to the length of the rectangle to be verified exist, indicating that the polygon to be verified can include the preset rectangle, wherein the graph blocks are more than one graph blocks with the number of circles formed by the moved edge and the remaining edge of the polygon being positive, such as 1. By the verification method for the rectangle inclusion rule in the integrated circuit layout verification, the rectangle inclusion rule verification is rapidly and effectively realized.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a flow chart of a verification method for rectangular inclusion rules in verification of an integrated circuit layout in an embodiment of the present application;
FIG. 2 is an example of a polygon to be verified in an embodiment of the present application;
FIG. 3 is a schematic diagram of a result of edge movement processing in a first preset direction for the polygon to be verified shown in FIG. 2 according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a process for determining a graphics block by scanning a scan line in an embodiment of the present application;
fig. 5 is a schematic diagram of a composition structure of a verification device for verifying a rectangular inclusion rule in integrated circuit layout in an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It is to be understood that the terms "first," "second," and the like, as used herein, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
The steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.
Fig. 1 is a flow chart of a verification method of rectangular inclusion rule in verification of an integrated circuit layout in an embodiment of the present application, and as shown in fig. 1, may include:
step 100: moving the edge of the polygon to be verified in the first preset direction to the width of a preset matrix in the second preset direction; the polygon to be verified is a graph of a certain layer in the integrated circuit layout, and the direction of the outer contour edge of the polygon to be verified is opposite to the direction of the inner contour edge of the polygon to be verified; the angle of the polygon to be verified is consistent with the angle of the preset rectangle.
In an exemplary embodiment, fig. 2 is an example of a polygon to be verified in the embodiment of the present application, where, as shown by the arrow direction on the sides of the polygon to be verified in fig. 2, the direction of the outer contour side of the polygon to be verified in the embodiment is clockwise, the direction of the inner contour side of the polygon to be verified is counterclockwise, that is, the direction of the side of the inner hole of the polygon to be verified is counterclockwise, and the direction of the outer contour side of the polygon to be verified is opposite to the direction of the inner contour side thereof.
In an exemplary embodiment, as shown in fig. 2, the coordinates of the vertices of the polygon formed by the outer contour sides of the polygon to be verified are (2, 0), (0, 7) and (6, 2), respectively, the directions of the outer contour sides are clockwise, a hole is formed in the polygon to be verified, the coordinates of the vertices of the polygon formed by the outer contour sides of the hole (i.e., the inner contour sides of the polygon to be verified) are (3, 1), (4, 2) and (2, 3), respectively, and the directions of the sides of the hole are counterclockwise. In one embodiment, as shown in fig. 2, this embodiment takes as an example a horizontally placed preset rectangle for verifying whether any polygon to be verified can include a left-right span, i.e. a width W, and a top-bottom span, i.e. a length L, such as a preset rectangle having a width W of 1 and a length L of 2, so that the angle of the polygon to be verified is horizontally placed in the X direction.
In other embodiments, to verify whether any polygon to be verified can include any preset rectangle placed at will, then, only the polygon to be verified is placed at the angle of the arbitrary angle with the X direction, that is, the polygon to be verified is rotated by the arbitrary angle to be consistent with the angle of the preset rectangle. The verification method for the rectangle inclusion rule in the integrated circuit layout verification is applicable to any polygon to be verified, and the preset rectangle can be a scene placed at any angle, so long as the direction of the angle where the preset rectangle is located is reduced by rotating the original polygon to be verified.
In one illustrative example, the first predetermined direction edge may be an upward edge. In computer graphics, an edge is typically defined by two endpoints, a start point and an end point. The direction of the edge points from the start point to the end point. In the scanline algorithm, the upward edge refers to an edge having a rising slope, i.e., an edge extending from the bottom to the top.
In an exemplary embodiment, the second preset direction may be a direction in which the polygon to be processed is located, such as a horizontal direction in fig. 2. In one embodiment, the second predetermined direction is an X-direction, i.e., a right-direction translation. Taking the polygon to be verified as shown in fig. 2 as an example, moving the upward side of the polygon to be verified to the right by a preset rectangular width W, and for the polygon formed by the outer contour sides of the polygon to be verified, the starting point is (2, 0) and the end point is (0, 7), and after the upward side moves to the right by the width W of 1, as shown in fig. 3, obtaining a line segment with the starting point of (3, 0) and the end point of (1, 7); for the polygon formed by the inner contour sides of the polygon to be verified, the sides with the starting point (3, 1) and the ending point (4, 2) and the sides with the starting point (4, 2) and the ending point (2, 3) are both upward sides, and after the two upward sides move to the right by the width W of 1, as shown in FIG. 3, a line segment with the starting point (4, 1) and the ending point (5, 2) and a line segment with the starting point (5, 2) and the ending point (3, 3) are obtained.
In the above embodiments, the side moving upward in the horizontal direction from left to right is merely taken as an example, and the scope of protection of the present application is not limited. In other embodiments, the first preset direction may be a certain direction of the edge, such as a downward edge, a leftward edge, etc., and the second preset direction may be other directions, such as a vertical direction, etc.
In an exemplary embodiment, all y coordinates of the polygon to be verified shown in fig. 2 may be acquired first, and a first Edge Table (Edge Table) and a first active Edge Table (Active Edge Table) are initialized by using a scan line algorithm, and for an upward Edge, the upward Edge is shifted to the right by a distance equal to the width W of the preset rectangle, and fig. 3 graphically illustrates the processing of the Edge of the polygon to be verified in fig. 2, where all upward edges are shifted to the right by a distance equal to the width w=1 of the preset rectangle.
Step 101: and determining more than one graph blocks with positive numbers of surrounding numbers formed by the moved edges and the polygon residual edges.
In an exemplary embodiment, the first active side table is updated by scanning the scan line (e.g., the scan line scans from bottom to top), so that the graphic blocks with the number of circles being positive, for example, 1 are continuously acquired, and after the scanning is completed, all the graphic blocks with the number of circles being positive, for example, 1 are acquired. The shaded portion shown in fig. 3 is a graphic block in which all the surrounding numbers are positive numbers such as 1. It should be noted that, since all y coordinates of the polygon to be verified are obtained, it is relatively convenient to update the first active edge table according to the y value, but in practice, only the information of all the graphics blocks can be obtained finally, and what scanning direction is used for scanning is not limited.
A graphic block whose number of windings (winding number) is positive, such as 1, generally refers to a graphic formed by a path around a certain point in a complex plane. The wrap-around number may be used to determine whether a point is inside or outside the closed curve. When the number of circles is positive, this point is shown inside the closed curve; when the number of circles is negative, this point is indicated to be outside the closed curve; when the wrap-around number is zero, this point is indicated on the closed curve. If the number of windings of a graphic block is equal to 1, then the boundary of this graphic block forms a closed curve that wraps exactly one round around a point on the complex plane. Such a graphic block may be of various shapes such as a circle, an ellipse, a polygon, etc., as long as the closed curve formed by its boundary is wound just one turn around a certain point, and the number of turns is 1.
Step 102: and scanning the determined graph blocks by using a scanning line, and if the graph blocks with the upper and lower spans being larger than or equal to the length of the rectangle to be verified exist, indicating that the polygon to be verified can contain the preset rectangle.
In one illustrative example, step 102 may include:
acquiring all x coordinates of the graph block, and initializing a new second side table and a second movable side table by using a scanning line algorithm;
updating the second movable edge table by scanning the scanning line (the scanning line scans horizontally such as from left to right or from right to left), and acquiring the y coordinate of each intersection point of the scanning line and the edges forming the graph block to obtain the up-down span of the graph block; in this embodiment, in the process of updating the second active edge table by scanning the scan line, there may be many intersections between the scan line and the edges constituting the graphics block, and the upper and lower spans of the graphics block are obtained by obtaining the y coordinate of each intersection;
if a certain up-down span is greater than or equal to the length L of the preset rectangle in the scanning process, the polygon to be verified can comprise a preset rectangle which is horizontally placed, and the left-right span is the width W, and the up-down span is the length L.
In this embodiment of the present application, if the scan line continues to be moved until the end, and if a length L with a span of up and down greater than or equal to the preset rectangle cannot be found until the end, it indicates that the polygon to be verified cannot include the preset rectangle.
This is illustrated in fig. 4, where the arrow shows the vertical line moving from left to right as the scan line, the scan direction from left to right, and the intersection points a, B are the intersection points of the current scan line and the edges of the graphic block. In fig. 4, the difference between the y coordinates of the intersection points a and B is greater than 2, which indicates that the polygon to be verified can be placed in a preset rectangle with a horizontal span, i.e., a width W of 1 and a vertical span, i.e., a length L of 2. In one embodiment, the upward sides of the original polygon to be verified are horizontally moved, the moving distance is the left-right span of the preset rectangle, the number of circles formed by all the moved sides is positive, for example, a vertical line segment in a graphic block equal to 1 is in one-to-one correspondence with a horizontally placed rectangle contained in the polygon to be verified.
The scan line in fig. 4 is a straight line that is vertical, and a scan line at a certain position has an intersection with the side constituting the graphics block. These adjacent intersections are connected inside the graphic block to form one or more line segments, i.e., vertical line segments. These vertical line segments are the portions where the scan lines overlap the graphics block. The vertical span of a vertical line segment is in fact the height of a rectangle that can just be accommodated, the horizontal length of this rectangle being the distance moved to the right. It should be noted that, in one embodiment, the graphics block is obtained by moving the upward edge to the right, and then the original polygon to be verified may be restored by moving the upward edge to the left. That is, the vertical line segment is the right and left sides of the rectangle that can just be accommodated. The original polygon to be verified is restored by moving the left side upwards, and the left side is also moved leftwards, and after the original polygon to be verified is restored, the middle rectangle formed by the left side and the right side is inevitably inside the polygon.
As can be seen from the embodiment of the present application, any preset rectangle is a horizontally placed polygon, and if the polygon to be verified may include a horizontally placed preset rectangle, the number of circles of the polygon to be verified in the preset rectangle area is positive, for example, equal to 1, and vice versa. Thus, for the embodiment of moving the upward sides of the polygon to be verified horizontally to the right, the synchronous movement to the right may include the left side of the preset rectangle until the left side and the right side of the preset rectangle overlap into a line segment, during which the preset rectangle (the last line segment) that is continuously narrowed in the horizontal direction is always located in the area where the number of circles made up of all sides of the polygon to be verified is positive, such as 1. Conversely, if the vertical line segment with the length equal to the height of the polygon to be verified can be found in the area with the final number of circles being positive, such as 1, the preset rectangle is found. The verification method for the rectangle inclusion rule in the integrated circuit layout verification provided by the embodiment of the application can be used for rapidly and effectively realizing the verification of the rectangle inclusion rule.
The application further provides a computer readable storage medium storing computer executable instructions for executing the verification method of rectangular inclusion rules in integrated circuit layout verification according to any one of the above.
The present application further provides a computer device comprising a memory and a processor, wherein the memory stores instructions executable by the processor to: a step of executing the verification method of rectangle containing rule in integrated circuit layout verification according to any one of the above.
Fig. 5 is a schematic diagram of a composition structure of a verification device for verifying a rectangular inclusion rule in integrated circuit layout according to an embodiment of the present application, and as shown in fig. 5, may include: the device comprises a processing module, a determining module and a verification module; wherein,
the processing module is used for moving the edge of the polygon to be verified in the first preset direction to the width of the preset matrix in the second preset direction; the polygon to be verified is a graph of a certain layer in the integrated circuit layout, and the direction of the outer contour edge of the polygon to be verified is opposite to the direction of the inner contour edge of the polygon to be verified; the angle of the polygon to be verified is consistent with the angle of the preset rectangle;
the determining module is used for determining more than one graph blocks with positive surrounding numbers formed by the moved edges and the polygonal residual edges;
and the verification module is used for scanning the determined graphic blocks by using the scanning lines, and if the graphic blocks with the upper and lower spans being greater than or equal to the length of the rectangle to be verified exist, the polygon to be verified can contain the preset rectangle.
In one illustrative example, a processing module may be used to:
all y coordinates of the polygon to be verified are obtained, a scanning line algorithm is used, a first edge table and a first movable edge table are initialized, and for the edges in the first preset direction, the edges in the first preset direction are translated to the second preset direction by the distance of the width W of the preset rectangle.
In one illustrative example, the determination module may be to:
and updating the first movable edge table by utilizing scanning line scanning, continuously acquiring the graph blocks with the surrounding number equal to 1, and acquiring all the graph blocks with the surrounding number equal to 1 after the scanning is completed.
In one illustrative example, the verification module may be configured to:
acquiring all x coordinates of the graph block, and initializing a new second side table and a second movable side table by using a scanning line algorithm;
updating the second movable edge table by scanning the scanning line, and acquiring the y coordinate of each intersection point of the scanning line and the edges forming the graph block to obtain the upper span and the lower span of the graph block;
if a certain length L with the upper and lower spans larger than or equal to the preset rectangle exists in the scanning process, the polygon to be verified can comprise the preset rectangle placed in the second preset direction.
The verifying device for verifying the rectangle containing rule in the integrated circuit layout comprises a step of moving the edge of the polygon to be verified in the first preset direction to the width of a preset matrix in the second preset direction, and a step of utilizing a scanning line to scan the determined graph blocks, wherein if the graph blocks with the upper span and the lower span being greater than or equal to the length of the rectangle to be verified exist, the polygon to be verified can contain the preset rectangle, and the graph blocks are more than one graph blocks with the surrounding number being equal to 1, wherein the surrounding number is formed by the moved edge and the remaining edge of the polygon. By the verification method for the rectangle inclusion rule in the integrated circuit layout verification, the rectangle inclusion rule verification is rapidly and effectively realized.
Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims appended hereto.
Claims (11)
1. A verification method for rectangular inclusion rule in integrated circuit layout verification is characterized by comprising the following steps:
moving the edge of the polygon to be verified in the first preset direction to the width of a preset matrix in the second preset direction; the polygon to be verified is a graph of a certain layer in the integrated circuit layout, and the direction of the outer contour edge of the polygon to be verified is opposite to the direction of the inner contour edge of the polygon to be verified; the angle of the polygon to be verified is consistent with the angle of the preset rectangle;
determining more than one graph blocks with positive surrounding numbers formed by the moved edges and the polygonal residual edges;
and scanning the determined graph blocks by using a scanning line, and if the graph blocks with the upper and lower spans being larger than or equal to the length of the rectangle to be verified exist, indicating that the polygon to be verified can contain the preset rectangle.
2. The method according to claim 1, wherein moving the sides of the polygon to be verified in the first predetermined direction by a width of a predetermined matrix in the second predetermined direction comprises:
and acquiring all y coordinates of the polygon to be verified, initializing a first edge table and a first movable edge table by using a scanning line algorithm, and translating the edge in the first preset direction to the distance of the width of the preset rectangle in the second preset direction for the edge in the first preset direction.
3. The method according to claim 2, wherein determining the more than one graphics block whose number of circles formed by the moved edge and the polygon remaining edge is positive includes:
and updating the first movable edge table by utilizing scanning line scanning, continuously obtaining the graph blocks with the surrounding number equal to 1, and obtaining more than one graph block after the scanning is completed.
4. A method of validating as claimed in claim 1, 2 or 3, wherein the indicating that the polygon to be validated can comprise a preset rectangle comprises:
acquiring all x coordinates of the graph block, and initializing a second edge table and a second movable edge table by using a scanning line algorithm;
updating a second movable edge table by scanning a scanning line, and acquiring the y coordinate of each intersection point of the scanning line and the edge forming the graph block to obtain the up-down span of the graph block;
and if the length of the upper span and the lower span which are larger than or equal to the preset rectangle exists in the scanning process, indicating that the polygon to be verified contains the preset rectangle.
5. The method of claim 1, wherein the first predetermined direction edge is an upward edge; the second preset direction is a horizontal direction.
6. A computer-readable storage medium storing computer-executable instructions for performing the verification method of rectangular inclusion rules in integrated circuit layout verification of any one of claims 1-5.
7. A computer device comprising a memory and a processor, wherein the memory has stored therein instructions executable by the processor to: a step for executing the verification method of rectangular inclusion rule in the integrated circuit layout verification of any one of claims 1 to 5.
8. A verification apparatus for verifying a rectangular inclusion rule in an integrated circuit layout, comprising: the device comprises a processing module, a determining module and a verifying module; wherein,
the processing module is used for moving the edge of the polygon to be verified in the first preset direction to the width of the preset matrix in the second preset direction; the polygon to be verified is a graph of a certain layer in the integrated circuit layout, and the direction of the outer contour edge of the polygon to be verified is opposite to the direction of the inner contour edge of the polygon to be verified; the angle of the polygon to be verified is consistent with the angle of the preset rectangle;
the determining module is used for determining more than one graph blocks with positive surrounding numbers formed by the moved edges and the polygonal residual edges;
and the verification module is used for scanning the determined graphic blocks by using the scanning lines, and if the graphic blocks with the upper and lower spans being greater than or equal to the length of the rectangle to be verified exist, the polygon to be verified can contain the preset rectangle.
9. The authentication device of claim 8, wherein the processing module is configured to:
and acquiring all y coordinates of the polygon to be verified, initializing a first edge table and a first movable edge table by using a scanning line algorithm, and translating the edge in the first preset direction to the distance of the width of the preset rectangle in the second preset direction for the edge in the first preset direction.
10. The authentication device of claim 9, wherein the determining module is configured to:
and updating the first movable edge table by utilizing scanning line scanning, continuously obtaining the graph blocks with the surrounding number equal to 1, and obtaining more than one graph block after the scanning is completed.
11. The authentication device of claim 8, 9 or 10, wherein the authentication module is configured to:
acquiring all x coordinates of the graph block, and initializing a second edge table and a second movable edge table by using a scanning line algorithm;
updating a second movable edge table by scanning a scanning line, and acquiring the y coordinate of each intersection point of the scanning line and the edge forming the graph block to obtain the up-down span of the graph block;
and if the length of the upper span and the lower span which are larger than or equal to the preset rectangle exists in the scanning process, indicating that the polygon to be verified contains the preset rectangle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410281550.9A CN117875261B (en) | 2024-03-13 | 2024-03-13 | Verification method and device for rectangular inclusion rule in integrated circuit layout verification |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410281550.9A CN117875261B (en) | 2024-03-13 | 2024-03-13 | Verification method and device for rectangular inclusion rule in integrated circuit layout verification |
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| CN117875261A true CN117875261A (en) | 2024-04-12 |
| CN117875261B CN117875261B (en) | 2024-05-24 |
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