CN117872530A - Preparation method of photonic chip and photonic chip - Google Patents
Preparation method of photonic chip and photonic chip Download PDFInfo
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- CN117872530A CN117872530A CN202410059037.5A CN202410059037A CN117872530A CN 117872530 A CN117872530 A CN 117872530A CN 202410059037 A CN202410059037 A CN 202410059037A CN 117872530 A CN117872530 A CN 117872530A
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- 238000002360 preparation method Methods 0.000 title abstract description 12
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- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 34
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- 238000001312 dry etching Methods 0.000 claims description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 7
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- 238000005516 engineering process Methods 0.000 claims description 4
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- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 claims description 3
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- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
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- 229910001868 water Inorganic materials 0.000 description 3
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 2
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- Optical Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of semiconductor photoelectricity, in particular to a preparation method of a photonic chip and the photonic chip. By providing a photonic structure; the photon structure comprises a supporting substrate and a lithium tantalate layer positioned on the supporting substrate; forming a patterned photoresist layer on the lithium tantalate layer; etching the lithium tantalate layer by taking the patterned photoresist layer as a mask so as to form a lithium tantalate waveguide on the supporting substrate; and removing the photoresist to obtain the photonic chip. By deep etching the lithium tantalate layer, the obtained strip waveguide can effectively improve the light field limitation in the horizontal direction and reduce the limitation of the bending radius of the waveguide, so that the lithium tantalate photonic chip with higher integration density is obtained.
Description
Technical Field
The invention relates to the technical field of semiconductor photoelectricity, in particular to a preparation method of a photonic chip and the photonic chip.
Background
With the rapid increase of data transmission quantity of data centers, cloud services, super computing centers and the like, the high-density optical interconnection technology compatible with the application is not quite variable, lower energy consumption and faster data transmission rate can be realized, and low-loss data interconnection, high-computation-power and high-fidelity signal processing are ensured. Whether it is a widely-known photoelectric hybrid computing or a commercial optical module, the photoelectric device based on the electro-optic modulation completes the fast switching of the optical signal and the electrical signal, which makes the photonic chip applied to the above fields a research hot spot.
The conventional photonic chip is usually a silicon-based photonic chip, but the high-speed electro-optic effect which is not possessed by the silicon material still limits the application of the silicon-based photonic chip in the scenes of high linearity, high transmission rate (800G) and low optical loss, so how to prepare the photonic chip with high linearity and high-speed electro-optic modulation and ensuring low-loss transmission becomes a problem to be solved by related personnel.
Disclosure of Invention
In order to solve the above technical problems, the present application discloses a method for manufacturing a photonic chip, which includes:
providing a photon structure; the photon structure comprises a supporting substrate and a lithium tantalate layer positioned on the supporting substrate;
forming a patterned photoresist layer on the lithium tantalate layer;
etching the lithium tantalate layer by taking the patterned photoresist layer as a mask so as to form a lithium tantalate waveguide on the supporting substrate;
and removing the photoresist to obtain the photonic chip.
In a possible embodiment, the forming a patterned photoresist layer on the lithium tantalate layer includes:
coating photoresist on the lithium tantalate layer;
heating the supporting substrate of the photon structure to bake the photoresist;
and exposing and developing the photoresist in sequence to form a patterned photoresist layer on the lithium tantalate layer.
In one possible embodiment, the photoresist is an electron beam photoresist;
the temperature of the heating treatment is 60-200 ℃ and the time is 1-30 minutes.
In one possible embodiment, the optical waveguide of the photonic chip includes a straight waveguide and a curved waveguide.
In a possible embodiment, the etching the lithium tantalate layer includes:
etching the lithium tantalate layer by using a dry etching process;
the dry etching process comprises ion beam etching, and the etching gas comprises argon.
In one possible embodiment, the exposing and developing the photoresist includes:
exposing and developing the photoresist by using a photoetching process;
the photoetching process comprises ion beam photoetching, wherein the photoresist is subjected to multiple exposure technology, and the exposure dose is 50-3000 mu C/cm each time 2 The total exposure dose is 200-12000 mu C/cm 2 。
In a possible embodiment, the removing the photoresist includes:
and removing the photoresist by wet etching, wherein the wet etching solution comprises ethanolamine, and the concentration of the ethanolamine is 1-50%.
In a possible embodiment, the photoresist layer has a thickness of 300 to 800nm.
In one possible embodiment, the support substrate comprises a sapphire substrate, a silicon oxide-silicon carbide substrate, or a quartz substrate.
The application also discloses a photonic chip which is prepared based on the method.
Embodiments of the present application provide a photonic structure; the photon structure comprises a supporting substrate and a lithium tantalate layer positioned on the supporting substrate; forming a patterned photoresist layer on the lithium tantalate layer; etching the lithium tantalate layer by taking the patterned photoresist layer as a mask so as to form a lithium tantalate waveguide on the supporting substrate; and removing the photoresist to obtain the photonic chip. By deep etching the lithium tantalate layer, the obtained strip waveguide can effectively improve the light field limitation in the horizontal direction and reduce the limitation of the bending radius of the waveguide, so that the lithium tantalate photonic chip with higher integration density is obtained.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for fabricating a photonic chip provided in the present application;
FIGS. 2-7 are schematic illustrations of structures provided herein during the fabrication of a waveguide structure;
the following supplementary explanation is given to the accompanying drawings:
1-a support substrate; 11-a substrate; 12-an optical insulating layer; a lithium 2-tantalate layer; 3-a photoresist layer; a 4-lithium tantalate waveguide.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the terms "upper," "lower," "top," "bottom," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description and simplicity of description, and do not indicate or imply that the apparatus or elements in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein.
When a range of values is disclosed herein, the range is considered to be continuous and includes both the minimum and maximum values for the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values of the range is included. Further, when multiple range description features or characteristics are provided, the ranges may be combined. In other words, unless otherwise indicated, all ranges disclosed herein are to be understood to include any and all subranges subsumed therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between the minimum value of 1 and the maximum value of 10. Exemplary subranges from 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, and the like.
Lithium tantalate has similar characteristics as lithium niobate as a ferroelectric material, such as the pockels effect and a high non-linear coefficient. Lithium tantalate has a higher optical damage threshold, a wider transparent window, and a lower birefringence effect than lithium niobate, making it one of the candidate material platforms for high performance electro-optic modulators. In recent years, with the progress of the preparation technology of high-quality lithium tantalate thin films on insulators, lithium tantalate photonics research has received attention from a plurality of international research units. For lithium tantalate photonic chips, an increase in system complexity typically requires large-scale photonic device integration. The conventional waveguide forming process is a ridge waveguide obtained by a shallow etching process, and shows extremely low propagation loss in a straight waveguide. However, limited by the weaker lateral optical field of the rib waveguide, its loss in the curved waveguide increases significantly, preventing further reduction of the lithium tantalate waveguide bend radius. Therefore, with the integration of high-density photonic devices provided by the application, the adoption of a deep etching process to obtain the strip waveguide is a better choice.
Referring to fig. 1, a method for manufacturing a photonic chip provided in the present application includes:
s101: providing a photon structure; the photonic structure comprises a support substrate 1 and a lithium tantalate layer 2 on the support substrate 1.
In a possible embodiment, the support substrate 1 comprises a sapphire substrate, a silicon oxide-silicon carbide substrate, or a quartz substrate. In the preparation of a photonic chip, since a waveguide is used for transmission of an optical field, plays an important role in photoelectric transmission, and in order to avoid leakage of light to the substrate 11 during light transmission, an optical insulating layer 12 may be provided between the substrate 11 and the waveguide, as in the photonic structure shown in fig. 2, the support substrate 1 includes the substrate 11 and the optical insulating layer 12 on the substrate 11. In one possible embodiment, the material of the optical insulation layer 12 comprises silicon oxide; the material of the substrate 11 comprises quartz, silicon carbide or sapphire. In a possible embodiment, the refractive index of the waveguide is greater than the refractive index of the optical insulation layer 12.
In this embodiment, the photonic structure in step S101 may be formed by direct bonding, and then formed by using a chemical mechanical polishing process, specifically, a substrate 11 may be provided first, an optical insulating layer 12 is formed by depositing on the substrate 11, a support substrate 1 is obtained, a lithium tantalate wafer is provided, and then the lithium tantalate wafer is bonded to the support substrate 1, and then the lithium tantalate wafer is thinned by using the chemical mechanical polishing process until reaching a preset thickness, so as to obtain the photonic structure. In another embodiment, the preparation method can be formed by ion implantation and annealing stripping, so that the preparation method is high in preparation efficiency, the stripped waveguide material can be recycled, and the preparation cost is reduced. Specifically, the support substrate 1 may be first prepared, and a lithium tantalate wafer is provided, and ion implantation is performed on the lithium tantalate wafer to form a defect layer at a preset position of the lithium tantalate wafer, and then the defect layer is bonded to the support substrate 11, and annealing stripping treatment is performed on the bonding structure, so that the bonding structure can be separated into two structures along the defect layer, one structure only includes the waveguide material, and the other structure includes the support substrate 1 and the lithium tantalate layer 2 (i.e., the photon structure) located on the support substrate 1.
S103: a patterned photoresist layer 3 is formed on the lithium tantalate layer 2.
In one possible embodiment, the implementation of step S103 may include: coating photoresist on the lithium tantalate layer 2 to obtain a structure shown in figure 3; heating the supporting substrate 1 of the photon structure to bake the photoresist; the photoresist is sequentially exposed and developed to form a patterned photoresist layer 3 on the lithium tantalate layer 2, wherein the exposed structure may be the structure shown in fig. 3 and the patterned photoresist layer 3 may be the structure shown in fig. 5. In a possible embodiment, the thickness of the photoresist layer 3 is 300-800 nm, alternatively, the thickness of the photoresist may be 300nm,400nm,500nm,600nm,700nm, 800nm, or the like. In one possible embodiment, the photoresist is an electron beam photoresist; the temperature of the heating treatment is 60-200 ℃ for 1-30 minutes, and optionally, the temperature of the heating treatment can be 60 ℃,80 ℃,100 ℃,120 ℃,140 ℃,160 ℃,180 ℃ or 200 ℃; the time may be 1 minute, 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, or 30 minutes. In a possible embodiment, to increase the accuracy of the exposed lines, multiple exposure techniques (e.g., 3 times, 4 times, 5 times, etc.) may be used for the photoresist, each exposure dose being 50-3000 μC/cm 2 The total exposure dose is 200-12000 mu C/cm 2 。
S105: and etching the lithium tantalate layer 2 by taking the patterned photoresist layer 3 as a mask so as to form a lithium tantalate waveguide 4 on the support substrate 1.
In a possible embodiment, the etching the lithium tantalate layer 2 in step S105 includes: etching the lithium tantalate layer 2 by using a dry etching process; the dry etching process comprises ion beam etching and reactive coupling plasma etching, and the etching gas comprises argon.
Alternatively, during dry etching, the etching gas can physically sputter and chemically react with the lithium tantalate layer 2 and produce an etch redeposition that adheres to the lithium tantalate waveguide 4 sidewall. After the etching of the lithium tantalate layer 2 is completed, a structure as shown in fig. 6 can be obtained.
S107: and removing the photoresist to obtain the photonic chip.
In this embodiment, after the photoresist is removed, the structure shown in fig. 7 may be obtained.
In one possible embodiment, the optical waveguide of the photonic chip includes a straight waveguide and a curved waveguide.
In a possible embodiment, in step S107, the specific manner of removing the photoresist may be: and removing the photoresist by wet etching, wherein the wet etching solution comprises ethanolamine, and the concentration of the ethanolamine is 1-50%.
As can be seen from the above description, since etching redeposition is generated to adhere to the sidewall of the lithium tantalate waveguide 4 after the lithium tantalate layer 2 is etched by the dry etching process, the optical performance of the waveguide is affected, and for this purpose, after the photoresist is removed in step S107, the etching redeposition may be removed by using a preset etching solution; the preset corrosive liquid is a mixed solution of hydrogen peroxide and a strong alkali solution. In a possible embodiment, the preset etching solution is a mixed solution of hydrogen peroxide and a strong alkali solution; the strong alkali solution comprises sodium hydroxide, potassium hydroxide or a mixture of the sodium hydroxide, the potassium hydroxide and water or ammonia water. Optionally, the temperature of the preset corrosive liquid is 50-100 ℃. In an alternative embodiment for removing the etch redeposit 4, the temperature of the pre-set etching solution may be 50 degrees celsius, 60 degrees celsius, 70 degrees celsius, 80 degrees celsius, 90 degrees celsius, 100 degrees celsius. Optionally, the preset corrosive liquid may be a composition of hydrogen peroxide and potassium hydroxide, a composition of hydrogen peroxide and sodium hydroxide, a composition of hydrogen peroxide, water, ammonia water and potassium hydroxide, or a composition of hydrogen peroxide, water, ammonia water and sodium hydroxide. When the preset corrosive liquid is a composition of potassium hydroxide and hydrogen peroxide, the volume ratio of the potassium hydroxide to the hydrogen peroxide is 1:1 to 10:1. Alternatively, the volume ratio of potassium hydroxide to hydrogen peroxide may be 1:1,2:1,3:1,4:1,5:1,6:1,7:1,8:1,9:1 or 10:1.
In one possible embodiment, after the step of removing the etch redeposition, the method further comprises: the lithium tantalate waveguide 4 is subjected to a high temperature treatment to repair lattice damage caused to the lithium tantalate waveguide 4 during the above-described dry etching process, so that the optical performance of the lithium tantalate waveguide 4 can be improved. In one possible embodiment, the high temperature treatment is performed at a temperature of 150 to 700 degrees celsius in an atmosphere comprising oxygen for a period of 2 to 5 hours. In an alternative embodiment of the processing temperature of the high temperature process, the processing temperature may be 150 degrees celsius, 200 degrees celsius, 250 degrees celsius, 300 degrees celsius, 350 degrees celsius, 400 degrees celsius, 450 degrees celsius, 500 degrees celsius, 600 degrees celsius, 650 degrees celsius, or 700 degrees celsius. In an alternative embodiment of the treatment time for the high temperature treatment, the treatment time may be 2 hours, 2.5 hours, 3 hours, 3.5 hours, 4 hours, 4.5 hours or 5 hours. It should be noted that, for some materials, the high temperature treatment temperature must be less than the curie temperature to ensure that the polarization direction is unchanged (e.g., barium titanate needs to be less than 150 degrees celsius, lithium tantalate needs to be less than 600 degrees celsius).
The embodiment of the application provides a preparation method of a photonic chip, which can be specifically realized by spin-coating electron beam photoresist on a photonic structure, wherein the photonic structure is a lithium tantalate wafer on a silicon-based insulator, namely the photonic structure can be a laminated structure of lithium tantalate-silicon dioxide-silicon. The electron beam photoresist adopts ma-N, can be used as a hard mask for dry etching after exposure, and the substrate 11 should be baked after spin coating the photoresist, wherein the baking temperature is 60-200 ℃ and the baking time is 1-30 min. In the electron beam lithography process, the electron beam resist is exposed and developed to transfer the device pattern to the resist layer 3. In exposure, in order to improve the roughness of the exposed device sidewall, multiple exposure techniques are employed to reduce noise and environmental impact from the system, which is beneficial to producing smoother sidewalls and reducing field splice errors. The exposed lithium tantalate layer 2 on the surface of the substrate 11 is etched by ion beam etching by using the exposed and developed electron beam photoresist as a mask, and the device pattern is transferred to the lithium tantalate layer 2 by using argon as etching gas. And removing the residual electron beam photoresist by utilizing the ethanolamine wet etching, and obtaining the lithium tantalate photon chip with high integration density.
The present application provides an embodiment for specifically preparing a photonic chip, where the preparation parameters are as follows: spin-coating electron beam photoresist on the surface of the photon structure; the photon structure is a lithium tantalate wafer on a silicon-based insulator, the electron beam photoresist is ma-N, and the thickness of the photoresist layer 3 is 800nm. And baking the spin-coated electron beam photoresist at a baking temperature of 100 ℃ for 3min. Carrying out electron beam lithography and development to transfer the device pattern to the photoresist layer 3; wherein the exposure mode is multiple exposure, which is divided into 4 exposure, and each exposure dose is 500 muC/cm 2 The total exposure dose was 2000. Mu.C/cm 2 . Carrying out dry etching on the lithium tantalate layer 2 exposed after electron beam lithography, and transferring the device pattern to the lithium tantalate layer 2; the dry etching is to take the electron beam photoresist as a mask, and transfer the device pattern to the lithium tantalate layer 2 by utilizing ion beam etching; wherein the etching gas is argon. And corroding the surface residual electron beam photoresist by using an ethanolamine solution with the concentration of 5% to obtain the lithium tantalate photon chip.
The application further discloses a photonic chip which is prepared based on any one of the above methods. The application illustrates a method for deep etching lithium tantalate to obtain a small turning radius waveguide by using photoresist as a mask, thereby improving the integration density of the lithium tantalate photonic chip. Compared with the ridge waveguide obtained by the shallow etching process, the strip waveguide obtained by the method can effectively improve the light field limitation in the horizontal and vertical directions and reduce the limitation of the bending radius of the waveguide, so that the lithium tantalate photonic chip with higher integration density is obtained.
In the embodiment of the application, the photonic chip can be specifically a micro-ring resonator, a Mach-Zender interferometer, an on-chip filter and the like.
The foregoing description of the preferred embodiments is provided for the purpose of illustration only and is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A method of fabricating a photonic chip comprising:
providing a photon structure; the photon structure comprises a supporting substrate and a lithium tantalate layer positioned on the supporting substrate;
forming a patterned photoresist layer on the lithium tantalate layer;
etching the lithium tantalate layer by taking the patterned photoresist layer as a mask so as to form a lithium tantalate waveguide on the supporting substrate;
and removing the photoresist to obtain the photonic chip.
2. The method of claim 1, wherein forming a patterned photoresist layer over the lithium tantalate layer comprises:
coating photoresist on the lithium tantalate layer;
heating the supporting substrate of the photon structure to bake the photoresist;
and exposing and developing the photoresist in sequence to form a patterned photoresist layer on the lithium tantalate layer.
3. The method of claim 2, wherein the photoresist is an ultraviolet photoresist;
the temperature of the heating treatment is 60-200 ℃ and the time is 1-30 minutes.
4. The method of manufacturing according to claim 1, wherein the optical waveguide of the photonic chip comprises a straight waveguide and a curved waveguide.
5. The method of claim 1, wherein etching the lithium tantalate layer comprises:
etching the lithium tantalate layer by using a dry etching process;
the dry etching process comprises ion beam etching, and the etching gas comprises argon.
6. The method of claim 2, wherein exposing and developing the photoresist comprises:
exposing and developing the photoresist by using a photoetching process;
the photoetching process comprises ion beam photoetching, wherein the photoresist is subjected to multiple exposure technology, and the exposure dose is 50-3000 mu C/cm each time 2 The total exposure dose is 200-12000 mu C/cm 2 。
7. The method of manufacturing according to claim 1, wherein the removing the photoresist comprises:
and removing the photoresist by wet etching, wherein the wet etching solution comprises ethanolamine, and the concentration of the ethanolamine is 1-50%.
8. The method of claim 1, wherein the photoresist layer has a thickness of 300 to 800nm.
9. The method of manufacturing according to claim 1, wherein the supporting substrate comprises a sapphire substrate, a silicon oxide-silicon carbide substrate, or a quartz substrate.
10. A photonic chip prepared according to the method of any one of claims 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410059037.5A CN117872530A (en) | 2024-01-15 | 2024-01-15 | Preparation method of photonic chip and photonic chip |
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| CN202410059037.5A CN117872530A (en) | 2024-01-15 | 2024-01-15 | Preparation method of photonic chip and photonic chip |
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