CN117858496A - Method for preparing static random access memory unit - Google Patents
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- CN117858496A CN117858496A CN202410257179.2A CN202410257179A CN117858496A CN 117858496 A CN117858496 A CN 117858496A CN 202410257179 A CN202410257179 A CN 202410257179A CN 117858496 A CN117858496 A CN 117858496A
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- 238000000034 method Methods 0.000 title claims abstract description 116
- 230000003068 static effect Effects 0.000 title abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 74
- 238000005468 ion implantation Methods 0.000 claims abstract description 73
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 230000005540 biological transmission Effects 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 238000002513 implantation Methods 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract
The invention provides a preparation method of a static random access memory unit, which comprises the following steps: providing a substrate, wherein two first active areas, two second active areas, two third active areas and a groove isolation structure are formed in the substrate; forming two pull-down gate structures, two transmission gate structures and two pull-up gate structures; executing a first ion implantation process to form a first source region, a first drain region, a second source region and a second drain region; forming a patterned mask layer to cover the first active region, the second active region, the trench isolation structure between the first active region and the third active region, and the trench isolation structure between the second drain region and the transmission gate structure and the third active region; executing a second ion implantation process to form a third source region and a third drain region; a third ion implantation process is performed to reduce the doping concentration of the second source region. The invention improves the static noise margin of the static random access memory unit.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a static random access memory unit.
Background
Static random access memory (SRAM, static Random Access Memory) is an integral part of on-chip memory, which has the advantage of low power consumption and high speed, and comprises a number of SRAM cells. Sram cells are typically 6T structures that include 2 pull-up transistors (PU, pull Up transistor), 2 pull-down transistors (PD, pull Down transistor), and 2 pass transistors (PG, pass Gate transistor). In the design of sram cells, a sufficiently large beta ratio, i.e., the ratio of the turn-on current of the pull-down transistor to the turn-on current of the pass transistor, is typically ensured to achieve a sufficiently high static noise margin (SNM, static Noise Margin).
FIG. 1 is a top view of a prior art SRAM cell. Referring to fig. 1, in order to improve the static noise margin, the difference between the widths of the first active region 11 corresponding to the pull-down transistor and the second active region 12 corresponding to the pass transistor is generally increased, and if the difference is too large, the morphology of the second active region 12 corresponding to the pass transistor is easily deformed due to the limitation of photolithography and etching tools in the process of manufacturing the sram cell, resulting in reduced yield.
In another manufacturing process, the turn-on current of the pull-down transistor is increased by lowering the threshold voltage of the pull-down transistor, which generally requires separate ion implantation processes for the pull-down transistor and the pass transistor using different reticles, which increases process steps and manufacturing costs; and the setting of threshold voltages of the pull-down transistor, the transmission transistor and the pull-up transistor is required to ensure that the static random access memory unit can work normally and has high enough yield, so that the range of the threshold voltages for free adjustment is smaller, and the performance of the static random access memory unit is not beneficial to improvement.
Disclosure of Invention
The invention aims to provide a preparation method of a static random access memory unit, which improves the static noise margin of the static random access memory unit.
In order to achieve the above object, the present invention provides a method for manufacturing a sram cell, comprising:
providing a substrate, wherein two first active regions, two second active regions and two third active regions are formed in the substrate, and a trench isolation structure is formed in the substrate, and the first active regions, the second active regions and the third active regions are defined by the trench isolation structure;
forming two pull-down gate structures respectively located on the two first active areas, forming two transmission gate structures respectively located on the two second active areas, and forming two pull-up gate structures respectively located on the two third active areas;
performing a first ion implantation process, forming a first source region and a first drain region in the first active regions at two sides of the pull-down gate structure, and forming a second source region and a second drain region in the second active regions at two sides of the transmission gate structure synchronously;
forming a patterned mask layer to cover the first active region, the second active region, and the trench isolation structure between the first active region and the third active region, and to cover the second drain region and the trench isolation structure between the transfer gate structure and the third active region; the method comprises the steps of,
performing a second ion implantation process by taking the patterned mask layer as a mask, and forming a third source region and a third drain region in the third active region at two sides of the pull-up gate structure; and performing a third ion implantation process, wherein the second source region is doped obliquely to reduce the doping concentration of the second source region, and the doping type of the third ion implantation process is opposite to that of the first ion implantation process.
Optionally, one of the first active regions is connected to one of the second active regions, and the third active region has a gap from the first active region and the second active region.
Optionally, the second ion implantation process is a vertical ion implantation process.
Optionally, the third ion implantation process is an inclined ion implantation process, and an included angle between an implantation direction of the third ion implantation process and the surface of the substrate is 5-85 degrees.
Optionally, the doping concentration of the third ion implantation process is smaller than the doping concentration of the first ion implantation process.
Optionally, the third ion implantation process is performed twice, and doping is performed on the second source regions corresponding to the two transmission gate structures respectively.
Optionally, the doping concentrations of the two third ion implantation processes are the same.
Optionally, the implantation direction of the third ion implantation process is performed twice and the included angle between the surface of the substrate is the same.
Optionally, the doping types of the second ion implantation process and the third ion implantation process are the same.
Optionally, after performing the second ion implantation process and the third ion implantation process, the patterned mask layer is removed.
In the method for manufacturing the static random access memory unit, a first ion implantation process is firstly carried out to synchronously form a first source region, a first drain region, a second source region and a second drain region, and then a specific patterned mask layer is formed, wherein the mask layer covers the first active region, the second active region, a groove isolation structure between the first active region and a third active region, and covers the second drain region, a groove isolation structure between a transmission grid structure and the third active region; furthermore, by using the patterned mask layer as a mask, the second ion implantation process is performed to form a third source region and a third drain region, and the third ion implantation process is performed to dope the second source region obliquely to reduce the doping concentration of the second source region.
Drawings
FIG. 1 is a top view of a prior art SRAM cell.
Fig. 2 is a flowchart of a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 3 is a top view of a sram cell according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a first active region and a second active region in a substrate provided in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a third active region in a substrate provided in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view illustrating a method for manufacturing a sram cell with a trench isolation structure between a second active region and a third active region according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view illustrating a method for manufacturing a sram cell with a trench isolation structure between a first active region and a third active region according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view illustrating a pull-down gate structure and a transfer gate structure formed in a method for fabricating a sram cell according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view illustrating a pull-up gate structure formed in a method for fabricating a sram cell according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view illustrating formation of a first source region, a first drain region, a second source region, and a second drain region in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view illustrating a second source region formed in a method for manufacturing a sram cell according to an embodiment of the invention.
Fig. 12 is a schematic cross-sectional view illustrating formation of a first drain region in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 13 is a schematic cross-sectional view illustrating a patterned mask layer formed to cover a first active region and a second active region in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 14 is a schematic cross-sectional view illustrating a trench isolation structure between a second active region and a third active region formed by forming a patterned mask layer in a method for fabricating a sram cell according to an embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view illustrating a method for forming a patterned mask layer covering a trench isolation structure between a first active region and a third active region in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 16 is a schematic cross-sectional view illustrating a third source region and a third drain region formed by performing a second ion implantation process in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 17 is a schematic cross-sectional view illustrating a third source region formed in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 18 is a schematic cross-sectional view illustrating formation of a third drain region in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 19 is a schematic cross-sectional view illustrating a third ion implantation process performed on the second source region in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 20 is a schematic cross-sectional view of a patterned mask layer as a barrier layer of a first drain region and a first source region when a third ion implantation process is performed in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 21 is a schematic cross-sectional view illustrating removal of patterned mask layers on the first active region and the second active region in a method for manufacturing a sram cell according to an embodiment of the present invention.
Fig. 22 is a schematic cross-sectional view illustrating removal of a patterned mask layer on a second active region and a trench isolation structure in a method for fabricating a sram cell according to an embodiment of the present invention.
Fig. 23 is a schematic cross-sectional view illustrating removal of a patterned mask layer on a first active region and a trench isolation structure in a method for fabricating a sram cell according to an embodiment of the present invention.
The reference numerals in fig. 1 are:
11-a first active region; 12-a second active region;
the reference numerals in fig. 3 to 23 are:
100-a substrate; 110-a first active region; 120-a second active region; 130-a third active region; 200-trench isolation structures; 310-a pull-down gate structure; 320-a transfer gate structure; 330-pull-up gate structure; 411-a first source region; 412-a first drain region; 421-a second source region; 422-a second drain region; 431-a third source region; 432-a third drain region; 500-patterned masking layer.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 2 is a flowchart of a method for manufacturing a sram cell according to the present embodiment. Referring to fig. 2, the embodiment provides a method for manufacturing a sram cell, which includes:
step S1: providing a substrate, wherein two first active areas, two second active areas and two third active areas are formed in the substrate, and a trench isolation structure is formed in the substrate and defines the first active areas, the second active areas and the third active areas;
step S2: forming two pull-down gate structures respectively located on the two first active areas, forming two transmission gate structures respectively located on the two second active areas, and forming two pull-up gate structures respectively located on the two third active areas;
step S3: performing a first ion implantation process, forming a first source region and a first drain region in the first active regions at both sides of the pull-down gate structure, and forming a second source region and a second drain region in the second active regions at both sides of the transfer gate structure simultaneously;
step S4: forming a patterned mask layer to cover the first active region, the second active region, the trench isolation structure between the first active region and the third active region, and the trench isolation structure between the second drain region and the transmission gate structure and the third active region;
step S5: performing a second ion implantation process by taking the patterned mask layer as a mask, and forming a third source region and a third drain region in the third active region at two sides of the pull-up gate structure; and performing a third ion implantation process, wherein the second source region is doped obliquely to reduce the doping concentration of the second source region, and the doping type of the third ion implantation process is opposite to that of the first ion implantation process.
The following describes the method for manufacturing the sram cell provided in this embodiment in detail with reference to fig. 3 to 23, wherein fig. 3 is a top view of the sram cell provided in this embodiment, fig. 4, 8, 10, 13 and 21 are schematic cross-sectional views along A1A2 direction in fig. 3, fig. 5, 9 and 16 are schematic cross-sectional views along B1B2 direction in fig. 3, fig. 6, 11, 14, 17, 19 and 22 are schematic cross-sectional views along C1C2 direction in fig. 3, and fig. 7, 12, 15, 18, 20 and 23 are schematic cross-sectional views along D1D2 direction in fig. 3. For clarity of presentation of the cross-sectional schematic, the dimensions of fig. 3-23 are larger than those of fig. 2 (for illustration only, not to scale).
Step S1 is executed: referring to fig. 4 and 5, a substrate 100 is provided, wherein a material of the substrate 100 includes one or more of silicon, germanium, gallium, nitrogen, or carbon, and a first active region 110, a second active region 120, and a third active region 130 are formed in the substrate 100. In this embodiment, the doping types of the first active region 110 and the second active region 120 are the same, and the doping types of the third active region 130 and the first active region 110 are opposite.
Referring to fig. 3, two first active regions 110, two second active regions 120 and two third active regions 130 are formed in the substrate, wherein one first active region 110 is connected to one second active region 120, the width of the first active region 110 along the X direction in fig. 3 is greater than the width of the second active region 120 along the X direction in fig. 3, and the length of the first active region 110 along the Y direction in fig. 3 and the length of the second active region 120 along the Y direction in fig. 3 are not limited. The third active region 130 has a gap from both the first active region 110 and the second active region 120.
Referring to fig. 6 and 7, a trench isolation structure 200 is formed in the substrate 110, the trench isolation structure 200 defines a first active region 110, a second active region 120 and a third active region 130, the trench isolation structure 200 is formed between the first active region 110 and the third active region 130, the trench isolation structure 200 is formed between the second active region 120 and the third active region 130, and a blank region between the third active region 130 and the first active region 110 and the second active region 120 in fig. 3 is the trench isolation structure 200 (not shown in fig. 3).
Step S2 is executed: referring to fig. 8 and 9, a pull-down gate structure 310, a transmission gate structure 320, and a pull-up gate structure 330 are formed on the first active region 110, the second active region 120, and the third active region 130, respectively, where the pull-down gate structure 310, the transmission gate structure 320, and the pull-up gate structure 330 each include a gate polysilicon layer, a gate oxide layer, and a sidewall (not shown), and after the gate oxide layer and the gate polysilicon layer are formed, the sidewall is formed on the sides of the gate oxide layer and the gate polysilicon layer. And, before forming the sidewalls in the pull-down gate structure 310, the transfer gate structure 320, and the pull-up gate structure 330, lightly doped regions (all not shown) are formed in the first active region 110, the second active region 120, and the third active region 130, and then the sidewalls are formed to constitute the pull-down gate structure 310, the transfer gate structure 320, and the pull-up gate structure 330.
Step S3 is executed: referring to fig. 10, a first ion implantation process is performed to form a first source region 411 and a first drain region 412 in the first active region 110 at both sides of the pull-down gate structure 310, to form a second source region 421 and a second drain region 422 in the second active region 120 at both sides of the transfer gate structure 320 in synchronization, and to connect the second drain region 422 and the first drain region 412. In the present embodiment, since the first source region 411, the first drain region 412, the second source region 421 and the second drain region 422 are formed by doping simultaneously, the doping types of the first source region 411, the first drain region 412, the second source region 421 and the second drain region 422 are the same and the doping concentrations are the same, and the doping types of the first source region 411 and the first active region 110 are opposite. In this embodiment, the transfer transistor includes a transfer gate structure 320, a second source region 421, and a second drain region 422, and the pull-down transistor includes a pull-down gate structure 310, a first source region 411, and a first drain region 412.
Referring to fig. 11 and 12, another cross-section of the second source region 421 is shown in fig. 11, and another cross-section of the first drain region 412 is shown in fig. 12.
Step S4 is executed: referring to fig. 13 and 3, the dashed box in fig. 3 simply illustrates the patterned mask layer 500, and the patterned mask layer 500 is formed to cover the first active region 110 and the second active region 120, exposing the third active region 130; referring to fig. 14 and 3, the patterned mask layer 500 further covers the second drain region 422 and the trench isolation structure (not shown in fig. 3, the blank region is the trench isolation structure) between the transmission gate structure 320 and the third active region 130, and the patterned mask layer 500 exposes the trench isolation structure 200 between the second active region 120 and the third active region 130; referring to fig. 15, the patterned mask layer 500 further covers the trench isolation structure 200 between the first active region 110 and the third active region 130.
Step S4 is executed: referring to fig. 16 to fig. 18, a second ion implantation process (the arrow direction in the drawing is the implantation direction) is performed by using the patterned mask layer 500 as a mask, a third source region 431 and a third drain region 432 are formed in the third active region 130 at both sides of the pull-up gate structure 330, the doping types of the third source region 431 and the third drain region 432 are the same, and the doping types of the third source region 431 and the second source region 421 are opposite, and the doping types of the third source region 431 and the third active region 130 are opposite. In this embodiment, the pull-up transistor includes a pull-up gate structure 330, a third source region 431, and a third drain region 432. Another cross-section of the third source region 431 is shown in fig. 17 and another cross-section of the third drain region 432 is shown in fig. 18.
Referring to fig. 19 and 20, a third ion implantation process is performed using the patterned mask layer 500 as a mask, and the second source region 421 is doped obliquely, wherein the doping type of the third ion implantation process is opposite to that of the first ion implantation process, and the doping concentration of the second source region 421 can be reduced by doping ions of opposite conductivity types into the second source region 421. In this embodiment, the doping types of the second ion implantation process and the third ion implantation process are the same, the doping concentration of the third ion implantation process is smaller than that of the first ion implantation process, and the included angle between the implantation direction (the direction of the arrow in the figure is the implantation direction) of the third ion implantation process and the surface of the substrate 100 is 5 degrees to 85 degrees, such as 15 degrees, 25 degrees, 35 degrees.
Referring to fig. 3, since the sram cell in the present embodiment is a 6T structure, it includes two pull-up transistors, two pull-down transistors and two transmission transistors forming a symmetrical 6T structure, wherein the pull-up transistors are PMOS transistors, the pull-down transistors and the transmission transistors are NMOS transistors, the first active region 110, the second active region 120, the third active region 130 and the patterned mask layer (shown in phantom) are not illustrated in fig. 3 for convenience, and the first source region 411, the first drain region 412, the second source region 421, the second drain region 422, the third source region 431 and the third drain region 432 are not labeled. Therefore, two times of third ion implantation process are required to be performed to dope the second source regions in the two transmission transistors respectively, and the doping concentrations of the two times of third ion implantation process are the same, and the implantation direction of the two times of third ion implantation process is the same as the included angle between the surface of the substrate.
In this embodiment, the second ion implantation process is performed by using the specific patterned mask layer, so that not only the third source region and the third drain region can be formed, but also the second source region can be doped obliquely by performing the third ion implantation process to reduce the doping concentration of the second source region, and since the original doping concentrations of the first source region and the second source region are the same, after the doping concentration of the second source region is reduced, the doping concentration of the first source region is greater than the doping concentration of the second source region, and the larger the doping concentration is, the smaller the resistance of the source region is, the larger the on-current of the transistor is, that is, the resistance of the first source region is smaller than the resistance of the second source region, and the on-current of the corresponding pull-down transistor is greater than the on-current of the transmission transistor, so that a higher β ratio can be obtained, thereby improving the static noise margin of the static random access memory cell.
Further, referring to fig. 21 to 23, after the second ion implantation process and the third ion implantation process are performed, the patterned mask layer 500 is removed.
Further, the subsequent manufacturing process further comprises forming a passivation layer to cover the first active region, the second active region, the third active region, the pull-down gate structure, the transmission gate structure and the pull-up gate structure; and forming a source plug and a drain plug in the passivation layer, wherein the source plug penetrates through the passivation layer to be electrically connected with the first source region and the second source region, and the drain plug penetrates through the passivation layer to be electrically connected with the first drain region and the second drain region.
In summary, in the method for manufacturing a sram cell provided by the present invention, a first ion implantation process is performed to form a first source region, a first drain region, a second source region, and a second drain region simultaneously, and then a specific patterned mask layer is formed, which covers the first active region, the second active region, and a trench isolation structure between the first active region and the third active region, and covers the second drain region and a trench isolation structure between the transmission gate structure and the third active region; furthermore, by using the patterned mask layer as a mask, the second ion implantation process is performed to form a third source region and a third drain region, and the third ion implantation process is performed to dope the second source region obliquely to reduce the doping concentration of the second source region.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method for fabricating a sram cell, comprising:
providing a substrate, wherein two first active regions, two second active regions and two third active regions are formed in the substrate, and a trench isolation structure is formed in the substrate, and the first active regions, the second active regions and the third active regions are defined by the trench isolation structure;
forming two pull-down gate structures respectively located on the two first active areas, forming two transmission gate structures respectively located on the two second active areas, and forming two pull-up gate structures respectively located on the two third active areas;
performing a first ion implantation process, forming a first source region and a first drain region in the first active regions at two sides of the pull-down gate structure, and forming a second source region and a second drain region in the second active regions at two sides of the transmission gate structure synchronously;
forming a patterned mask layer to cover the first active region, the second active region, and the trench isolation structure between the first active region and the third active region, and to cover the second drain region and the trench isolation structure between the transfer gate structure and the third active region; the method comprises the steps of,
performing a second ion implantation process by taking the patterned mask layer as a mask, and forming a third source region and a third drain region in the third active region at two sides of the pull-up gate structure; and performing a third ion implantation process, wherein the second source region is doped obliquely to reduce the doping concentration of the second source region, and the doping type of the third ion implantation process is opposite to that of the first ion implantation process.
2. The method of manufacturing a sram cell of claim 1, wherein one of said first active regions is connected to one of said second active regions, and wherein said third active region is spaced from said first active region and said second active region.
3. The method of claim 1, wherein the second ion implantation process is a vertical ion implantation process.
4. The method of claim 1, wherein the third ion implantation process is an oblique ion implantation process, and an included angle between an implantation direction of the third ion implantation process and a surface of the substrate is 5-85 degrees.
5. The method of claim 1 or 4, wherein the doping concentration of the third ion implantation process is less than the doping concentration of the first ion implantation process.
6. The method of claim 5, wherein the third ion implantation process is performed twice to dope the second source regions corresponding to the two transfer gate structures, respectively.
7. The method of claim 6, wherein the doping concentrations of the third ion implantation process performed twice are the same.
8. The method of claim 7, wherein the third ion implantation process is performed twice in the same direction as the angle between the surface of the substrate.
9. The method of claim 1, wherein the doping type of the second ion implantation process and the third ion implantation process are the same.
10. The method of claim 1, wherein the patterned masking layer is removed after performing the second ion implantation process and the third ion implantation process.
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