CN117854409A - Source driver and method for detecting crack of display panel - Google Patents

Abstract

The application relates to a source driver and a method for detecting cracks of a display panel. A method of detecting a panel crack in a display panel and a display device are disclosed. A source driver may include: a first circuit configured to apply first data to a data line connected to a subpixel of the display panel to charge a first driving voltage; and a second circuit formed on the display panel, applying a first driving voltage to a detection line formed on the display panel to detect the presence of a crack in the display panel based on an illumination state of the sub-pixel, wherein the detection line includes a first detection node and a second detection node formed on one side of the display panel in an extending direction of the detection line, wherein the first detection node is connected to data lines of the first sub-pixel and the third sub-pixel, and wherein the second detection node is connected to data lines of the second sub-pixel.

Description

Source driver and method for detecting crack of display panel

Technical Field

The present disclosure relates to a method and a display device for detecting or determining a crack in a display panel.

Background

The display market is expanding from a large home appliance such as a conventional TV to a mobile market, and even various home appliances.

Display devices equipped with such displays may have defects and are often inspected for defects, i.e. cracks in the display panel, prior to transporting the product.

As a result of the confirmation, the display device equipped with the broken display panel should not be transported due to the defect.

This is because, when a crack occurs in the display panel, foreign substances such as moisture may infiltrate into the crack region, and thus the infiltrated foreign substances may cause the display panel to be defective.

Accordingly, since there is no need to transport a defective display device, a technique for accurately measuring and determining cracks in a display panel is required.

Display crack detection methods are designed in response to these needs, but because the administrator must perform the test procedure each time, the method is not intuitive and there is a possibility of errors in the detection.

Disclosure of Invention

Technical proposal

The technical problem to be solved by the present disclosure is to provide a display device including a panel crack detection circuit that can intuitively detect whether a crack occurs in a display panel, and a method for measuring a crack of the display panel.

Technical proposal

A source driver may include: a first circuit configured to apply first data to a data line connected to a subpixel of the display panel to charge a first driving voltage; and a second circuit formed on the display panel to apply a first driving voltage to a detection line formed on the display panel to detect the presence of a crack in the display panel based on an illumination state of the sub-pixel, wherein the detection line includes a first detection node and a second detection node formed on one side of the display panel in an extending direction of the detection line, wherein the first detection node is connected to data lines of the first sub-pixel and the third sub-pixel, and wherein the second detection node is connected to data lines of the second sub-pixel.

A method of measuring a panel crack in a display device may include: applying first data to a data line connected to a subpixel of the display panel to charge a first driving voltage; and applying a first driving voltage to a detection line formed in the display panel to detect a crack in the display panel based on an illumination state of the sub-pixel, wherein the detection line includes a first detection node and a second detection node formed on one side of the display panel, wherein the first detection node is connected to data lines of the first sub-pixel and the third sub-pixel, and wherein the second detection node is connected to data lines of the second sub-pixel.

Effects of the invention

According to at least one of the various embodiments of the present disclosure, whether a crack occurs in the display panel may be intuitively detected.

Drawings

Fig. 1 is a block diagram of a display device according to at least one of the various embodiments of the present disclosure.

Fig. 2 illustrates a diagram of a connection relationship between a display panel and a crack detection circuit according to at least one of various embodiments of the present disclosure.

Fig. 3 shows a detailed configuration of PCD circuit 520.

Fig. 4 shows a detailed configuration of the reference resistance generation circuit.

Fig. 5 and 6 are flowcharts illustrating a method of measuring a panel crack in a display device.

Fig. 7 illustrates an operation of the display panel 100 in the case where a crack occurs.

Fig. 8 to 11 show various configurations for evaluating the presence of cracks in the display panel.

Detailed Description

A display device according to various embodiments of the present disclosure will be described in detail.

Fig. 1 is a block diagram of a display device according to at least one of the various embodiments of the present disclosure.

Fig. 2 illustrates a diagram of a connection relationship between a display panel and a crack detection circuit according to at least one of various embodiments of the present disclosure.

Referring to fig. 1, a display device 1000 according to an embodiment of the present disclosure includes a display panel 100 and a display driving device 200.

The display device 1000 may accommodate various types of display panels, and is not limited to at least one Thin Film Transistor (TFT) and an Organic Light Emitting Diode (OLED).

In addition to organic light emitting displays, display device 1000 may be implemented with other displays including, but not limited to, liquid crystal displays, field emission displays, electroluminescent displays, and electrophoretic displays.

A plurality of pixels (P) may be arranged in the display panel 100, and data lines and gate lines connected to the plurality of pixels (P) may also be arranged in the display panel 100.

The display driving apparatus 200 may supply data signals to a plurality of pixels (P) to display an image through the display panel 100.

The display driving apparatus 200 may include a timing controller 300, a gate driving apparatus 400, a data driving apparatus 500, and the like.

The timing controller 300 may receive various timing signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a Data Enable (DE) signal, a clock signal (CLK), etc., from an external system (not shown).

The timing controller 300 may generate signals such as a Gate Control Signal (GCS) for controlling the gate driving apparatus 400 and a Data Control Signal (DCS) for controlling the data driving apparatus 500.

Further, the timing controller 300 may receive image signals (RGB) from the system, perform conversion to create image signals (RGB ') in a format that can be processed by the data driving apparatus 500, and then control the image signals (RGB') to be output.

The host system may convert the digital image data into a format suitable for display on the display panel 100. The host system may also transmit timing signals to the timing controller 300 along with digital image data. The host system may be implemented as one of the following: a television system, a set-top box, a navigation system, a DVD player, a blu-ray player, a Personal Computer (PC), a home theater system, or a telephone system, and receives an input video signal.

The gate driving apparatus 400 may receive a Gate Control Signal (GCS) from the timing controller 300. Subsequently, the gate driving apparatus 400 may generate a gate pulse (or a scan pulse) synchronized with the data signal based on the received Gate Control Signal (GCS) and shift the generated gate pulse to be sequentially supplied to the gate lines (G1 to Gm).

The data driving apparatus 500 may receive a Data Control Signal (DCS) and an image signal (RGB') from the timing controller 300.

The gate driving apparatus 400 may establish a connection between each pixel (P) and the data line by transmitting a Scan Signal (SS) to the gate line. The data driving apparatus 500 may drive each pixel (P) by supplying a data voltage (Vdata) corresponding to image data to the data line.

The timing controller 300 may transmit a Gate Control Signal (GCS) to the gate driving apparatus 400 and a Data Control Signal (DCS) to the data driving apparatus 500 to control a driving timing of each pixel (P). In this context, the gate driving apparatus 400 may be alternatively referred to as a Gate Driver IC (GDIC), and the data driving apparatus 500 may also be referred to as a Source Driver IC (SDIC).

Referring to fig. 2, the source driver IC 500 may include a driving circuit 510 and a PCD circuit 520.

In fig. 2, only one source driver IC 500 is depicted for convenience, but this is not limiting.

The driving circuit 510 converts the received image signals (RGB') into analog data signals, and supplies the converted analog data signals to the pixels (P) as sub-pixels through the plurality of data lines (D1 to Dn).

The PCD circuit 520 is capable of assessing the presence of cracks in the display panel 100.

PCD circuitry 520 may be connected to detection nodes (or PCD nodes) 120, 130 formed on display panel 100.

In order to evaluate whether the display panel 100 has a crack, a pre-designed inspection line 110 is provided on the display panel 100, and at one end, a plurality of inspection nodes 120, 130 connected to the inspection line 110 are formed.

The sense line may create a closed circuit between the first sense node (or PCD1 node) 120 and the second sense node (or PCD2 node) 130.

In this case, a sensing line resistance (R) on the sensing line 110 may be formed between the first sensing node 120 and the second sensing node 130 _{pcd_line} )。

Further, the detection line extending from the first detection node 120 may be connected to the data lines of the first and third sub-pixels among the sub-pixels of each pixel.

Further, the detection line extending from the second detection node 130 may be connected to the data line of the second sub-pixel among the sub-pixels of each pixel.

In this case, a switch is established between the detection node of each sub-pixel and the data line. Therefore, by switching the switch on or off, the detection node is connected or disconnected to the data line of each sub-pixel.

The PCD circuit 520 may provide predetermined data through the first detection node 120 formed on the display panel 100, and then provide the predetermined data again through the second detection node 130. This process allows the presence of a crack on the display panel 100 to be detected or determined. In this case, the crack on the display panel 100 may be determined, for example, by whether at least one pixel (P) located on the display panel 100 emits light. Further, the predetermined data may include black data, but is not limited thereto.

Fig. 3 shows a detailed configuration of PCD circuit 520.

Fig. 4 shows a detailed configuration of the reference resistance generation circuit.

Referring to fig. 3, the PCD circuit 520 may include a driving voltage generator (e.g., PCD AMP) 521, a reference resistance generation circuit 522, and a comparator 523.

The driving voltage generator 521 may receive a VIN value (pcd_vin) and apply a predetermined voltage value, which may correspond to black data, to the first detection node 120. Further, the voltage value corresponding to the predetermined data (i.e., black data) may not be the same as the VDD value, and it may be referred to as a driving voltage.

Referring to fig. 3 and 4, the reference resistance generating circuit 522 may be composed of a plurality of resistors and switches, so that it is possible to control the resistance (R _{pcd_line} ) Voltage drop across.

Referring to fig. 4, for example, six resistors (R1 to R6) connected in series may be included in the reference resistance generating circuit 522.

In this configuration, each resistor may have a total of five switches (r_sw0 to r_sw4) formed at both ends.

In fig. 4, R1 may have a resistance of 1600kΩ, R2 may have a resistance of 800kΩ, R3 may have a resistance of 400kΩ, R4 may have a resistance of 200kΩ, R5 may have a resistance of 100kΩ, and R6 may have a resistance of 100kΩ.

In fig. 4, R1 is configured with the highest resistance, and R5 or R6 has the lowest resistance. However, the configuration is not limited thereto, and may be the opposite. In other words, R1 may have the lowest resistance value, and R5 or R6 may have the highest resistance value.

In fig. 4, the resistance values of R1 to R5 may have a multiple relationship (e.g., 1/2) and may decrease in sequence. However, it should be noted that the present disclosure is not limited to this configuration and may not necessarily have multiple relationships.

In addition, in fig. 4, R1 to R5 may be configured to have a gradually smaller resistance value, but this configuration is not necessarily limited thereto.

Meanwhile, although fig. 4 shows that R5 and R6 may be configured with the same resistance value, the present disclosure is not limited to this configuration.

For example, R6 may have a smaller or larger resistance value than R5.

Referring to fig. 4, switches formed at both ends of the resistor may be controlled (turned on or off) to arbitrarily determine the resistance value generated in the reference resistance generating circuit 522.

In this case, the resistance value determined in the reference resistance generating circuit 522 may be determined to be larger than, for example, the resistance value (R _{pcd_line} )。

This aims to control the voltage drop within a normal range when no crack occurs on the display panel 100 in the detection line 110. Here, the normal range of the voltage drop may be illustrated by, for example, the extent or range of the voltage drop occurring in the data line of the second subpixel (G) in fig. 7 (b).

In other words, if no crack occurs on the display panel 100, the voltage drop in the data line of the second sub-pixel (G) may indicate a level of the voltage drop that prevents the corresponding sub-pixel from emitting light.

In contrast, as shown in (c) of fig. 7, in the case where a crack occurs on the display panel 100, a significant voltage drop occurs in the second sub-pixel (G) with respect to the extent of the voltage drop occurring in the data line of the second sub-pixel (G), thereby causing it to emit light.

Meanwhile, when configuring the reference resistance generating circuit 522 as shown in fig. 4 and determining each resistance value, the size of the display panel 100 may be considered.

In other words, the value (R _{pcd_line} ) May vary according to the size of the display panel 100.

Therefore, as described above, the reference resistance value generated by the reference resistance generating circuit 522 should be sufficiently larger than the resistance value (R _{pcd_line} )。

To achieve this, as shown in fig. 4, for example, a 5-bit variable resistor may be employed to appropriately adapt a resistance value (R _{pcd_line} ) Is a variation of (c).

This allows forPreventing unintentional sub-pixel illumination even when no crack occurs on the display panel 100, but due to the resistance value (R _{pcd_line} ) While there is a significant voltage drop.

The present disclosure does not relate to applying a VDD voltage to the sensing line 110 to measure a resistance value of the sensing line to determine whether the display panel is broken.

In contrast, black data may be applied to the detection lines to evaluate the state of the display panel 100 based on whether a particular subpixel emits light due to a voltage drop associated with a crack.

In an embodiment, the PCD circuit 520 may not necessarily be a circuit configuration for measuring the resistance value of the detection line 110.

Fig. 5 and 6 are flowcharts illustrating a method of measuring a panel crack in a display device.

Referring to fig. 5, the method for measuring a panel crack may be performed as follows.

In S110, the data line may be charged with the first driving voltage by applying the first data to the data line connected between the sub-pixels of the display panel 100.

In S120, the first driving voltage is reapplied to the detection line 110 formed in the display panel 100, and the panel crack may be detected based on whether the sub-pixel emits light.

Specifically, a controller (not shown) of the Source driver IC 500 may control pre-application of black data to the data lines through a second driving voltage generator (Source AMP) included in the driving circuit 510 to charge for detecting panel cracks, and then may control the second driving voltage generator to operate at Hi-Z.

Subsequently, the controller may control the switch 140 formed in the display panel 100 to activate and control the black driving voltage to be reapplied from the first driving voltage generator 521 to the already charged data line.

At this time, the data lines of the first and third sub-pixels connected to the first detection node 120 may be supplied with a black driving voltage, and the data lines of the second sub-pixels connected to the second detection node 130 may be supplied with a voltage lower than the black driving voltage.

At this time, when the resistance of the detection line 110 exceeds the threshold value, a voltage drop exceeding the threshold value may be triggered, resulting in illumination of the second sub-pixel (G), as shown in fig. 7 described later.

When the second sub-pixel (G) is thus illuminated, the controller may detect the occurrence of a crack in the display panel 100.

Unlike fig. 5, the panel crack detection or determination method in fig. 6 may be performed as follows.

S210 is similar to S110 described above in fig. 5.

In S220, the reference resistance generation circuit 522 can generate a reference resistance (R _{pcd_line} ) Corresponding reference resistance.

In S230, the comparator 523 can compare the voltage of the second detection node 130 with a predetermined reference voltage.

In S240, the controller may evaluate whether the voltage at the second detection node 130 is lower than the reference voltage.

If the controller can detect that the voltage at the second detection node 130 is equal to or lower than the reference voltage as determined in S240, it is determined that a crack has occurred in the display panel 100 (S250-1).

In contrast, if the voltage at the second detection node 130 exceeds the reference voltage, it is determined that no crack occurs in the display panel 100 (S250-1).

Specifically, by comparing the reference voltage V _REF A comparison is made with the voltage at the second detection node 130 to determine that a crack exists in the display panel 100.

At this time, reference voltage V _REF May be half of the voltage output from the first driving voltage generator 521, but is not limited thereto.

If the resistance of the sense line 110 exceeds the reference resistance, then when the voltage on the second sense node 130 exceeds the reference voltage (V _REF ) When the crack has occurred in the display panel 100, the controller may determine that the crack has occurred. Conversely, in the opposite case, the controller may determine that no crack has occurred.

Fig. 7 illustrates an operation of the display panel 100 in the case where a crack occurs.

First, referring to (a) of fig. 7, the operation of each sub-pixel will be described as follows.

Referring to the circuit in (a) of fig. 7, the operation of the corresponding sub-pixel may be based on the voltage (V) of the capacitor formed between VDD and the data line _SG ) But vary.

For example, a higher V _SG The TFT may be activated.

Accordingly, when the TFT is activated and the switch (TFT sw) is closed, the corresponding sub-pixel emits light.

In (a) of fig. 7, the black driving voltage supplied to the data line may be equal to or less than VDD.

In the case of applying the black driving voltage to the data line, V _SG Has a very small value to deactivate the TFT.

However, in the case where a crack occurs in the display panel 100, the resistance of the detection line 110 may increase, resulting in a voltage drop exceeding a threshold value.

Thus V _SG May be applied at a value greater than that when the black driving voltage may be applied to the data line.

V _SG The value may ultimately activate the TFT.

Therefore, when the TFT is activated, power is supplied to the light source of the corresponding subpixel, and finally light is emitted.

If the sub-pixels emit light in this way, it can be recognized that a crack has occurred in the display panel.

Fig. 7 (b) is a timing chart showing the operation of the normal panel.

Referring to (b) of fig. 7, a black driving voltage may be applied from the source electrode to the data line.

Subsequently, the source may be controlled to operate at Hi-Z.

A black driving voltage is applied through the source electrode, and no voltage drop occurs in the first and third data lines.

In other words, each of the subpixels (i.e., the first subpixel (R) and the third subpixel (B)) connected to the first data line and the third data line does not emit light.

In addition, when a black driving voltage is applied through the source electrode, a voltage drop may occur on the second data line.

However, in this case, the voltage drop may be minimal. Here, the minimum voltage drop may indicate that there is no crack in the display panel 100, resulting in a low detection line resistance value (R _{pcd_line} ) And then causes a smaller voltage drop.

Furthermore, a smaller voltage drop may indicate that it is insufficient to activate the TFT of the corresponding subpixel.

Thus, the sub-pixels may remain non-emitting while the TFT remains inactive.

Assuming that the second sub-pixel (G) does not emit light, it can be easily recognized that no crack occurs in the display panel 100.

In contrast, fig. 7 (c) is a timing chart showing the operation of the abnormal panel.

Here, the term "abnormal panel" refers to a panel in which a crack has occurred.

As described previously, similar to (b) of fig. 7, when a black driving voltage is applied to each data line through the source electrode, no voltage drop occurs in the first and third data lines, and thus the TFTs remain inactive, and thus they do not emit light.

On the other hand, in the second data line, the resistance value (R _{pcd_line} ) Exceeds the threshold value, due to the resistance value (R _{pcd_line} ) Exceeding the threshold results in a voltage drop greater than that observed in fig. 7 (b).

This ultimately indicates a decrease in the voltage applied to the second data line, and V _SG The value of (2) increases.

Thus, when V _SG When the value of (2) increases, the TFT may become active.

Once the TFT is activated and the switch (TFT sw) is turned on, the second subpixel (G) connected to the second data line emits light.

In other words, it is intuitively obvious that a crack has occurred on the display panel 100.

Referring to (b) and (c) of fig. 7, the black driving voltage applied from the source may be simultaneously applied to the first to third data lines, and then the detection switch (or PCD switch) 140 may be controlled.

When the detection switch 140 is controlled in this way, as described above, no voltage drop occurs in the first data line and the third data line, and a voltage drop may occur in the second data line, as shown in the drawing.

However, unlike in (b) of fig. 7, in the normal panel, a voltage drop may occur in the second data line to such an extent that the TFT is not activated, and in (c) of fig. 7, in the abnormal panel, the second data line may experience a voltage drop sufficient to activate the TFT.

Meanwhile, in the above context, controlling the detection switch 140 may imply turning off the first detection switch 141 and the third detection switch 143 while turning on the second detection switch 142.

As described above, the first and third detection switches 141 and 143 are connected or disconnected between the first detection node 120 and the first and third data lines, and the second detection switch 142 is connected or disconnected between the second detection node 130 and the second data line.

In connection with the present disclosure, the presence of panel cracks may be assessed and identified on a row and/or column basis, depending on the design of the sense lines (or PCD lines) in the display panel 100.

This ultimately represents the ability to determine whether a panel crack exists in a particular row or a particular column.

In general, when checking for cracks during product shipment, if cracks are detected in the same row or column unit across a plurality of display panels 100, a potential problem of a portion of the display panel manufacturing apparatus corresponding to the particular row or column unit may be raised.

By making such evaluations and providing guidance, problems in the additional panel can be actively prevented.

Similarly, if a single display panel is created, for example, by connecting a plurality of physical blocks, the present disclosure may also be applied on a per physical block basis.

Fig. 8 to 11 show various configurations for evaluating the presence of cracks in the display panel.

For convenience we will describe using the example where one display panel is formed of six physical blocks (1-6), but this is not intended to be limiting.

In particular, fig. 9-11 may be more suitable for assessing the presence of cracks in large panels.

First, fig. 8 shows an example of evaluating the presence of cracks in all six physical blocks using a single PCD circuit included in the source driver IC 500 as described in fig. 1 to 5 above.

In fig. 9, unlike fig. 8, two PCD circuits are included in one source driver IC 500, and each PCD circuit (PCD 1 and PCD 2) may detect and determine whether a crack exists in the panel row by row.

In particular, the first PCD circuitry may determine whether blocks 1 through 3 have cracks, and the second PCD circuitry may determine whether blocks 4 through 6 have cracks.

In fig. 10, unlike fig. 8 or 9, a single source driver IC 500 includes three PCD circuits (PCD 1 to PCD 3), and each PCD circuit can detect and determine a panel crack column by column.

Specifically, the first PCD circuitry determines whether blocks 1 and 4 have cracks, the second PCD circuitry determines whether blocks 2 and 5 have cracks, and the third PCD circuitry determines whether blocks 3 and 6 have cracks.

In fig. 11, unlike fig. 8 to 10, one source driver IC 500 includes six PCD circuits (PCD 1 to PCD 6), and each PCD circuit is independently allocated to each block, thereby allowing panel cracks in each respective block to be detected and determined.

In fig. 9 to 11, the determination of whether the panel is broken may be performed on a column-by-column basis, a row-by-row basis, or on a separate block-by-block basis, independently or sequentially. In this case, if it is determined that a crack exists during the panel crack determination process, the subsequent crack determination step may be skipped. For example, in fig. 9, using the first PCD circuitry to determine whether a panel crack is present in a first row comprising the first to third blocks allows for determining a panel crack in the fourth to sixth blocks only if no crack is found in the corresponding block. In other words, if a crack has been detected in the first to third blocks, it may not be necessary to perform an operation of determining whether or not there is a panel crack in the fourth to sixth blocks. A similar approach can also be applied in fig. 10 and 11.

This allows for a more rapid and intuitive determination of whether a panel is broken and the particular panel piece in which the break occurred, as the case may be.

When the PCD circuit configuration in fig. 9-11 is used to determine the presence of a crack, it provides the advantage of identifying whether a particular block is cracked. By collecting and aggregating this data, areas of the device where cracks mainly occur can be determined, revealing problems with that particular line throughout the production line.

In fig. 9 to 11, each PCD circuit may be included in each source driver IC. Alternatively, a plurality of PCD circuits may be included in one source driver IC. Alternatively, at least one of the PCD circuits may be formed in another component of the display device 1000 other than the source driver IC, or may be formed in a separate IC.

Claims (10)

1. A source driver, the source driver comprising:

a first circuit configured to apply first data to a data line connected to a subpixel of the display panel to charge a first driving voltage;

a second circuit formed on the display panel, the second circuit applying the first driving voltage to a detection line formed on the display panel to detect a crack in the display panel based on an illumination state of the sub-pixel,

wherein the sensing line includes a first sensing node and a second sensing node formed at one side of the display panel along an extension direction of the sensing line,

wherein the first detection node is connected to the data lines of the first sub-pixel and the third sub-pixel, and

wherein the second detection node is connected to the data line of the second sub-pixel.

2. The source driver of claim 1, wherein the second circuit comprises a drive voltage generator configured to apply the first drive voltage to the detection line through the first detection node, and

wherein the first driving voltage applied by the second circuit is supplied to the data lines of the sub-pixels through switches formed between the detection nodes included in the detection lines and the data lines.

3. The source driver of claim 2, wherein the second circuit further comprises a reference resistance generation circuit configured to generate a reference resistance based on a voltage drop caused by a resistance formed in the detection line to prevent each sub-pixel from emitting light.

4. The source driver of claim 1, wherein,

the first data includes black data, and

the first circuit is configured to operate in a Hi-Z state when the data line is charged with the first driving voltage by applying the first data to the data line.

5. The source driver of claim 2, wherein the second circuit further comprises a third circuit configured to generate a reference resistance with respect to a resistance formed in the detection line, and

wherein the second circuit is configured to compare a predetermined reference voltage with a voltage of the second detection node to detect a crack in the display panel.

6. A method of measuring panel cracks in a display device, the method comprising the steps of:

applying first data to a data line connected to a subpixel of the display panel to charge a first driving voltage; and

applying the first driving voltage to a detection line formed in the display panel to detect a crack in the display panel based on an illumination state of the sub-pixel,

wherein the sensing line includes a first sensing node and a second sensing node formed at one side of the display panel,

wherein the first detection node is connected with the data lines of the first sub-pixel and the third sub-pixel, and

the second detection node is connected with the data line of the second sub-pixel.

7. The method of claim 6, wherein the first driving voltage is applied through the first detection node and is supplied to the data line of the corresponding sub-pixel via a switch formed between the detection node and each data line.

8. The method of claim 6, further comprising the step of:

a reference resistance is generated based on a voltage drop caused by a resistance formed in the detection line to prevent each sub-pixel from emitting light.

9. The method of claim 6, wherein,

the first data includes black data, and

the first circuit is configured to operate in a Hi-Z state when the data line is charged with the first driving voltage by applying the first data to the data line.

10. The method of claim 6, further comprising the step of:

generating a reference resistance with respect to the resistance formed in the detection line; and

comparing a preset reference voltage with the voltage of the second detection node to detect cracks in the display panel.