CN117852481A - Method and system for quickly determining integrated circuit layout netlist information - Google Patents
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Abstract
The invention discloses a method and a system for quickly determining information of an integrated circuit layout netlist, and relates to the technical field of integrated circuits. Comprising the following steps: reading in via connections and gold wire connections between different layers of the integrated circuit to form node pairs; reading in the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon set; reading in the network and the layer of each component pin of the integrated circuit and the pin coordinates and forming pin nodes; forming an initial triangle mesh subdivision for all polygon vertexes and nodes positioned in each layer of the integrated circuit layout; inserting new grid nodes at the intersections of the edges of different polygons aiming at the missing edges of all polygons of each layer of the integrated circuit layout after forming the triangle grids, and recovering the edges of the polygons to form new triangle grid subdivision; and sequentially obtaining different geometric figures of all layers, gold wires and networks of through holes based on a triangle traversal method, and rapidly determining netlist information of an integrated circuit layout.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method and a system for quickly determining information of an integrated circuit layout netlist.
Background
The fabrication process of integrated circuits typically involves schematic design, layout design, and fabrication of the integrated circuit based on the layout of the design. Integrated circuit fabrication is accomplished by integrated circuit suppliers, whose processes typically include tens of steps of circuit mask fabrication, wafer polishing, oxidation, hybridization, photolithography, diffusion, deposition, and metallization, ultimately effecting transfer of the circuit mask to the wafer, thereby effecting very complex circuit functions through the high density of electronic circuitry and component distribution of the wafer. When an integrated circuit design company designs a product and exports the design file to other suppliers, in order to achieve confidentiality of the design, the complete design file is usually exported separately for different suppliers, and information related to the designed circuit is wiped off as much as possible, for example, a copper-clad layer with complex shape described for the layout shape is not exported directly, but the complex polygon is decomposed into overlapping geometric figures (filled or hollowed rectangle, circle, ellipse, sector and ellipse sector) with a plurality of simple shapes, and a file is formed as geometric figure information of the complete design file for export. Meanwhile, the component and netlist information in the design file are respectively exported through other files. In order to improve the primary yield of integrated circuit fabrication, after taking the fabrication related files provided by the designer, the integrated circuit manufacturer still needs to manually diagnose the layout of the integrated circuit to find potential layout errors before actual fabrication, thereby reducing the fabrication cost. However, the netlist information given in the prior art only includes the network in which the pins of different components are located, and the coordinate information of the pins of the components, and the circuit related information of the integrated circuit is not complete. Therefore, it is currently necessary to diagnose the integrated circuit layout based on the netlist information of the integrated circuit layout provided by the designer.
Disclosure of Invention
The invention aims to provide a method for quickly determining the netlist information of an integrated circuit layout, which can quickly integrate the netlist information of the circuit layout based on files provided by a designer, and improve the integrity of the related information of the circuit, thereby meeting the requirement of accurately diagnosing the integrated circuit layout.
The invention is realized by the following technical scheme:
a method for quickly determining information of an integrated circuit layout netlist comprises the following steps: reading in via connection and gold wire connection among different layers of an integrated circuit layout, and forming node pairs by connecting nodes among different layers; reading in the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon; reading in the network and pin coordinates of all component pins of each layer of the integrated circuit layout, and forming pin nodes of the layer according to the pin coordinates; forming initial triangle mesh division of each layer aiming at vertexes of all polygons, nodes in the node pairs and the pin nodes of each layer of the integrated circuit layout; inserting new grid nodes at the intersections of all the polygons of each layer of the integrated circuit layout with the edges of the other polygons to obtain the recovery edges of the polygons so as to form a new triangle mesh; the missing side is a side which is not the common side of the two triangles; starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining the network of all grid nodes based on a triangle grid traversing method.
The method for traversing the triangle mesh based on the grid nodes of all component pins of the integrated circuit layout sequentially obtains the network of all the grid nodes, which comprises the following steps: step 6.1: initializing and setting grid nodes of all triangle grids of the new triangle grid subdivision; step 6.2: finding out a triangle unit containing the current ith component pin coordinate in the triangle mesh subdivision, setting the network to which all mesh nodes of the triangle unit belong as the network to which the ith component pin belongs, adding the triangle unit into a peripheral traversing mesh unit set, and marking the processing state of the mesh unit as processed; step 6.3: taking one of the triangle units from the set of peripheral traversal grid units and removing the triangle unit from the set of peripheral traversal grid units; step 6.4: judging whether the peripheral traversing grid cell set is an empty set or not, if not, turning to a step 6.2; if yes, setting to be i=i+1, if i > the pin number of the component, entering the next step, otherwise, entering the step 6.2; step 6.5: outputting the geometric figure, gold thread or the network of through holes corresponding to the grid nodes of the triangle units extracted from the peripheral traversing grid unit set.
The initializing the mesh nodes of the new triangle mesh to divide all triangle meshes comprises the following steps: setting the processing states of all triangles, geometric figures, gold wires, through holes and wires as unprocessed; setting a peripheral grid cell set traversed by the current triangle as null; setting the current processing ith component pin, and obtaining the network of the ith component pin and the grid node corresponding to the pin coordinate.
The retrieving one triangle element from the set of peripheral traversal grid elements and removing the triangle element from the set of peripheral traversal grid elements includes: step 6.3.1: setting a network where the triangle units extracted from the peripheral traversing grid unit set are located as an extracted triangle network, if any vertex of the triangle is a node in any of the node pairs, setting the network where the via holes or gold wires corresponding to the node pairs are located as the extracted triangle network, and marking the via holes or gold wires corresponding to the node pairs as processed; for the associated triangle with all vertexes being the other node in the node pair, if the processing state is unprocessed, adding the associated triangle into the peripheral traversing grid cell set, marking the processing state of the associated triangle as processed, setting the network where the associated triangle is located as the extracted triangle network, and entering the next step; step 6.3.2: if none of the three sides of the associated triangle is a polygon side, any one of the neighboring triangles of the associated triangle is unprocessed, and the common side of the one or more neighboring triangles and the associated triangle is not a polygon side, adding the corresponding neighboring triangle into the peripheral traversing grid unit set, marking the neighboring triangle added into the peripheral traversing grid unit set as processed, setting the network where the corresponding neighboring triangle is located as the triangle-taking network, and turning to step 6.4; otherwise, entering the next step; step 6.3.3: if one or more sides of the associated triangle are sides of any polygon and the associated triangle is a left triangle corresponding to the side of the polygon, setting the network where the associated triangle is located as the triangle-taking network when the associated triangle is unprocessed, adding the associated triangle into the peripheral traversal grid cell set, and entering the next step; otherwise, turning to step 6.4; step 6.3.4: for the left triangle of all sides of the corresponding polygon of the above-mentioned associated triangle, if its processing state is unprocessed, setting the network to which the left triangle belongs as the above-mentioned fetch triangle network, and adding the left triangle into the above-mentioned peripheral traversal grid cell set.
Reading the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon set, wherein the method comprises the following steps: grouping the geometric figures of each layer into a group, setting the copper-clad polygon as a polygon with positive=1, and setting the hollowed polygon as a polygon with positive= -1; where positive=1 indicates a positive polygon, its polygon vertices are arranged in a counterclockwise order, positive= -1 indicates a negative polygon, and its polygon vertices are arranged in a clockwise order.
The initial triangle mesh division of each layer is formed by the vertexes and the nodes of all polygons positioned on each layer of the integrated circuit layout, and the initial triangle mesh division comprises the following steps: step 4.1: respectively obtaining a point set P aiming at all polygon vertexes and nodes positioned in each layer of the integrated circuit layout, calculating a bounding box of the point set P, and adding four vertexes of the bounding box into the point set P to obtain a point set P'; generating two supertriangles according to the bounding box to form Delaunay triangulation; step 4.2: all points in the point set P were inserted one by one into the Delaunay triangulation described above and adjusted as follows: step 4.2.1: if any insertion point is positioned in a certain triangle, connecting the insertion point with three vertexes of the corresponding triangle to split the original triangle into 3 split triangles; step 4.2.2: judging whether the circumscribed circles of the split triangles contain all vertexes of the split triangles or not, if so, carrying out edge exchange on the public edges of the triangle and the neighbor triangles to form two new triangles until the two new triangles are not satisfied; step 4.3: until all points in the point set P are inserted into triangulation, and after the edge exchange operation is completed, obtaining a new Delaunay triangulation of the point set P'; and deleting four vertexes of the bounding box from the new Delaunay triangulation, and removing triangles connected with the four vertexes of the bounding box by all the triangle vertexes to finally form the Delaunay triangulation of the point set P, namely the initial triangle mesh subdivision.
The above-mentioned losing the edge in the initial triangle mesh subdivision to all polygons of each layer of the integrated circuit layout, insert the new mesh node in the junction of the edge of losing the edge and edge of other polygons, get the recovery edge of the polygon, in order to form the new triangle mesh subdivision, including: step 5.1: collecting Lost edges of all polygons in the initial triangle mesh subdivision to form a set Lost; step 5.2: taking out the longest edge of the edge length from the set Lost and removing the longest edge from the set Lost; setting a starting end point as one end point of the longest side, and setting a terminating end point as the other end point of the longest side; step 5.3: searching a switching triangle which comprises the starting end point and has two vertexes of the triangle positioned at the two sides of the side corresponding to the starting end point to the ending end point, if no triangle exists, turning to step 5.6, otherwise, turning to the next step; step 5.4: judging whether the edge of the exchange triangle is the edge of other polygons, if so, turning to step 5.5; if not, carrying out edge exchange on the public edges of the exchange triangle and the neighbor triangle corresponding to the starting endpoint to obtain two new triangles of the public edge formed by connecting the non-common points of the exchange triangle and the corresponding neighbor triangle, and turning to step 5.3; the neighbor triangle corresponding to the starting endpoint is: a triangle comprising two vertices of the switch triangle other than the start endpoint; step 5.5: newly adding a grid node at the intersection point of the longest edge and the edges of other polygons, wherein the intersection point divides two intersected edges into four edges sharing the vertex; setting the initial endpoint as a newly added grid node, and turning to step 5.3; step 5.6: judging whether the set Lost is an empty set or not, if not, returning to the step 5.2; if yes, the next step is carried out.
A system for rapid determination of information about an integrated circuit layout netlist, comprising: reading in via connection and gold wire connection among different layers of an integrated circuit layout, and forming node connection modules of node pairs by connecting nodes among different layers; the image conversion module is used for reading the geometric figures of each layer of the integrated circuit layout and converting the geometric figures of each layer into polygons; reading in the network and the pin coordinates of all component pins of each layer of the integrated circuit layout, and forming a pin reading module of the pin node of the layer according to the pin coordinates; an initial mesh division module for forming initial triangle mesh division of each layer aiming at vertexes of all polygons, nodes in the node pair and the pin nodes of each layer of the integrated circuit layout; inserting new grid nodes at the intersection points of the lost edges and the edges of other polygons aiming at the lost edges of all polygons of each layer of the integrated circuit layout in the initial triangle mesh subdivision to obtain the recovery edges of the polygons so as to form a mesh secondary subdivision module of the new triangle mesh subdivision; the missing side is a side which is not the common side of the two triangles; starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining netlist information modules of networks to which all grid nodes belong based on a triangle grid traversing method.
An electronic device comprising a memory, a processor and a computer program stored in said memory and executable on said processor, said processor implementing the steps of any one of the above-described methods for rapid determination of integrated circuit layout netlist information when said computer program is executed.
A computer readable storage medium storing a computer program which when executed by a processor performs the steps of a method for rapidly determining information of an integrated circuit layout netlist as claimed in any one of the preceding claims.
Compared with the prior art, the invention has the following advantages and beneficial effects:
reading in via hole connection and gold wire connection among different layers of an integrated circuit layout to form node pairs by connecting nodes among different layers; reading in the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon; reading in the network, the layer and the coordinates of the pins of each component of the integrated circuit, and forming pin nodes of the layer according to the pin coordinates; thus, triangular mesh subdivision is formed primarily for all polygon vertexes, via connections, gold thread connection nodes and pin nodes which are positioned in each layer of the integrated circuit layout; aiming at the missing edges of all polygons of each layer of the integrated circuit layout in the initial triangle mesh generation, restoring the edges of the polygons in a mode of inserting new mesh nodes at the intersections among different polygons, and updating the triangle mesh generation; starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining the network of all grid nodes based on a triangle grid traversing method. The invention realizes triangle mesh subdivision based on polygon vertexes and nodes of different layers of the layout, and performs mesh unit recovery and perfection by utilizing intersection points among different polygons, thereby realizing traversal of each layer of circuit information, improving the integrity of relevant information of a circuit based on netlist information of a file rapid integrated circuit layout provided by a designer, and being suitable for accurately diagnosing the integrated circuit layout.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a flow chart of a method for rapid determination of information about an integrated circuit layout netlist in accordance with embodiment 1 of the present application;
FIG. 2 is a schematic diagram of the connection relationship of a 3-level integrated circuit layout according to embodiment 1 of the present application;
fig. 3 is a schematic diagram of a polygon edge restoring operation in embodiment 1 of the present application.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Example 1
As shown in fig. 1, an embodiment of the present application provides a method for quickly determining netlist information of an integrated circuit layout, including: reading in via connection and gold wire connection among different layers of an integrated circuit layout, and forming node pairs by connecting nodes among different layers; reading in the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon; reading in the network and pin coordinates of all component pins of each layer of the integrated circuit layout, and forming pin nodes of the layer according to the pin coordinates; forming initial triangle mesh division of each layer aiming at vertexes of all polygons, nodes in the node pairs and the pin nodes of each layer of the integrated circuit layout; inserting new grid nodes at the intersections of all the polygons of each layer of the integrated circuit layout with the edges of the other polygons to obtain the recovery edges of the polygons so as to form a new triangle mesh; the missing side is a side which is not the common side of the two triangles; starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining the network of all grid nodes based on a triangle grid traversing method.
Specifically, via hole connection between layers is read in, gold wire connection between different layers is realized, and node pair sets formed by nodes of two different layers connected by the gold wire connection are expressed as:. Reading in the geometry of each layer of an integrated circuit layoutA set of graphics, converting these geometric figures into a set of polygons, expressed as: { P }. The filled geometric figure-converted polygon is a positive polygon, the vertexes of the filled geometric figure-converted polygon are arranged anticlockwise, the hollowed geometric figure-converted polygon is a negative polygon, and the vertexes of the hollowed geometric figure-converted polygon are arranged clockwise. The network set where the pins of each component of each layer are read in can be expressed as: />And the coordinate set of each pin is expressed as: />And forming the pin node of the layer according to the pin coordinates. For each layer in turn, an initial Delaunay triangle mesh subdivision is formed based on the vertices of the polygon and the nodes located in that layer in the node pair set. And sequentially aiming at each layer of layout, recovering missing edges of all polygons in the initial triangle mesh subdivision by inserting new mesh nodes at the intersection points of different polygons, and forming the triangle mesh subdivision with recovered edges. And starting from each component pin, sequentially obtaining networks where different geometric figures, gold wires and through holes of all layers are positioned based on a triangle traversing method, thereby determining the netlist information of the whole integrated circuit layout.
The method for traversing the triangle mesh based on the grid nodes of all component pins of the integrated circuit layout sequentially obtains the network of all the grid nodes, which comprises the following steps: step 6.1: initializing and setting grid nodes of all triangle grids of the new triangle grid subdivision; step 6.2: finding out a triangle unit containing the current ith component pin coordinate in the triangle mesh subdivision, setting the network to which all mesh nodes of the triangle unit belong as the network to which the ith component pin belongs, adding the triangle unit into a peripheral traversing mesh unit set, and marking the processing state of the mesh unit as processed; step 6.3: taking one of the triangle units from the set of peripheral traversal grid units and removing the triangle unit from the set of peripheral traversal grid units; step 6.4: judging whether the peripheral traversing grid cell set is an empty set or not, if not, turning to a step 6.2; if yes, setting to be i=i+1, if i > the pin number of the component, entering the next step, otherwise, entering the step 6.2; step 6.5: outputting the geometric figure, gold thread or the network of through holes corresponding to the grid nodes of the triangle units extracted from the peripheral traversing grid unit set.
The initializing the mesh nodes of the new triangle mesh to divide all triangle meshes comprises the following steps: setting the processing states of all triangles, geometric figures, gold wires, through holes and wires as unprocessed; setting a peripheral grid cell set traversed by the current triangle as null; setting the i-th component pin of the current process and obtaining the network of the i-th component pinAnd the above pin coordinates->Corresponding mesh nodes.
The retrieving one triangle element from the set of peripheral traversal grid elements and removing the triangle element from the set of peripheral traversal grid elements includes: step 6.3.1: setting a network where the triangle units extracted from the peripheral traversing grid unit set are located as an extracted triangle network, if any vertex of the triangle is a node in any of the node pairs, setting the network where the via holes or gold wires corresponding to the node pairs are located as the extracted triangle network, and marking the via holes or gold wires corresponding to the node pairs as processed; for the associated triangle with all vertexes being the other node in the node pair, if the processing state is unprocessed, adding the associated triangle into the peripheral traversing grid cell set, marking the processing state of the associated triangle as processed, setting the network where the associated triangle is located as the extracted triangle network, and entering the next step; step 6.3.2: if none of the three sides of the associated triangle is a polygon side, any one of the neighboring triangles of the associated triangle is unprocessed, and the common side of the one or more neighboring triangles and the associated triangle is not a polygon side, adding the corresponding neighboring triangle into the peripheral traversing grid unit set, marking the neighboring triangle added into the peripheral traversing grid unit set as processed, setting the network where the corresponding neighboring triangle is located as the triangle-taking network, and turning to step 6.4; otherwise, entering the next step; step 6.3.3: if one or more sides of the associated triangle are sides of any polygon and the associated triangle is a left triangle corresponding to the side of the polygon, setting the network where the associated triangle is located as the triangle-taking network when the associated triangle is unprocessed, adding the associated triangle into the peripheral traversal grid cell set, and entering the next step; otherwise, turning to step 6.4; step 6.3.4: for the left triangle of all sides of the corresponding polygon of the above-mentioned associated triangle, if its processing state is unprocessed, setting the network to which the left triangle belongs as the above-mentioned fetch triangle network, and adding the left triangle into the above-mentioned peripheral traversal grid cell set.
If any vertex v of the associated triangle t is a node pair setNode pairs of->One of them sets up node pair +.>The corresponding via hole or gold wire belongs to the network of +.>And sets its processing status to processed and +.>A triangle associated with another node in the hierarchy, adding the triangle to the set of peripheral traversal grid cells if its processing state is unprocessed +.>And add new set +.>The identification status of the triangle of (2) is set to processed, the network to which it belongs is set to +.>。
If three sides of the triangle t are not sides of any polygon, and processing states of any one or more neighbor triangles in the three adjacent neighbor triangles are unprocessed, and a common side of the one or more neighbor triangles and the triangle is not a side of any polygon, adding the one or more neighbor triangles of the triangle t into a setAnd add new set +.>The identification status of the triangle of (2) is set to processed, the network to which it belongs is set to +.>Step 6.4; otherwise, the next step is entered. Wherein the common side is the side of the triangle adjacent to the triangle t and the triangle t.
If one or more sides of the triangle t are the jth polygon And triangle t is a polygon +.>Left triangle of side e of (2), set up polygon +.>The network is->Go to step 6.3.4; otherwise, turning to step 6.4; polygonal->The left triangle of the side e of (a) is a triangle containing the side e and having the same direction as the direction of the polygon side e.
For polygonsIf the processing state is unprocessed, setting the network to which the left triangle belongs as +.>And add it to the collection->Is a kind of medium.
Determining a set of peripheral traversal grid cellsWhether the set is an empty set or not, if not, turning to a step 6.2; if yes, set to i=i+1, if i>And (6) the pin number of the component enters the next step, otherwise, the step 6.2 is carried out. .
As shown in fig. 2, the present embodiment gives a 3-layer 4-network of geometry, gold wires and Kong Liancheng: VSS, VCC, VDD and VO, these 4 networks are given by pins 1-4, respectively. The left graph is shown as geometry of the copper-clad polygon and the right graph is shown as the copper-clad area. In the upper graph, firstly performing Delaunay mesh subdivision on geometric figures and node pairs of each layer, recovering missing edges to form triangular mesh subdivision, respectively starting from nodes corresponding to pins 1-4, finding out triangles where the triangles are located, setting the triangles as networks corresponding to the pins, and sequentially obtaining networks where all geometric figures, gold threads and through holes are located by a triangle unit traversing method.
Reading the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon set, wherein the method comprises the following steps: grouping the geometric figures of each layer into a group, setting the copper-clad polygon as a polygon with positive=1, and setting the hollowed polygon as a polygon with positive= -1; where positive=1 indicates a positive polygon, its polygon vertices are arranged in a counterclockwise order, positive= -1 indicates a negative polygon, and its polygon vertices are arranged in a clockwise order.
The initial triangle mesh division of each layer is formed by the vertexes and the nodes of all polygons positioned on each layer of the integrated circuit layout, and the initial triangle mesh division comprises the following steps: step 4.1: respectively obtaining a point set P aiming at all polygon vertexes and nodes positioned in each layer of the integrated circuit layout, calculating a bounding box of the point set P, and adding four vertexes of the bounding box into the point set P to obtain a point set P'; generating two supertriangles according to the bounding box to form Delaunay triangulation; step 4.2: all points in the point set P were inserted one by one into the Delaunay triangulation described above and adjusted as follows: step 4.2.1: if any insertion point is positioned in a certain triangle, connecting the insertion point with three vertexes of the corresponding triangle to split the original triangle into 3 split triangles; step 4.2.2: judging whether the circumscribed circles of the split triangles contain all vertexes of the split triangles or not, if so, carrying out edge exchange on the public edges of the triangle and the neighbor triangles to form two new triangles until the two new triangles are not satisfied; step 4.3: until all points in the point set P are inserted into triangulation, and after the edge exchange operation is completed, obtaining a new Delaunay triangulation of the point set P'; and deleting four vertexes of the bounding box from the new Delaunay triangulation, and removing triangles connected with the four vertexes of the bounding box by all the triangle vertexes to finally form the Delaunay triangulation of the point set P, namely the initial triangle mesh subdivision.
Step 4.2.2: respectively judging whether the 3 triangles obtained by splitting meet the empty circle property, if not, carrying out edge exchange operation on the triangle, including exchanging the public edges of the triangle and the neighboring triangles thereof to form two new triangles until all the triangles meet the empty circle property, and obtaining a new Delaunay triangulation comprising the insertion point at the moment; the open circle property means that the circumscribed circle of a triangle does not contain all the vertices of the triangle. The Delaunay triangulation the initial Delaunay triangulation may be obtained using the Lawson algorithm.
The above-mentioned losing the edge in the initial triangle mesh subdivision to all polygons of each layer of the integrated circuit layout, insert the new mesh node in the junction of the edge of losing the edge and edge of other polygons, get the recovery edge of the polygon, in order to form the new triangle mesh subdivision, including: step 5.1: collecting Lost edges of all polygons in the initial triangle mesh subdivision to form a set Lost; step 5.2: taking out the longest edge of the edge length from the set Lost and removing the longest edge from the set Lost; setting a starting end point as one end point of the longest side, and setting a terminating end point as the other end point of the longest side; step 5.3: searching a switching triangle which comprises the starting end point and has two vertexes of the triangle positioned at the two sides of the side corresponding to the starting end point to the ending end point, if no triangle exists, turning to step 5.6, otherwise, turning to the next step; step 5.4: judging whether the edge of the exchange triangle is the edge of other polygons, if so, turning to step 5.5; if not, carrying out edge exchange on the public edges of the exchange triangle and the neighbor triangle corresponding to the starting endpoint to obtain two new triangles of the public edge formed by connecting the non-common points of the exchange triangle and the corresponding neighbor triangle, and turning to step 5.3; the neighbor triangle corresponding to the starting endpoint is: a triangle comprising two vertices of the switch triangle other than the start endpoint; step 5.5: newly adding a grid node at the intersection point of the longest edge and the edges of other polygons, wherein the intersection point divides two intersected edges into four edges sharing the vertex; setting the initial endpoint as a newly added grid node, and turning to step 5.3; step 5.6: judging whether the set Lost is an empty set or not, if not, returning to the step 5.2; if yes, the next step is carried out.
As shown in fig. 3, the longest sideIs sent out by a vertex A, and two vertexes C, D of the triangle which contain the vertex A are searched and are positioned on the longest sideΔacd on both sides, edge of ΔacdMeanwhile, the triangle is also another polygon edge, a grid node E is inserted at the intersection point of the triangle, and meanwhile, the adjacent neighbor triangle delta DCG of the delta ACD is split into 4 triangles: ΔAED, ΔACE, ΔCGE, and ΔEGD, edges of a polygon、Split into 4 sides of a polygon:、、、. Setting a starting endpoint as a newly added grid node E, and searching the edge of the delta EGDAt the edgeTwo sides and edgesEdges other than polygons, exchanging ΔEGD with common edges of its neighbors ΔDGF, resulting in edges with common edgesΔdef and Δegf of (a); repeating the above operation until the longest edgeIs fully restored, where the edgeIs restored as、Which are both sides of a triangle.
Example 2
The embodiment of the application provides a rapid determination system for integrated circuit layout netlist information based on embodiment 1, which comprises the following steps: reading in via connection and gold wire connection among different layers of an integrated circuit layout, and forming node connection modules of node pairs by connecting nodes among different layers; the image conversion module is used for reading the geometric figures of each layer of the integrated circuit layout and converting the geometric figures of each layer into polygons; reading in the network and the pin coordinates of all component pins of each layer of the integrated circuit layout, and forming a pin reading module of the pin node of the layer according to the pin coordinates; an initial mesh division module for forming initial triangle mesh division of each layer aiming at vertexes of all polygons, nodes in the node pair and the pin nodes of each layer of the integrated circuit layout; inserting new grid nodes at the intersection points of the lost edges and the edges of other polygons aiming at the lost edges of all polygons of each layer of the integrated circuit layout in the initial triangle mesh subdivision to obtain the recovery edges of the polygons so as to form a mesh secondary subdivision module of the new triangle mesh subdivision; the missing side is a side which is not the common side of the two triangles; starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining netlist information modules of networks to which all grid nodes belong based on a triangle grid traversing method.
The principle of the embodiment of the present application is the same as that of embodiment 1, and a repetitive description thereof will not be made here.
In summary, the present application provides a method and a system for quickly determining netlist information of an integrated circuit layout:
reading in via hole connection and gold wire connection among different layers of an integrated circuit layout to form node pairs by connecting nodes among different layers; reading in the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon; reading in the network, the layer and the coordinates of the pins of each component of the integrated circuit, and forming pin nodes of the layer according to the pin coordinates; thus, triangular mesh subdivision is formed primarily for all polygon vertexes, via connections, gold thread connection nodes and pin nodes which are positioned in each layer of the integrated circuit layout; aiming at the missing edges of all polygons of each layer of the integrated circuit layout in the initial triangle mesh generation, restoring the edges of the polygons in a mode of inserting new mesh nodes at the intersections among different polygons, and updating the triangle mesh generation; starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining the network of all grid nodes based on a triangle grid traversing method. The invention realizes triangle mesh subdivision based on polygon vertexes and nodes of different layers of the layout, and performs mesh unit recovery and perfection by utilizing intersection points among different polygons, thereby realizing traversal of each layer of circuit information, improving the integrity of relevant information of a circuit based on netlist information of a file rapid integrated circuit layout provided by a designer, and being suitable for accurately diagnosing the integrated circuit layout.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the present invention, and is not meant to limit the scope of the invention, but to limit the scope of the invention.
Claims (10)
1. A method for quickly determining information of an integrated circuit layout netlist is characterized by comprising the following steps:
reading in via connection and gold wire connection among different layers of an integrated circuit layout, and forming node pairs by connecting nodes among different layers;
reading in the geometric figure of each layer of the integrated circuit layout, and converting the geometric figure of each layer into a polygon;
reading in the network and pin coordinates of all component pins of each layer of the integrated circuit layout, and forming pin nodes of the layer according to the pin coordinates;
forming initial triangle mesh division of each layer aiming at vertexes of all polygons, nodes in the node pair and the pin nodes of each layer of the integrated circuit layout;
inserting new grid nodes at the intersection points of all the polygons of each layer of the integrated circuit layout and the edges of other polygons to obtain the recovery edges of the polygons so as to form a new triangle mesh; the lost edge is an edge which is not a common edge of the two triangles;
Starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining the network of all grid nodes based on a triangle grid traversing method.
2. The method for quickly determining netlist information of an integrated circuit layout according to claim 1, wherein the method for sequentially obtaining the belonging network of all grid nodes based on triangle grid traversal from the grid nodes of all component pins of the integrated circuit layout comprises the steps of:
step 6.1: initializing and setting grid nodes of all triangle grids of the new triangle grid subdivision;
step 6.2: finding out a triangle unit containing the current ith component pin coordinate in the triangle mesh subdivision, setting the network of all mesh nodes of the triangle unit as the network of the ith component pin, adding the triangle unit into a peripheral traversing mesh unit set, and marking the processing state of the mesh unit as processed;
step 6.3: retrieving one of the triangle elements from the set of peripheral traversal grid elements and removing the triangle element from the set of peripheral traversal grid elements;
Step 6.4: judging whether the peripheral traversal grid cell set is an empty set or not, if not, turning to a step 6.2; if yes, setting to be i=i+1, if i > the pin number of the component, entering the next step, otherwise, entering the step 6.2;
step 6.5: outputting the network of the geometric figure, gold thread or via corresponding to the grid node of the triangle unit taken out from the peripheral traversing grid unit set.
3. The method for quickly determining netlist information of integrated circuit layout according to claim 2, wherein the initializing the mesh nodes of all triangle meshes of the new triangle mesh subdivision comprises:
setting the processing states of all triangles, geometric figures, gold wires, through holes and wires as unprocessed; setting a peripheral grid cell set traversed by the current triangle as null; setting an ith component pin in current processing, and obtaining the network of the ith component pin and grid nodes corresponding to the pin coordinates.
4. The method for quickly determining netlist information of an integrated circuit layout of claim 2, wherein the retrieving one of the triangle elements from the set of peripheral traversal lattice elements and removing the triangle element from the set of peripheral traversal lattice elements comprises:
Step 6.3.1: setting a network where the triangle units extracted from the peripheral traversal grid unit set are located as an extracted triangle network, if any vertex of the triangle is a node in any node pair, setting the network where a via or gold wire corresponding to the node pair is located as the extracted triangle network, and marking the via or gold wire corresponding to the node pair as processed; for all the associated triangles with vertexes being the other node in the node pair, if the processing state is unprocessed, adding the associated triangles into the peripheral traversing grid cell set, marking the processing state of the associated triangles as processed, setting the network where the associated triangles are located as the triangle extraction network, and carrying out the next step;
step 6.3.2: if none of the three sides of the associated triangle is a polygon side, an unprocessed neighbor triangle of any one of the adjacent neighbor triangles of the associated triangle, and if the common side of the one or more neighbor triangles and the associated triangle is not a polygon side, adding the corresponding neighbor triangle into the peripheral traversing grid unit set, marking the neighbor triangle added into the peripheral traversing grid unit set as processed, setting the network where the corresponding neighbor triangle is located as the triangle-taking network, and turning to step 6.4; otherwise, entering the next step;
Step 6.3.3: if one or more sides of the associated triangle are sides of any polygon and the associated triangle is a left triangle corresponding to the side of the polygon, setting a network where the associated triangle is located as the triangle-taking network when the associated triangle is unprocessed, adding the associated triangle into the peripheral traversal grid cell set, and entering the next step; otherwise, turning to step 6.4;
step 6.3.4: and for the left triangle of all sides of the corresponding polygon of the associated triangle, if the processing state is unprocessed, setting the network to which the left triangle belongs as the triangle fetching network, and adding the left triangle into the peripheral traversing grid cell set.
5. The method for quickly determining netlist information of an integrated circuit layout according to claim 1, wherein the reading in the geometry of each layer of the integrated circuit layout and converting the geometry of each layer into a set of polygons comprises:
grouping the geometric figures of each layer into a group, setting the copper-clad polygon as a polygon with positive=1, and setting the hollowed polygon as a polygon with positive= -1; where positive=1 indicates a positive polygon, its polygon vertices are arranged in a counterclockwise order, positive= -1 indicates a negative polygon, and its polygon vertices are arranged in a clockwise order.
6. The method for quickly determining netlist information of an integrated circuit layout according to claim 1, wherein the forming of initial triangle mesh segments for each layer for vertices and nodes of all polygons in each layer of the integrated circuit layout includes:
step 4.1: respectively obtaining a point set P aiming at all polygon vertexes and nodes positioned in each layer of the integrated circuit layout, calculating a bounding box of the point set P, and adding four vertexes of the bounding box into the point set P to obtain a point set P'; generating two supertriangles according to the bounding box to form Delaunay triangulation;
step 4.2: all points in the point set P are inserted one by one into the Delaunay triangulation and adjusted as follows:
step 4.2.1: if any insertion point is positioned in a certain triangle, connecting the insertion point with three vertexes of the corresponding triangle, so that the original triangle is split into 3 split triangles;
step 4.2.2: judging whether the circumscribed circles of the split triangles contain all vertexes of the split triangles or not, if so, carrying out edge exchange on the public edges of the triangle and the neighbor triangles to form two new triangles until the two new triangles are not satisfied;
Step 4.3: until all points in the point set P are inserted into triangulation and the edge exchange operation is completed, obtaining a new Delaunay triangulation of the point set P'; and deleting four vertexes of the bounding box from the new Delaunay triangulation, and removing triangles connected with the four vertexes of the bounding box by all the triangle vertexes to finally form Delaunay triangulation of the point set P, namely the initial triangle mesh subdivision.
7. The method for quickly determining netlist information of an integrated circuit layout according to claim 1, wherein the step of inserting new mesh nodes at intersections of all polygons of each layer of the integrated circuit layout with the edges of other polygons to obtain restored edges of the polygons to form a new triangle mesh, comprises:
step 5.1: collecting Lost edges of all polygons in the initial triangle mesh subdivision to form a set Lost;
step 5.2: taking the longest edge of the edge length from the set Lost and removing the longest edge from the set Lost; setting a starting end point as one end point of the longest side, and setting a terminating end point as the other end point of the longest side;
Step 5.3: searching a switching triangle which comprises the starting endpoint and has two vertexes of the triangle positioned at the two sides of the edge corresponding to the starting endpoint to the terminating endpoint, if no triangle exists, turning to step 5.6, otherwise, entering the next step;
step 5.4: judging whether the edge of the exchange triangle is the edge of other polygons, if so, turning to step 5.5; if not, carrying out edge exchange on the public edges of the exchange triangle and the neighbor triangle corresponding to the starting endpoint to obtain two new triangles of the public edge formed by connecting the non-common points of the exchange triangle and the corresponding neighbor triangle, and turning to step 5.3; the neighbor triangle corresponding to the starting endpoint is: a triangle comprising two vertices of the switch triangle other than the starting endpoint;
step 5.5: newly adding a grid node at the intersection point of the longest edge and the edges of other polygons, wherein the intersection point divides two intersected edges into four edges sharing the vertex; setting the initial endpoint as a newly added grid node, and turning to step 5.3;
step 5.6: judging whether the set Lost is an empty set or not, if not, returning to the step 5.2; if yes, the next step is carried out.
8. A system for rapid determination of information about an integrated circuit layout netlist, comprising:
reading in via connection and gold wire connection among different layers of an integrated circuit layout, and forming node connection modules of node pairs by connecting nodes among different layers;
the image conversion module is used for reading the geometric figures of each layer of the integrated circuit layout and converting the geometric figures of each layer into polygons;
reading in the network and the pin coordinates of all component pins of each layer of the integrated circuit layout, and forming a pin reading module of the pin node of the layer according to the pin coordinates;
the initial mesh generation module is used for forming initial triangle mesh generation of each layer aiming at vertexes of all polygons, nodes in the node pair and the pin nodes of each layer of the integrated circuit layout;
inserting new grid nodes at the intersections of all the polygons of each layer of the integrated circuit layout with the edges of the other polygons to obtain the recovery edges of the polygons so as to form a grid secondary subdivision module of the new triangle mesh subdivision; the lost edge is an edge which is not a common edge of the two triangles;
Starting from the grid nodes of all component pins of the integrated circuit layout, sequentially obtaining netlist information modules of networks to which all grid nodes belong based on a triangle grid traversing method.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized by: the steps of the method for quickly determining information of an integrated circuit layout netlist according to any of claims 1 to 7 are implemented when the processor executes the computer program.
10. A computer-readable storage medium storing a computer program, characterized in that: the computer program, when executed by a processor, performs the steps of a method for fast determining information of an integrated circuit layout netlist as claimed in any of claims 1 to 7.
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