CN117849596A - Vector reduction-oriented distributed automatic test vector generation method and system - Google Patents

Abstract

The application discloses a vector reduction-oriented distributed automatic test vector generation method and a vector reduction-oriented distributed automatic test vector generation system. The system comprises: the method comprises the steps that a remote procedure is adopted to call a master node and a plurality of slave nodes of a GRPC framework, and the master node transmits test tasks to the slave nodes, wherein the test tasks comprise a to-be-tested fault subset; after the slave node utilizes the original test vector to perform fault simulation on the test task, a corresponding relation between the original test vector and the fault which can be detected is established to obtain a fault dictionary, all the original test vectors in the slave node are reduced by utilizing the fault dictionary in a mode of converting vector reduction into set coverage, the reduced fault dictionary and the test vectors are sent to the master node, the master node obtains a combined fault dictionary, and the test vectors of all the slave nodes are reduced by utilizing the combined fault dictionary to obtain the test vectors which are finally used, so that the technical problem that the distributed ATPG method in the related art can bring about expansion of the number of the test vectors is solved.

Description

Vector reduction-oriented distributed automatic test vector generation method and system

Technical Field

The application relates to the field of chip testing, in particular to a distributed automatic test vector generation method and system for vector reduction.

Background

This section is intended to provide a background or context for the matter recited in the claims or specification, which is not admitted to be prior art by inclusion in this section.

The conventional ATPG (i.e., automatic Test Pattern Generation) method relies mainly on test tools on a single computer to generate test vectors and apply them to each module of a chip to test the integrity of the chip. However, in handling large-scale test programs, a single computer is faced with limitations in test time and computational resources.

To address these challenges, the distributed ATPG method improves test efficiency by distributing test work over multiple computers, handling large-scale test programs, and reducing test time. The distributed automatic test vector generation method (i.e., distributed Automatic Test Pattern Generation) is an emerging technology for implementing chip-level integrated circuit testing. It is able to run large-scale test programs and process large-scale data simultaneously by utilizing the computing power of a computer cluster. The distributed ATPG method can improve the test efficiency, but it also causes a problem of expanding the number of test vectors.

In view of the above problems, no effective solution has been proposed at present.

Disclosure of Invention

The embodiment of the application provides a vector reduction-oriented distributed automatic test vector generation method and a vector reduction-oriented distributed automatic test vector generation system, which at least solve the technical problem that the distributed ATPG method in the related art can bring about expansion of the number of test vectors.

According to one aspect of the embodiments of the present application, there is provided a distributed automatic test vector generation system for vector reduction, including: the system comprises a master node and a plurality of slave nodes, wherein the master node and the plurality of slave nodes adopt a remote procedure call GRPC framework to realize communication between the master node and each slave node; the master node is used for: issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list; the slave nodes receive the simplified fault dictionary and test vectors, and combine the fault dictionaries of all the slave nodes to obtain a first fault dictionary; the method comprises the steps that through a mode of converting vector reduction into set coverage, test vectors of all slave nodes are reduced by using a first fault dictionary, and finally used target test vectors are obtained; each slave node is configured to: generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task; performing fault simulation on the fault to be tested by using the original test vector; after the test is completed, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary; and simplifying all original test vectors by utilizing a second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to a master node.

According to another aspect of the embodiments of the present application, there is further provided a method for generating a distributed automatic test vector for vector reduction, including: issuing test tasks to each slave node, wherein the test tasks comprise task identifications and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list; the slave nodes receive the simplified fault dictionary and test vectors, and combine the fault dictionaries of all the slave nodes to obtain a first fault dictionary; and simplifying the test vectors of all the slave nodes by using the first fault dictionary in a mode of converting vector reduction into set coverage to obtain the final target test vector.

Optionally, issuing the test task to each slave node includes: configuring a communication channel for each slave node, and establishing connection with the corresponding slave node by utilizing the configured communication channel; obtaining a fault list comprising all faults to be tested of the target chip from the netlist and the vector format file of the target chip by using a static learning method; dividing faults to be tested in the fault list to obtain a task list, wherein the task list comprises test tasks and task identifiers of the test tasks; and sending the netlist and the vector format file of the target chip to each slave node, and distributing the test tasks in the task list to each slave node in a concurrent mode.

Optionally, receiving the reduced fault dictionary and the test vector from the slave nodes, merging the fault dictionaries of all the slave nodes to obtain a first fault dictionary, including: summarizing the detected faults transmitted back from the nodes to obtain new detected faults in the detected faults obtained in the last time; under the condition that the number of the new test faults exceeds a preset threshold value, synchronizing the new test faults to all slave nodes; sending an indication of the end of the task to each slave node in the case that all tasks in the task list have been completed; and receiving the simplified fault dictionary and test vectors from the slave nodes, and combining the fault dictionaries of all the slave nodes to obtain a first fault dictionary.

Optionally, a set of all faults that can be detected by one test vector is taken as a second subset of faults, wherein the test vectors of all slave nodes are reduced by using a first fault dictionary in a mode of converting vector reduction into set coverage, so as to obtain a target test vector for final use, which comprises the following steps: selecting a plurality of second fault subsets meeting the following conditions from the second fault subsets corresponding to all the test vectors: the faults in the plurality of second fault subsets cover all faults in the fault list, and the number of subsets of the plurality of second fault subsets is minimal; and merging the test vectors corresponding to the plurality of second fault subsets to obtain a target test vector.

According to another aspect of the embodiments of the present application, there is further provided a method for generating a distributed automatic test vector for vector reduction, including: generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task; performing fault simulation on the fault to be tested by using the original test vector; after the test is completed, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary; and simplifying all original test vectors by utilizing a second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to a master node.

According to another aspect of the embodiments of the present application, there is further provided a device for generating a distributed automatic test vector for vector reduction, including: the issuing unit is used for issuing test tasks to each slave node, wherein the test tasks comprise task identifications and a first fault subset of the fault list, and the first fault subset comprises part of faults to be tested in the fault list; the merging unit is used for receiving the simplified fault dictionaries and the test vectors from the slave nodes, merging the fault dictionaries of all the slave nodes and obtaining a first fault dictionary; and the first simplifying unit is used for simplifying the test vectors of all the slave nodes by utilizing the first fault dictionary in a mode of converting vector simplification into set coverage to obtain the final used target test vector.

According to another aspect of the embodiments of the present application, there is further provided a device for generating a distributed automatic test vector for vector reduction, including: the generating unit is used for generating corresponding original test vectors for all faults to be tested in the first fault subset of the test task; the simulation unit is used for performing fault simulation on the fault to be tested by using the original test vector; the building unit is used for building a corresponding relation between each original test vector and the fault which can be detected after the test is completed, so as to obtain a second fault dictionary; and the second simplifying unit is used for simplifying all the original test vectors by utilizing the second fault dictionary in a mode of converting vector simplification into set coverage, and sending the simplified fault dictionary and the simplified test vectors to the master node.

According to another aspect of the embodiments of the present application, there is also provided a computer-readable storage medium including a stored program, which when run performs the above-described method.

According to another aspect of the embodiments of the present application, there is also provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the method described above by the computer program.

According to one aspect of the present application, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the steps of any of the embodiments of the method described above.

In an embodiment of the present application, a distributed automatic test vector generation system for vector reduction is provided, including: the system comprises a master node and a plurality of slave nodes, wherein the master node and the plurality of slave nodes adopt a remote procedure call GRPC framework to realize communication between the master node and each slave node; the master node is used for: issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list; the slave nodes receive the simplified fault dictionary and test vectors, and combine the fault dictionaries of all the slave nodes to obtain a first fault dictionary; the method comprises the steps that through a mode of converting vector reduction into set coverage, test vectors of all slave nodes are reduced by using a first fault dictionary, and finally used target test vectors are obtained; each slave node is configured to: generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task; performing fault simulation on the fault to be tested by using the original test vector; after the test is completed, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary; and simplifying all original test vectors by utilizing a second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to a master node. The scheme is based on vector reduction of a special set coverage problem solver, and performs two-stage vector reduction, so that a final reduced vector set is obtained, and the technical problem that the distributed ATPG method in the related technology can bring about expansion of the number of test vectors is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a schematic diagram of an alternative vector reduction oriented distributed automatic test vector generation system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an alternative fault dictionary and set coverage problem according to an embodiment of the present application;

FIG. 3 is a flow chart of an alternative vector reduction oriented distributed automatic test vector generation method according to an embodiment of the present application;

FIG. 4 is a flow chart of an alternative vector reduction oriented distributed automatic test vector generation method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an alternative vector reduction oriented distributed automatic test vector generation apparatus according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an alternative vector reduction oriented distributed automatic test vector generation apparatus according to an embodiment of the present application;

fig. 7 is a block diagram of a terminal according to an embodiment of the present application.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The Test Graph (Test Graph) is a Graph representation method used in chip testing, and is used for describing the relationship between the logic function and the Test point of the chip to be tested, and the Test Graph can help a Test engineer understand and analyze the Test requirement of the chip and guide Test tasks such as Test generation, fault simulation and the like. The test chart is usually a directed chart and can contain the following main elements:

logic Gates (Logic Gates): the logic gate is a basic logic element in the chip, such as an AND gate, an OR gate, an NOT gate and the like, and represents a logic function in the chip, and a node in the test chart usually corresponds to one logic gate;

signal Lines (Signal Lines): signal lines are used to pass signals between logic gates, and in the test pattern, the signal lines are generally represented as directed edges connecting the logic gate nodes;

test Points (Test Points): test points are special signal lines or logic gates on a chip for testing, and can be used for inputting test vectors, outputting test results or controlling a test process, and are usually represented as special nodes or marks in a test chart;

test requirements (Test Requirements): the test requirements describe the goals and requirements of testing the chip. The test requirements may include information such as logic paths, fault models, test coverage, etc. that need to be covered, and the test requirements may be defined according to specific test targets and expressed as specific nodes or marks in the test chart.

Through the test chart, a test engineer can know the logic structure of the chip, the signal transmission path and the positions of the test points, so as to guide the design of a test generation algorithm and the execution of fault simulation. The test chart can help a test engineer analyze the complexity of the test requirement, optimize the generation of the test vector and the efficiency of fault simulation, and finally improve the coverage rate and the reliability of the chip test.

The distributed ATPG method comprises the following steps:

1) Dividing a fault set to be tested: the fault set to be tested of the whole chip is split into a plurality of subsets, the basis of the division of the fault set to be tested is that the correlation between the two divided subsets is small enough (the difficulty level of the fault set measured by the same test vector set is measured), the common fault division method has the advantages that the fault division effect is greatly influenced by different division methods according to the level division of the circuit, the input division of the circuit and the like.

2) Generating a test vector: the split fault subsets to be tested are respectively transmitted to a plurality of sub-nodes, parallel test vector generation tasks are carried out by the plurality of sub-nodes, and test vectors are generated according to design specifications and other rules and are used for testing circuits in each sub-test chart.

3) Aggregating test vectors: the generated test vectors are combined together to form a test set for chip testing.

The inventors have recognized through extensive analysis of the distributed ATPG method that it is capable of generating and processing test vectors on a large scale and significantly reducing test time, thereby improving test efficiency, as compared with the conventional ATPG method. Although improving the test efficiency, it also causes a problem of expansion in the number of test vectors due to the influence of the segmentation and aggregation steps in the distributed ATPG method.

First, in the process of dividing the set of faults to be tested, the set of faults to be tested of the whole chip is divided into a plurality of sub-sets of faults. Each sub-fault set needs to be tested independently, which requires the generation of a corresponding test vector. Since each sub-fault set is only a portion of the entire chip test pattern to be tested, the number of test vectors generated for each sub-fault set is much less than the number of test vectors generated for the entire chip test pattern.

However, since the generated test vectors can detect faults in other sub-fault sets in the process of generating vectors for different sub-fault sets, redundancy is generated in the generation of the test vectors of the distributed ATPG, which is why the test vectors expand (i.e. multiple test vectors are generated for the same group of faults between single machine multiple threads, resulting in redundancy calculation).

In order to solve the problem, the application provides a vector reduction-oriented distributed automatic test vector generation system, which converts a test vector reduction problem into a set coverage problem by establishing a corresponding relation between a vector generated by a fault dictionary description ATPG algorithm and a fault which can be detected, solves the problem by using a special set coverage solver, reduces redundant vectors, and solves the problem of vector expansion of distributed ATPG.

As shown in fig. 1, the system includes:

a master node 101 and a plurality of slave nodes 103 (the nodes may be a single computer device or a cluster), and the master node and the plurality of slave nodes use a remote procedure call GRPC framework to implement communications between the master node and each slave node;

the master node is used for: issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list; the slave nodes receive the simplified fault dictionary and test vectors, and combine the fault dictionaries of all the slave nodes to obtain a first fault dictionary; the method comprises the steps that through a mode of converting vector reduction into set coverage, test vectors of all slave nodes are reduced by using a first fault dictionary, and finally used target test vectors are obtained;

Each slave node is configured to: generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task; performing fault simulation on the fault to be tested by using the original test vector; after the test is completed, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary; and simplifying all original test vectors by utilizing a second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to a master node.

The inventors found during the course of the study that in the test set, each test vector could detect a part of the faults in the fault set, and the static compaction problem of the test vector was converted into the set coverage problem by converting the faults that each test vector could detect into a subset of faults, with the goal of finding a set of subsets of faults, so that each fault in the fault list is covered at least once, while minimizing the number of subsets of faults that need to be contained, also the number of vectors.

As shown in fig. 2, a fault dictionary (i.e., a second fault dictionary) is established at the slave node (the master node is similar to the master node) to describe a one-to-one correspondence between faults and vectors, and in fig. 2, there are 5 faults, 4 vectors, and thus, f1 represents a set of test vectors including: { p1, p4}, because the test vector is 1 and the value on bit 1 and 4 is 1. Similarly, f2 represents a set containing the following test cases: { p3}, f3 represents a set containing the following test cases: { p3}, f4 represents a set containing the following test cases: { p2, p4}, f5 represents a set containing the following test cases: { p1, p2, p4}.

Now, it is necessary to find a set of sets that contains at least once each fault, while minimizing the number of sets used, i.e. the number of vectors. This is a typical aggregate coverage problem.

The problem is an NP-hard problem that can be solved using either an approximation algorithm or a heuristic algorithm. Common solutions include greedy algorithms, approximation algorithms, and algorithms based on integer programming. The special set coverage problem solver, such as a Pure MaxSAT (Pure Maximum Satisfiability) solver, can also be directly adopted, and has better solving effect and higher solving speed.

Pure MaxSAT refers to a constraint condition that a problem is represented by two different types of logical clauses, namely a hard clause and a soft clause, in a boolean expression, and the aim is to maximize or minimize the number of soft clauses to be satisfied on the premise of satisfying the hard clause. The truth assignment of the variables must satisfy all the Hard Clauses (Hard Clauses are the basic constraint in the problem, must be satisfied, if a Hard clause cannot be satisfied, then the solution is invalid, a Hard clause usually contains constraints related to the nature of the problem, which are essential to the legal solution of the problem) and maximize or minimize the satisfaction of the Soft Clauses (Soft Clauses are optional constraint in the problem, they do not have to satisfy, the objective of Soft MaxSAT is to satisfy as many Soft Clauses as possible on the premise of satisfying the Hard Clauses, each Soft clause has an associated weight representing its importance or cost, the objective is to find a solution such that the sum of weights of the satisfied Soft Clauses is maximized, or the sum of weights of the satisfied Soft Clauses is minimized, depending on whether the problem is maximized or minimized.

The vector expansion problem brought by the distributed ATPG framework is relieved by the vector reduction-oriented distributed automatic test vector generation method.

FIG. 3 is a flowchart of an alternative method for generating a distributed automatic test vector for vector reduction, applied to a master node, according to an embodiment of the present application, and as shown in FIG. 3, the method may include the following steps:

step S302, issuing test tasks to each slave node, wherein the test tasks comprise task identifications and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list.

Specifically, a communication channel can be configured for each slave node, and connection is established between the configured communication channel and the corresponding slave node; obtaining a fault list comprising all faults to be tested of the target chip from the netlist and the vector format file of the target chip by using a static learning method; dividing faults to be tested in the fault list to obtain a task list, wherein the task list comprises test tasks and task identifiers of the test tasks; and sending the netlist and the vector format file of the target chip to each slave node, and distributing the test tasks in the task list to each slave node in a concurrent mode.

The basic idea of static learning methods is to statically model the structure of a circuit without performing fault simulation, for example, by analyzing the circuit structure and logic relationships, then analyzing the circuit to be tested, including logic gates, signal paths, circuit structures, etc., and then determining the points or portions of faults to be tested, once the points of faults to be tested are identified, the static learning method will attempt to statically generate test patterns to cover those faults, unlike traditional dynamic learning methods, which generally require fault simulation to generate test patterns, the goal of the static learning method is to determine test patterns in advance, thereby saving computational resources and time, and in some cases improving test coverage.

And step S304, receiving the simplified fault dictionary and the test vectors from the slave nodes, and combining the fault dictionaries of all the slave nodes to obtain a first fault dictionary.

The detected faults transmitted back from the nodes can be summarized first to obtain new detected faults (i.e. faults different from the historical detected faults) in the detected faults obtained last time; under the condition that the number of the new test faults exceeds a preset threshold (such as 10), synchronizing the new test faults to all slave nodes; in the event that all tasks in the task list have been completed, an indication of the end of the task is sent to each slave node. The method comprises the steps of receiving simplified fault dictionaries and test vectors from slave nodes, merging fault dictionaries of all the slave nodes to obtain a first fault dictionary, specifically, for each slave node, transmitting a simplified fault dictionary (namely, the simplified fault dictionary is obtained on the basis of a second fault dictionary, the correspondence between the test vectors of the slave nodes and the detectable faults is represented, the detectable faults cover all faults of the slave nodes), and merging the fault dictionaries transmitted by all the slave nodes to obtain the first fault dictionary.

And step S306, simplifying the test vectors of all the slave nodes by using the first fault dictionary in a mode of converting vector reduction into set coverage to obtain a target test vector which is finally used.

Selecting a plurality of second fault subsets meeting the following conditions from the second fault subsets corresponding to all the test vectors: the faults in the plurality of second fault subsets cover all faults in the fault list, and the number of subsets of the plurality of second fault subsets is minimal; and merging the test vectors corresponding to the plurality of second fault subsets to obtain a target test vector.

The static reduced problem of the test vector is converted into a set coverage problem, and the detailed implementation process of solving by using a Pure MaxSAT solver is as follows:

the inputs and outputs of the problem are determined, and the inputs of the Pure MaxSAT solver are: a fault set and a test vector set, wherein the fault set contains all faults and the test vector set contains all test vectors; the formula output is: a set of subsets, wherein each subset corresponds to a test vector, and a union of subsets covers a failure set.

The Hard clause (Hard classes) is a condition that must be satisfied, and if it is not satisfied, the problem is solved, and in the static compaction problem of the test vector, the function of the Hard clause is to ensure that the following condition is satisfied: each fault must be covered by at least one test vector;

Soft Clauses (Soft classes) are optional conditions for optimizing the objective function, in the static compaction problem of test vectors, the role of Soft Clauses is to help optimize the following objectives: minimizing the number of subsets that need to be included: by adding soft clauses, the objective function is set to minimize the number of selected test vectors, so that the number of required test vectors can be reduced as much as possible on the premise of meeting the requirement of hard clauses, and static reduction of the test vector set is realized.

By combining the hard clauses and the soft clauses, the static compaction problem of the test vector can be converted into a Pure MaxSAT problem, and the Pure MaxSAT solver is used for solving. The hard clause ensures that the basic constraints of the problem are satisfied, while the soft clause is used to optimize the objective function to obtain a minimized set of test vectors.

Solving the problem using the Pure MaxSAT solver: the converted Pure MaxSAT problem is input into a Pure MaxSAT solver, the solver tries to find a solution of a minimized objective function meeting the constraint condition, and an output result of the solver, namely a set of minimized test vectors meeting the constraint condition, is obtained.

In the technical solution of the present application, each test vector in the test set can detect a part of faults in the total fault set (i.e. the fault list), which means that each test vector has a certain fault coverage capability, can excite and detect certain faults, based on this characteristic, static reduced problems of the test vectors can be converted into set coverage problems, specifically, the faults which can be detected by each test vector can be regarded as a fault subset instead of the whole test vector as a set, so that a mapping relationship (i.e. a second fault dictionary) between the test vector and the fault subset (including all faults which can be detected by the test vector) is established, and then, the objective is to find a group of fault subsets, so that each fault in the fault set is covered at least once, and at the same time, the number of subsets which need to be contained is minimized, because the number of subsets and the test vector are in one-to-one correspondence, that is, the number of test vectors which need to be minimized. The benefit of this conversion is that by converting the fault coverage capability of each test vector into a subset of faults, aggregate coverage can be performed at a finer granularity, and various algorithms, such as heuristic, greedy, or approximation algorithms, can be employed to solve the problem of aggregate coverage after this conversion. These algorithms will take into account the selection strategy of the subset of faults and the coverage situation of the faults, build up the coverage set step by step until all faults are covered or a stop condition is reached. Eventually a set of smallest subsets of faults can be found such that each fault in the set of faults is covered at least once. The static compaction problem of the test vector is converted into the set coverage problem, and an appropriate algorithm is applied to solve the problem, so that the minimum fault subset can be effectively selected to meet the fault coverage requirement. The method can improve the test efficiency and optimize the utilization of the test resources, and simultaneously reduce the test time and cost.

FIG. 4 is a flowchart of an alternative method of generating a distributed automatic test vector for vector reduction, applied to a slave node, as shown in FIG. 4, according to an embodiment of the present application, the method may include the steps of:

step S402, generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task;

and S404, performing fault simulation on the fault to be tested by using the original test vector.

Step S406, after the work is completed, a corresponding relation between each original test vector and the fault which can be detected is established, and a second fault dictionary is obtained.

Specifically: and taking the set of all faults which can be detected by one test vector on the slave node as a third fault subset, and establishing a corresponding relation between the test vector and the third fault subset so as to obtain a second fault dictionary.

In step S408, all the original test vectors are reduced by using the second fault dictionary in a manner of converting vector reduction into set coverage, and the reduced fault dictionary and test vectors are sent to the master node.

Specifically, a plurality of third failure subsets satisfying the following conditions are selected from the third failure subsets corresponding to the test vectors of all the slave nodes: the faults in the third plurality of fault subsets cover all faults in the first subset of faults (i.e., all faults that the slave node needs to handle), and the number of subsets of the third plurality of fault subsets is minimal. Thereby obtaining a reduced fault dictionary (only the mapping relation between the reduced third fault subsets and the corresponding test vectors is reserved), and sending the reduced fault dictionary (which naturally comprises the reduced test vectors) to the master node.

The implementation in the embodiment shown in fig. 4 is the same as that in the previous embodiment, and will not be repeated here.

As an alternative example, the technical solution of the present application is further described in the following in conjunction with the following detailed description:

the distributed ATPG framework adopted by the method uses the GRPC framework to realize communication between the Master and the Slave. Master initializes state and configures GRPC channel, and establishes connection with each Slave. Master reads and parses the netlist and vector format files and creates a fault list, which is then divided into task lists. Master transmits files to each Slave concurrently, and the Slave parses the netlist and the vector format file and builds a fault list. Master is tasked with each Slave, the Slave generates test vectors and performs fault simulation, and then the tested faults are returned to the Master. The Master collects the measured faults returned by the Slave and counts the new measured faults in the measured faults. If the number of the new test faults is larger than the threshold value, the Master synchronizes all the new test faults to each Slave, and the Slave updates a fault list. And when the Master detects that all tasks are completed, sending out an end signal, terminating service by the Slave, and stopping operation of the Master after all the Slave ends.

In addition to the distributed ATPG framework, a vector reduction module is added, and a module schematic diagram of the whole framework is shown in fig. 1:

The Master module is functionally differentiated and may comprise the following sub-modules:

1) Initialization and task division module:

first, the Master module needs to initialize its state and configure the channel of the distributed programming framework GPRC, including the channel maximum transmission message size and the channel identification id. The Master module then needs to create a connection with each Slave. The Master module then reads and parses the netlist and vector format files. If the static learning method in ATPG is started, the Master module needs to set parameters of static learning and run the static learning. The Master module then creates a fault list and divides it into task lists, each task consisting of a subset of task ids and fault lists. Thus, initialization of the Master-related data structures is complete.

2) Task allocation and result reclamation:

the Master module transmits the netlist and the vector format file to each Slave end concurrently, after the transmission is completed, the Slave ends start to analyze the netlist and the vector format file, and the Master blocks to wait for the completion of all Slave ends. The Master module would then assign a task to each Slave from the task list. Once the Slave obtains the task, test vector generation is performed according to a fault list in the task, and then fault simulation is performed. The Slave collects faults marked as detected in the simulation result and returns the faults to the Master. Thereafter, the Master aggregates the measured faults returned by the Slave and counts the new measured faults therein. If the number of new test faults exceeds the threshold, the Master synchronizes all new test faults to each Slave in the next task assignment, and the Slave updates its own fault list. When the Master detects that all tasks are completed, it will send out an end signal and stop running after all Slave ends.

3) The global vector reduction module:

after all batches of ATPG are executed by the Slave, the vectors are summarized to the Master uniformly and are input to the global vector reduction module. This module is used to reduce the number of test vectors and test time by simplifying the test vectors generated by all the Slave devices. The module needs to aggregate all test vectors, then operates a machine word parallel fault simulation algorithm, establishes a corresponding relation between each vector and the fault which can be detected according to the detectability of each fault, namely a fault dictionary, and then uses a Pure MaxSAT solver which is used for solving the problem of set coverage, converting the fault dictionary into an input format file of the Pure MaxSAT solver, and finally obtaining a reduced test vector set, wherein the fault coverage of the reduced test vector set does not have any loss.

The fault coverage problem is converted into a Pure MaxSAT problem. The following is how Pure MaxSAT and related concepts are used to solve this problem:

assume we have the set of faults and test vectors shown in fig. 2:

fault set: { f1, f2, f3, f4, f5};

test vector set: { p1, p2, p3, p4};

the goal is to find a set of fault subsets such that each fault in the fault set is covered at least once while minimizing the number of subsets that need to be included, i.e. minimizing the number of test vectors that are needed.

For example, the following steps may be performed:

3.1 Defining variables:

for each test vector, a boolean variable is defined, indicating whether the vector is selected for use, and p1, p2, p3, p4 may be used to represent these variables.

3.2 Building a soft clause:

for each test vector, a soft clause is created to indicate whether this vector should be reduced.

For all test vectors and faults in the example, the following soft clause (symbol "¬" corresponds to logic gate not) may be constructed:

¬ p1

¬ p2

¬ p3

¬ p4

3.3 Building a hard clause):

for each fault, a hard clause is created that contains the variable (i.e., vector) that detected the fault. For example, the fault f1 can be detected by the vectors p1, p4, and thus the clause p1 v p4 (meaning that the mathematical logic symbol "ζ" is and meaning that the "v" is or meaning) is created.

For all faults in the example, the following hard clauses (assignment of corresponding faults f1 to f 5) may be constructed:

p1 ∨ p4，

p3，

p3，

p2 ∨ p4，

p1 ∨ p2 ∨ p4。

3.4 Defining an objective function:

an objective function is defined that aims at minimizing the number of subsets required, i.e. the number of test vectors required. The objective function may be defined as p1+p2+p3+p4.

3.5 A Pure MaxSAT formula is constructed:

The soft clause and the hard clause are combined into a boolean formula. While adding the objective function to the formula.

An example MaxSAT formula may be expressed as:

(p1 ∨ p4) ∧ p3 ∧ p3 ∧ (p2 ∨ p4) ∧ (p1 ∨ p2 ∨ p4)，

objective function: p1+p2+p3+p4.

3.6 Solving the MaxSAT problem:

the boolean formula is solved using a MaxSAT solver.

The solver will try to find a solution that satisfies as many soft clauses as possible, i.e. prunes away more test vectors, and satisfies all hard clauses.

By solving the MaxSAT problem, a minimum subset that meets the coverage requirement can be obtained, and each fault in these subsets is covered at least once. At the same time, by minimizing the number of test vectors required, we can minimize the cost and time of testing.

3.7 Finally generated test vector and test report:

finally, the Master module generates test vectors and test reports. The test vector is used for testing the correctness of the circuit, and the test report can be used for evaluating the effect and quality of the test, wherein the test report comprises key indexes such as fault coverage rate, test vector number, test period and the like.

The Slave module comprises the following sub-modules:

1) Receiving a Master assigned sub-fault list:

in the Slave module, it needs to receive the Master-allocated sub-fault list in batches and perform the ATPG process according to this list. While the Master will assign some of the ATPG algorithm initialization parameters for initializing the ATPG.

2) ATPG is performed:

once the Slave receives the tasks allocated by the Master, it generates test vectors according to the fault list in the tasks, and then performs fault simulation. The Slave collects faults marked as detected in the simulation result and returns the faults to the Master.

3) Local vector reduction module of Slave module:

vectors generated after each batch of ATPG is executed are temporarily reserved in the Slave, and after all batches of tasks in the sub-fault list are executed, the Slave collects all locally generated vectors and inputs the locally generated vectors to a local vector reduction module of the Slave module. The composition of the module is consistent with that of the global vector reduction module, a Pure MaxSAT solver is adopted, a machine word parallel fault simulation is used for establishing a fault dictionary, only the local vector reduction module performs preliminary reduction on the locally generated vector of each Slave, and the reduced vector set and the fault dictionary thereof return to a Master for further global reduction.

The application provides a vector reduction module based on a special set coverage problem solver outside a distributed ATPG framework for carrying out two-stage vector reduction, so as to obtain a final reduced vector set. The first key point of the method is that a vector reduction module based on a special set coverage problem solver is provided, a fault dictionary is established through fault simulation, the vector reduction problem is converted into a set coverage problem, then the set coverage problem is solved by using a Pure MaxSAT solver, and the number of generated vectors can be reduced on the premise of maintaining the fault coverage rate of the distributed ATPG system. The second key point is to provide a two-stage vector reduction mechanism, the scale of the fault dictionary is large, after ATPG is executed, the fault dictionary needs to be transmitted back to the Master for summarizing and then reduction, and in order to save network transmission time in the distributed system, the fault dictionary after local reduction is transmitted back to the Master for global reduction after local reduction is carried out at the Slave end.

The method is verified on a large-scale commercial RISCV reference circuit, the performance of the test vector generation method is comprehensively evaluated, and compared with a distributed ATPG frame without a vector reduction module, the method can obtain a more reduced vector set.

It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method described in the embodiments of the present application.

According to another aspect of the embodiments of the present application, there is further provided a vector reduction-oriented distributed automatic test vector generation apparatus for implementing the vector reduction-oriented distributed automatic test vector generation method. FIG. 5 is a schematic diagram of an alternative vector reduction oriented distributed automatic test vector generation apparatus according to an embodiment of the present application, as shown in FIG. 5, the apparatus may include:

a issuing unit 501, configured to issue a test task to each slave node, where the test task includes a task identifier and a first failure subset of the failure list, and the first failure subset includes a part of failures to be tested in the failure list;

a merging unit 503, configured to receive the reduced fault dictionaries and test vectors from the slave nodes, merge the fault dictionaries of all the slave nodes, and obtain a first fault dictionary;

the first compacting unit 505 is configured to compact the test vectors of all the slave nodes by using the first fault dictionary in a manner of converting vector compaction into set coverage, so as to obtain a target test vector for final use.

Optionally, the issuing unit is further configured to: configuring a communication channel for each slave node, and establishing connection with the corresponding slave node by utilizing the configured communication channel; obtaining a fault list comprising all faults to be tested of the target chip from the netlist and the vector format file of the target chip by using a static learning method; dividing faults to be tested in the fault list to obtain a task list, wherein the task list comprises test tasks and task identifiers of the test tasks; and sending the netlist and the vector format file of the target chip to each slave node, and distributing the test tasks in the task list to each slave node in a concurrent mode.

Optionally, the merging unit is further configured to: summarizing the detected faults transmitted back from the nodes to obtain new detected faults in the detected faults obtained in the last time; under the condition that the number of the new test faults exceeds a preset threshold value, synchronizing the new test faults to all slave nodes; sending an indication of the end of the task to each slave node in the case that all tasks in the task list have been completed; and receiving the simplified fault dictionary and test vectors from the slave nodes, and combining the fault dictionaries of all the slave nodes to obtain a first fault dictionary.

Optionally, the first reduction unit is further configured to select, from the second failure subsets corresponding to all the test vectors, a plurality of second failure subsets satisfying the following conditions, using a set of all failures that can be detected by one test vector as the second failure subset: the faults in the plurality of second fault subsets cover all faults in the fault list, and the number of subsets of the plurality of second fault subsets is minimal; and merging the test vectors corresponding to the plurality of second fault subsets to obtain a target test vector.

According to another aspect of the embodiments of the present application, there is further provided a vector reduction-oriented distributed automatic test vector generation apparatus for implementing the vector reduction-oriented distributed automatic test vector generation method. FIG. 6 is a schematic diagram of an alternative vector reduction oriented distributed automatic test vector generation apparatus according to an embodiment of the present application, as shown in FIG. 6, the apparatus may include:

A generating unit 601, configured to generate a corresponding original test vector for each fault to be tested in the first subset of faults of the test task;

the simulation unit 603 is configured to perform fault simulation on the fault to be tested by using the original test vector;

a building unit 605, configured to build a correspondence between each original test vector and a detectable fault after the test is completed, so as to obtain a second fault dictionary;

the second reduction unit 607 is configured to reduce all original test vectors by using the second fault dictionary in a manner of converting vector reduction into set coverage, and send the reduced fault dictionary and test vectors to the master node.

It should be noted that the above modules are the same as examples and application scenarios implemented by the corresponding steps, but are not limited to what is disclosed in the above embodiments. It should be noted that the above modules may be implemented in software or in hardware as part of the apparatus shown in fig. 1, where the hardware environment includes a network environment.

According to another aspect of the embodiments of the present application, a server or a terminal for implementing the above-mentioned vector reduction-oriented distributed automatic test vector generation method is also provided.

Fig. 7 is a block diagram of a terminal according to an embodiment of the present application, and as shown in fig. 7, the terminal may include: one or more (only one is shown in the figure) processors 701, memory 703, and transmission means 705, as shown in fig. 7, the terminal may further comprise an input output device 707.

The memory 703 may be used to store software programs and modules, such as program instructions/modules corresponding to the method and apparatus for generating a vector-oriented reduced distributed automatic test vector in the embodiments of the present application, and the processor 701 executes various functional applications and data processing by running the software programs and modules stored in the memory 703, thereby implementing the method for generating a vector-oriented reduced distributed automatic test vector. The memory 703 may include high speed random access memory, but may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory. In some examples, the memory 703 may further include memory located remotely from the processor 701, which may be connected to the terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 705 is used for receiving or transmitting data via a network, and may also be used for data transmission between a processor and a memory. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 705 includes a network adapter (Network Interface Controller, NIC) that may be connected to other network devices and routers via a network cable to communicate with the internet or a local area network. In one example, the transmission device 705 is a Radio Frequency (RF) module for communicating with the internet wirelessly.

Among them, the memory 703 is used to store, in particular, application programs.

The processor 701 may call an application program stored in the memory 703 through the transmission means 705 to perform the steps of:

issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list; establishing a corresponding relation between the test vector received from the slave node and the fault which can be detected, and obtaining a first fault dictionary; and simplifying all the test vectors of the slave nodes by utilizing the first fault dictionary in a mode of converting vector reduction into set coverage to obtain a target test vector which is finally used.

The processor 701 is further configured to perform the steps of:

generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task; performing fault simulation on the fault to be tested by using the original test vector; after the test is completed, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary; and simplifying all the original test vectors by utilizing the second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to a master node.

Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the structure shown in fig. 7 is only illustrative, and the terminal may be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a palmtop computer, a mobile internet device (Mobile Internet Devices, MID), a PAD, etc. Fig. 7 is not limited to the structure of the electronic device. For example, the terminal may also include more or fewer components (e.g., network interfaces, display devices, etc.) than shown in fig. 7, or have a different configuration than shown in fig. 7.

Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be implemented by a program for instructing a terminal device to execute in association with hardware, the program may be stored in a computer readable storage medium, and the storage medium may include: flash disk, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), magnetic or optical disk, and the like.

Embodiments of the present application also provide a storage medium. Alternatively, in this embodiment, the storage medium may be used to execute the program code of the distributed automatic test vector generation method for vector reduction.

Alternatively, in this embodiment, the storage medium may be located on at least one network device of the plurality of network devices in the network shown in the above embodiment.

Alternatively, in the present embodiment, the storage medium is configured to store program code for performing the steps of:

issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list; establishing a corresponding relation between the test vector received from the slave node and the fault which can be detected, and obtaining a first fault dictionary; and simplifying all the test vectors of the slave nodes by utilizing the first fault dictionary in a mode of converting vector reduction into set coverage to obtain a target test vector which is finally used.

Optionally, the storage medium is further arranged to store program code for performing the steps of:

generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task; performing fault simulation on the fault to be tested by using the original test vector; after the test is completed, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary; and simplifying all the original test vectors by utilizing the second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to a master node.

Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments, and this embodiment is not described herein.

Alternatively, in the present embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The integrated units in the above embodiments may be stored in the above-described computer-readable storage medium if implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause one or more computer devices (which may be personal computers, servers or network devices, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

In several embodiments provided in the present application, it should be understood that the disclosed client may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, such as the division of the units, is merely a logical function division, and may be implemented in another manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.

Claims (10)

1. A vector reduction oriented distributed automatic test vector generation system, comprising:

the system comprises a master node and a plurality of slave nodes, wherein the master node and the plurality of slave nodes adopt remote procedure call GRPC frames to realize communication between the master node and each slave node;

The master node is configured to: issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list; receiving the simplified fault dictionary and test vectors from the slave nodes, and merging all the fault dictionaries of the slave nodes to obtain a first fault dictionary; the method comprises the steps of simplifying all test vectors of the slave nodes by utilizing the first fault dictionary in a mode of converting vector simplification into set coverage, so as to obtain a target test vector which is finally used;

each of the slave nodes is configured to: generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task; performing fault simulation on the fault to be tested by using the original test vector; after the test is completed, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary; and simplifying all the original test vectors by utilizing the second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to the master node.

2. A method for generating a distributed automatic test vector for vector reduction, which is applied to the master node in claim 1, and comprises the following steps:

issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list;

receiving the simplified fault dictionary and test vectors from the slave nodes, and merging all the fault dictionaries of the slave nodes to obtain a first fault dictionary;

and simplifying all the test vectors of the slave nodes by utilizing the first fault dictionary in a mode of converting vector reduction into set coverage to obtain a target test vector which is finally used.

3. The method of claim 2, wherein issuing test tasks to each of the slave nodes comprises:

configuring a communication channel for each slave node, and establishing connection with the corresponding slave node by utilizing the configured communication channel;

obtaining the fault list comprising all faults to be tested of the target chip from a netlist and a vector format file of the target chip by using a static learning method;

Dividing faults to be detected in the fault list to obtain a task list, wherein the task list comprises a test task and a task identifier of the test task;

and sending the netlist and the vector format file of the target chip to each slave node, and distributing the test tasks in the task list to each slave node in a concurrent mode.

4. The method of claim 2, wherein receiving the reduced fault dictionary and test vectors from the slave nodes, merging all of the fault dictionaries of the slave nodes to obtain a first fault dictionary, comprises:

summarizing the detected faults transmitted back from the nodes to obtain new detected faults in the detected faults obtained in the last time;

synchronizing the new test faults to all the slave nodes under the condition that the number of the new test faults exceeds a preset threshold value;

sending an indication of the end of the task to each slave node in the case that all tasks in the task list have been completed;

and receiving the simplified fault dictionary and test vectors from the slave nodes, and merging all the fault dictionaries of the slave nodes to obtain the first fault dictionary.

5. The method according to claim 2, wherein the set of all faults that can be detected by one test vector is taken as a second subset of faults, and wherein the first fault dictionary is used to reduce the test vectors of all the slave nodes in a manner of converting vector reduction into set coverage, so as to obtain a target test vector for end use, and the method comprises:

selecting a plurality of second fault subsets meeting the following conditions from the second fault subsets corresponding to all the test vectors: the faults in the plurality of second fault subsets cover all faults in the fault list, and the number of subsets of the plurality of second fault subsets is minimal;

and merging the test vectors corresponding to the plurality of second fault subsets to obtain the target test vector.

6. A method for generating a distributed automatic test vector for vector reduction, which is applied to the slave node in claim 1, and comprises the following steps:

generating corresponding original test vectors for each fault to be tested in the first fault subset of the test task;

performing fault simulation on the fault to be tested by using the original test vector;

after completion, establishing a corresponding relation between each original test vector and the fault which can be detected, and obtaining a second fault dictionary;

And simplifying all the original test vectors by utilizing the second fault dictionary in a mode of converting vector reduction into set coverage, and transmitting the simplified fault dictionary and test vectors to a master node.

7. A distributed automatic test vector generation device for vector reduction, which is applied to the master node in claim 1, and comprises:

the issuing unit is used for issuing a test task to each slave node, wherein the test task comprises a task identifier and a first fault subset of a fault list, and the first fault subset comprises part of faults to be tested in the fault list;

the merging unit is used for receiving the simplified fault dictionary and the test vector from the slave nodes, merging all the fault dictionaries of the slave nodes and obtaining a first fault dictionary;

and the first simplifying unit is used for simplifying the test vectors of all the slave nodes by utilizing the first fault dictionary in a mode of converting vector simplification into set coverage to obtain the final used target test vector.

8. A distributed automatic test vector generation device for vector reduction, which is applied to the slave node in claim 1, and comprises:

The generating unit is used for generating corresponding original test vectors for all faults to be tested in the first fault subset of the test task;

the simulation unit is used for performing fault simulation on the fault to be tested by using the original test vector;

the establishing unit is used for establishing a corresponding relation between each original test vector and the fault which can be detected after the test is completed, so as to obtain a second fault dictionary;

and the second simplifying unit is used for simplifying all the original test vectors by utilizing the second fault dictionary in a mode of converting vector simplification into set coverage, and sending the simplified fault dictionary and test vectors to the master node.

9. A computer readable storage medium, characterized in that the storage medium comprises a stored program, wherein the program when run performs the method of any of the preceding claims 2 to 6.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor performs the method according to any of the preceding claims 2 to 6 by means of the computer program.