CN117836843A - Light emitting diode display device and driving method thereof - Google Patents

Light emitting diode display device and driving method thereof Download PDF

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Publication number
CN117836843A
CN117836843A CN202280049584.4A CN202280049584A CN117836843A CN 117836843 A CN117836843 A CN 117836843A CN 202280049584 A CN202280049584 A CN 202280049584A CN 117836843 A CN117836843 A CN 117836843A
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China
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transistor
light emitting
emitting diode
digital
signal
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CN202280049584.4A
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Chinese (zh)
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金范植
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Yashi Electronic Technology Co ltd
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Yashi Electronic Technology Co ltd
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Priority claimed from KR1020220076210A external-priority patent/KR20230011229A/en
Application filed by Yashi Electronic Technology Co ltd filed Critical Yashi Electronic Technology Co ltd
Priority claimed from PCT/KR2022/009174 external-priority patent/WO2023287065A1/en
Publication of CN117836843A publication Critical patent/CN117836843A/en
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Abstract

The invention provides a light emitting diode display device, which comprises: a display panel including a plurality of pixels; light emitting diodes disposed in each configuration; a first transistor connected between the light emitting diode and a light emitting high potential voltage, one of N-type and P-type; and a light emitting diode display device connected between the light emitting diode and the light emitting low potential voltage and including a second transistor which is the other of the N-type and the P-type.

Description

Light emitting diode display device and driving method thereof
Technical Field
The present invention relates to a light emitting diode display device, and more particularly, to a light emitting diode display device including pixels having N-type transistors and P-type transistors and a driving method thereof.
Background
The organic light emitting diode display device (Organic light emitting diode display device) or the micro light emitting diode display device (Micro light emitting diode display device) is formed of one of an N-type transistor and a P-type transistor as a pixel, thereby saving manufacturing cost.
However, there is a problem in that a change in the power supply voltage or the like may cause a change in characteristics or other operation restrictions.
Fig. 1 is a schematic diagram showing one pixel of an organic light emitting diode display device according to a first example of the present invention, and fig. 2 is a waveform diagram (waveform diagram) showing signals utilized in the organic light emitting diode display device according to the first example of the present invention.
As shown in fig. 1, one pixel (P) of the organic light emitting diode display device according to the first example of the present invention includes P-type first to seventh transistors (M1 to M7), a first Capacitor (C1), and a light emitting diode (Del).
The 1 st transistor (M1) switches (swiping) the connection between the high potential voltage (EVDD) and the 1 st capacitor (C1) and the 2 nd and 4 th transistors (M2, M4) according to the light emission signal (EM), and the 2 nd transistor (M2) switches (swiping) the connection between the DATA signal (DATA) and the 1 st and 4 th transistors (M1, M4) according to the N-th GATE signal (GATE (N)).
The 3 rd transistor (M3) switches (swaying) the connection between the first capacitor (C1), the 4 th and 5 th transistors (M4, M5) and the initialization Voltage (VINT) and the 5 th transistor (M7) according to the first (N-1) GATE signal (GATE (N-1)),
the 4 th transistor (M4) switches (swaying) the connection between the 1 st and 2 nd transistors (M1, M2) and M5 and M6 according to the voltage of the connection node of the 1 st capacitor (C1), 3 rd and 5 th transistors (M3, M5).
The 5 th transistor (M5) switches (swaying) the connection between the 1 st capacitor (C1), the 3 rd and 4 th transistors (M3, M4) and the 4 th and 6 th transistors (M4, M6) according to the N GATE signal (GATE (N)),
the 6 th transistor (M6) switches (swaying) the connection between the 4 th and 5 th transistors (M4, M5) and the light emitting diode (Del) according to the light emitting signal (EM).
The 7 th transistor (M7) switches (switches) the connection between the initialization Voltage (VINT) and the 3 rd transistor (M3) and the light emitting diode (Del) according to the nth GATE signal (GATE (N)).
The 1 st electrode of the 1 st capacitor (C1) is connected to the high potential voltage (EVDD) and the 1 st transistor (M1), and the 2 nd electrode of the 1 st capacitor (C1) is connected to the 3 rd, 4 th and 5 th transistors (M3, M4, M5).
The positive electrode of the light emitting diode (Del) is connected to the 6 th and 7 th transistors (M6, M7), and the negative electrode of the light emitting diode (Del) is connected to the low potential voltage (EVSS).
As shown in fig. 2, the DATA signal (DATA) has an active (valid) interval per frame, the (N-1) th GATE signal (GATE (N-1)) has a low level during an initialization interval (Tin) corresponding to an active interval of a previous frame of the DATA signal (DATA),
the nth GATE signal (GATE (N)) has a low level during a sensing and programming interval (Tsp) corresponding to an active interval of a current frame of the DATA signal (DATA), and the light-emitting signal (EM) has a low level during a corresponding light-emitting interval (Tem) after an active interval of a next frame of the DATA signal (DATA).
Therefore, during the initialization interval (Tin), the 3 rd transistor (M3) is switched (turn-on), and the initialization Voltage (VINT) is charged to the 1 st capacitor (C1).
During the sensing and programming interval (Tsp), the 2 nd transistor (M2) is turned (turn-on), the DATA signal (DATA) is applied to the source of the 4 th transistor (M4), the 5 th transistor (M5) is turned (turn-on), the threshold voltages of the DATA signal (DATA) and the 4 th transistor (M4) are charged to the 1 st capacitor (C1), the 7 th transistor (M7) is turned (turn-on), and the initialization Voltage (VIN) is applied to the light emitting diode (Del).
During the light emission section (Tem), the 1 st transistor (M1) is turned (turn-on), the high potential voltage (EVDD) is applied to the source of the 4 th transistor (M4), the 6 th transistor (M6) is turned (turn-on), the current corresponding to the DATA signal (DATA) is supplied to the light emitting diode (Del), and the light emitting diode (Del) emits light corresponding to the DATA signal (DATA).
However, since the pixels (P) operate based on the high potential voltage (EVDD), when the high potential voltage (EVDD) supplied to each pixel (P) in the display panel fluctuates, a current flowing through the 4 th transistor (M4) as a driving transistor changes, so that the luminance of light displayed by each pixel (P) can be changed, and the overall luminance characteristics can be changed according to the average luminance or the mirror shape of the display panel.
Such non-uniformity of the light emission luminance may be less perceived by a user in one display panel, but when a large display system is constructed by connecting two or more display panels as in the case of the led display device, there is a problem in that a luminance difference between the display panels occurs in the form of cotton stains which are perceived by the user.
Fig. 3 is a schematic view of one pixel of an organic light emitting diode display device according to a second example.
As shown in fig. 3, one pixel (P) of the organic light emitting diode display device according to example 2 includes N-type 1 st to 3 rd transistors (M1 to M3), a 1 st capacitor (C1), and a light emitting diode (Del).
The gate of the 1 st transistor (M1), the source of the 2 nd transistor (M2), the 1 st electrode of the 1 st capacitor (C1) are connected to each other to constitute the 1 st node (N1), the source of the 1 st transistor (M1), the source of the 3 rd transistor (M3), the 2 nd electrode of the 1 st capacitor (C1), and the anode of the light emitting diode (Del) are connected to each other to constitute the 2 nd node (N2).
The 1 st transistor (M1) switches (sways) a connection between the high potential voltage (EVDD) and the 2 nd node (N2) according to the voltage of the 1 st node (N1), and the 2 nd transistor (M2) switches (sways) a connection between the DATA signal (DATA) and the 1 st node (N1) according to the GATE signal (GATE).
The 3 rd transistor (M3) switches (swaps) the connection between the reference Voltage (VREF) and the 2 nd node (N2) according to the reference signal (REF).
The 1 st electrode of the 1 st capacitor (C1) is connected to the 1 st node (N1), and the 2 nd electrode of the 1 st capacitor (C1) is connected to the 2 nd node (N2).
The positive electrode of the light emitting diode (Del) is connected to the 2 nd node (N2), and the negative electrode of the light emitting diode (Del) is connected to the low potential voltage (EVSS).
Accordingly, in a section where the GATE signal (GATE) and the reference signal (REF) have high levels, respectively, the 2 nd transistor (M2) is turned (turn-on), the DATA signal (DATA) is applied to the 1 st node (N1), the 3 rd transistor (M3) is turned (turn-on), the reference Voltage (VREF) is recognized to the 2 nd node (N2), and the 1 st electrode and the 2 nd electrode of the first capacitor (C1) input the DATA signal (DATA) and the reference Voltage (VREF), respectively.
In a section where the GATE signal (GATE) and the reference signal (REF) have low levels, respectively, the second and third transistors (M2, M3) are switched (turn-off), respectively, so that the voltage of the first node (N1) is boosted (boosting) to correspond to the threshold voltage, and the degree of boosting is different according to the level of the low potential voltage (EVSS), so that luminance unevenness may be caused.
That is, when the low potential voltage (EVSS) supplied to each pixel (P) of the display panel fluctuates, the current flowing through the 1 st transistor (M1) as the driving transistor changes, so that the luminance of light displayed by each pixel (P) may be changed, and the overall luminance characteristics may be changed according to the average luminance or the image form of the display panel.
Such unevenness of the light emission luminance may be less perceived by a user in one display panel, but when a large display system is constructed by connecting two or more display panels as in the case of the led display device, there is a problem in that a luminance difference between the display panels is recognized by the user in the form of cotton stains.
Fig. 4 is a schematic diagram of a large display system using the device.
As shown in fig. 4, the large-sized display system from the perspective includes a plurality of light emitting diode display panels arranged in a 3*3 matrix form in the 1 st to 3 rd panel rows (PR 1 to PR 3) and the 1 st to 3 rd panel rows (PC 1 to PC 3).
When the current of the driving transistor is changed due to fluctuation of a high potential voltage (EVDD) or a low potential voltage (EVSS), the luminance unevenness may not be recognized in one light emitting diode display panel, but in many light emitting diode display panels of two-dimensional Tiling, if the luminance unevenness is recognized, it may be a bad phenomenon such as a stain.
Disclosure of Invention
Technical problem to be solved
An object of the present invention is to solve the problems and to provide a light emitting diode display device and a driving method thereof that improve uniformity of light emission luminance by supplying a uniform current to a light emitting diode even when a power supply voltage fluctuates by connecting a current source transistor and a source follower transistor to the positive and negative electrodes of the light emitting diode, respectively.
In addition, it is an object of the present invention to provide a light emitting diode display device and a driving method thereof, which improve defect detection capability in a manufacturing process by connecting a test transistor to positive and negative electrodes of a light emitting diode, and which easily repair defects, thereby reducing manufacturing costs.
Technical proposal
In order to achieve the object, the present invention includes a display panel and a plurality of pixels; a light emitting diode and a light emitting diode disposed at each of the plurality of pixels; at least one current source and a voltage source connected between the light emitting diode and a light emitting high potential voltage or between the light emitting diode and a light emitting low potential voltage; a light emitting diode display device is provided, which includes a control circuit part that provides a control signal to at least one current source.
In addition, the at least one current source is connected between the light emitting diode and the light emitting high potential voltage, and one of an N-type and a P-type first transistor; and a second transistor connected between the light emitting diode and the light emitting low potential voltage and may include the other of an N-type and a P-type.
In addition, the control circuit part is used for controlling the control circuit part,
A latch connected between the digital high potential voltage and the digital low potential voltage for generating the 1 st and 2 nd output signals by using the image data and the programming signal; the level shifter is connected between the high-potential voltage of the plug and the low-potential voltage of the plug, and can comprise a level shifter for generating the 3 rd and 4 th output signals for respectively switching (swiping) the 1 st and 2 nd transistors by the 1 st and 2 nd output signals.
Also, the latch includes
Switching (swiping) the P-type 1 st digital transistor and the transmission of the 1 st output signal according to the program signal; switching (swiping) the N type 2 digital transistor and the N type 2 digital transistor of the image data transmission according to the program signal;
switching the N type 3 rd digital transistor of the digital low potential voltage according to a reset signal;
switching a P-type fourth digital transistor of the digital high potential voltage according to the first output signal or the digital low potential voltage;
switching (swiping) an N-type 5 th digital transistor sum of the transfer of the digital low potential voltage according to the 1 st output signal or the digital low potential voltage;
switching (swiping) the P-th digital transistor and the P-th digital transistor of the transfer of the digital high potential voltage according to the 2 nd output signal;
The transfer of the digital low potential voltage according to the 2 nd output signal includes an N-type 7 th digital transistor for switching (swing) transmission;
the level shifter may include
Switching (swiping) the P-type 8 th digital transistor and the P-type 8 th digital transistor of the pin high potential voltage transfer according to the 3 rd output signal;
switching (swiping) the N-type 9 th digital transistor and the transmission of the pin low potential voltage according to the 1 st output signal;
switching (swiping) the P-type 10 th digital transistor and the P-type 10 th digital transistor of the pin high potential voltage transfer according to the 4 th output signal;
and switching (swiping) the N type 11 digital transistor for transmitting the pin low potential voltage according to the 4 th output signal.
The control circuit section includes
Connected between the high potential voltage and the low potential voltage of the pin, and respectively switching (swiping) the 1 st and 2 nd transistors to generate 1 st and 1 nd transistors by using image data, programming signals and luminous signals
An integrated level shifter for the 2 nd output signal,
the integrated level shifter comprises
Switching (swiping) an N-type 1 st digital transistor and a transmission of the 1 st output signal according to the light-emitting signal;
switching (swiping) the P-type 2 nd digital transistor and the transmission of the 1 st output signal according to the programming signal;
Switching (swiping) the N-type 3 rd digital transistor and the N-type 3 rd digital transistor for transmitting the image data according to the programming signal;
switching (swiping) the P-type 4 th digital transistor of the pin high potential voltage according to the 1 st output signal or the mapping data;
switching (swiping) an N-type 5 th digital transistor and a transmission of the pin low potential voltage according to the 1 st output signal or the image data;
switching (swiping) the P-th digital transistor and the P-th digital transistor of the transmission of the pin high potential voltage according to the light emitting signal;
switching (swiping) the P-th digital transistor and the P-th digital transistor of the pin high potential voltage transmission according to the 2 nd output signal;
an N-type 8 th digital transistor is included for switching (swiping) the communication of the pin low potential voltage according to the 2 nd output signal.
Also, the light emitting diode display device further includes a third transistor connected between the positive and negative electrodes of the light emitting diode, the 1 st and 3 rd transistors being of N type, and the 2 nd transistor being possibly of P type.
The control circuit unit may include
Switching (swiping) an N-type fourth transistor sum of a connection between the 1 st data signal and the gate of the 1 st transistor according to the 1 st programming signal; an N-type 5 th transistor switching (swiping) a connection between a 2 nd data signal and a source of the 1 st transistor according to a 2 nd programming signal; and a 1 st capacitor connected between the gate and the source of the 1 st transistor.
The control circuit unit may include
Switching (swiping) an N-type fourth transistor sum of a connection between the 1 st data signal and the gate of the 1 st transistor according to the 1 st programming signal; an N-type 5 th transistor switching (swiping) connection between the 2 nd data signal and the source of the 1 st transistor according to a programming signal; and a 1 st capacitor connected between the gate and the source of the 1 st transistor.
The control circuit unit may include
Switching (swiping) a connection between a data signal and a gate of the 1 st transistor according to a programming signal; switching (toggling) a connected N-type 5 th transistor sum between a reference signal and a source of the 1 st transistor according to a sense signal; a 1 st capacitor connected between the gate of the 1 st transistor and the drain of the 5 th transistor.
Then, the control circuit part includes
A level shifter and a level shifter connected between the high potential voltage of the pin and the low potential voltage of the pin, for generating the 1 st and the 2 nd output signals by using the 1 st and the 2 nd image data, the programming signal, the input signal;
a latch connected between the pin high potential voltage and the pin low potential voltage for switching the 3 rd and 4 th output signals of the 1 st and 2 nd transistors according to the 1 st and 2 nd output signals, respectively,
The level shifter may include
Switching (swiping) a connected 1 st digital transistor sum between the pin high potential voltage and a drain of the 3 rd digital transistor according to the 1 st output signal;
switching (swiping) a connected 2 nd digital transistor sum between the pin high potential voltage and a drain of a fourth digital transistor according to the 2 nd output signal;
switching (swiping) the 3 rd digital transistor sum of the connection between the drain of the 1 st digital transistor and the drain of the 9 th digital transistor according to the 1 st output signal;
switching (swiping) the connected 4 th digital transistor sum between the drain of the second digital transistor and the drain of the ninth digital transistor in accordance with the 2 nd output signal;
switching (swiping) a 5 th digital transistor sum of a connection between a drain of the 1 st digital transistor and a drain of the 9 th digital transistor according to a voltage of a 1 st electrode of the 1 st capacitor;
switching (swiping) a connected 6 th digital transistor sum between a drain of the 2 nd digital transistor and a drain of the 9 th digital transistor according to a voltage of the 1 st electrode of the 2 nd capacitor;
switching (swiping) a 7 th digital transistor sum of a connection between the 1 st video data and the gate of the 5 th digital transistor according to the programming signal;
Switching (swiping) a connected 8 th digital transistor sum between the 2 nd image data and the gate of the 6 th digital transistor according to the programming signal;
switching (swiping) the 9 th digital transistor and the connection between the sources of the 3 rd to 6 th digital transistors and the pin low potential voltage according to the input signal;
the 1 st capacitor connected between the source of the 7 th digital transistor and the pin low potential voltage;
the 2 nd capacitor is connected between the source of the 8 nd digital transistor and the pin low potential voltage.
The control circuit section includes
A level shifter and a level shifter connected between the pin high potential voltage and the pin low potential voltage for generating an output signal by using the mapping data, the programming signal and a Pre-charge (Pre-charge) electrical signal;
a latch connected between the pin high potential voltage and the pin low potential voltage, for generating 3 rd and 4 th output signals by switching (toggling) the 1 st and 2 nd transistors, respectively, with the output signal,
the level shifter may include
Switching (swiping) a 1 st digital transistor sum of a connection between the pin high potential voltage and a drain of the 3 rd digital transistor according to the precharge signal;
Switching (swiping) a connected 2 nd digital transistor sum between the pin high potential voltage and a drain of the 4 nd digital transistor according to the voltage of the 1 st electrode of the 2 nd capacitor;
switching (swiping) the 3 rd digital transistor sum of the connection between the drain of the 1 st digital transistor and the drain of the 6 th digital transistor according to the precharge;
switching (swiping) the connected 4 th digital transistor sum between the drain of the 2 nd digital transistor and the pin low potential voltage according to the voltage of the 1 st electrode of the 2 nd capacitor;
switching (swiping) a 5 th digital transistor and a connection between the image data and a gate of the 6 th digital transistor according to the programming signal;
switching (swiping) a 6 th digital transistor sum of a connection between a source of the 3 rd digital transistor and a pin low potential voltage according to a voltage of a first electrode of the 1 st capacitor;
a 1 st capacitor connected between the source of the 5 th digital transistor and the pin low potential voltage;
the 2 nd capacitor is connected between the gate of the 2 nd digital transistor and the latch low potential voltage.
In addition, the at least one current source is connected between the light emitting diode and the light emitting high potential voltage, and includes a first transistor of one of an N type and a P type, the light emitting diode display device further includes a third transistor connected between an anode of the light emitting diode and the test voltage, and a cathode of the light emitting diode may be connected to the light emitting low potential voltage.
In addition, the control circuit part may include a latch sum connected between the digital high potential voltage and the digital low potential voltage, generating the 1 st and 2 nd output signals using the image data and the programming signal; and a level shifter connected between the pin high potential voltage and the pin low potential voltage, and configured to generate a 3 rd output signal for switching (swiping) the 1 st transistor using the 1 st and 2 nd output signals.
In addition, the control circuit part may include an integrated level shifter connected between the pin high potential voltage and the pin low potential voltage, and programming the signal using the mapping data, and may include an integrated level shifter generating a first output signal for switching the first transistor.
In addition, the control circuit part may include
Switching (swiping) an N-type 4 th transistor sum of a connection between a 1 st data signal and a gate of the 1 st transistor according to a 1 st programming signal;
an N-type 5 th transistor switching (swiping) a connection between a 2 nd data signal and a source of the 1 st transistor according to a 2 nd programming signal;
a 1 st capacitor may be further included connected between the gate and the source of the 1 st transistor.
The control circuit unit may include
Switching (swiping) the N-type 4 th transistor sum of the connection between the data signal and the gate of the 1 st transistor according to the programming signal;
an N-type 5 th transistor switching (swiping) connection between the 2 nd data signal and the source of the 1 st transistor according to a programming signal;
a 1 st capacitor connected between the gate and the source of the 1 st transistor.
The control circuit unit may include
An N-type fourth transistor and switching a connection between a (swing) data signal and a gate of the 1 st transistor according to a programming signal;
switching (toggling) a connected N-type 5 th transistor sum between a reference signal and a source of the 1 st transistor according to a sense signal;
a 1 st capacitor connected between the gate of the 1 st transistor and the drain of the 5 th transistor.
The control circuit unit may include
A latch sum connected between the digital high potential voltage and the digital low potential voltage for generating the 1 st and 2 nd output signals by using the image data and the programming signal;
switching (swiping) an N-type 4 th transistor and a connection between the 1 st output signal and a source of the 1 st transistor according to a reference signal;
Switching (swiping) an N-type 5 th transistor sum of a connection between the 2 nd output signal and a gate of the 1 st transistor according to the reference signal;
switching (swiping) a P-type 6 th transistor and a connection between a light-emitting high potential voltage and a source of the 1 st transistor according to the 1 st light-emitting signal;
switching (swiping) an N-type 7 th transistor sum of a connection between a drain electrode of the 1 st transistor and an anode electrode of the light emitting diode according to a 2 nd light emitting signal;
a first capacitor connected between the gate of the first transistor and the source of the first transistor.
The control circuit part may include
A latch sum connected between the digital high potential voltage and the digital low potential voltage for generating the 1 st and 2 nd output signals by using the image data and the programming signal;
switching (swiping) an N-type 4 th transistor and a connection between the 1 st output signal and a gate of the 1 st transistor according to a reference signal;
switching (swiping) an N-type 5 th transistor sum of a connection between the 2 nd output signal and a source of the 1 st transistor according to the reference signal;
switching (swiping) a P-type 6 th transistor and a connection between a light-emitting high potential voltage and a drain electrode of the 1 st transistor according to the 1 st light-emitting signal;
Switching (swiping) an N-type 7 th transistor sum of a connection between a source of the 1 st transistor and an anode of the light emitting diode according to a 2 nd light emitting signal;
a first capacitor connected between the gate of the first transistor and the source of the first transistor.
Technical effects
In the present invention, by connecting the current source transistor and the source follower transistor to the positive electrode and the negative electrode of the light emitting diode, respectively, even when the power supply voltage fluctuates, a uniform current can be supplied to the light emitting diode, thereby improving the uniformity of the light emission luminance.
In addition, the present invention improves the defect detection capability in the manufacturing process and facilitates repair of defects by connecting the test transistor to the positive and negative electrodes of the light emitting diode, thereby reducing the manufacturing cost.
Drawings
Fig. 1 is a schematic view of a pixel of an organic light emitting diode display device according to embodiment 1.
Fig. 2 is a waveform diagram showing signals utilized in the organic light emitting diode display device according to the conventional embodiment 1.
Fig. 3 is a schematic diagram of a pixel of an organic light emitting diode display device according to embodiment 2.
Fig. 4 is a schematic diagram of a conventional large-scale display system.
Fig. 5 is a schematic view of a light emitting diode display device according to embodiment 1 of the present invention.
Fig. 6 is a schematic view of a light emitting diode display device according to embodiment 1 of the present invention.
Fig. 7 is a schematic view of a light emitting diode display device according to embodiment 1 of the present invention.
Fig. 8 is a waveform diagram showing signals utilized in a pixel of the light emitting diode display device according to embodiment 1 of the present invention.
Fig. 9 is a waveform diagram showing signals utilized in a pixel of a light emitting diode display device according to embodiment 2 of the present invention.
Fig. 10 is a schematic view of a pixel of a light emitting diode display device according to embodiment 3 of the present invention.
Fig. 11 is a schematic view of a pixel of a light emitting diode display device according to embodiment 4 of the present invention.
Fig. 12 is a waveform diagram of signals utilized in a pixel of a light emitting diode display device according to a fourth embodiment of the present invention.
Fig. 13 is a schematic view of a pixel of a light emitting diode display device according to embodiment 5 of the present invention.
Fig. 14 is a schematic view of a pixel of a light emitting diode display device according to embodiment 6 of the present invention.
Fig. 15 is a schematic view of a pixel of a light emitting diode display device according to embodiment 6 of the present invention.
Fig. 16 is a diagram of a light emitting portion of a pixel of a light emitting diode display device according to embodiment 7 of the present invention.
Fig. 17 is a diagram of a light emitting portion of a pixel of a light emitting diode display device according to embodiment 8 of the present invention.
Fig. 18 is a waveform diagram showing signals utilized in the light emitting portion of the pixel of the light emitting diode display device according to embodiment 8 of the present invention.
Fig. 19 is a diagram of a light emitting portion of a pixel of a light emitting diode display device according to embodiment 9 of the present invention.
Fig. 20 is a waveform diagram showing signals utilized in the light emitting portion of the pixel of the light emitting diode display device according to embodiment 9 of the present invention.
Fig. 21 is a pixel diagram of a light emitting diode display device according to embodiment 10 of the present invention.
Fig. 22 is a schematic diagram of signals utilized in a pixel of the light emitting diode display device according to embodiment 10 of the present invention.
Fig. 23 is a pixel diagram of a light emitting diode display device according to embodiment 11 of the present invention.
Fig. 24 is a pixel diagram of a light emitting diode display device according to embodiment 12 of the present invention.
Fig. 25 is a pixel diagram of a light emitting diode display device according to embodiment 13 of the present invention.
Fig. 26 is a schematic diagram of a pixel of a light emitting diode display device according to embodiment 14 of the present invention.
Fig. 27 is a level shifter diagram of a pixel of a light emitting diode display device according to embodiment 14 of the present invention.
Fig. 28 is a waveform diagram showing signals utilized in the level shifter of the pixel of the light emitting diode display device according to embodiment 14 of the present invention.
Fig. 29 is a level shifter diagram of a pixel of a light emitting diode display device according to embodiment 15 of the present invention.
Fig. 30 is a waveform diagram showing signals utilized in a level shifter of a pixel of a light emitting diode display device according to embodiment 15 of the present invention.
Fig. 31 is a schematic view of a pixel of a light emitting diode display device according to embodiment 16 of the present invention.
Fig. 32 is a pixel diagram of a light emitting diode display device according to embodiment 17 of the present invention.
Detailed Description
The following describes the details of the present invention with reference to the drawings.
Fig. 5 is a schematic view of a light emitting diode display device according to embodiment 1 of the present invention, and fig. 6 is a schematic view of a pixel of the light emitting diode display device according to embodiment 1 of the present invention.
As shown in fig. 5 and 6, the light emitting diode display device (110) according to the first embodiment of the present invention includes a timing control part (120), a gate driving part (130), a data driving part (140), and a display panel (160).
The timing control part (120) receives a video signal (IMS) and a plurality of timing signals (DE, HSY, VSY, CLK) from an external system such as a television system or a video card to generate video data (RGB), a Gate Control Signal (GCS) and a Data Control Signal (DCS), and supplies the generated Gate Control Signal (GCS) to the gate driving part (130), and supplies the generated video data (RGB) and data control signal to the data driving part (140).
The gate driving part (130) generates a plurality of switching signals such as a gate signal (gate voltage), a sensing signal, and a light emitting signal using a Gate Control Signal (GCS), and supplies the generated plurality of switching signals to the display panel (160).
The data driving unit (140) converts the image data (RGB) into a data signal (data voltage) using a Data Control Signal (DCS), and supplies the converted data signal to the display panel (160) through a data wiring (DL).
The display panel (160) displays a video using gate signals and data signals, and for this purpose, the display panel (160) includes gate wirings (GL) and data wirings (DL) crossing each other to define pixels (P), latches (latch: digital storage element, 172) formed on each pixel (P), level shift (174), first and second transistors (M1, M2), and a light emitting diode (Del).
A latch (172) of a control circuit section for supplying a control signal to a current source receives video data (RGB), a program signal (PGM), and a Reset Signal (RS), and outputs 1 st and 2 nd output signals using a digital high potential Voltage (VCC) and a digital low potential Voltage (VSS), and the 1 st and 2 nd output signals may be inverted signals.
In other embodiments, the Reset Signal (RS) may be omitted.
A level shifter (174) of a control circuit section for supplying a control signal to a current source receives the 1 st and 2 nd output signals, and outputs the 3 rd and 4 th output signals by using a latch high Potential Voltage (PVDD) and a latch low Potential Voltage (PVSS), and the 3 rd and 4 th output signals may be inverted signals.
The first transistor (M1) operates with a first current source (182) to cause the light emitting diode (Del) to flow a certain current, and switches (swiping) the connection between the light emitting high potential voltage (EVDD) and the light emitting diode (Del) according to a third output signal, and the second transistor (M2) switches (swiping) the connection between the light emitting diode (Del) and the light emitting low potential voltage (EVSS) according to a fourth output signal.
The first transistor (M1) has an N-type (negative type), and a gate of the first transistor (M1) is connected to the third output signal of the level shifter (174) to constitute a first node (N1), a drain of the first transistor (M1) is connected to a light-emitting high potential voltage (EVDD), and a source of the first transistor (M1) is connected to an anode of the light-emitting diode to constitute a second node (N2).
A second transistor (M2) for operating a second current source (184) for causing a light emitting diode (Del) to flow a certain current has a P-type (positive type), a source of the second transistor (M2) is connected to a cathode of the light emitting diode (Del) to constitute a third node (N3), a gate of the second transistor (M2) is connected to a fourth output signal of the level shifter (174) to constitute a fourth node (N4), and a drain of the second transistor (M2) is connected to a light emitting low potential voltage (EVSS).
The 1 st and 2 nd transistors (M1, M2) and the light emitting diode (Del) constitute a light emitting portion of each pixel (P).
In this pixel (P), the current level of the light emitting diode (Del) is determined by the voltages of the 1 st and 4 th nodes (N1, N4) and the operating characteristics (L-I-V characteristics) of the light emitting diode (Del).
That is, the voltage condition of the steady state (step state) is shown in the following formula (1).
V (N1) is the voltage of the 1 st node (N1), V (N4) is the voltage of the 4 th node (N4), vgs (M1) is the voltage difference between the gate and the source of the 1 st transistor (M1), V (Del) is the voltage difference between the anode and the cathode of the light emitting diode (Del), vgs (M2) is the voltage difference between the source and the gate of the 2 nd transistor (M2).
If equation (1) is solved to voltages of the 1 st to 4 th nodes (N1 to N4), the following equation (2) is expressed.
V (N1) -V (N4) = { V (N1) -V (N2) } ++ { V (N2) -V (N3) } + { V (N3) -V (4) } - - - - - - - -, 2
V (N2) is the voltage of the 2 nd node (N2), and V (N3) is the voltage of the 4 th node (N4).
Therefore, the current level of the light emitting diode (Del) is determined by the voltages of the 1 st and 4 th nodes (N1, N4) and the operating characteristics of the light emitting diode (Del) irrespective of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), and therefore, in the level shifter (174), when the voltage drop (voltage drop) caused by the DC bypass (DC bypass) current is not present, a constant current flows to the light emitting diode irrespective of the brightness of the image.
That is, when the level shifter (174) outputs the 3 rd and 4 th output signals using the 1 st and 2 nd signals of the latch (172) to which the digital storage concept is applied, the direct current bypass current in the level shifter (174) can be prevented, in which case the light emitting diode (Del) can emit light of a certain brightness if the image brightness does not exceed the limit (the 1 st and 2 nd transistors (M1, M2) operated in the saturation region for light emission with the source code follower).
Here, the image data (RGB) inputted to the latch (172) has a digital type of digital voltage level.
As described above, in the pixel (P) of the light emitting diode display device (110) according to embodiment 1 of the present invention, the latch (172) generates flicker (flicker) or the like as little as possible, the 1 st and 2 nd output signals of a constant direct current voltage level are output, and the level shifter (174) applies the 3 rd and 4 th signals necessary for light emission to the gates of the 1 st and 4 th transistors (M1, M4), so that a certain current can flow through the light emitting diode (Del) regardless of fluctuations in the light emitting high potential voltage (EVDD) and the light emitting low potential voltage (EVSS).
In addition, when the pixel (P) includes light emitting diodes (Del) emitting red, green and blue light, a current reflecting a difference in operation characteristics of the red, green and blue light emitting diodes (Del) may flow through the light emitting diodes (Del) by adjusting aspect ratios (aspect ratios) of the 1 st and 2 nd transistors (M1, M2).
The latch (172) and the level shifter (174) may be composed of a plurality of transistors and are described with reference to the drawings.
Fig. 7 is a schematic diagram of a pixel of a light emitting diode display device according to embodiment 1 of the present invention, and fig. 8 is a waveform diagram of signals utilized in the pixel of the light emitting diode display device according to embodiment 1 of the present invention, and the description will be made with reference to fig. 5 and 6.
As shown in fig. 7, the pixel (P) of the light emitting diode display device (110) according to embodiment 1 of the present invention includes a latch (172), a level shifter (174), 1 st and 2 nd transistors (M1, M2), and a light emitting diode (Del), the latch (172) includes 1 st to 7 th digital transistors (Q1 to Q7), the level shifter (174) includes 8 th to 11 th digital transistors (Q8 to Q11), the 1 st and 1 st transistors (M1, mel 2), and the light emitting diode (Del) constitutes a light emitting portion.
The 1 st, 4 th, 6 th, 8 th, 10 th digital transistors (Q1, Q4, Q6, Q8, Q10) have P-type, and the 2 nd, 3 rd, 5 th, 7 th, 9 th, 11 th digital transistors (Q2, Q3, Q5, Q7, Q9, Q11) have N-type.
The 1 st digital transistor (Q1) switches (swaying) the connection between the 1 st output signal and the gates of the 4 st and 5 th digital transistors (Q4 and Q5) according to a program signal (PGM) which is a signal for inputting the image data (RGB) to the latch (172), and the 2 nd digital transistor (Q2) switches (swaying) the connection between the image data (RGB) and the gates of the 4 th and 5 th digital transistors (Q4 and Q5) according to the program signal (PGM).
The 3 rd digital transistor (Q3) resets the signal of the latch (172) according to the Reset Signal (RS), switching the connection between the digital low potential Voltage (VSS) and the gates of the 4 th and 5 th digital transistors (Q4 and Q5).
In other embodiments, the Reset Signal (RS) and the third digital transistor (Q3) may be omitted.
The fourth digital transistor (Q4) switches (swaying) a connection between the digital high potential Voltage (VCC) and the 2 nd output signal according to the 1 st output signal or the digital low potential Voltage (VSS), and the 5 th digital transistor (Q5) switches (swaying) a connection between the digital low potential Voltage (VSS) and the 2 nd output signal according to the 1 st output signal or the digital low potential Voltage (VSS).
The sixth digital transistor (Q6) switches (swaying) the connection between the digital high potential Voltage (VCC) and the 1 st output signal according to the 2 nd output signal, and the 7 th digital transistor (Q7) switches (swaying) the connection between the digital low potential Voltage (VSS) and the 2 nd output signal according to the 2 nd output signal.
The 8 th digital transistor (Q8) switches (swiping) the connection between the pin high voltage (PVDD) and the 4 th output signal according to the 3 rd output signal, and the 9 th digital transistor (Q9) switches (swiping) the connection between the pin low voltage (PVSS) and the 4 th output signal according to the 1 st output signal.
The 10 th digital transistor (Q10) switches (swiping) the connection between the pin high voltage (PVDD) and the 3 rd output signal according to the 4 th output signal, and the 11 th digital transistor (Q11) switches (swiping) the connection between the pin low voltage (PVSS) and the 3 rd output signal according to the 4 th output signal.
Here, the pin high Potential Voltage (PVDD) and the pin low Potential Voltage (PVSS) allow current flow required for the 1 st and 2 nd transistors (M1, M2) and the light emitting diode (Del) responsible for light emission, and the 1 st and 2 nd transistors (M1, M2) can operate in a saturation region so as to have a voltage level at which the source follower operates normally.
For example, the latch high voltage (PVDD) may be greater than the digital high Voltage (VCC) by a value less than the light-emitting high voltage (EVDD).
As shown in fig. 8, the image data (RGB) has a valid (valid) interval per frame, the Reset Signal (RS) has a high level during a reset interval (Trs) corresponding to the valid interval of the current frame of the image data (RGB), and the program signal (PGM) has a high level during a program interval (Tpg) corresponding to the valid interval of the current frame of the image data (RGB).
Therefore, during the reset period (Trs), the 1 st and 2 nd output signals of the latch (172) are input to the low (0) and high (1) level shifter (174), respectively, and the 3 rd and 4 th output signals of the level shifter (174) are transferred from the low (0) and high (1) to the 1 st and 4 th nodes (N1, N4), respectively, with the result that the 1 st and 2 nd transistors (M1, M2) are switched (turn-off), respectively, so that the light emitting diode does not emit light.
During the programming section (Tpg), the 1 st and 2 nd output signals of the latch (172) become high (1) and low (0) respectively and are input to the level shifter (174), the 3 rd and 4 th output signals of the level shifter (174) become high (1) and low (0) respectively and are transmitted to the 1 st and 4 th nodes (N1, N4), with the result that the 1 st and 2 nd transistors (M1, M2) are switched (turn-on) respectively, and the light emitting diode emits light.
That is, the light emitting diode (Del) is a non-light emitting section (Tne) that emits no light between the rising time of the reset section (Trs) and the rising time of the programming section (Tpg), and the light emitting diode (Del) is a light emitting section (Tem) that emits light between the rising time of the programming section (Tpg) and the rising time of the reset section (Trs) of the next frame.
As described above, in the light emitting diode display device (110) according to embodiment 1 of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode (Del), respectively, the digital memory element latch (172) outputting the 1 st and 2 nd output signals of the constant dc voltage level and the 1 st and 2 nd transistors (M1, M2) are switched by using the level shift (174) outputting the 3 rd and 4 th output signals of the voltage level required for light emission, and as a result, a certain current can be made to flow through the light emitting diode (Del) irrespective of the variations of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), and as a result, the uniformity of the light emission luminance can be improved.
In other embodiments, the reset interval may not be used, but may be described with reference to the drawings.
Fig. 9 is a waveform diagram showing signals utilized in a pixel of a light emitting diode display device according to embodiment 2 of the present invention, and the description of the same portions as embodiment 1 is omitted.
As shown in fig. 9, the image data (RGB) has a valid (valid) section for each frame, the Reset Signal (RS) has a low level, and the program signal (PGM) has a high level during a program section (Tpg) corresponding to the valid section of the current frame of the image data (RGB).
Thus, during the programming interval (Tpg), the 1 st and 2 nd output signals of the latch (172) are input to the level shifter (174) by high (1) and low (0), respectively, and the 3 rd and 4 th output signals of the level shifter (174) are transferred to the 1 st and 4 th nodes (N1, N4) by high (1) and low (0), respectively, with the result that the 1 st and 2 nd transistors (M1 and M2) are switched (turn-on), respectively, and the light emitting diode (Del) emits light.
That is, the light emitting diode (Del) is a light emitting section (Tem) that emits light between the rising point of the programming section (Tpg) and the rising point of the programming section (Tpg) of the next frame.
As described above, in the light emitting diode display device according to embodiment 2 of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode, respectively, and the 1 st and 2 nd transistors (M1, M2) can be switched (swiping) by the latch (172) and the level shifter (174), irrespective of the variation of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), a certain current can be caused to flow through the light emitting diode (Del), with the result that the uniformity of the light emission luminance can be improved.
In other embodiments, the detection and repair of defects may be performed by connecting both ends of the light emitting diode to the test transistor, and will be described with reference to the drawings.
Fig. 10 is a schematic view of a pixel of a light emitting diode display device according to embodiment 3 of the present invention, and the descriptions of the same parts as those of embodiments 1 and 2 are omitted.
As shown in fig. 10, the pixel (P) of the light emitting diode display device according to embodiment 3 of the present invention includes a latch (172), a level shifter (174), 1 st, 2 nd and 3 rd transistors (M1, M2, M3), a light emitting diode (Del), the latch (172) includes 1 st to 7 th digital transistors (Q1 to Q7), the level shifter (174) includes 8 th to 11 th digital transistors (Q8 to Q11), 1 st, 2 nd and 3 rd transistors (M1, M2, M3), and the light emitting diode (Del) constitute a light emitting section.
A first transistor M1, which is a current source for causing a light emitting diode Del to flow a constant current, switches a connection between a light emitting high potential voltage EVDD and the light emitting diode Del according to a third output signal, a second transistor M2, which is a current source for causing a light emitting diode Del to flow a constant current, switches a connection between the light emitting diode Del and a light emitting low potential voltage EVSS according to a fourth output signal, and a 3 rd transistor M3 switches a connection between a positive electrode and a negative electrode of the light emitting diode Del according to a test signal TE.
The gate of the N-type 1 st transistor (M1) is connected to the 3 rd output signal of the level shifter (174) to constitute the 1 st node (N1), the drain of the 1 st transistor (M1) is connected to the light-emitting high potential voltage (EVDD), and the source of the 1 st transistor (M1) is connected to the anode of the light-emitting diode (Del) to constitute the 2 nd node (N2).
The source of the P-type 2 nd transistor (M2) is connected to the cathode of the light emitting diode (Del) to constitute a 3 rd node (N3), the gate of the 2 nd transistor (M2) is connected to the 4 th output signal of the level shifter (174) to constitute a fourth node (N4), and the drain of the 2 nd transistor (M2) is connected to the light emitting low potential voltage (EVSS).
The drain and source of the N-type 3 rd transistor (M3) are connected to the 2 nd and 3 rd nodes (N2, N3), respectively, and the gate of the 3 rd transistor (M3) is connected to the test signal (TE).
The light emitting diode display device according to embodiment 3 of the present invention can be operated in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, and defects of the 1 st to 11 th digital transistors (Q1 to Q11) and the 1 st and 2 nd transistors of the latch (172) and the level shifter (174) are detected using the image data (RGB), the Reset Signal (RS), the program signal (PGM).
Here, in the manufacturing process, before the light emitting diode (Del) is connected between the 2 nd and 3 rd nodes (N2, N3), the third transistor (M3) may be turned on (turn-on) to detect whether the elements other than the light emitting diode (Del) are operating normally.
In the manufacturing process, after the light emitting diode (Del) is connected between the 2 nd and 3 rd nodes (N2 and N3), in order to make the voltage difference between the 2 nd and 3 rd nodes (N2 and N3) smaller than the light emitting threshold voltage of the light emitting diode (Del), the 3 rd transistor (M3) may be rotated (turn-on) to detect whether the devices other than the light emitting diode (Del) are operating normally.
As described above, in the light emitting diode display device according to embodiment 3 of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode, respectively, and by switching (swiping) the 1 st and 2 nd transistors (M1, M2) by the latch (172) and the level shifter (174), a constant current can be made to flow through the light emitting diode (Del) irrespective of variations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), with the result that uniformity of light emission luminance can be improved.
In addition, the 3 rd transistor (M3) is connected to the positive and negative electrodes of the light emitting diode (Del), and the 3 rd transistor (M3) is switched (turn-on), so that defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.
In the 3 rd embodiment of fig. 10, the 2 nd transistor (M2) is connected between the cathode of the light emitting diode (Del) and the light emitting low potential voltage (EVSS) as an example, but in other embodiments, the 2 nd transistor (M2) is omitted, the cathode of the light emitting diode (Del) may be directly connected to the light emitting low potential voltage (EVSS), in which case the level shifter (174) may output the 3 rd output signal without outputting the fourth output signal, and the source of the 3 rd transistor (M3) may be connected to the test voltage (TM) instead of the 3 rd node (N3), which will be described in detail in fig. 14 and 15.
In another embodiment, the latch and level shifter may also consist of one level shifter and will be described with reference to the accompanying drawings.
Fig. 11 is a schematic diagram of a pixel of a light emitting diode display device according to embodiment 4 of the present invention, fig. 12 is a schematic waveform diagram of a signal of a pixel of a light emitting diode display device according to embodiment 4 of the present invention, and descriptions of the same parts as those of embodiments 1 to 3 are omitted.
As shown in fig. 11, the pixel (P) of the light emitting diode display device according to embodiment 4 of the present invention includes an integrated level shifter (176), 1 st and 2 nd transistors (M1, M2), a light emitting diode (Del), 1 st and 2 nd transistors (M1, M2), and a light emitting diode (Del) to constitute a light emitting portion.
An integrated level shifter (176) of a control circuit part supplying a control signal to a current source receives video data (RGB), a program signal (PGM), a light emitting signal (EM), and outputs 1 st and 2 nd output signals using a latch high Potential Voltage (PVDD) and a latch low Potential Voltage (PVSS), and the first and 2 nd output signals may be inverted signals.
The 1 st transistor (M1) operating a current source for flowing a light emitting diode (Del) with a constant current switches (swaying) a connection between a light emitting high potential voltage (EVDD) and the light emitting diode (Del) according to the 1 st output signal, and the 2 nd transistor (M2) operating a current source for flowing a light emitting diode (Del) with a constant current switches (swaying) a connection between the light emitting diode (Del) and a light emitting low potential voltage (EVSS) according to the 2 nd output signal.
The 1 st transistor (M1) has an N type (positive type), a gate of the 1 st transistor (M1) is connected to the 1 st output signal of the integrated level shifter (176) to constitute a 1 st node (N1), a drain of the 1 st transistor (M1) is connected to a light emitting high potential voltage (EVDD), and a source of the 1 st transistor (M1) is connected to an anode of the light emitting diode to constitute a 2 nd node (N2).
The 2 nd transistor (M2) has a P-type (active type), the source of the 2 nd transistor (M2) is connected to the cathode of the light emitting diode (Del) to constitute a third node (N3), the gate of the 2 nd transistor (M2) is connected to the 2 nd output signal of the integrated level shifter (176) to constitute a 4 nd node (N4), and the drain of the 2 nd transistor (M2) is connected to a light emitting low potential voltage (EVSS).
The integrated level shifter shift (176) includes 1 st to 8 th digital transistors (Q1 to Q8).
The 2 nd, 4 th, 6 th, 7 th digital transistors (Q2, Q4, Q6, Q7) have P-type, and the 1 st, 3 rd, 5 th, 8 th digital transistors (Q1, Q3, Q5, Q8) have N-type.
The 1 st digital transistor (Q1) switches (swaying) the connection between the 1 st output signal and the gates of the 4 th and 5 th digital transistors (Q4, Q5) according to the light emission signal (EM), and the 2 nd digital transistor (Q2) switches (swaying) the connection between the 1 st output signal and the gates of the 4 th and 5 th digital transistors (Q4, Q5) according to the programming signal (PGM).
The 3 rd digital transistor (Q3) switches (swaying) the connection between the image data (RGB) and the gates of the 4 th and 5 th digital transistors (Q4 and Q5) according to the programming signal (PGM).
The 4 th digital transistor (Q4) switches (swaps) the connection between the pin high Potential Voltage (PVDD) and the 2 nd output signal according to the 1 st output signal or the video data (RGB), and the fifth digital transistor (Q5) switches (swaps) the connection between the pin low Potential Voltage (PVSS) and the 2 nd output signal according to the 1 st output signal or the video data (RGB).
The 6 th digital transistor (Q6) switches (swiping) the connection between the pin high Potential Voltage (PVDD) and the 2 nd output signal according to the light emission signal (EM), the 7 th digital transistor (Q7) switches (swiping) the connection between the pin high Potential Voltage (PVDD) and the 1 st output signal according to the 2 nd output signal, and the 8 th digital transistor (Q8) switches (swiping) the connection between the pin low Potential Voltage (PVSS) and the 1 st output signal according to the 2 nd output signal.
Here, the latch high Potential Voltage (PVDD) and the latch low Potential Voltage (PVSS) may flow a current required for the first and second transistors (M1, M2) and the light emitting diode (Del) responsible for light emission, and the 1 st and 2 nd transistors (M1, M2) may operate in a saturation region, so that the source follower operates at a normal voltage level.
For example, the latch high Potential Voltage (PVDD) may be less than the light emitting high potential voltage (EVDD).
In addition, by adjusting the aspect ratios of the 1 st to 8 th digital transistors (Q1 to Q8), the integrated level shifter (176) can perform a function of changing the image data (RGB) to voltages of the pin high Potential Voltage (PVDD) and the pin low Potential Voltage (PVSS) and a function of storing the image data (RGB).
As shown in fig. 12, the image data (RGB) has a valid (valid) interval per frame, the light emitting signal (EM) has a low level during a non-storage interval (Tns) corresponding to the valid interval of the current frame of the image data (RGB), and the program signal (PGM) has a high level during a program interval (Tpg) corresponding to the valid interval of the current frame of the image data (RGB).
Thus, during the non-storage portion (Tns), the 1 st and 2 nd output signals of the integrated level shifter (176) are transferred to the 1 st and 4 th nodes (N1, N4) by low (0) and high (1), respectively, with the result that the 1 st and 2 nd transistors (M1, M2) are switched (turn-off), respectively, and the light emitting diode (Del) does not emit light.
During the programming portion (Tpg), the 1 st and 2 nd output signals of the integrated level shifter (176) are transmitted to the 1 st and 4 th nodes (N1, N4) by high (1) and low (0), respectively, with the result that the 1 st and 2 nd transistors (M1, M2) are turned on (turn-on), respectively, and the light emitting diode (Del) emits light.
That is, a section between the time of falling of the non-memory section (Tns) and the time of rising of the programming section (Tpg) becomes a non-light-emitting section (Tne) in which the light emitting diode (Del) does not emit light, and a section between the time of rising of the programming section (Tpg) and the time of falling of the non-memory section (Tns) of the next frame becomes a light-emitting section (Tem) in which the light emitting diode (Del) emits light.
In addition, in a section where the light emission signal (EM) has a high level and the program setting signal (PGM) has a low level, the image data (RGB) is stored in the integrated level shifter shift (176).
As described above, in the light emitting diode display device according to the fourth embodiment of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode, respectively, and by switching (swiping) the 1 st and 2 nd transistors (M1, M2) by the integrated level shifter (176), a constant current can be made to flow through the light emitting diode (Del) irrespective of variations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), with the result that uniformity of light emission luminance can be improved.
In other embodiments, the detection and repair of defects may be performed by connecting both ends of the light emitting diode to the test transistor, and will be described with reference to the drawings.
Fig. 13 is a schematic view of a pixel of a light emitting diode display device according to a fifth embodiment of the present invention, and the description of the same parts as those of embodiments 1 to 4 is omitted.
As shown in fig. 13, a pixel (P) of a light emitting diode display device according to a fifth embodiment of the present invention includes an integrated level shifter (176), first, second and third transistors (M1, M2, M3), and a light emitting diode (Del), the integrated level shifter (176) includes first to eighth digital transistors (Q1 to Q8), and the first, second and third transistors (M1, M2, M3), and the light emitting diode (Del) constitute a light emitting portion.
A first transistor (M1) for operating a current source for flowing a light emitting diode (Del) with a certain current, a second transistor (M2) for operating a current source for flowing a light emitting diode (Del) with a certain current by switching (swiping) a connection between a light emitting high potential voltage (EVDD) and the light emitting diode (Del) according to a first output signal, a connection between the light emitting diode (Del) and a light emitting low potential voltage (EVSS) according to a second output signal, and a 3 rd transistor (M3) for switching (swiping) a connection between a positive electrode and a negative electrode of the light emitting diode (Del) according to a test signal (TE).
The gate of the N-type 1 st transistor (M1) is connected to the 1 st output signal of the integrated level shifter (176) to constitute the 1 st node (N1), the drain of the 1 st transistor (M1) is connected to the light-emitting high potential voltage (EVDD), and the source of the 1 st transistor (M1) is connected to the anode of the light-emitting diode (Del) to constitute the second node (N2).
The source of the P-type 2 nd transistor (M2) is connected to the cathode of the light emitting diode (Del) to constitute a 3 rd node (N3), the gate of the 2 nd transistor (M2) is connected to the 2 nd output signal of the integrated level shifter (176) to constitute a fourth node (N4), and the drain of the 2 nd transistor (M2) is connected to the light emitting low potential voltage (EVSS).
The drain and source of the N-type 3 rd transistor (M3) are connected to the 2 nd and 3 rd nodes (N2, N3), respectively, and the gate of the 3 rd transistor (M3) is connected to the test signal (TE).
The light emitting diode display device according to embodiment 5 of the present invention can be operated in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, and defects of the 1 st to 8 th digital transistors (Q1 to Q8) and the 1 st and 2 nd transistors (M1, M2) of the integrated level shifter (176) are detected by using the image data (RGB), the program signal (PGM), and the light emitting signal (EM).
During the manufacturing process, when the light emitting diode (Del) is before the connection between the 2 nd and the 3 rd nodes (N2, N3), the switching (turn-on) of the 3 rd transistor (M3) can detect whether the elements except the light emitting diode (Del) work normally or not.
In the manufacturing process, after the light emitting diode (Del) is connected between the 2 nd and 3 rd nodes (N2 and N3), in order to make the voltage difference between the 2 nd and 3 rd nodes (N2 and N3) smaller than the light emitting threshold voltage of the light emitting diode (Del), the 3 rd transistor (M3) may be rotated (turn-on) to detect whether the devices other than the light emitting diode (Del) are operating normally.
As described above, in the light emitting diode display device according to the fifth embodiment of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode, respectively, and by switching (swiping) the 1 st and 2 nd transistors (M1, M2) by the integrated level shifter (176), a constant current can be made to flow through the light emitting diode (Del) irrespective of variations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), with the result that uniformity of light emission luminance can be improved.
In addition, the 3 rd transistor (M3) is connected to the positive and negative electrodes of the light emitting diode (Del), and the 3 rd transistor (M3) is switched (turn-on), so that defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.
In other embodiments, the 2 nd transistor (M2) is omitted, and the cathode of the light emitting diode (Del) may also be directly connected to the light emitting low potential voltage (EVSS), which is described with reference to the drawings.
Fig. 14 is a schematic diagram of a pixel of a light emitting diode display device according to embodiment 6 of the present invention, fig. 15 is a waveform diagram of a signal of a pixel of a light emitting diode display device according to embodiment 6 of the present invention, and the descriptions of the same parts as those of embodiments 1 to 5 are omitted.
As shown in fig. 14, the pixel (P) of the light emitting diode display device according to embodiment 6 of the present invention includes an integrated level shifter (176), 1 st and 3 rd transistors (M1, M3), a light emitting diode (Del), and 1 st and 3 rd transistors (M1, M3), the light emitting diode (Del) constitute a light emitting portion.
An integrated level shifter (176) of a control circuit part providing a control signal to a current source includes 1 st to 8 th digital transistors (Q1 to Q8), receives image data (RGB), a program signal (PGM), a light emitting signal (EM), and outputs a first output signal using a latch high Potential Voltage (PVDD) and a latch low Potential Voltage (PVSS).
The 1 st transistor (M1) is used as a current source, a light emitting diode (Del) flows a certain current, the connection between the light emitting high potential voltage (EVDD) and the light emitting diode (Del) is switched according to the 1 st output signal, and the 3 rd transistor (M3) is used for switching the connection between the positive electrode of the light emitting diode (Del) and the test voltage (TM) according to the test signal (TE).
The gate of the N-type 1 st transistor (M1) is connected to the 1 st output signal of the integrated level shifter (176) to constitute the 1 st node (N1), the drain of the 1 st transistor (M1) is connected to the light-emitting high potential voltage (EVDD), and the source of the 1 st transistor (M1) is connected to the anode of the light-emitting diode (Del) to constitute the 2 nd node (N2).
The drain and source of the N-type 3 rd transistor (M3) are connected to the 2 nd node (N2) and the test voltage (TM), respectively, and the gate of the 3 rd transistor (M3) is connected to the test signal (TE).
The light emitting diode display device according to embodiment 6 of the present invention can operate in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, the 2 nd node (N2) is initialized to the test voltage (TM) to prevent a decrease to a certain voltage from being less than full, or the characteristics of the 1 st transistor (M1) or the light emitting diode (Del) may be measured.
As shown in fig. 15, in the test mode of the light emitting diode display device, the image data (RGB) has a test data (test input data) section, the light emitting signal (EM) has a low level in a non-storage section (Tns) corresponding to the test data section of the image data (RGB), the program signal (PGM) has a high level in a program section (Tpg) corresponding to the test data section of the image data (RGB), and the test signal (TE) has a high level in a test section (Tts) corresponding to the next frame of the image data (RGB).
Therefore, during the non-storage section (Tns), the 1 st output signal of the integrated level shifter (176) is low (0) and passed to the 1 st node (N1), and the gate of the 1 st transistor (M1) is initialized.
During the programming interval (Tpg), the 1 st output signal shifted by the integrated level shifter (176) is passed high (1) to the 1 st node (N1), and the gate of the 1 st transistor (M1) reflects the pixel state.
During the test interval (Tts), the test signal (TE) is high (1), the 3 rd transistor (M3) is turned on (turn-on), and the test voltage (TM) is transferred to the 2 nd node (N2) as the source of the 1 st transistor (M1) to detect a characteristic change of the 1 st transistor (M1) or the light emitting diode (Del).
As described above, in the light emitting diode display device according to the sixth embodiment of the present invention, the 1 st transistor (M1) is connected to both poles of the light emitting diode (Del), and by switching (swiping) the 1 st transistor (M1) by the integrated level shifter (176), a certain current can be caused to flow through the light emitting diode (Del) irrespective of fluctuations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), with the result that the uniformity of the light emission luminance can be improved.
In addition, by connecting the 3 rd transistor (M3) to the positive electrode of the light emitting diode (Del), and switching (turn-on) the 3 rd transistor (M3), defects in the manufacturing process can be detected and repaired, and as a result, manufacturing cost can be reduced.
In other embodiments, the current source and the source follower may be connected to the anode and the cathode of the light emitting diode, respectively, and are described with reference to the drawings.
Fig. 16 is a schematic view of a light emitting portion of a pixel of a light emitting diode display device according to a seventh embodiment of the present invention, and the description of the same portions as those of embodiments 1 to 6 is omitted.
As shown in fig. 16, the light emitting portion of the pixel (P) of the light emitting diode display device according to embodiment 7 of the present invention includes the 1 st, 3 rd to 5 th transistors (M1, M3 to M5) of the N type, the 2 nd transistor (M2) of the N type, the 1 st capacitor (C1) and the light emitting diode (Del).
A 1 st transistor (M1) for operating a current source for flowing a constant current through the light emitting diode (Del), a connection between the (switching) light emitting high potential voltage (EVDD) and the light emitting diode (Del) is switched according to the voltage of the 1 st node (N1), a 2 nd transistor (M2) for operating a current source for flowing a constant current through the light emitting diode (Del), a connection between the (switching) light emitting diode (Del) and the light emitting low potential voltage (EVSS) is switched according to the voltage of the 3 rd node (N3), and a connection between the positive electrode and the negative electrode of the (switching) light emitting diode (Del) is switched according to the test signal (TE).
A4 th transistor (M4) of a control circuit section that supplies a control signal to a current source switches (swiping) a connection between a1 st DATA signal (DATA 1) and a1 st node (N1) according to a1 st programming signal (PGM 1), and a 5 th transistor (M5) of a control circuit section that supplies a control signal to a current source switches (swiping) a connection between a2 nd DATA signal (DATA 2) and a2 nd node (N2) according to a2 nd programming signal (PGM 2).
The 1 st transistor (M1) has an N type (positive type), the gate of the 1 st transistor (M1) is connected to the 1 st node (N1), the drain of the 1 st transistor (M1) is connected to the light-emitting high potential voltage (EVDD), and the source of the 1 st transistor (M1) is connected to the 1 st node (N2).
The 2 nd transistor (M2) has a P-type (active type), the gate of the 2 nd transistor (M2) is connected to the emission signal (EM), the source of the 2 nd transistor (M2) is connected to the 3 rd node (N3), and the drain of the 2 nd transistor (M2) is connected to the emission low potential voltage (EVSS).
The 3 rd transistor (M3) has an N-type, the gate of the 3 rd transistor (M3) is connected to the test signal (TE), the drain of the 3 rd transistor (M3) is connected to the 2 nd node (N2), and the source of the 3 rd transistor (M3) is connected to the 3 rd node (N3).
The 4 th transistor (M4) has an N-type, the gate of the 4 th transistor (M4) is connected to the 1 st program signal (PGM 1), the drain of the 4 th transistor (M4) is connected to the 1 st DATA signal (DATA 1), and the source of the 4 th transistor (M4) is connected to the 1 st node (N1).
The 5 th transistor (M5) has an N type, the gate of the 5 th transistor (M5) is connected to the 2 nd program signal (PGM 2), the drain of the 5 th transistor (M5) is connected to the 2 nd DATA signal (DATA 2), and the source of the 5 th transistor (M5) is connected to the 2 nd node (N2).
The 1 st electrode and the 2 nd electrode of the 1 st capacitor (C1) of the control circuit section for supplying a control signal to the current source are connected to the 1 st and 2 nd nodes (N1, N2), respectively.
The positive and negative electrodes of the light emitting diode (Del) are connected to the 2 nd and 3 rd nodes (N2, N3), respectively.
The gate of the 1 st transistor (M1), the source of the 4 th transistor (M4), the 1 st electrode of the 1 st capacitor (C1) constitute the 1 st node (N1),
the source of the 1 st transistor, the drain of the 3 rd transistor (M3), the source of the 5 th transistor (M5), the 2 nd electrode of the 1 st capacitor (C1), the anode of the light emitting diode (Del) forms the 2 nd node (N2),
the source of transistor 2 (M2), the source of transistor 3 (M3), and the cathode of the light emitting diode (Del) form node 3 (N3).
The light emitting diode display device according to embodiment 7 of the present invention can operate in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, and defects of the 1 st to 5 th transistors (M1 to M5) are detected by using the 1 st and 2 nd DATA signals (DATA 1, DATA 2), the 1 st and 2 nd program signals (PGM 1, PGM 2), and the light emitting signal (EM).
In this case, in the manufacturing process, when the light emitting diode (Del) is connected between the 2 nd and 3 rd nodes (N2, N3), the 3 rd transistor (M3) rotates (turn-on) to detect whether the elements other than the light emitting diode (Del) are operating normally.
In the manufacturing process, after the light emitting diode (Del) is connected between the 2 nd and 3 rd nodes (N2 and N3), the third transistor (M3) may be rotated (turn-on) to detect whether the elements other than the light emitting diode (Del) are operating normally in order to make the voltage difference between the 2 nd and 3 rd nodes (N2 and N3) smaller than the light emitting threshold voltage of the light emitting diode (Del).
As described above, in the light emitting diode display device according to embodiment 7 of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode, respectively, and by using the 4 th and 5 th transistors (M4, M5), the 1 st and 2 nd transistors (M1, M2) are operated by the current source and the source, respectively, irrespective of the fluctuation of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), a certain current can be caused to flow through the light emitting diode (Del), with the result that the uniformity of the light emission luminance can be improved.
In addition, the 3 rd transistor (M3) is connected to the positive and negative electrodes of the light emitting diode (Del), and the 3 rd transistor (M3) is switched (turn-on), so that defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.
In the 7 th embodiment of fig. 16, the 2 nd transistor (M2) is connected between the cathode of the light emitting diode (Del) and the light emitting low potential voltage (EVSS) as an example, but in other embodiments similar to fig. 14 and 15, the 2 nd transistor (M2) is omitted, the cathode of the light emitting diode (Del) may be directly connected to the light emitting low potential voltage (EVSS), in which case the source of the 3 rd transistor (M3) may be connected to the Test (TM) instead of the 3 rd node (3).
In other embodiments, the 4 th and 5 th transistors may be switched (swiping) as one signal and will be described with reference to the drawings.
Fig. 17 is a schematic diagram of a pixel of a light emitting diode display device according to embodiment 8 of the present invention, fig. 18 is a waveform diagram showing signals utilized in a light emitting portion of the pixel of the light emitting diode display device according to embodiment 8 of the present invention, and descriptions of the same portions as those of embodiments 1 to 7 are omitted.
As shown in fig. 17, the light emitting portion of the pixel (P) of the light emitting diode display device according to embodiment 8 of the present invention includes the 1 st, 3 rd to 5 th transistors (M1, M3 to M5) of the N type, the 2 nd transistor (M2) of the N type, the 1 st capacitor (C1), and the light emitting diode (Del).
A1 st transistor (M1) for operating a current source for flowing a constant current through the light emitting diode (Del), wherein the connection between the light emitting high potential voltage (EVDD) and the light emitting diode (Del) is switched (swiping) according to the voltage of the 1 st node (N1), and a2 nd transistor (M2) for operating a current source for flowing a constant current through the light emitting diode (Del) switches the connection between the light emitting diode (Del) and the light emitting low potential voltage (EVSS) according to the voltage of the 3 rd node (N3), wherein the 3 rd transistor (M3) switches the connection between the positive electrode and the negative electrode of the light emitting diode (Del) according to the test signal (TE).
A4 th transistor (M4) of the control circuit section supplying the control signal to the current source switches (sways) the connection between the 1 st DATA signal (DATA 1) and the 1 st node (N1) according to the programming signal (PGM), and a fifth transistor (M5) of the control circuit section supplying the control signal to the current source switches (sways) the connection between the 2 nd DATA signal (DATA 2) and the 2 nd node (N2) according to the programming signal (PGM).
The 1 st transistor (M1) has an N type (positive type), the gate of the 1 st transistor (M1) is connected to the 1 st node (N1), the drain of the 1 st transistor (M1) is connected to the light-emitting high potential voltage (EVDD), and the source of the 1 st transistor (M1) is connected to the 2 nd node (N2).
The 2 nd transistor (M2) has a P-type (active type), the gate of the 2 nd transistor (M2) is connected to the emission signal (EM), the source of the 2 nd transistor (M2) is connected to the 3 rd node (N3), and the drain of the 2 nd transistor (M2) is connected to the emission low potential voltage (EVSS).
The 3 rd transistor (M3) has an N-type, the gate of the 3 rd transistor (M3) is connected to the test signal (TE), the drain of the 3 rd transistor (M3) is connected to the 2 nd node (N2), and the source of the 3 rd transistor (M3) is connected to the 3 rd node (N3).
The 4 th transistor (M4) has an N-type, the gate of the 4 th transistor (M4) is connected to the program signal (PGM 1), the drain of the 4 th transistor (M4) is connected to the 1 st DATA signal (DATA 1), and the source of the 4 th transistor (M4) is connected to the 1 st node (N1).
The 5 th transistor (M5) has an N type, a gate of the 5 th transistor (M5) is connected to the program signal (PGM), a drain of the 5 th transistor (M5) is connected to the 2 nd DATA signal (DATA 2), and a source of the 5 th transistor (M5) is connected to the 2 nd node (N2).
The 1 st electrode and the 2 nd electrode of the 1 st capacitor (C1) of the control circuit section for supplying a control signal to the current source are connected to the 1 st and 2 nd nodes (N1, N2), respectively.
The positive and negative electrodes of the light emitting diode (Del) are connected to the 2 nd and 3 rd nodes (N2, N3), respectively.
The gate of the 1 st transistor (M1), the source of the 4 th transistor (M4), the 1 st electrode of the 1 st capacitor (C1) constitute the 1 st node (N1),
the source of the 1 st transistor, the drain of the 3 rd transistor (M3), the source of the 5 th transistor (M5), the 2 nd electrode of the 1 st capacitor (C1), the anode of the light emitting diode (Del) forms the 2 nd node (N2),
the source of transistor 2 (M2), the source of transistor 3 (M3), and the cathode of the light emitting diode (Del) form node 3 (N3).
The light emitting diode display device according to embodiment 8 of the present invention can be operated in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, and defects of the 1 st to 5 th transistors (M1 to M5) are detected using the 1 st and 2 nd DATA signals (DATA 1, DATA 2), the program signal (PGM), and the light emitting signal (EM).
Before the connection between the 2 nd and 3 rd nodes (N2, N3), in the manufacturing process, when the light emitting diode (Del) is connected after the 2 nd and 3 rd nodes (N2, N3), in order to make the voltage difference between the 2 nd and 3 rd nodes (N2, N3) smaller than the light emitting threshold voltage of the light emitting diode (Del), the third transistor (M3) may be rotated (turn-on) to detect whether the elements other than the light emitting diode (Del) are operating normally.
As shown in fig. 18, the 1 st DATA signal (DATA 1) has an active (valid) interval for each frame, the 2 nd DATA signal (DATA 2) has a low level, the light-emitting signal (EM) has a high level during a non-light-emitting interval (Tne) corresponding to an active interval of a current frame of the 1 st DATA signal (DATA 1), has a low level during a light-emitting interval (Tem) other than the non-light-emitting interval (Tne), and the program signal (PGM) has a high level during a program interval (Tpg) corresponding to an active interval of a current frame of the 1 st DATA signal (DATA 1).
Therefore, during the non-light emitting interval (Tne), the second transistor (M2) is switched (turn-off), and the light emitting diode (Del) does not emit light.
During the programming section (Tpg), the 4 th and 5 th transistors (M4, M5) are turned on (turn-on) and the 1 st and 2 nd DATA signals (DATA 1, DATA 2) are respectively sent to the 1 st and 2 nd nodes (N1, N2), with the result that the 1 st capacitor (C1) stores the voltage difference of the 1 st and 2 nd DATA signals (DATA 1, DATA 2).
During the light emission interval (Tem), the 1 st transistor (M1) rotates (turn-on) according to the 1 st and 2 nd DATA signals (DATA 1, DATA 2) of the 1 st capacitor (C1) due to a voltage difference to supply a current source (current source) of a constant current, and the 2 nd transistor (M2) rotates (turn-on) to operate as a source follower (source follower) of a constant current.
Therefore, the light emitting diode (Del) emits light of uniform brightness by a constant current regardless of the variation of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS).
As described above, in the light emitting diode display device according to embodiment 8 of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode, respectively, and by using the 4 th and 5 th transistors (M4, M5), the 1 st and 2 nd transistors (M1, M2) operate as a current source and a source follower, respectively, irrespective of variations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), a constant current can be caused to flow through the light emitting diode (Del), with the result that uniformity of light emission luminance can be improved.
In addition, the 3 rd transistor (M3) is connected to the positive and negative electrodes of the light emitting diode (Del), and the 3 rd transistor (M3) is switched (turn-on), so that defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.
In the 8 th embodiment of fig. 17, the 2 nd transistor (M2) is connected between the negative electrode of the light emitting diode (Del) and the light emitting low potential voltage (EVSS) as an example, but in other embodiments, the 2 nd transistor (M2) is omitted, the negative electrode of the light emitting diode (Del) may be directly connected to the light emitting low potential voltage (EVSS), in which case the source of the 3 rd transistor (M3) may be connected to the test voltage (TM) instead of the 3 rd node (N3).
In other embodiments, the voltage of the 2 nd electrode of the 1 st capacitor may be fixed and described with reference to the drawings.
Fig. 19 is a schematic view of a light emitting portion of a pixel of a light emitting diode display device according to embodiment 9 of the present invention, fig. 20 is a waveform diagram showing signals utilized in the light emitting portion of the pixel of the light emitting diode display device according to embodiment 9 of the present invention, and the description of the same portions as those of embodiments 1 to 8 is omitted.
As shown in fig. 19, the light emitting portion of the pixel (P) of the light emitting diode display device according to embodiment 9 of the present invention includes the 1 st, 3 rd to 5 th transistors (M1, M3 to M5) of the N type, the 2 nd transistor (M2) of the N type, the 1 st capacitor (C1), and the light emitting diode (Del).
A 1 st transistor (M1) for operating a current source for flowing a constant current through the light emitting diode (Del), a connection between the (switching) light emitting high potential voltage (EVDD) and the light emitting diode (EVSD) is switched according to the voltage of the 1 st node (N1), a 2 nd transistor (M2) for operating a current source for flowing a constant current through the light emitting diode (Del), a connection between the (switching) light emitting diode and the light emitting low potential voltage (EVSS) is switched according to the voltage of the 3 rd node (N3), and a connection between the positive electrode and the negative electrode of the (switching) light emitting diode (Del) is switched according to the test signal (TE).
A4 th transistor (M4) of the control circuit unit supplying the control signal to the current source switches (sways) the connection between the DATA signal (DATA) and the 1 st node (N1) according to the programming signal (PGM), and a 5 th transistor (M5) of the control circuit unit supplying the control signal to the current source switches (sways) the connection between the reference signal (REF) and the 2 nd node (N2) according to the sensing Signal (SE).
The 1 st transistor (M1) has an N type (positive type), the gate of the 1 st transistor (M1) is connected to the 1 st node (N1), the drain of the 1 st transistor (M1) is connected to the light-emitting high potential voltage (EVDD), and the source of the 1 st transistor (M1) is connected to the 2 nd node (N2).
The 2 nd transistor (M2) has a P-type (active type), the gate of the 2 nd transistor (M2) is connected to the emission signal (EM), the source of the 2 nd transistor (M2) is connected to the 3 rd node (N3), and the drain of the 2 nd transistor (M2) is connected to the emission low potential voltage (EVSS).
The 3 rd transistor (M3) has an N-type, the gate of the 3 rd transistor (M3) is connected to the test signal (TE), the drain of the 3 rd transistor (M3) is connected to the 2 nd node (N2), and the source of the 3 rd transistor (M3) is connected to the 3 rd node (N3).
The 4 th transistor (M4) has an N-type, a gate of the 4 th transistor (M4) is connected to the program signal (PGM), a drain of the 4 th transistor (M4) is connected to the DATA signal (DATA), and a source of the 4 th transistor (M4) is connected to the 1 st node (N1).
The 5 th transistor (M5) has an N-type, the gate of the 5 th transistor (M5) is connected to the sensing Signal (SE), the drain of the 5 th transistor (M5) is connected to the reference signal (REF) and the 2 nd electrode of the 1 st capacitor, and the source of the 5 th transistor (M5) is connected to the 2 nd node (N2).
The 1 st electrode of the 1 st capacitor (C1) of the control circuit section for supplying a control signal to the current source is connected to the 1 st node (N1), and the 2 nd electrode of the 1 st capacitor (C1) is connected to the reference signal (REF) and the drain of the 5 th transistor (M5).
The positive and negative electrodes of the light emitting diode (Del) are connected to the second and third nodes (N2, N3), respectively.
The gate of the 1 st transistor (M1), the source of the 4 th transistor (M4), the 1 st electrode of the 1 st capacitor (C1) constitute the 1 st node (N1),
the source of the 1 st transistor, the drain of the 3 rd transistor (M3), the source of the 5 th transistor (M5), the anode of the light emitting diode (Del) forms the 2 nd node (N2),
the source of transistor 2 (M2), the source of transistor 3 (M3), and the cathode of the light emitting diode (Del) form node 3 (N3).
The light emitting diode display device according to embodiment 9 of the present invention can be operated in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, and defects of the 1 st to 5 th transistors (M1 to M5) are detected by the DATA signal (DATA), the sensing Signal (SE), the programming signal (PGM), and the light emitting signal (EM).
In the manufacturing process, before the light emitting diode (Del) is connected between the 2 nd and 3 rd nodes (N2, N3), the third transistor (M3) is turned on (turn-on) to detect whether the element other than the light emitting diode (Del) is operating normally.
In the manufacturing process, after the light emitting diode (Del) is connected between the 2 nd and 3 rd nodes (N2 and N3), in this case, in order to make the voltage difference between the 2 nd and 3 rd nodes (N2 and N3) smaller than the light emitting threshold voltage of the light emitting diode (Del), the third transistor (M3) is rotated (turn-on) to detect whether the elements other than the light emitting diode (Del) are operating normally.
As shown in fig. 20, the DATA signal (DATA) has an active (valid) interval in each frame, the light-emitting signal (EM) has a high level during a non-light-emitting interval (Tne) corresponding to an active interval of a current frame of the DATA signal (DATA), has a low level during a light-emitting interval (Tem) other than the non-light-emitting interval (Tne), the program signal (PGM) has a high level within a programming interval corresponding to an active interval of a current frame of the DATA signal, has a high level in an active interval of the current frame, and the sense Signal (SE) has a high level during a sense interval (SE) corresponding to an active interval of a current frame of the DATA signal (DATA).
Therefore, during the non-light emitting interval (Tne), the 2 nd transistor (M2) is switched (turn-off), and the light emitting diode (Del) does not emit light.
During the programming interval (Tpg), the 4 th transistor (M4) is turned on (turn-on), the DATA signal (DATA) is transferred to the 1 st node (N1), and the voltage of the 2 nd electrode of the 1 st capacitor (C1) is maintained to be the reference signal (REF) to some extent, with the result that the voltage difference of the DATA signal (DATA) and the reference signal (REF) is stored in the 1 st capacitor (C1).
During the sensing period (SE), the fifth transistor (M5) is turned on (turn-on), a reference signal (REF) is sent to the 2 nd node (N2), and as a result, the anode of the light emitting diode (Del) is initialized, thereby improving the characteristics of the video response time (moving picture response time).
During the light emission section (Tem), the 1 st transistor (M1) is switched according to the DATA signal (DATA) of the 1 st capacitor (C1) to operate with a source follower (source follower) through which a certain current flows, and the 2 nd transistor (M2) is operated with a source follower (turn-on) through which a certain current flows. Therefore, the light emitting diode (Del) emits light of uniform brightness by a constant current regardless of the variation of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS).
Here, the current of the light emitting diode (Del) is determined by the voltage difference between the 1 st and 2 nd transistors (M1, M2) operated by the source follower, and when the pixel (P) includes the light emitting diode (Del) emitting red light, green light, blue light, the current reflecting the difference in the operating characteristics of the red, green, blue light emitting diodes (Del) can be directed to the light emitting diode (Del) by adjusting the aspect ratio (aspect ratio) of the 1 st and 2 nd transistors (M1, M2).
As described above, in the light emitting diode display device according to embodiment 9 of the present invention, the 1 st and 2 nd transistors (M1, M2) are connected to the positive electrode and the negative electrode of the light emitting diode, respectively, and the 4 th and 5 th transistors (M4, M5) are used, respectively, and the 1 st and 2 nd transistors (M1, M2) operate as source followers, irrespective of variations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), respectively, and as a result, a constant current can be caused to flow through the light emitting diode (Del), with the result that uniformity of light emission luminance can be improved.
In addition, the 3 rd transistor (M3) is connected to the positive and negative electrodes of the light emitting diode (Del), and the 3 rd transistor (M3) is switched (turn-on), so that defects in the manufacturing process can be detected and repaired, and as a result, the manufacturing cost can be reduced.
In embodiment 9 of fig. 19, the 2 nd transistor (M2) is connected between the cathode of the light emitting diode (Del) and the light emitting low potential voltage (EVSS) as an example, but in other embodiments, the 2 nd transistor (M2) is omitted, the cathode of the light emitting diode (Del) may be directly connected to the light emitting low potential voltage (EVSS), in which case the source of the 3 rd transistor (M3) may be connected to the test voltage (TM) instead of the 3 rd node (N3).
In other embodiments, each pixel may be composed of a latch and a light emitting portion, and will be described with reference to the drawings.
Fig. 21 is a schematic diagram of a pixel of a light emitting diode display device according to embodiment 10 of the present invention, fig. 22 is a waveform diagram of a signal of a pixel of a light emitting diode display device according to embodiment 10 of the present invention, and the description of the same parts as those of embodiments 1 to 9 is omitted.
As shown in fig. 21, a pixel (P) of a light emitting diode display device according to embodiment 10 of the present invention includes a latch (172), a light emitting portion (178), the latch (172) including 1 st to 7 th digital transistors (Q1 to Q7), the light emitting portion (178) including 1 st, 3 rd, 4 th to 7 th transistors (M1, M3, M4 to M7), a 1 st capacitor (C1), and a light emitting diode (Del).
A latch (172), 4 th to 7 th transistors (M4 to M7), a 1 st capacitor (C1) constitutes a control circuit section that supplies a control signal to the 1 st transistor (M1) as a current source, the 1 st, 4 th, 6 th digital transistors (Q1, Q4, Q6) have P-type, the 2 nd, 3 rd, 5 th, 7 th digital transistors (Q2, Q3, Q5, Q7) have N-type, the 1 st, 6 th transistors (M1, M6) have P-type, the 3 rd to 5 th, and the 7 th transistors (M3 to M5 and M7) have N-type.
The 1 st digital transistor (Q1) switches (swaying) the connection between the 1 st output signal and the gates of the fourth and fifth digital transistors (Q4, Q5) according to a programming signal (PGM) which is a signal for inputting the image data (RGB) in the latch (172), and the 2 nd digital transistor (Q2) switches (swaying) the connection between the image data (RGB) and the gates of the 4 th and 5 th digital transistors (Q4, Q5) according to the programming signal (PGM).
The 3 rd digital transistor (Q3) resets the signal of the latch (172) according to the Reset Signal (RS), and switches (swaying) the connection between the digital low potential Voltage (VSS) and the gates of the 4 th and 5 th digital transistors (Q4, Q5) according to the Reset Signal (RS).
In other embodiments, the Reset Signal (RS) and the third digital transistor (Q3) may be omitted.
The 4 th digital transistor (Q4) switches (swaying) the connection between the digital high potential Voltage (VCC) and the 2 nd output signal according to the 1 st output signal or the digital low potential Voltage (VSS),
the 5 th digital transistor (Q5) switches (swaying) the connection between the digital low potential Voltage (VSS) and the 2 nd output signal according to the 1 st output signal or the digital low potential Voltage (VSS),
the 6 th digital transistor (Q6) switches (swaying) the connection between the digital high potential Voltage (VCC) and the first output signal according to the 2 nd output signal,
a7 th digital transistor (Q7) switches (swaying) a connection between the digital low potential Voltage (VSS) and the second output signal according to the 2 nd output signal.
The 1 st transistor (M1) serves as a current source for allowing a light emitting diode (Del) to flow a certain current, and the connection between the 6 th transistor (M6) and the 7 th transistor (M7) is switched (swiping) according to the voltage of the 1 st node (N1), and the 3 rd transistor (M3) switches (swiping) the connection between the drain of the 7 th transistor (M7) and the test voltage (TM) according to the test signal (TE).
The gate of the 1 st transistor (M1) is connected to the 2 nd electrode of the 1 st capacitor (C1) and the 5 th transistor (M5) to constitute the 1 st node (N1), the source of the 1 st transistor (M1) is connected to the 1 st electrode of the 1 st capacitor (C1) and the 6 th transistor (M6), and the drain of the 1 st transistor (M1) is connected to the 3 rd transistor (M3) and the 7 th transistor (5M 7) to constitute the second node N2).
The 4 th transistor (M4) switches (swaying) the connection between the 1 st output signal and the 1 st electrode of the 1 st capacitor (C1) according to the reference signal (RF),
the 5 th transistor (M5) switches (swaying) the connection between the 2 nd output signal and the 1 st node (N1) according to the reference signal (RF).
The 6 th transistor (M6) switches (swiping) the connection between the light-emitting high potential voltage (EVDD) and the 1 st transistor (M1) according to the 1 st light-emitting signal (EM 1),
the 7 th transistor (M7) switches (swaying) the connection between the 1 st transistor (M1) and the light emitting diode (Del) according to the 2 nd light emitting signal (EM 2).
The 1 st electrode of the 1 st capacitor (C1) is connected to the 1 st transistor (M1), the 4 th transistor (M4) and the 6 th transistor (M6),
the 2 nd electrode of the 1 st capacitor (C1) is connected to the 1 st node (N1),
the positive electrode of the light-emitting 2-pole transistor (Del) is connected to the 7 th transistor (M7),
the negative electrode of the light-emitting 2-pole tube (Del) is connected to a light-emitting low potential voltage (EVSS).
The light emitting diode display device according to embodiment 10 of the present invention can operate in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, the 2 nd node (N2) is initialized to the test voltage (TM) to prevent a decrease to a certain voltage from being less than full, or the characteristics of the 1 st transistor (M1) or the light emitting diode (Del) may be measured.
In this case, the third transistor (M3) is turned to temperature (turn-on) before the light emitting diode (Del) is connected to the second node (N2) in the manufacturing process, so that it is possible to detect whether the element other than the light emitting diode (Del) is operating normally.
During the manufacturing process, after the light emitting diode (Del) is connected to the 2 nd node (N2), in this case, the voltage difference between the 2 nd and 3 rd nodes (N2, N3) is smaller than the light emitting threshold voltage of the light emitting diode (Del), so that the 3 rd transistor (M3) can be rotated (turn-on) to detect whether the elements other than the light emitting diode (Del) are operating normally.
As shown in fig. 22, between the 1 st and 2 nd timings (T1 and T2), the 3 rd digital transistor (Q3) is turned on (turn-on) according to the Reset Signal (RS) of the high level, and the gates of the 4 th and 5 th digital transistors (Q4, Q5) are reset to the digital low potential Voltage (VSS).
The image data (RGB) is input to the latch (172) according to a high level programming signal (PGM) between the 3 rd and 4 th timings (T3, T4), and the 1 st and 2 nd output signals are output from the latch (172).
Between the 5 th and 10 th timings (T5, T10), the 7 th transistor (M7) is switched (turn-off) according to the 2 nd light emission signal (EM 2) of the low level, and between the 6 th and 9 th timings (T6, T9), the 6 th transistor (M6) is switched (turn-off) according to the 1 st light emission signal (EM 1) of the high level, and the light emitting diode (Del) becomes a non-light emitting state.
Between the 7 th and 8 th timings (T7, T8), the 4 th and 5 th transistors (M4, M5) are turned on (turn-on) according to a high level reference signal (RF), and the 1 st and 2 nd output signals of the latch (172) are transferred to the source and gate of the 1 st transistor (M1), respectively.
In the 9 th and 10 th timings (T9, T10), the 6 th and 7 th transistors (M6 and M7) are turned on (turn-on), respectively, and the light emitting diode (Del) is in a light emitting state.
Therefore, the 1 st transistor (M1) is switched (turn-on) according to the 2 nd output signal of the 1 st capacitor (C1) to operate with a source follower (source follower) through which a certain current flows, and the light emitting diode (Del) emits light of uniform brightness according to the certain current irrespective of the variation of the light emitting high potential voltage (EVDD) and the light emitting low potential voltage (EVSS).
Here, the current of the light emitting diode (Del) is determined by the voltage difference between the 1 st transistor (M1) operating as a source follower and the light emitting low potential voltage (EVSS), and when the pixel (P) includes the light emitting diode (Del) emitting red, green, and blue light, the current reflecting the difference in the operating characteristics of the red, green, and blue light emitting diodes (Del) can be made to flow to the light emitting diode by adjusting the aspect ratio (aspect ratio) of the 1 st transistor (M1).
As described above, in the light emitting diode display device according to embodiment 10 of the present invention, the 1 st transistor (M1) is connected to both poles of the light emitting diode (Del), and by operating the 1 st transistor (M1) as a source follower with the 4 th and 5 th transistors (M4 and M5), a certain current can be caused to flow through the light emitting diode (Del) irrespective of variations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), with the result that uniformity of light emission luminance can be improved.
In addition, by connecting the 3 rd transistor (M3) to the anode of the light emitting diode (Del) and the 3 rd transistor (M3) is switched (turn-on), defects in the manufacturing process can be detected and repaired, with the result that manufacturing costs can be reduced.
In other embodiments, the 1 st transistor (M1) of the N type may be connected to the 4 th transistor (T4), and will be described with reference to the drawings.
Fig. 23 is a schematic view of a pixel of a light emitting diode display device according to embodiment 11 of the present invention, and the description of the same parts as those of embodiments 1 to 10 is omitted.
As shown in fig. 23, a pixel (P) of a light emitting diode display device according to embodiment 11 of the present invention includes a latch (172) and a light emitting portion (178), the latch (172) includes 1 st to 7 th digital transistors (Q1 to Q7), and the light emitting unit (178) includes 1 st, 3 rd to 7 th transistors (M1, M3 to M7), 1 st capacitor (C1), and a light emitting diode (Del).
The latch (172), the 4 th to 7 th transistors (M4 to M7), the 1 st capacitor (C1) constitutes a control circuit section that supplies a control signal to the current source, the 1 st, 4 th, 6 th digital transistors (Q1, Q4, Q6) have P-type, the 2 nd, 3 rd, 5 th, 7 th digital transistors (Q2, Q3, Q5, Q7) have N-type, and the constitution and operation of the latch (172) for each pixel (P) of the light emitting diode display device according to the 11 th embodiment are the same as those of the latch (172) for each pixel (P) of the light emitting diode display device according to the 10 th embodiment.
The 6 th transistor (M6) has a P-type, the 1 st 3 rd to 5 th, and the 7 th transistors (M1, M3 to M5, M7) have an N-type.
The 1 st transistor (M1) serves as a current source for allowing a light emitting diode (Del) to flow a certain current, the connection between the 6 th transistor (M6) and the 7 th transistor (M7) is switched according to the voltage of the 1 st node (N1), and the 3 rd transistor (M3) switches (swaying) the connection between the drain of the 7 th transistor (M7) and the test voltage (TM) according to the test signal (TE).
The gate of the 1 st transistor (M1) is connected to the 1 st electrode of the 1 st capacitor (C1) and the fourth transistor (M4) to constitute the 1 st node (N1), the drain of the 1 st transistor (M1) is connected to the 6 th transistor (M6), the source of the 1 st transistor (M1) is connected to the 2 nd electrode of the first capacitor (C1), the 3 rd transistor (M3), the 5 th transistor (M5) and the 7 th transistor (M7) to constitute the 2 nd node (N2).
The 4 th transistor (M4) switches (swaying) the connection between the 1 st output signal and the 1 st node (N1) according to the reference signal (RF), and the 5 th transistor (M5) switches (swaying) the connection between the 2 nd output signal and the 2 nd node (N2) according to the reference signal (RF).
The 6 th transistor (M6) switches (swiping) the connection between the light-emitting high potential voltage (EVDD) and the 1 st transistor (M1) according to the 1 st light-emitting signal (EM 1), and the 7 th transistor (M7) switches (swiping) the connection between the 1 st transistor (M1) and the light-emitting diode (Del) according to the 2 nd light-emitting signal (EM 2).
A first electrode of the 1 st capacitor (C1) is connected to the first node (N1), a 2 nd electrode of the 1 st capacitor (C1) is connected to the 2 nd node (N2),
the positive electrode of the light-emitting 2-pole transistor (Del) is connected to the 7 th transistor (M7),
the cathode of the light emitting 2-pole tube (Del) is connected to a light emitting low potential voltage (EVSS).
The light emitting diode display device according to embodiment 11 of the present invention can be operated in a display mode and a test mode.
In the display mode, the 3 rd transistor (M3) is switched (turn-off), the light emitting diode (Del) emits light, and the led display device displays an image.
In the test mode, the 3 rd transistor (M3) is turned on (turn-on), the light emitting diode (Del) does not emit light, the 2 nd node (N2) is initialized to the test voltage (TM) to prevent a decrease to a certain voltage from being less than full, or the characteristics of the 1 st transistor (M1) or the light emitting diode (Del) may be measured.
Here, in the manufacturing process, before the light emitting diode (Del) is connected to the 2 nd node (N2), in this case, the 3 rd transistor (M3) may be turned to temperature (turn-on) to detect whether or not elements other than the light emitting diode (Del) are operating normally.
During the manufacturing process, after the light emitting diode (Del) is connected to the 2 nd node (N2), in this case, the voltage difference between the 2 nd and 3 rd nodes (N2, N3) is smaller than the light emitting threshold voltage of the light emitting diode (Del), so that the 3 rd transistor (M3) can be rotated (turn-on) to detect whether the elements other than the light emitting diode (Del) are operating normally.
The light emitting diode display device according to embodiment 11 of the present invention operates according to the waveform diagram of fig. 22.
As described above, in the light emitting diode display device according to embodiment 11 of the present invention, the 1 st transistor (M1) is connected to the positive electrode of the light emitting diode (Del), and by operating the 1 st transistor (M1) as a source follower with the fourth and 5 th transistors (M4 and M5), a certain current can be caused to flow through the light emitting diode (Del) irrespective of variations in the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS), with the result that uniformity of light emission luminance can be improved.
In addition, by connecting the third transistor (M3) to the positive electrode of the light emitting diode (Del), and switching (turn-on) the 3 rd transistor (M3), defects in the manufacturing process can be detected and repaired, and as a result, manufacturing performance can be reduced.
In other embodiments, the current source may be disposed at one of the anode and cathode of the light emitting diode, which is described with reference to the drawings.
Fig. 24 and 25 are pixel diagrams of light emitting diode display devices according to embodiments 12 and 13 of the present invention, respectively, and the descriptions of the same parts as those of embodiments 1 to 11 are omitted.
As shown in fig. 24, a pixel (P) of a light emitting diode display device according to embodiment 12 of the present invention includes a latch (172), a level shifter (174), a current source (182) and a light emitting diode (Del), the latch (172) and the level shifter (174) constituting a control circuit portion that supplies a control signal to the current source (182), and the current source (182) and the light emitting diode (Del) constituting a light emitting portion.
The latch (172) receives the image data (RGB), the program signal (PGM), and the Reset Signal (RS), and outputs the 1 st and 2 nd output signals, which may be inverted signals, using the digital high Voltage (VCC) and the digital low Voltage (VSS).
In other embodiments, the Reset Signal (RS) may be omitted.
The level shifter (174) receives the 1 st and 2 nd output signals and outputs the 3 rd and 4 th output signals using a latch high voltage (PVDD) and a latch low voltage (PVSS), and the 3 rd and 4 th output signals may be inverted signals.
A current source (182) receives at least one of the 3 rd and 4 th output signals, is connected to the anode of the light emitting diode (Del), and causes the light emitting diode (Del) to flow a certain current using at least one of the 3 rd and 4 th output signals.
For example, the latch (172) and the level shifter (174) include a plurality of transistors, and the current source (182) may include a transistor and a capacitor.
When the level shifter (174) outputs the 3 rd and 4 th output signals using the 1 st and 2 nd signals of the latch (172) of the digital storage concept, in this case, the direct bypass current in the level shifter (174) can be prevented and the light emitting diode (Del) can emit light of a certain brightness.
Here, the image data (RGB) inputted to the latch (172) has a digital type of digital voltage level.
As shown in fig. 25, a pixel (P) of a light emitting diode display device according to embodiment 13 of the present invention includes a latch (172), a level shifter (174), a current source (184), and a light emitting diode (Del), the latch (172) and the level shifter (174) constitute a control circuit portion that supplies a control signal to the current source (184), and the current source (184) and the light emitting diode (Del) constitute a light emitting portion.
The latch (172) receives the image data (RGB), the program signal (PGM), and the Reset Signal (RS), and outputs the first and second output signals using the digital high Voltage (VCC) and the digital low Voltage (VSS), and the 1 st and 2 nd output signals may be inverted signals.
In other embodiments, the Reset Signal (RS) may be omitted.
The level shifter (174) receives the 1 st and 2 nd output signals and outputs the 3 rd and 4 th output signals using a latch high voltage (PVDD) and a latch low voltage (PVSS), and the 3 rd and 4 th output signals may be inverted signals.
A current source (184) receives at least one of the 3 rd and 4 th output signals, is connected to the cathode of the light emitting diode (Del), and causes the light emitting diode (Del) to flow a current using at least one of the 3 rd and 4 th output signals.
For example, the latch (172) and the level shifter (174) include a plurality of transistors, and the current source (182) may include a transistor and a capacitor.
When the level shifter (174) outputs the 3 rd and 4 th output signals using the 1 st and 2 nd signals of the latch (172) of the digital storage concept, the direct current bypass current in the level shifter (174) can be prevented and the light emitting diode (Del) can emit light of a certain brightness.
Here, the image data (RGB) inputted to the latch (172) has a digital type of digital voltage level.
As described above, in the pixel (P) of the light emitting diode display device according to the 12 th and 13 th embodiments of the present invention, the 1 st and 2 nd output signals of a certain dc voltage level are output to prevent the latch (172) from generating flicker (flicker) or the like, and the level shifter (174) applies at least one of the 3 rd and 4 th output signals required for light emission to the current sources (182, 184), and a certain current can be made to flow through the light emitting diode (Del) irrespective of the variations of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS).
In other embodiments, the output signal of the level shifter may be stored in a latch and then provided to a current source and described with reference to the drawings.
Fig. 26 is a schematic diagram of a pixel of a light emitting diode display device according to embodiment 14 of the present invention, fig. 27 is a level shifter diagram of a pixel of a light emitting diode display device according to embodiment 14 of the present invention, and fig. 28 is a schematic waveform diagram of a level shifter signal of a pixel of a light emitting diode display device according to embodiment 14 of the present invention, and the same parts as those of embodiments 1 to 13 are omitted.
As shown in fig. 26, a pixel (P) of a light emitting diode display device according to embodiment 14 of the present invention includes a level shifter (174), a latch (172), 1 st and 2 nd current sources (182, 184), and a light emitting diode (Del), the level shifter (174) and the latch (172) constitute a control circuit portion that supplies control signals to the 1 st and 2 nd current sources (182, 184), and the 1 st and 2 nd current sources (182, 184) and the light emitting diode (Del) constitute a light emitting portion.
The level shifter (174) receives the image data (RGB), the program signal (PGM), and the Reset Signal (RS), and outputs at least one of the 1 st and 2 nd output signals, which may be inverted signals, using the latch high voltage (PVDD) and the latch low voltage (PVSS).
In other embodiments, the Reset Signal (RS) may be omitted.
The latch (172) receives at least one of the 1 st and 2 nd output signals and outputs at least one of the 3 rd and 4 th output signals, which may be inverted signals, using a latch high voltage (PVDD) and a latch low voltage (PVSS).
A current source 1 (182) receives the third output signal, is coupled to the anode of the light emitting diode (Del), and flows a current through the light emitting diode (Del) using the 3 rd output signal.
A2 nd current source (184) receives the fourth output signal, is connected to the cathode of the light emitting diode, and uses the 4 th output signal to cause a current to flow through the light emitting diode (Del).
For example, the level shifter (174) and the latch (172) include a plurality of transistors, and the 1 st and 2 nd current sources (182, 184) may include transistors and capacitors.
The image data (RGB) input to the level shifter (174) has a digital type of digital voltage level.
As shown in fig. 27, the level shifter (174) of the pixel (P) of the light emitting diode display device according to embodiment 14 of the present invention includes 1 st to 9 th digital transistors (Q1 to Q9), 1 st and 2 nd capacitors (C1, C2).
*353 1 st and 2 nd digital transistors (Q1, Q2) have P-type and 3 rd to 9 th digital transistors (Q3 to Q9) have N-type.
The 1 st digital transistor (Q1) switches (swiping) the connection between the pin high voltage (PVDD) and the drain of the 3 rd digital transistor (Q3) according to the 1 st output signal (LSO 1), and the 2 nd digital transistor (Q2) switches (swiping) the connection between the pin high voltage (PVDD) and the drain of the 4 th digital transistor (Q4) according to the 2 nd output signal (LSO 2).
The 3 rd digital transistor (Q3) switches (swiping) a connection between the drain of the 1 st digital transistor (Q1) and the drain of the 9 th digital transistor (Q9) according to the 1 st output signal (LSO 1), and the 4 th digital transistor (Q4) switches (swiping) a connection between the drain of the 2 nd digital transistor (Q2) and the drain of the 9 th digital transistor (Q9) according to the 2 nd output signal (LSO 2).
The 5 th digital transistor (Q5) switches (swiping) the connection between the drain of the 1 st digital transistor (Q1) and the drain of the 9 th digital transistor (Q9) according to the voltage of the 1 st electrode of the 1 st capacitor (C1), and the 6 th digital transistor (Q6) switches (swiping) the connection between the drain of the 2 nd digital transistor (Q2) and the drain of the 9 th digital transistor (Q9) according to the voltage of the 1 st electrode of the 2 nd capacitor (C2).
The 7 th digital transistor (Q7) switches (swaying) the connection between the 1 st video data (RGB 1) and the gate of the 5 th digital transistor (Q5) according to the program signal (PGM) at the signal of the level shifter (174) input the first and second video data (RGB 1, RGB 2).
And the 8 th digital transistor (Q8) switches (swaying) the connection between the 2 nd image data (RGB 2) and the gate of the 6 th digital transistor (Q6) according to the program signal (PGM).
The 9 th digital transistor (Q9) switches (swaying) the connection between the sources of the 3 rd to 6 th digital transistors (Q3 to Q6) and the latch low Potential Voltage (PVSS) according to a signal Enable signal (LSE) outputted from the active level shifter (174).
The 1 st capacitor (C1) is connected between the source of the 7 th digital transistor (Q7) and the plug low Potential Voltage (PVSS), and the 2 nd capacitor (C2) is connected between the source of the 8 th digital transistor (Q8) and the plug low Potential Voltage (PVSS).
* As shown in 360 degrees 28, the 1 st and 2 nd image data (RGB 1, RGB 2) have valid intervals for each frame, the sequence design signal (PGM) has a high level during a program interval (Tpg) corresponding to the valid interval of the current frame of the first and second image data (RGB 1, RGB 2), and the Enable signal (LSE) has a high level during the output Enable interval (Toe).
Thus, during the programming section (Tpg), the 7 th and 8 th digital transistors (Q7, Q8) are turned on (turn-on), the 1 st and 2 nd image data (RGB 1, RGB 2) are stored in the 1 st and 2 nd capacitors (C1, C2), respectively, and then the 1 st and 2 nd output signals (LSO 1, LSO 2) valid during the output section (Toe) are output.
Although not shown, the latch (172) may be provided to the light emitting diode (Del) at an appropriate time after storing the 1 st and 2 nd output signals (LSO 1 and LSO 2).
Fig. 29 is a level shifter diagram of a pixel of a light emitting diode display device according to embodiment 15 of the present invention, and fig. 30 is a level shifter signal of a pixel of a light emitting diode display device according to embodiment 15 of the present invention, which is a schematic waveform diagram, and is described with reference to fig. 26.
As shown in fig. 29, the level shifter (174) of the pixel (P) of the light emitting diode display device according to embodiment 15 of the present invention includes 1 st to 6 th digital transistors (Q1 to Q6), 1 st and 2 nd capacitors (C1, C2).
The 1 st and 2 nd digital transistors (Q1, Q2) have P-type and the 3 rd to 6 th digital transistors (Q3 to Q6) have N-type.
The 1 st digital transistor (Q1) switches (swiping) a connection between the pin high Potential Voltage (PVDD) and the drain of the 3 rd digital transistor (Q3) according to the precharge signal (PCG), and the 2 nd digital transistor (Q2) switches (swiping) a connection between the pin high Potential Voltage (PVDD) and the drain of the 4 th digital transistor (Q4) according to the voltage of the 1 st electrode of the 2 nd capacitor (C2).
The 3 rd digital transistor (Q3) switches (swiping) the connection between the drain of the 1 st digital transistor (Q1) and the drain of the 6 th digital transistor (Q6) according to the precharge signal (PCG),
the 4 th digital transistor (Q4) switches (swaps) the connection between the drain of the 2 nd digital transistor (Q2) and the pin low Potential Voltage (PVSS) according to the voltage of the 1 st electrode of the 2 nd capacitor (C2).
The 5 th digital transistor (Q5) switches (swiping) a connection between the video data (RGB) and the gate of the 6 th digital transistor (Q6) according to a program signal (PGM), and the 6 th digital transistor (Q6) switches (swiping) a connection between the source of the 3 rd digital transistor (Q2) and the latch low Potential Voltage (PVSS) according to the voltage of the 1 st electrode of the 1 st capacitor (C1).
The 1 st capacitor (C1) is connected between the source of the 5 th digital transistor (Q5) and the plug low Potential Voltage (PVSS), and the 2 nd capacitor (C2) is connected between the gate of the 2 nd digital transistor (Q2) and the plug low Potential Voltage (PVSS).
An output signal (LSO) is outputted from a node between the drain of the 2 nd digital transistor (Q2) and the drain of the 4 th digital transistor (Q4).
As shown in fig. 30, the image data (RGB) has an active (valid) section for each frame, the precharge signal (PCG) has a low level during a precharge section (Tpc) preceding the active section of the current frame of the image data (RGB), and the program signal (PGM) has a high level during a program section (Tpg) corresponding to the active section of the current frame of the image data (RGB).
Thus, during the precharge interval (Tpc), the 1 st digital transistor (Q1) is switched (turn-on), the latch high Potential Voltage (PVDD) is stored in the 2 nd capacitor (C2), and during the programming interval (Tpg), the 5 th digital transistor (Q5) is switched (turn-on), the map data (RGB) is stored in the 1 st capacitor (C1), and the valid output signal (LSO) is output.
Although not depicted, the latch (172) may be provided to the light emitting diode (Del) at an appropriate time after the output signal (LSO) is stored.
As described above, in the pixel (P) of the light emitting diode display device according to the 14 th and 15 th embodiments of the present invention, the level shifter (174) can make a certain current flow through the light emitting diode (Del) by outputting one of the 1 st and 2 nd output signals using the image data (RGB), the program signal (PGM) and the Reset Signal (RS), and the latch (172) applies at least one of the 3 rd and 4 th output signals required for light emission to the current sources (182 and 184) irrespective of the variation of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS).
In other embodiments, the current source may be disposed at one of the anode and cathode of the light emitting diode, which is described with reference to the drawings.
Fig. 31 and 32 are pixel diagrams of the light emitting diode display devices according to the 16 th and 17 th embodiments of the present invention, respectively, and the descriptions of the same portions as those of the 1 st to 15 th embodiments are omitted.
As shown in fig. 31, a pixel (P) of a light emitting diode display device according to embodiment 16 of the present invention includes a level shifter (174), a latch (172), a current source (184), and a light emitting diode (Del), the level shifter (174) and the latch (172) constituting a control circuit portion that supplies a control signal to the current source (184), and the current source (184) and the light emitting diode (Del) constituting a light emitting portion.
The level shifter (174) receives the image data (RGB), the program signal (PGM), and the Reset Signal (RS), and outputs at least one of the 1 st and 2 nd output signals, which may be inverted signals, using the latch high voltage (PVDD) and the latch low voltage (PVSS).
In other embodiments, the Reset Signal (RS) may be omitted.
The latch (172) receives at least one of the 1 st and 2 nd output signals and outputs at least one of the 3 rd and 4 th output signals, which may be inverted signals, using a latch high voltage (PVDD) and a latch low voltage (PVSS).
A current source (184) receives at least one of the 3 rd and 4 th output signals, is connected to the cathode of the light emitting diode (Del), and causes the light emitting diode (Del) to flow a current using at least one of the 3 rd and 4 th output signals.
For example, the level shifter (174) and the latch (172) include a plurality of transistors, and the current source (184) may include a transistor and a capacitor.
The image data (RGB) input to the level shifter (174) has a digital type of digital voltage level.
As shown in fig. 32, a pixel (P) of a light emitting diode display device according to embodiment 17 of the present invention includes a level shifter (174), a latch (172), a current source (182), and a light emitting diode (Del), the level shifter (174) and the latch (172) constitute a control circuit portion that supplies a control signal to the current source, and the current source (182) and the light emitting diode (Del) constitute a light emitting portion.
The level shifter (174) receives the image data (RGB), the program signal (PGM), and the Reset Signal (RS), and outputs at least one of the 1 st and 2 nd output signals, which may be inverted signals, using the latch high voltage (PVDD) and the latch low voltage (PVSS).
In other embodiments, the Reset Signal (RS) may be omitted.
The latch (172) receives at least one of the 1 st and 2 nd output signals and outputs at least one of the 3 rd and 4 th output signals, which may be inverted signals, using a latch high voltage (PVDD) and a latch low voltage (PVSS)
A current source (182) receives at least one of the 3 rd and 4 th output signals, is connected to the anode of the light emitting diode (Del), and causes a current to flow through the light emitting diode (Del) using at least one of the 3 rd and 4 th output signals.
For example, the level shifter (174) and the latch (172) include a plurality of transistors, and the current source (182) may include a transistor and a capacitor.
The image data (RGB) input to the level shifter (174) has a digital type of digital voltage level.
As described above, in the pixel (P) of the light emitting diode display device according to the 16 th and 17 th embodiments of the present invention, the level shifter (174) can make a certain current flow through the light emitting diode (Del) by outputting one of the 1 st and 2 nd output signals using the image data (RGB), the program signal (PGM), the Reset Signal (RS), and the latch (172) applying at least one of the 3 rd and 4 th output signals required for light emission to the current sources (182, 184) irrespective of the variation of the light emission high potential voltage (EVDD) and the light emission low potential voltage (EVSS).
While the preferred embodiments of the present invention have been described with reference to the above, it will be understood by those skilled in the relevant art that various modifications and changes can be made to the present invention without departing from the technical spirit and scope of the present invention as set forth in the following claims.

Claims (21)

1. A display device having a light emitting diode and a driving method thereof, comprising:
a display panel of a plurality of pixels; and
a light emitting diode disposed at each of the plurality of pixels; and
at least one current source connected between the light emitting diode and a light emitting high potential voltage or between the light emitting diode and a light emitting low potential voltage; and
and a control circuit section for supplying a control signal to the at least one current source.
2. The display device with light emitting diode and driving method thereof according to claim 1, comprising:
the at least one current source is configured to provide a current,
a first transistor connected between the light emitting diode and the light emitting high potential voltage, one of N-type and P-type;
and a second transistor connected between the light emitting diode and a light emitting low potential voltage, the other one of the N-type and P-type.
3. The display device with light emitting diode and driving method thereof according to claim 2, comprising:
the control circuit portion is configured to control the operation of the electronic device,
a latch connected between the digital high potential voltage and the digital low potential voltage for generating the 1 st and 2 nd output signals by using the image data and the programming signal;
and a level shifter connected between the high-potential voltage and the low-potential voltage to generate the 3 rd and 4 th output signals for switching (swiping) the 1 st and 2 nd transistors by the 1 st and 2 nd output signals, respectively.
4. A display device having a light emitting diode and a driving method thereof according to claim 3, comprising:
the latch-up of the latch-up is carried out,
switching (swiping) the P-type 1 st digital transistor and the transmission of the 1 st output signal according to the program signal;
switching (swiping) the N type 2 digital transistor and the N type 2 digital transistor of the image data transmission according to the program signal;
switching (swiping) a P-th digital transistor of the digital high potential voltage according to the 1 st output signal or the digital low potential voltage;
switching (swiping) an N-type 5 th digital transistor sum of the transfer of the digital low potential voltage according to the 1 st output signal or the digital low potential voltage;
Switching (toggling) the P-th digital transistor of the digital high-potential voltage according to the 2 nd output signal;
an N-type 7 th digital transistor for switching (swing) transmission including the digital low potential voltage according to the 2 nd output signal;
the level shifter is used to shift the level of the light source,
switching (swiping) the P-type 8 th digital transistor of the pin high potential voltage according to the 3 rd output signal;
switching (swiping) the N9 th digital transistor of the pin low potential voltage according to the 1 st output signal;
switching (swiping) the P-type 10 digital transistor of the pin high potential voltage according to the 4 th output signal;
and switching (swiping) the N type 11 digital transistor of the pin low potential voltage according to the 4 th output signal.
5. The display device with light emitting diode and driving method thereof according to claim 2, comprising:
the control circuit portion is configured to control the operation of the electronic device,
the 1 st and 2 nd transistors are respectively switched (swiping) between the high potential voltage of the pin and the low potential voltage of the pin by using image data, a programming signal and a light-emitting signal, and comprise integrated level shifters for generating 1 st and 2 nd output signals,
The integrated level shifter is described as an integrated level shifter,
switching (swiping) an N-type 1 st digital transistor and a transmission of the 1 st output signal according to the light-emitting signal;
switching (swiping) the P-type 2 nd digital transistor and the transmission of the 1 st output signal according to the programming signal;
switching (swiping) the N-type 3 rd digital transistor and the N-type 3 rd digital transistor for transmitting the image data according to the programming signal;
switching (swiping) the P-type 4 th digital transistor of the pin high potential voltage according to the 1 st output signal or the mapping data;
switching (swiping) an N-type 5 th digital transistor and a transmission of the pin low potential voltage according to the 1 st output signal or the image data;
switching (swiping) the P-th digital transistor and the P-th digital transistor of the transmission of the pin high potential voltage according to the light emitting signal;
switching (swiping) the P-th digital transistor and the P-th digital transistor of the pin high potential voltage transmission according to the 2 nd output signal;
and switching (swiping) the N-type 8 th digital transistor for conveying the pin low-potential voltage according to the 2 nd output signal.
6. The display device with light emitting diode and driving method thereof according to claim 2, further comprising:
In the light-emitting diode display device,
a third transistor connected between the positive electrode and the negative electrode of the light emitting diode,
the 1 st and 3 rd transistors are N-type and the 2 nd transistor is P-type.
7. The display device with light emitting diode and driving method thereof according to claim 6, further comprising:
the control circuit portion is configured to control the operation of the electronic device,
switching (swiping) an N-type fourth transistor sum of a connection between the 1 st data signal and the gate of the 1 st transistor according to the 1 st programming signal;
an N-type 5 th transistor switching (swiping) a connection between a 2 nd data signal and a source of the 1 st transistor according to a 2 nd programming signal;
and a 1 st capacitor connected between the gate and the source of the 1 st transistor.
8. The display device with light emitting diode and driving method thereof according to claim 6, further comprising: the control circuit portion is configured to control the operation of the electronic device,
switching (swiping) the N-type 4 th transistor sum of the connection between the 1 st data signal and the gate of the 1 st transistor according to a programming signal;
switching (swiping) an N-type 5 th transistor and a connection between a 2 nd data signal and a source of a 1 st transistor according to the programming signal;
A 1 st capacitor connected between the gate and the source of the 1 st transistor.
9. The display device with light emitting diode and driving method thereof according to claim 6, further comprising:
the control circuit part is included in the control circuit part,
switching (swiping) a connection between a data signal and a gate of the 1 st transistor according to a programming signal;
switching (toggling) a connected N-type 5 th transistor sum between a reference signal and a source of the 1 st transistor according to a sense signal;
a 1 st capacitor connected between the gate of the 1 st transistor and the drain of the 5 th transistor.
10. The display device with light emitting diode and driving method thereof according to claim 2, comprising:
the control circuit portion is configured to control the operation of the electronic device,
a level shifter and a level shifter connected between the high potential voltage of the pin and the low potential voltage of the pin, for generating the 1 st and the 2 nd output signals by using the 1 st and the 2 nd image data, the programming signal, the input signal; comprising a latch connected between said pin high potential voltage and said pin low potential voltage for generating 3 rd and 4 th output signals for switching (swiping) said 1 st and 2 nd transistors, respectively, using said 1 st and 2 nd output signals,
The level shifter is used to shift the level of the light source,
switching (swiping) a connected 1 st digital transistor sum between the pin high potential voltage and a drain of a third digital transistor according to the 1 st output signal;
switching (toggling) a connected 2 nd digital transistor sum between the pin high potential voltage and a drain of a fourth digital transistor according to the 2 nd output signal;
switching (swiping) the 3 rd digital transistor sum of the connection between the drain of the 1 st digital transistor and the drain of the 9 th digital transistor according to the 1 st output signal;
switching (swiping) the connected 4 th digital transistor sum between the drain of the second digital transistor and the drain of the ninth digital transistor in accordance with the 2 nd output signal;
switching (swiping) a 5 th digital transistor sum of a connection between a drain of the 1 st digital transistor and a drain of the 9 th digital transistor according to a voltage of a 1 st electrode of the 1 st capacitor;
switching (swiping) a connected 6 th digital transistor sum between a drain of the 2 nd digital transistor and a drain of the 9 th digital transistor according to a voltage of the 1 st electrode of the 2 nd capacitor;
switching (swiping) a 7 th digital transistor sum of a connection between the 1 st video data and the gate of the 5 th digital transistor according to the programming signal;
Switching (swiping) a connected 8 th digital transistor sum between the 2 nd image data and the gate of the 6 th digital transistor according to the programming signal;
the 9 th digital transistor and the source of the 3 rd to 6 th digital transistors, the connection between the pin low potential voltage and the switching (toggling) being switched according to the input signal;
the 1 st capacitor connected between the source of the 7 th digital transistor and the pin low potential voltage;
the 2 nd capacitor is connected between the source of the 8 nd digital transistor and the pin low potential voltage.
11. The display device with light emitting diode and driving method thereof according to claim 2, comprising: the control circuit portion is configured to control the operation of the electronic device,
a level shifter for generating an output signal by connecting the pin high potential voltage and the pin low potential voltage and using the image data, the program signal and the precharge signal,
comprising a latch connected between said pin high potential voltage and said pin low potential voltage for generating 3 rd and 4 th output signals for switching said 1 st and 2 nd transistors respectively using said output signals,
the level shifter is used to shift the level of the light source,
Switching (swiping) a 1 st digital transistor sum of a connection (swiping) between the pin high potential voltage and a drain of the 3 rd digital transistor according to the precharge signal;
a 2 nd digital transistor and a connection (swiping) between the pin high potential voltage and a drain of the 4 nd digital transistor according to a voltage switching (swiping) of the 1 st electrode of the 2 nd capacitor;
-switching (swiping) the 3 rd digital transistor sum of the connection between the drain of the 1 st digital transistor and the drain of the 6 th digital transistor according to the precharge;
switching (swiping) the 4 th digital transistor and the connection between the drain of the 2 nd digital transistor and the latch low potential voltage according to the voltage of the 1 st electrode of the 2 nd capacitor;
a 5 th digital transistor sum for switching (swiping) a connection between gates of the 6 th digital transistors and the image data according to the programming signal;
a 6 th digital transistor sum according to a connection between a source of a 3 rd digital transistor and a pin low potential voltage according to voltage switching (swiping) of a first electrode of the 1 st capacitor;
a 1 st capacitor connected between the source of the 5 th digital transistor and the pin low potential voltage;
The 2 nd capacitor is connected between the gate of the 2 nd digital transistor and the pin low potential voltage.
12. The display device with light emitting diode and driving method thereof according to claim 1, comprising:
the light-emitting diode(s) of the present invention,
further comprising a 3 rd transistor connected between the anode of said light emitting diode and a test voltage,
the at least one current source is configured to provide a current,
comprises a 1 st transistor which is connected between the light emitting diode and a light emitting high potential voltage and comprises one of an N type and a P type,
the cathode of the light emitting diode is connected to a light emitting low potential voltage.
13. The display device with light emitting diode and driving method thereof according to claim 12, comprising:
the control circuit portion is configured to control the operation of the electronic device,
a latch connected between the digital high potential voltage and the digital low potential voltage for generating the 1 st and 2 nd output signals using the mapping data and the programming signal;
and a level shifter connected between the latch high potential voltage and the latch low potential voltage and generating a 3 rd output signal for switching (swiping) the 1 st transistor using the 1 st and 2 nd output signals.
14. The display device with light emitting diode and driving method thereof according to claim 12, comprising:
The control circuit portion is configured to control the operation of the electronic device,
and an integrated level shifter connected between the pin high potential voltage and the pin low potential voltage for generating a first output signal for switching (swiping) the first transistor by using the image data, the programming signal and the light emitting signal.
15. The display device with light emitting diode and driving method thereof according to claim 12, further comprising:
switching (swiping) the N-type 4 th transistor sum of the connection between the first data signal and the gate of the 1 st transistor according to the 1 st programming signal;
an N-type 5 th transistor switching (swiping) a connection between a 2 nd data signal and a source of the 1 st transistor according to a 2 nd programming signal;
a 1 st capacitor connected between the gate and the source of the 1 st transistor.
16. The display device with light emitting diode and driving method thereof according to claim 12, further comprising: the control circuit portion is configured to control the operation of the electronic device,
switching (swiping) the N-type 4 th transistor sum of the connection between the 1 st data signal and the gate of the 1 st transistor according to a programming signal;
switching (swiping) a fifth transistor sum of N-type of connection between a second data signal and a source of the first transistor according to the programming signal;
A first capacitor connected between the gate and the source of the first transistor.
17. The display device with light emitting diode and driving method thereof according to claim 12, further comprising: the control circuit portion is configured to control the operation of the electronic device,
an N-type fourth transistor and switching a connection between a (swing) data signal and a gate of the 1 st transistor according to a programming signal;
switching (toggling) a connected N-type 5 th transistor sum between a reference signal and a source of the 1 st transistor according to a sense signal;
a 1 st capacitor connected between the gate of the 1 st transistor and the drain of the 5 th transistor.
18. The display device with light emitting diode and driving method thereof according to claim 12, further comprising: the control circuit portion is configured to control the operation of the electronic device,
switching (swiping) an N-type 4 th transistor and a connection between the 1 st output signal and a source of the 1 st transistor according to a reference signal;
switching (swiping) an N-type 5 th transistor sum of a connection between the 2 nd output signal and a gate of the 1 st transistor according to the reference signal;
switching (swiping) a P-type 6 th transistor and a connection between a light-emitting high potential voltage and a source of the 1 st transistor according to the 1 st light-emitting signal;
Switching (swiping) an N-type 7 th transistor sum of a connection between a drain electrode of the 1 st transistor and an anode electrode of the light emitting diode according to a 2 nd light emitting signal;
a 1 st capacitor connected between the gate of the 1 st transistor and the source of the 1 st transistor,
the control circuit portion is configured to control the operation of the electronic device,
the latch is connected between the digital high voltage and the digital low voltage and generates the 1 st and 2 nd output signals by using the image data and the programming signal.
19. The display device with light emitting diode and driving method thereof according to claim 12, further comprising:
the control circuit portion is configured to control the operation of the electronic device,
switching (toggling) the N-type 4 th transistor sum of the connection between the 1 st output signal and the gate of the 1 st transistor according to a reference signal;
switching (swiping) an N-type 5 th transistor sum of a connection between the 2 nd output signal and a source of the 1 st transistor according to the reference signal;
switching (swiping) a P-type 6 th transistor and a connection between a light-emitting high potential voltage and a drain electrode of the 1 st transistor according to the 1 st light-emitting signal;
an N-type 7 th transistor switching a connection between a source of the 1 st transistor and an anode of the light emitting diode according to the 2 nd light emitting signal;
A 1 st capacitor connected between the gate of the 1 st transistor and the source of the 1 st transistor,
the control circuit portion is configured to control the operation of the electronic device,
a latch is connected between the digital high voltage and the digital low voltage for generating the 1 st and 2 nd output signals using the mapping data and the programming signal.
20. The display device with light emitting diode and driving method thereof according to claim 1, comprising: the at least one current source is configured to provide a current,
and a second transistor connected between the light emitting diode and a light emitting high potential voltage, including the other of the N-type and the P-type.
21. The display device with light emitting diode and driving method thereof according to claim 1, comprising:
the at least one current source is configured to provide a current,
and a second transistor connected between the light emitting diode and a light emitting low potential voltage and including the other of the N-type and P-type.
CN202280049584.4A 2021-07-13 2022-06-28 Light emitting diode display device and driving method thereof Pending CN117836843A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2021-0091332 2021-07-13
KR10-2022-0076210 2022-06-22
KR1020220076210A KR20230011229A (en) 2021-07-13 2022-06-22 Light Emitting Diode Display Device And Method Of Driving The Same
PCT/KR2022/009174 WO2023287065A1 (en) 2021-07-13 2022-06-28 Light-emitting diode display device and method for driving same

Publications (1)

Publication Number Publication Date
CN117836843A true CN117836843A (en) 2024-04-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202280049584.4A Pending CN117836843A (en) 2021-07-13 2022-06-28 Light emitting diode display device and driving method thereof

Country Status (1)

Country Link
CN (1) CN117836843A (en)

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