CN117832107A - Test structure and manufacturing method thereof - Google Patents
Test structure and manufacturing method thereof Download PDFInfo
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- CN117832107A CN117832107A CN202211197543.8A CN202211197543A CN117832107A CN 117832107 A CN117832107 A CN 117832107A CN 202211197543 A CN202211197543 A CN 202211197543A CN 117832107 A CN117832107 A CN 117832107A
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- 238000012360 testing method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 104
- 239000011241 protective layer Substances 0.000 claims abstract description 47
- 238000004140 cleaning Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 406
- 239000000463 material Substances 0.000 claims description 110
- 238000002955 isolation Methods 0.000 claims description 57
- 239000004065 semiconductor Substances 0.000 claims description 36
- 238000000059 patterning Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 11
- 230000002378 acidificating effect Effects 0.000 claims description 10
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 229910002704 AlGaN Inorganic materials 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 41
- 238000012512 characterization method Methods 0.000 abstract description 5
- 238000005457 optimization Methods 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 description 6
- 238000004458 analytical method Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000011165 process development Methods 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H01L29/45—
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- H01L29/778—
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a test structure and a manufacturing method thereof, wherein the manufacturing method of the test structure is characterized in that a protective layer is introduced into a gate structure as a hard mask to protect gate metal through collaborative optimization of a gate structure layout and a process flow, the gate metal is prevented from being damaged in an ohmic contact hole cleaning process, and after an ohmic contact process module is completed, comprehensive electrical characterization can be performed on the completed process module in real time.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and relates to a test structure and a manufacturing method thereof.
Background
The P-type gate technology is a main method for realizing enhancement of a GaN high electron mobility device (HEMT) power device, and is a mainstream technology adopted by commercial products. In the manufacturing process, after the preparation of ohmic contact metal and gate contact metal is finished, electrical test is carried out on the single-gate finger small device, the process is evaluated through parameters such as threshold voltage and on-resistance, and the product performance is predicted, so that the aim of screening defective products in advance is fulfilled.
In the implementation scheme of the manufacturing process, since the gate metal is damaged by the post-cleaning of the dielectric etching process for the ohmic contact region, in order to protect the gate metal, a PAD (PAD) region of the gate metal is not opened in the ohmic contact opening, and a contact hole of the PAD region of the gate PAD can only be opened in the step of forming the first layer of interconnection metal through holes, so that the test of the small device can be performed after the first layer of interconnection metal is completed.
Therefore, how to optimize the gate structure layout and the process flow to achieve the objective of performing the electrical test of the test structure after the ohmic contact process is completed becomes an important technical problem to be solved by those skilled in the art.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a test structure and a manufacturing method thereof, which are used for solving the problems that the prior art scheme cannot perform an electrical test on the test structure immediately after the ohmic contact process is completed, which is not beneficial to timeliness and accuracy of failure analysis.
To achieve the above and other related objects, the present invention provides a method for manufacturing a test structure, comprising the steps of:
providing a semiconductor layer, forming an isolation structure in the semiconductor layer to isolate an active region in the semiconductor layer, wherein the semiconductor layer comprises a first material layer, a second material layer and a P-type layer which are sequentially arranged from bottom to top, the interface of the first material layer and the second material layer contains two-dimensional electron gas, and the isolation structure penetrates through the P-type layer and the second material layer;
forming a gate metal layer on the P-type layer, forming a protective layer on the gate metal layer, and patterning the protective layer, the gate metal layer and the P-type layer, wherein the patterned P-type layer comprises a P-type boss positioned in the active region, the patterned gate metal layer comprises a gate leading-out layer positioned on the P-type boss and a gate pad connecting layer positioned on the isolation structure, and the patterned protective layer covers the upper surface of the patterned gate metal layer;
forming an insulating layer to cover the isolation structure, the exposed surface of the second material layer and the protective layer, and patterning the insulating layer to obtain a source ohmic contact hole, a drain ohmic contact hole and a gate pad opening, wherein the source ohmic contact hole and the drain ohmic contact hole are both positioned in the active region and distributed on two sides of the P-type boss, the bottoms of the source ohmic contact hole and the drain ohmic contact hole expose the second material layer, the gate pad opening is positioned above the gate pad connecting layer, and the bottom of the gate pad opening exposes the protective layer;
Cleaning the surface of the second material layer exposed by the source ohmic contact hole and the drain ohmic contact hole;
removing the protective layer at the bottom of the gate pad opening to expose the gate pad connection layer;
an ohmic contact metal layer is formed on the insulating layer, the ohmic contact metal layer comprises a source electrode pad, a drain electrode pad, a gate electrode pad, a source electrode connecting wire and a drain electrode connecting wire, the source electrode pad, the drain electrode pad and the gate electrode pad are all located on the upper surface of the insulating layer above the isolation structure and are arranged at intervals, one end of the source electrode connecting wire is connected with the source electrode pad, the other end of the source electrode connecting wire extends into the source electrode ohmic contact hole to be electrically connected with the second material layer, one end of the drain electrode connecting wire is connected with the drain electrode pad, the other end of the drain electrode connecting wire extends into the drain electrode ohmic contact hole to be electrically connected with the second material layer, and the gate electrode pad is further filled into the gate electrode pad opening to be electrically connected with the gate electrode pad connecting layer.
Optionally, the semiconductor layer further includes a substrate layer and a buffer layer on the substrate layer, and the first material layer is on the buffer layer.
Optionally, the material of the substrate layer includes Si, the material of the buffer layer includes GaN, the material of the first material layer includes intrinsic GaN, the material of the second material layer includes AlGaN, and the material of the P-type layer includes P-type GaN.
Optionally, the cleaning solution used for cleaning the surface of the second material layer exposed by the source ohmic contact hole and the drain ohmic contact hole includes an acidic cleaning solution, and the acidic cleaning solution is used for removing a damaged layer on the surface of the second material layer.
Optionally, the acidic cleaning solution includes at least one of sulfuric acid and hydrogen peroxide.
Optionally, the etching solution used for removing the protective layer at the bottom of the gate pad opening includes diluted hydrofluoric acid.
Optionally, the diluted hydrofluoric acid is further used for cleaning the surface of the second material layer exposed by the source ohmic contact hole and the drain ohmic contact hole to remove metal etching additional products.
Optionally, the material of the protective layer comprises SiO 2 And at least one of SiON.
Optionally, the test structure is a single gate finger structure.
The invention also provides a test structure comprising:
the semiconductor layer comprises a first material layer, a second material layer and a P-type boss which are sequentially arranged from bottom to top, and the interface of the first material layer and the second material layer contains two-dimensional electron gas;
An isolation structure located in the semiconductor layer to isolate an active region in the semiconductor layer, the isolation structure penetrating through the second material layer, the P-type boss located in the active region and on the second material layer;
the grid metal layer comprises a grid lead-out layer positioned on the P-type boss and a grid pad connecting layer positioned on the isolation structure;
a protective layer covering the upper surface of the gate metal layer;
the insulating layer covers the isolation structure, the exposed surface of the second material layer and the surface of the protective layer;
the source ohmic contact holes and the drain ohmic contact holes are positioned in the active region and distributed on two sides of the P-type boss, the source ohmic contact holes and the drain ohmic contact holes penetrate through the insulating layer to expose the second material layer, and the gate pad opening is positioned above the gate pad connecting layer and penetrates through the insulating layer and the protective layer to expose the gate pad connecting layer;
ohmic contact metal layer is located on the insulating layer and comprises a source electrode pad, a drain electrode pad, a gate electrode pad, a source electrode connecting wire and a drain electrode connecting wire, wherein the source electrode pad, the drain electrode pad and the gate electrode pad are all located on the upper surface of the insulating layer above the isolation structure and are arranged at intervals, one end of the source electrode connecting wire is connected with the source electrode pad, the other end of the source electrode connecting wire extends into the source electrode ohmic contact hole to be electrically connected with the second material layer, one end of the drain electrode connecting wire is connected with the drain electrode pad, the other end of the drain electrode connecting wire extends into the drain electrode ohmic contact hole to be electrically connected with the second material layer, and the gate electrode pad is filled into the gate electrode pad opening to be electrically connected with the gate electrode pad connecting layer.
As described above, the manufacturing method of the test structure of the invention introduces the protective layer as the hard mask to protect the gate metal through the collaborative optimization of the gate structure layout and the process flow, thereby avoiding the gate metal from being damaged in the ohmic contact hole cleaning process, and the completed process module can be comprehensively and electrically characterized in time after the ohmic contact process module is completed.
Drawings
Fig. 1 shows a schematic structural diagram of a GaN HEMT.
Fig. 2a shows a schematic plan view of a single-gate finger device.
Fig. 2b is a schematic plan view of the active region and its vicinity of the single-gate finger device of fig. 2 a.
Fig. 2c is a schematic cross-sectional view of the active region of the single-gate finger device of fig. 2 a.
FIG. 3 is a schematic diagram of an initial state of the film layer provided in a manufacturing process implementation.
Fig. 4a is a schematic cross-sectional view of a source/drain pad region after forming an isolation structure in the film structure shown in fig. 3 to define an active region.
Fig. 4b is a schematic cross-sectional view of the active region after forming an isolation structure in the film structure shown in fig. 3 to define the active region.
Fig. 4c is a schematic cross-sectional view of the gate pad region after forming an isolation structure in the film structure shown in fig. 3 to define the active region.
Fig. 5a is a schematic cross-sectional view of a source/drain pad region after forming a gate contact metal layer on the structure shown in fig. 4 a-4 c and patterning the P-type GaN layer.
Fig. 5b is a schematic cross-sectional view of the active region after forming a gate contact metal layer on the structure shown in fig. 4 a-4 c and patterning the P-type GaN layer.
Fig. 5c is a schematic cross-sectional view showing a gate pad region after forming a gate contact metal layer on the structure shown in fig. 4 a-4 c and patterning the P-type GaN layer.
Fig. 6a is a schematic cross-sectional view showing the source/drain pad region after forming a passivation layer on the structure shown in fig. 5 a-5 c and forming an ohmic contact via.
Fig. 6b is a schematic cross-sectional view showing the active region after forming a passivation layer and ohmic contact vias on the structure shown in fig. 5 a-5 c.
Fig. 6c is a schematic cross-sectional view showing the gate pad region after forming a passivation layer on the structure shown in fig. 5 a-5 c and forming an ohmic contact via.
Fig. 7a is a schematic cross-sectional view of a source/drain pad region after ohmic contact metal is formed on the structure of fig. 6 a-6 c.
Figure 7b shows the active region after ohmic contact metal has been formed on the structure shown in figures 6 a-6 c
Fig. 7c is a schematic cross-sectional view of the gate pad region after ohmic contact metal is formed on the structure of fig. 6 a-6 c.
Fig. 8a is a schematic cross-sectional view of a source/drain pad region after forming a dielectric layer and forming an interconnect via over the structure shown in fig. 7 a-7 c.
Fig. 8b is a schematic cross-sectional view of the active region after forming a dielectric layer and forming an interconnect via over the structure shown in fig. 7 a-7 c.
Fig. 8c is a schematic cross-sectional view of the gate pad region after forming a dielectric layer and forming an interconnect via over the structure shown in fig. 7 a-7 c.
Fig. 9a is a schematic cross-sectional view of a source/drain pad region after forming a first layer of interconnect metal over the structure shown in fig. 8 a-8 c.
Fig. 9b is a schematic cross-sectional view of the active region shown after forming a first layer of interconnect metal over the structure shown in fig. 8 a-8 c.
Fig. 9c is a schematic cross-sectional view of the gate pad region after forming a first layer of interconnect metal over the structure shown in fig. 8 a-8 c.
Fig. 10 is a schematic plan view of a single gate finger structure to be fabricated in the first embodiment of the method for fabricating a test structure according to the present invention.
Fig. 11 is a diagram showing a structure of a semiconductor layer according to the first embodiment of the present invention.
Fig. 12a is a schematic cross-sectional view of a source/drain pad region after forming an isolation structure in the semiconductor layer to define an active region in the first embodiment of the test structure manufacturing method of the present invention.
Fig. 12b is a schematic cross-sectional view of an active region after forming an isolation structure in the semiconductor layer to define the active region according to the first embodiment of the test structure manufacturing method of the present invention.
Fig. 12c is a schematic cross-sectional view of a gate pad region after forming an isolation structure in the semiconductor layer to define an active region according to the first embodiment of the test structure manufacturing method of the present invention.
Fig. 13a is a schematic cross-sectional view showing a source/drain pad region after patterning the protective layer, the gate metal layer and the P-type layer, in which a gate metal layer is formed on the P-type layer and a protective layer is formed on the gate metal layer in the first embodiment of the test structure manufacturing method of the present invention.
Fig. 13b is a schematic cross-sectional view showing an active region after patterning the protective layer, the gate metal layer and the P-type layer, in which a gate metal layer is formed on the P-type layer and a protective layer is formed on the gate metal layer in the first embodiment of the test structure manufacturing method of the present invention.
Fig. 13c is a schematic cross-sectional view of a gate pad region after patterning the protective layer, the gate metal layer and the P-type layer, in which a gate metal layer is formed on the P-type layer and a protective layer is formed on the gate metal layer in the first embodiment of the test structure manufacturing method of the present invention.
Fig. 14a is a schematic cross-sectional view of a source/drain pad region after forming an insulating layer and patterning in the first embodiment of the test structure according to the present invention.
Fig. 14b is a schematic cross-sectional view of an active region after forming an insulating layer and patterning in the first embodiment of the test structure according to the present invention.
Fig. 14c is a schematic cross-sectional view of a gate pad region after forming and patterning an insulating layer in the first embodiment of the test structure manufacturing method of the present invention.
Fig. 15a is a schematic cross-sectional view of a source/drain pad region after removing the protective layer at the bottom of the gate pad opening to expose the gate pad connection layer in the first embodiment of the test structure manufacturing method of the present invention.
Fig. 15b is a schematic cross-sectional view of an active region of the test structure according to the first embodiment after the passivation layer at the bottom of the gate pad opening is removed to expose the gate pad connection layer.
Fig. 15c is a schematic cross-sectional view of a gate pad region after removing the protective layer at the bottom of the gate pad opening to expose the gate pad connection layer in the first embodiment of the test structure manufacturing method of the present invention.
Fig. 16a is a schematic cross-sectional view of a source/drain pad region of a test structure according to the first embodiment of the invention after an ohmic contact metal layer is formed on the insulating layer.
Fig. 16b is a schematic cross-sectional view of an active region of the test structure according to the first embodiment of the invention after an ohmic contact metal layer is formed on the insulating layer.
Fig. 16c is a schematic cross-sectional view of a gate pad region after an ohmic contact metal layer is formed on the insulating layer according to the first embodiment of the test structure manufacturing method of the present invention.
Description of element reference numerals
101. Buffer layer
102. Barrier layer
103 P-type layer
104. Grid electrode
105. Source electrode
106. Drain electrode
107. Two-dimensional electron gas layer
201. Gate pad
202. Source electrode bonding pad
203. Drain electrode bonding pad
204. First lead region
205. Second lead region
206. Third lead region
207 Si substrate
208 GaN buffer layer
209. Intrinsic GaN layer
210 AlGaN layer
211 P-type GaN layer
212. Gate metal layer
213. Isolation structure
214 Si 3 N 4 Layer(s)
215. Ohmic contact metal layer
301 Si substrate
302 GaN buffer layer
303. Intrinsic GaN layer
304 AlGaN layer
305 P-type GaN layer
306. Isolation structure
307. Gate contact metal layer
308. Passivation layer
309. Ohmic contact via
310. Ohmic contact metal layer
311. Dielectric layer
312. Interconnect via
313. First layer interconnect metal
401. Isolation structure
402. Gate pad
403. Source electrode bonding pad
404. Drain electrode bonding pad
405. Active region
406. First lead region
407. Second lead region
408. Third lead region
409. A first material layer
410. A second material layer
411 P-type layer
411a P type boss
412. Substrate layer
413. Buffer layer
414. Gate metal layer
414a gate lead-out layer
414b gate pad connection layer
415. Protective layer
416. Insulating layer
417. Source electrode ohmic contact hole
418. Drain ohmic contact hole
419. Gate pad opening
420. Source connecting wire
421. Drain electrode connecting wire
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-16 c. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Referring to fig. 1, a schematic structural diagram of a GaN HEMT is shown, which includes a buffer layer 101 (GaN), a barrier layer 102 (ALGaN), a P-type layer 103 (P- (Al) GaN), a gate 104, a source 105 and a drain 106, wherein the buffer layer 101 may be a GaN layer, the barrier layer 102 may be an ALGaN layer, the P-type layer 103 may be a P-type GaN layer or a P-type ALGaN layer, and a two-dimensional electron gas layer 107 is formed at an interface between the buffer layer 101 and the barrier layer 102.
In the manufacturing process of the GaN HEMT, a single-gate finger small device structure can be manufactured in a wafer dicing channel or other proper areas to serve as a test structure, after the ohmic contact metal and the gate contact metal are manufactured, the single-gate finger small device is subjected to electrical test, the process is evaluated through parameters such as threshold voltage, on-resistance and the like, and the product performance can be predicted, so that the aim of screening defective products in advance is achieved.
Referring to fig. 2a to 2c, a schematic structure of a single-gate finger device is shown, in which fig. 2a is a schematic plan view of the single-gate finger device, fig. 2b is a schematic plan view of an active region of the single-gate finger device and a region near the active region (a region indicated by a dotted line frame in fig. 2 a), and fig. 2c is a schematic cross-sectional view of the active region of the single-gate finger device (along a dotted line cross-section line in fig. 2 b). As shown in fig. 2a, the single gate finger device includes a gate pad 201, a source pad 202, and a drain pad 203; as shown in fig. 2b, the gate pad 201 is connected to the gate in the active region through a first lead region 204, and the source pad 202 is on Connected to the source electrode in the active region through the second lead region 205, and the drain pad 203 is connected to the drain electrode in the active region through the third lead region 206; as shown in fig. 2c, the single-gate finger device comprises a Si substrate 207, a GaN buffer layer 208, an intrinsic GaN layer 209, an AlGaN layer 210, a P-type GaN layer 211, a gate metal layer 212, an isolation structure 213, and Si 3 N 4 Layer 214 and ohmic contact metal layer 215.
In one implementation of the manufacturing process, in order to avoid damaging the gate metal layer by post-cleaning for the dielectric etching process of the ohmic contact region, the pad region of the gate metal is not opened in the ohmic contact opening step, but the contact hole of the gate pad region is opened again in the first layer interconnection metal via step, so the test of the small device needs to be performed after the first layer interconnection metal is completed, and the specific process is as follows:
(1) Referring to fig. 3, an initial state film structure is provided, the film structure includes a Si substrate 301, a GaN buffer layer 302, an intrinsic GaN layer 303, an AlGaN layer 304 and a P-type GaN layer 305 sequentially arranged from bottom to top, wherein the film structure shown in fig. 3 includes source/drain pad regions, an active region and a gate pad region.
(2) Referring to fig. 4a, fig. 4b, and fig. 4c, an isolation structure 306 is formed in the film layer structure to define an active region, wherein fig. 4a, fig. 4b, and fig. 4c respectively show cross-sectional views of the source/drain pad region, the active region, and the gate pad region after the isolation structure 306 is formed.
(3) Referring to fig. 5a, 5b and 5c, a gate contact metal layer 307 is formed and the P-type GaN layer 305 is patterned, wherein fig. 5a, 5b and 5c are schematic cross-sectional views of the source/drain pad region, the active region and the gate pad region after performing the steps, and a portion of the isolation structure 306 uncovered by the gate contact metal layer 307 is etched away along with the P-type GaN layer 305.
(4) Referring to fig. 6a, 6b and 6c, a passivation layer 308 is formed and ohmic contact holes 309 are formed to expose the source and drain regions, wherein fig. 6a, 6b and 6c are schematic cross-sectional views of the source/drain pad region, the active region and the gate pad region after performing the present step.
(5) Referring to fig. 7a, 7b and 7c, an ohmic contact metal layer 310 is formed and patterned, wherein fig. 7a, 7b and 7c are schematic cross-sectional structures of the source/drain pad region, the active region and the gate pad region, respectively, after performing the present step.
(6) Referring to fig. 8a, 8b and 8c, a dielectric layer 311 is formed and an interconnection via 312 is formed, wherein the interconnection via exposes a predetermined region of the ohmic contact metal layer 310 and a pad region of the gate contact metal layer 307, respectively, and fig. 8a, 8b and 8c show cross-sectional structures of the source/drain pad region, the active region and the gate pad region after performing the present step.
(7) Referring to fig. 9a, 9b and 9c, a first layer of interconnection metal 313 is formed, and the first interconnection metal 313 is filled into the interconnection via 312, wherein fig. 9a, 9b and 9c are schematic cross-sectional views of the source/drain pad region, the active region and the gate pad region after performing the present step.
In the above technical solution, since the pad area of the gate metal is not opened in the ohmic contact opening step, but the contact hole of the gate pad area is opened again in the first layer of interconnection metal through hole step, the electrical performance of the small device with the single gate finger structure cannot be represented immediately after the ohmic contact process is completed, and meanwhile, unnecessary disturbance variables are introduced, which is not beneficial to timeliness and accuracy of failure analysis. In addition, the delayed electrical performance test of the small device influences the high-efficiency execution of the experimental flow sheet plan, and is also a disadvantageous factor for improving the effective utilization rate of the production line resources. According to the invention, through collaborative optimization of the gate structure layout and the process flow, comprehensive electrical characterization of the completed process module can be realized immediately after the ohmic contact process module is completed, and compared with a process monitoring scheme of testing the electrical performance of the test structure after interconnection metal is completed, the performance characterization of the test structure can be advanced by two process layers, the flow period of process development is effectively shortened, the effective utilization rate of production line resources is improved, and more data acquisition nodes are provided for comprehensive failure analysis. The following describes the specific embodiments of the present invention in detail.
Example 1
The embodiment provides a manufacturing method of a test structure, which comprises the following steps:
s1: providing a semiconductor layer, forming an isolation structure in the semiconductor layer to isolate an active region in the semiconductor layer, wherein the semiconductor layer comprises a first material layer, a second material layer and a P-type layer which are sequentially arranged from bottom to top, the interface of the first material layer and the second material layer contains two-dimensional electron gas, and the isolation structure penetrates through the P-type layer and the second material layer;
s2: forming a gate metal layer on the P-type layer, forming a protective layer on the gate metal layer, and patterning the protective layer, the gate metal layer and the P-type layer, wherein the patterned P-type layer comprises a P-type boss positioned in the active region, the patterned gate metal layer comprises a gate leading-out layer positioned on the P-type boss and a gate pad connecting layer positioned on the isolation structure, and the patterned protective layer covers the upper surface of the patterned gate metal layer;
s3: forming an insulating layer to cover the isolation structure, the exposed surface of the second material layer and the protective layer, and patterning the insulating layer to obtain a source ohmic contact hole, a drain ohmic contact hole and a gate pad opening, wherein the source ohmic contact hole and the drain ohmic contact hole are both positioned in the active region and distributed on two sides of the P-type boss, the bottoms of the source ohmic contact hole and the drain ohmic contact hole expose the second material layer, the gate pad opening is positioned above the gate pad connecting layer, and the bottom of the gate pad opening exposes the protective layer;
S4: cleaning the surface of the second material layer exposed by the source ohmic contact hole and the drain ohmic contact hole;
s5: removing the protective layer at the bottom of the gate pad opening to expose the gate pad connection layer;
s6: an ohmic contact metal layer is formed on the insulating layer, the ohmic contact metal layer comprises a source electrode pad, a drain electrode pad, a gate electrode pad, a source electrode connecting wire and a drain electrode connecting wire, the source electrode pad, the drain electrode pad and the gate electrode pad are all located on the upper surface of the insulating layer above the isolation structure and are arranged at intervals, one end of the source electrode connecting wire is connected with the source electrode pad, the other end of the source electrode connecting wire extends into the source electrode ohmic contact hole to be electrically connected with the second material layer, one end of the drain electrode connecting wire is connected with the drain electrode pad, the other end of the drain electrode connecting wire extends into the drain electrode ohmic contact hole to be electrically connected with the second material layer, and the gate electrode pad is further filled into the gate electrode pad opening to be electrically connected with the gate electrode pad connecting layer.
By way of example, the test structures are fabricated in scribe line regions or other suitable regions of the wafer.
As an example, the test structure is a single-gate finger structure, please refer to fig. 10, which is a schematic plan view of the single-gate finger structure to be fabricated in this embodiment, and includes a gate pad 402, a source pad 403 and a drain pad 404 disposed on an isolation structure 401 at intervals, wherein the isolation structure 401 defines an active region 405, the gate pad 402 is connected to a gate in the active region through a first lead region 406, the source pad 403 is connected to a source in the active region through a second lead region 407, and the drain pad 404 is connected to a drain in the active region through a third lead region 408.
As an example, please refer to fig. 11, 12a, 12b and 12c, the step S1 is executed: a semiconductor layer is provided in which isolation structures 401 are formed to isolate active regions in the semiconductor layer.
Specifically, as shown in fig. 11, the semiconductor layer includes a first material layer 409, a second material layer 410, and a P-type layer 411 sequentially disposed from bottom to top, where an interface between the first material layer 409 and the second material layer 410 contains two-dimensional electron gas. In this embodiment, the material of the first material layer 409 includes intrinsic GaN, the material of the second material layer 410 includes AlGaN, and the material of the P-type layer 411 includes P-type GaN.
As an example, the semiconductor layer further includes a substrate layer 412 and a buffer layer 413 disposed on the substrate layer 412, where the first material layer 409 is disposed on the buffer layer 413, and in this embodiment, the material of the substrate layer 412 includes Si, and the material of the buffer layer 413 includes GaN.
Specifically, fig. 12a, 12b and 12c are schematic cross-sectional views of the source/drain pad region, the active region and the gate pad region after forming the isolation structure 401 in the semiconductor layer to define the active region. In this embodiment, an isolation trench may be formed in the semiconductor layer by a semiconductor process such as photolithography, etching, etc., and an isolation material may be filled in the isolation trench to obtain the isolation structure 401, where the isolation structure 401 penetrates through the P-type layer 411 and the second material layer 410.
Referring to fig. 13a, 13b and 13c, the step S2 is performed: forming a gate metal layer 414 on the P-type layer 411, and forming a protection layer 415 on the gate metal layer 414, and patterning the protection layer 415, the gate metal layer 414, and the P-type layer 411, wherein the patterned P-type layer 411 includes a P-type boss 411a located in the active region, the patterned gate metal layer 414 includes a gate lead-out layer 414a located on the P-type boss 411a and a gate pad connection layer 414b located on the isolation structure 401, and the patterned protection layer 415 covers the upper surface of the patterned gate metal layer 414. Fig. 13a, fig. 13b, and fig. 13c are schematic cross-sectional views of the source/drain pad region, the active region, and the gate pad region after performing the present step.
As an example, the material of the protective layer 415 includes SiO 2 And at least one of SiON, in this embodiment, the protective layer 415 is SiO 2 A layer.
It should be noted that, in the process of patterning the P-type layer 411, the isolation structure 401 in the region not covered by the patterned gate metal layer 414 is also removed by a certain thickness (as shown in fig. 13a and 13 b). The method of patterning the P-type layer 411 may be dry etching or other suitable method.
Referring to fig. 14a, 14b and 14c, the step S3 is performed: an insulating layer 416 is formed by chemical vapor deposition, physical vapor deposition or other suitable method to cover the isolation structure 401, the exposed surface of the second material layer 410 and the protection layer 415, and the insulating layer 416 is patterned to obtain a source ohmic contact hole 417, a drain ohmic contact hole 418 and a gate pad opening 419, wherein the source ohmic contact hole 417 and the drain ohmic contact hole 418 are both located in the active region and distributed on two sides of the P-type boss 411a, the bottoms of the source ohmic contact hole 417 and the drain ohmic contact hole 418 expose the second material layer 410, the gate pad opening 419 is located above the gate pad connection layer 414b, and the bottom of the gate pad opening 419 exposes the protection layer 415. Fig. 14a, fig. 14b, and fig. 14c are schematic cross-sectional views of the source/drain pad region, the active region, and the gate pad region after performing the present step.
As an example, the material of the insulating layer 416 includes silicon nitride.
The step S4 is then performed: the surface of the second material layer 410 exposed by the source ohmic contact hole 417 and the drain ohmic contact hole 418 is cleaned.
As an example, the surface of the second material layer 410 exposed by the source ohmic contact hole 417 and the drain ohmic contact hole 418 is cleaned with an acidic cleaning solution, and the acidic cleaning solution may remove the damaged layer on the surface of the second material layer 410.
As an example, the acidic cleaning solution includes at least one of sulfuric acid and hydrogen peroxide.
It should be noted that, during the process of cleaning the ohmic contact hole with the acidic cleaning solution, the protection layer 415 may serve as a hard mask to protect the gate metal layer 414 from being damaged during the ohmic contact hole cleaning process.
Referring to fig. 15a, 15b and 15c, the step S5 is performed: the protective layer 415 at the bottom of the gate pad opening 419 is removed to expose the gate pad connection layer 414b. Fig. 15a, 15b and 15c are schematic cross-sectional views of the source/drain pad region, the active region and the gate pad region after the step is performed.
In this embodiment, dilute HF (DHF) is used as an etching solution to remove the protective layer 415 at the bottom of the gate pad opening 419 to expose the gate pad connection layer 414b.
It should be emphasized that in step S3, the gate pad opening 419 is formed in the same photolithography and etching process as the source ohmic contact hole 417 and the drain ohmic contact hole 418, and in this step, the DHF is used to etch the protective layer 415 of the gate pad region to expose the gate pad connection layer 414b, so that no additional photolithography is required, and the production cost is not increased.
In addition, during the etching of the protective layer 415 of the gate pad region with DHF, DHF may have an effect of cleaning the surface of the second material layer 410 exposed by the source ohmic contact hole 417 and the drain ohmic contact hole 418 to remove the metal etching additional product.
Referring to fig. 16a, 16b and 16c, the step S6 is performed: an ohmic contact metal layer is formed on the insulating layer 416, where the ohmic contact metal layer includes a source pad 403, a drain pad 404, a gate pad 402, a source connection line 420 and a drain connection line 421, the source pad 403, the drain pad 404 and the gate pad 402 are all located on an upper surface of the insulating layer 416 above the isolation structure 401 and are disposed at intervals, one end of the source connection line 420 is connected to the source pad 403, the other end of the source connection line 420 extends into the source ohmic contact hole 417 to be electrically connected to the second material layer 410, one end of the drain connection line 421 is connected to the drain pad 404, the other end of the drain connection line 421 extends into the drain ohmic contact hole 418 to be electrically connected to the second material layer 410, and the gate pad 402 is further filled into the gate pad opening 419 to be electrically connected to the gate pad connection layer 414b. Fig. 16a, 16b and 16c are schematic cross-sectional structures of the source/drain pad region, the active region and the gate pad region, which are shown after this step is performed, and fig. 16a only shows the source pad 403.
Thus, a test structure is manufactured, and WAT test can be performed by adopting the test structure. It should be noted that the layout of the test structure is not limited to the schematic plan view shown in fig. 10, and may be adjusted according to actual needs.
Compared with a process monitoring scheme for testing the electrical performance of the test structure after the interconnection metal is finished, the manufacturing method of the test structure of the embodiment can perform comprehensive electrical characterization on the finished process module in real time after the ohmic contact process module is finished through optimization of the whole technical scheme of combining the grid metal protection layer with DHF cleaning, the performance characterization of the test structure such as a single-grid finger small device is advanced by two process layers, the flow period of process development is effectively shortened, the effective utilization rate of production line resources is improved, and more data acquisition nodes are provided for comprehensive failure analysis.
Example two
In this embodiment, a test structure is provided, which can be manufactured by the manufacturing method described in the first embodiment, please refer to fig. 10, 16a, 16b and 16c, wherein fig. 10 is a schematic plan view of the test structure when a single-gate finger structure is adopted, and fig. 16a, 16b and 16c are schematic cross-sectional views of the source/drain pad region, the active region and the gate pad region of the test structure respectively.
Specifically, the test structure includes a semiconductor layer, an isolation structure 401, a gate metal layer, a protection layer 415, an insulation layer 416, a source ohmic contact hole, a drain ohmic contact hole, a gate pad opening, and an ohmic contact metal layer, where the semiconductor layer includes a first material layer 409, a second material layer 410, and a P-type boss 411a sequentially disposed from bottom to top, and an interface between the first material layer 409 and the second material layer 410 contains two-dimensional electron gas; the isolation structure 401 is located in the semiconductor layer to isolate an active region in the semiconductor layer, the isolation structure 401 penetrates through the second material layer 410, and the P-type boss 411a is located in the active region and located on the second material layer 410; the gate metal layer includes a gate lead-out layer 414a on the P-type boss 411a and a gate pad connection layer 414b on the isolation structure 401; the protection layer 415 covers the upper surface of the gate metal layer; the insulating layer 416 covers the isolation structure 401, the exposed surface of the second material layer 410, and the surface of the protection layer 415; the source ohmic contact holes and the drain ohmic contact holes are located in the active region and distributed on two sides of the P-type boss 411a, and penetrate through the insulating layer 416 to expose the second material layer 410, and the gate pad opening is located above the gate pad connection layer 414b and penetrates through the insulating layer 416 and the protective layer 415 to expose the gate pad connection layer 414b; the ohmic contact metal layer is disposed on the insulating layer 416 and includes a source pad 403, a drain pad 404, a gate pad 402, a source connection line 420 and a drain connection line 421, the source pad 403, the drain pad 404 and the gate pad 402 are all disposed on an upper surface of the insulating layer 416 above the isolation structure 401 and are spaced apart, one end of the source connection line 420 is connected to the source pad 402, the other end of the source connection line 420 extends into the source ohmic contact hole to be electrically connected to the second material layer 410, one end of the drain connection line 421 is connected to the drain pad 404, the other end of the drain connection line 421 extends into the drain ohmic contact hole to be electrically connected to the second material layer 410, and the gate pad 402 is further filled into the gate pad opening to be electrically connected to the gate pad connection layer 414 b.
In summary, the manufacturing method of the test structure of the invention introduces the protective layer as the hard mask to protect the gate metal through the collaborative optimization of the gate structure layout and the process flow, thereby avoiding the gate metal from being damaged in the ohmic contact hole cleaning process, and the completed process module can be comprehensively and electrically characterized in real time after the ohmic contact process module is completed. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method of fabricating a test structure, comprising the steps of:
providing a semiconductor layer, forming an isolation structure in the semiconductor layer to isolate an active region in the semiconductor layer, wherein the semiconductor layer comprises a first material layer, a second material layer and a P-type layer which are sequentially arranged from bottom to top, the interface of the first material layer and the second material layer contains two-dimensional electron gas, and the isolation structure penetrates through the P-type layer and the second material layer;
forming a gate metal layer on the P-type layer, forming a protective layer on the gate metal layer, and patterning the protective layer, the gate metal layer and the P-type layer, wherein the patterned P-type layer comprises a P-type boss positioned in the active region, the patterned gate metal layer comprises a gate leading-out layer positioned on the P-type boss and a gate pad connecting layer positioned on the isolation structure, and the patterned protective layer covers the upper surface of the patterned gate metal layer;
forming an insulating layer to cover the isolation structure, the exposed surface of the second material layer and the protective layer, and patterning the insulating layer to obtain a source ohmic contact hole, a drain ohmic contact hole and a gate pad opening, wherein the source ohmic contact hole and the drain ohmic contact hole are both positioned in the active region and distributed on two sides of the P-type boss, the bottoms of the source ohmic contact hole and the drain ohmic contact hole expose the second material layer, the gate pad opening is positioned above the gate pad connecting layer, and the bottom of the gate pad opening exposes the protective layer;
Cleaning the surface of the second material layer exposed by the source ohmic contact hole and the drain ohmic contact hole;
removing the protective layer at the bottom of the gate pad opening to expose the gate pad connection layer;
an ohmic contact metal layer is formed on the insulating layer, the ohmic contact metal layer comprises a source electrode pad, a drain electrode pad, a gate electrode pad, a source electrode connecting wire and a drain electrode connecting wire, the source electrode pad, the drain electrode pad and the gate electrode pad are all located on the upper surface of the insulating layer above the isolation structure and are arranged at intervals, one end of the source electrode connecting wire is connected with the source electrode pad, the other end of the source electrode connecting wire extends into the source electrode ohmic contact hole to be electrically connected with the second material layer, one end of the drain electrode connecting wire is connected with the drain electrode pad, the other end of the drain electrode connecting wire extends into the drain electrode ohmic contact hole to be electrically connected with the second material layer, and the gate electrode pad is further filled into the gate electrode pad opening to be electrically connected with the gate electrode pad connecting layer.
2. The method of manufacturing a test structure according to claim 1, wherein: the semiconductor layer further comprises a substrate layer and a buffer layer positioned on the substrate layer, and the first material layer is positioned on the buffer layer.
3. The method of manufacturing a test structure according to claim 2, wherein: the material of substrate layer includes Si, the material of buffer layer includes GaN, the material of first material layer includes intrinsic GaN, the material of second material layer includes AlGaN, the material of P type layer includes P type GaN.
4. The method of manufacturing a test structure according to claim 1, wherein: the cleaning solution adopted for cleaning the surface of the second material layer exposed by the source electrode ohmic contact hole and the drain electrode ohmic contact hole comprises an acidic cleaning solution, and the acidic cleaning solution is used for removing a damaged layer on the surface of the second material layer.
5. The method of manufacturing a test structure according to claim 4, wherein: the acidic cleaning solution comprises at least one of sulfuric acid and hydrogen peroxide.
6. The method of manufacturing a test structure according to claim 1, wherein: the etching solution used for removing the protective layer at the bottom of the grid electrode bonding pad opening comprises diluted hydrofluoric acid.
7. The method of manufacturing a test structure according to claim 6, wherein: the diluted hydrofluoric acid is also used for cleaning the surface of the second material layer exposed by the source ohmic contact hole and the drain ohmic contact hole so as to remove metal etching additional products.
8. The method of manufacturing a test structure according to claim 1, wherein: the material of the protective layer comprises SiO 2 And at least one of SiON.
9. The method of manufacturing a test structure according to claim 1, wherein: the test structure is a single gate finger structure.
10. A test structure, comprising:
the semiconductor layer comprises a first material layer, a second material layer and a P-type boss which are sequentially arranged from bottom to top, and the interface of the first material layer and the second material layer contains two-dimensional electron gas;
an isolation structure located in the semiconductor layer to isolate an active region in the semiconductor layer, the isolation structure penetrating through the second material layer, the P-type boss located in the active region and on the second material layer;
the grid metal layer comprises a grid lead-out layer positioned on the P-type boss and a grid pad connecting layer positioned on the isolation structure;
a protective layer covering the upper surface of the gate metal layer;
the insulating layer covers the isolation structure, the exposed surface of the second material layer and the surface of the protective layer;
the source ohmic contact holes and the drain ohmic contact holes are positioned in the active region and distributed on two sides of the P-type boss, the source ohmic contact holes and the drain ohmic contact holes penetrate through the insulating layer to expose the second material layer, and the gate pad opening is positioned above the gate pad connecting layer and penetrates through the insulating layer and the protective layer to expose the gate pad connecting layer;
Ohmic contact metal layer is located on the insulating layer and comprises a source electrode pad, a drain electrode pad, a gate electrode pad, a source electrode connecting wire and a drain electrode connecting wire, wherein the source electrode pad, the drain electrode pad and the gate electrode pad are all located on the upper surface of the insulating layer above the isolation structure and are arranged at intervals, one end of the source electrode connecting wire is connected with the source electrode pad, the other end of the source electrode connecting wire extends into the source electrode ohmic contact hole to be electrically connected with the second material layer, one end of the drain electrode connecting wire is connected with the drain electrode pad, the other end of the drain electrode connecting wire extends into the drain electrode ohmic contact hole to be electrically connected with the second material layer, and the gate electrode pad is filled into the gate electrode pad opening to be electrically connected with the gate electrode pad connecting layer.
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