CN117826972A - Low-power mode control method and system - Google Patents
Low-power mode control method and system Download PDFInfo
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Abstract
The application relates to the field of electronic circuits and discloses a low-power-consumption mode control method and a system. The method comprises the following steps: receiving an instruction of the system entering a first low-power-consumption state, judging that the current system clock is a phase-locked loop clock, and if the current system clock is the phase-locked loop clock, switching the current system clock to a source clock of the phase-locked loop clock; closing other clocks except the current system clock; and starting to close the current system clock and delaying to close the current system clock for N clock cycles, generating a first-stage isolation signal at the last M clock falling edges before the current system clock is closed to close the peripheral module in a step-by-step mode, and respectively generating a power-off signal at the last clock falling edge before the current system clock is closed to close a system power supply and a second-stage isolation signal to isolate signals influenced by the closing of the system power supply. The embodiment of the invention can realize gradual and rapid response of low-power-consumption control, and simultaneously ensure the stability and reliability of the system in the low-power-consumption entering process.
Description
Technical Field
The present application relates to the field of electronic circuits, and in particular, to a low power mode control technique.
Background
At present, the chip low-power consumption management commonly used implementation method comprises the following steps: the chip architecture is divided into a plurality of power domains to supply power respectively, a module which does not need to run under low power consumption is powered off or cut off, and the power supply voltage of a part of modules which only needs to run at low speed or keep is reduced, so that the sleeping power consumption is as low as possible; and turning off the high-frequency clock under low power consumption, using the low-frequency clock to maintain the minimum running requirement of the system, and further turning off all clocks to realize lower sleep power consumption. However, the low power consumption control method using the low frequency clock may not achieve the lowest sleep power consumption on one hand, and consume additional power consumption in the process when the response time for entering and waking up is long on the other hand.
Disclosure of Invention
The purpose of the application is to provide a low-power-consumption mode control method and a system, which can realize gradual and rapid response of low-power-consumption control and simultaneously ensure the stability and reliability of the system in the low-power-consumption entering process.
The application discloses a low power consumption mode control method, which comprises the following steps:
receiving an instruction of the system entering a first low-power-consumption state, judging that the current system clock is a phase-locked loop clock, and if the current system clock is the phase-locked loop clock, switching the current system clock to a source clock of the phase-locked loop clock;
Closing other clocks except the current system clock;
and starting to close the current system clock and delaying to close the current system clock for N clock cycles, generating a first-stage isolation signal at the last M clock falling edges before the current system clock is closed to close the peripheral module in a step-by-step mode, and respectively generating a power supply closing signal at the last clock falling edge before the current system clock is closed to close a system power supply and a second-stage isolation signal to isolate signals influenced by the closing of the system power supply, wherein M, N is an integer, N is more than 1 and M is less than or equal to N.
In a preferred embodiment, the signal affected by system power shut down includes one or more of the following: power supply from the power down domain, control and configuration signals for the clock, reset signals from the power down domain, and configuration signals for wake-up logic and control and configuration signals for the real time clock from the non-power down domain.
In a preferred embodiment, the enabling and the delaying of the disabling of the current system clock for N clock cycles generates the first stage isolation signal to disable the peripheral module at the next to last (M) clock falling edge before the disabling of the current system clock, and generates the power disable signal to disable the system power and the second stage isolation signal to isolate the signal affected by the system power in a stepwise manner at the last clock falling edge before the disabling of the current system clock, respectively, further comprising:
And starting to close the current system clock and delaying to close the current system clock for N clock cycles, generating a first-stage isolation signal at the last M clock falling edge of the system clock which delays to close the N clock cycles in a step-by-step mode by utilizing an isolation circuit to close the peripheral module, and respectively generating a power-off signal at the last clock falling edge of the system clock which delays to close the N clock cycles to close the system power and a second isolation signal to isolate signals influenced by the system power-off.
In a preferred embodiment, the method further comprises:
the power supply detection and protection module receives a system wake-up instruction and asynchronously starts a system power supply; when the system power supply is detected to be built, generating and sending a power-down domain power-up completion mark signal to an isolation circuit, wherein the isolation circuit controls to release the first-stage isolation signal and the second-stage isolation signal based on an input wake-up signal and the power-down domain power-up completion mark signal, and asynchronously starting a system clock; and
the isolation circuit controls release of the first stage isolation signal and the second isolation signal based on an input reset signal.
In a preferred embodiment, the isolation circuit includes first to fourth inverters, first to third D flip-flops, first to second nor gates, and first to second or gates, where the input terminals of the first to fourth inverters, the second input terminal of the first nor gate, and the clock terminals of the second and third D flip-flops are respectively used as the first, second, sixth, and seventh input terminals of the isolation circuit for accessing the reset signal, the wake-up signal, the system clock, respectively, the third to fifth input terminals of the isolation circuit are respectively used for accessing the power-down domain up completion flag signal, the output terminals of the first inverter are respectively connected to the first input terminals of the second nor gate, the output terminals of the second nor gate are respectively connected to the clear terminals of the second and third D flip-flops, the output terminals of the second nor gate are respectively connected to the first input terminals of the first nor gate, the output terminals of the first nor gate are respectively connected to the first D flip-flop, the second output terminals of the second nor gate are respectively connected to the first input terminals of the first D flip-flop, the second output terminal of the second nor gate, the first D flip-flop is connected to the second output terminal of the first nor gate, the first D flip-flop is connected to the first D flip-flop, the second D flip-flop is respectively, the first D flip-flop is connected to the first output terminal of the first nor gate, and the third D flip-flop is connected to the first output terminal is connected to the first output signal, and the third output signal is respectively.
The application also discloses another low-power consumption mode control method, which comprises the following steps:
receiving an instruction of a system in a first running state to enter a second low-power-consumption state, judging that the current system clock is a phase-locked loop clock, and if yes, switching the current system clock to a source clock of the phase-locked loop clock;
closing other clocks except the current system clock;
and starting to close the current system clock and delaying to close the current system clock for N clock cycles, and generating a power supply mode switching signal at the last clock falling edge before closing the current system clock to switch the system power supply from a first power consumption mode to a second power consumption mode, wherein the current consumed by the first power consumption mode is larger than that of the second power consumption mode, and the power supply in the second power consumption mode is used for maintaining the states of all modules in the system so as to enable the system to recover to the first running state when a system wake-up instruction is received.
In a preferred embodiment, the method further comprises:
when the current system clock is started and closed, a low-power consumption cooperative signal is generated and input to a clock control and protection circuit;
when detecting source clock abnormality as a first clock source, switching a current system clock to an internal high-frequency second clock source and generating a first clock source abnormality signal to be input to the clock control and protection circuit;
The clock control and protection circuit controls the second clock to be kept on based on the input low-power consumption cooperative signal and the first clock source abnormal signal, and outputs a power control signal under low power consumption to a power detection and protection module;
the power supply detection and protection module controls and prevents mode switching of the system power supply based on an input low-power-consumption power supply control signal.
In a preferred embodiment, the method further comprises:
when the power supply detection and protection module receives a system wake-up instruction, the system power supply is controlled to be switched from the second power consumption mode to the first power consumption mode;
and when the power supply detection and protection module detects that the first power consumption mode is switched, generating and sending a power supply completion signal, and asynchronously starting a system clock.
In a preferred embodiment, the clock control and protection circuit includes an output terminal and an and gate, a nor gate, first to fourth inverters, a delay circuit, a first nand gate, a second nand gate, and an or gate, wherein an input terminal of the first inverter, first and second input terminals of the and gate, a second input terminal of the nor gate, an input terminal of the second inverter, and a second input terminal of the or gate are respectively used as first to sixth input terminals of the clock control and protection circuit, and the first to sixth input terminals are respectively used for accessing a first clock source exception signal, a wake-up signal, a power-down domain power-up completion flag signal, a second clock source, and a power-down co-processing signal; the output end of the OR gate is used as the output end of the clock control and protection circuit; the output end of the first inverter is connected to the first input end of the first NAND gate, the output end of the AND gate is connected to the first input end of the NOR gate, the output end of the NOR gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is respectively connected to the input end of the second inverter and the clock end of the delay circuit, the input end of the delay circuit is connected with the output end of the third inverter, the input end of the delay circuit is connected to the fourth inverter, the output ends of the third inverter and the fourth inverter are respectively connected to the first input end and the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the first input end of the OR gate.
The application also discloses a low power consumption mode control system, including:
the clock control module is used for receiving a command of the system entering the first low-power-consumption state, judging that the current system clock is a phase-locked loop clock, if yes, switching the current system clock to a source clock of the phase-locked loop clock, closing other clocks except the current system clock, starting to close the current system clock and delaying to close the current system clock for N clock cycles;
the power control module is used for generating a first-stage isolation signal at the last M clock falling edges before the current system clock is closed to close the peripheral module in a step-by-step mode, and respectively generating a power closing signal at the last clock falling edges before the current system clock is closed to close a system power supply and a second-stage isolation signal to isolate signals influenced by the system power supply closing, wherein M, N is an integer, N is more than 1 and M is more than 1 and less than or equal to N.
The application also discloses another low power consumption mode control system, which comprises:
the clock control module is used for receiving an instruction of the system entering a second low-power-consumption state, judging that the current system clock is a phase-locked loop clock, if yes, switching the current system clock to a source clock of the phase-locked loop clock, closing other clocks except the current system clock, starting to close the current system clock and delaying to close the current system clock for N clock cycles;
The power supply control module is used for generating a power supply mode switching signal at the last clock falling edge before the current system clock is closed so as to switch the system power supply from a first power consumption mode to a second power consumption mode, the current consumed by the first power consumption mode is larger than that consumed by the second power consumption mode, the power supply in the second power consumption mode is used for maintaining the states of all modules in the system so as to enable the system to be restored to the first running state when a system wake-up instruction is received, and N is an integer and is more than 1.
In this application embodiment, at least the following advantages and benefits are included: 1. the low power consumption entering process is not limited by clock types, the system clock is automatically switched to be a source clock, a non-system clock is closed, the system clock and a system power supply are gradually closed in a grading manner, and the grading isolation control is carried out, so that the dynamic power consumption is gradually reduced in a step-by-step manner, the step change of the load power consumption is reduced, and the system stability is improved. 2. The use of an external or internal high frequency clock ensures that the low power consumption entry and wake-up response is rapid. 3. When the clock is abnormal or the reset which cannot be shielded is generated, the clock control and protection circuit and the power supply detection and protection module can ensure the safety and reliability of the system in the low-power consumption control entering and waking process. 4. The wake-up operation is carried out through the change of the asynchronous signal, the power supply is firstly recovered by the asynchronous signal, and the clock is started and then synchronized after the reliable voltage of the power supply is recovered, so that the rapid and reliable wake-up operation is realized.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are all regarded as being already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
Fig. 1 is a flowchart of a low power mode control method according to a first embodiment of the present application.
Fig. 2 is a circuit diagram of an isolation circuit according to one embodiment of the present application.
Fig. 3 is a flowchart of a low power mode control method according to a second embodiment of the present application.
Fig. 4 is a circuit diagram of a clock control and protection circuit according to one embodiment of the present application.
FIG. 5 is a block diagram of a low power control system according to one embodiment of the present application.
FIG. 6 is a block diagram of a low power control process according to one embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
A first embodiment of the present application relates to a low power consumption mode control method, the flow of which is shown in fig. 1, and the method includes the following steps:
step 101, receiving a command of the system entering a first low-power-consumption state, judging that the current system clock is a phase-locked loop clock, and if yes, switching the current system clock to a source clock of the phase-locked loop clock. The system described herein may be a single chip or a system of multiple chips, etc.
Step 102, other clocks except the current system clock are turned off.
Step 103, starting to close the current system clock and delaying to close the current system clock for N clock cycles, and generating a first-stage isolation signal at the last M clock falling edge before the current system clock is closed to close the peripheral module in a step-by-step mode, and respectively generating a power-off signal at the last clock falling edge before the current system clock is closed to close a system power supply and a second-stage isolation signal to isolate signals influenced by the system power supply closing, wherein M, N is an integer, N is more than 1 and M is less than or equal to N.
Optionally, the signal affected by the system power off in step 103 includes one or more of the following: power supply from a power down domain, control and configuration signals for a clock, reset signals from a power down domain, and configuration signals for wake-up logic and control and configuration signals for a Real Time Clock (RTC) from a non-power down domain.
Optionally, the step 103 may further include the steps of: and starting to close the current system clock and delaying to close the current system clock for N clock cycles, generating a first-stage isolation signal at the last M clock falling edge of the system clock which delays to close the N clock cycles by using an isolation circuit in a step-by-step mode, and respectively generating a power-off signal at the last clock falling edge of the system clock which delays to close the N clock cycles to close the system power and a second isolation signal to isolate signals influenced by the system power off.
After the system enters and is in the first low power consumption state, optionally, performing a system wake-up operation by: the power supply detection and protection module receives a system wake-up instruction and asynchronously starts a system power supply; when the system power supply is detected to be built, a power-down domain power-on completion sign signal is generated and sent to an isolation circuit, and the isolation circuit controls and releases the first-stage isolation signal and the second-stage isolation signal based on the input wake-up signal and the power-down domain power-on completion sign signal, and then asynchronously starts a system clock. Since the system is in a low power state, the reset signal is a non-maskable signal, in one embodiment the isolation circuit controls the release of the first stage isolation signal and the second isolation signal based on the input reset signal.
In one embodiment, as shown in fig. 2, the isolation circuit includes first to fourth inverters, first to third D flip-flops, first to second nor gates, and first to second or gates, wherein the input terminals of the first to fourth inverters, the second input terminal of the first nor gate, and the clock terminals of the second and third D flip-flops are respectively used as the first, second, sixth, and seventh input terminals of the isolation circuit for accessing a reset signal, a wake-up signal, a system clock, and a system clock, respectively, the third to fifth input terminals of the isolation circuit are respectively used for accessing a power-down domain power-up completion flag signal (pwr_rdy=1), the output terminal of the first inverter is connected to the first input terminal of the second nor gate, the output terminal of the nor gate is respectively connected to the clear terminals of the second and third D flip-flops, the output end of the second inverter is connected to the first input end of the first nor gate, the output end of the first nor gate is connected to the clock end of the first D flip-flop, the output end of the first D flip-flop is connected to the second input end of the first nor gate, the input ends of the first to third D flip-flops are respectively connected to 1, the output ends of the second and third D flip-flops are respectively connected to the first input ends of the first and second or gates, the second input ends of the first and second or gates are respectively connected to the output ends of the third and fourth inverters, and the output ends of the first and second or gates and the output end of the third D flip-flop are respectively used as the output ends of the isolation circuit to respectively output the first isolation signal, the power-off control signal and the second isolation signal.
A second embodiment of the present application relates to a low power consumption mode control method, the flow of which is shown in fig. 3, and the method includes the following steps:
step 301, receiving an instruction that the system in the first running state enters the second low power consumption state, judging that the current system clock is a phase-locked loop clock, if yes, switching the current system clock to a source clock of the phase-locked loop clock;
step 302, other clocks except the current system clock are closed;
step 303, starting to close the current system clock and delay closing the current system clock for N clock cycles, and generating a power mode switching signal at the last clock falling edge before closing the current system clock to switch the system power supply from a first power consumption mode to a second power consumption mode, wherein the current consumed by the first power consumption mode is greater than that consumed by the second power consumption mode, and the power supply in the second power consumption mode is used for maintaining the states of all modules in the system so as to restore the system to the first running state when a system wake-up instruction is received, wherein N is an integer, and N is more than 1.
Optionally, the method further comprises: when the current system clock is started and closed, a low-power consumption cooperative signal is generated and input to a clock control and protection circuit; when detecting that the source clock serving as the first clock source is abnormal, switching the current system clock into a second clock source with internal high frequency and generating a first clock source abnormal signal to be input into the clock control and protection circuit; the clock control and protection circuit controls the second clock to be kept on based on the input low-power consumption cooperative signal and the first clock source abnormal signal, and outputs a low-power consumption power supply control signal (pwr_lp=1) to the power supply detection and protection module; the power supply detection and protection module controls and prevents mode switching of the system power supply based on an input low-power-consumption power supply control signal.
When the system enters and is in the first low-power consumption state, the system can be optionally awakened by the following steps: when the power supply detection and protection module receives a system wake-up instruction, the system power supply is controlled to be switched from the second power consumption mode to the first power consumption mode; when the power supply detection and protection module detects that the first power consumption mode is switched, a power supply completion signal is generated and sent, and then a system clock is started asynchronously.
In one embodiment, as shown in fig. 4, the clock control and protection circuit includes an output terminal and an and gate, a nor gate, first to fourth inverters, a delay circuit, a first nand gate, a second nand gate and an or gate, wherein an input terminal of the first inverter, first and second input terminals of the and gate, a second input terminal of the nor gate, an input terminal of the second inverter and a second input terminal of the or gate are respectively used as first to sixth input terminals of the clock control and protection circuit, and the first to sixth input terminals are respectively used for accessing a first clock source abnormality signal, a wake-up signal, a power-down power-up completion flag signal, a low power consumption co-processing signal, a second clock source, and a power low power consumption control signal; the output end of the OR gate is used as the output end of the clock control and protection circuit; the output end of the first inverter is connected to the first input end of the first NAND gate, the output end of the AND gate is connected to the first input end of the NOR gate, the output end of the NOR gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is respectively connected to the input end of the second inverter and the clock end of the delay circuit, the input end of the delay circuit is connected with the output end of the third inverter, the input end of the delay circuit is connected to the fourth inverter, the output ends of the third inverter and the fourth inverter are respectively connected to the first input end and the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the first input end of the OR gate.
A third embodiment of the present application relates to a low power mode control system that includes a clock control module and a power control module.
The clock control module is used for receiving an instruction of the system entering a first low-power-consumption state, judging that the current system clock is a phase-locked loop clock, if yes, switching the current system clock to a source clock of the phase-locked loop clock, closing other clocks except the current system clock, starting to close the current system clock, and delaying to close the current system clock for N clock cycles; the power control module is used for generating a first-stage isolation signal at the last M clock falling edges before the current system clock is closed to close the peripheral module in a step-by-step mode, and respectively generating a power closing signal at the last clock falling edges before the current system clock is closed to close a system power supply and a second-stage isolation signal to isolate signals influenced by the system power supply closing, wherein M, N is an integer, N is more than 1 and M is more than 1 and less than or equal to N. It will be appreciated that the clocks of the other modules, except for the low power mode control system, are gated prior to switching or shutting down the clocks.
Note that the first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.
A fourth embodiment of the present application relates to a low power mode control system that includes a clock control module and a power control module. The clock control module is used for receiving an instruction of the system entering a second low-power-consumption state, judging that the current system clock is a phase-locked loop clock, if yes, switching the current system clock to a source clock of the phase-locked loop clock, closing other clocks except the current system clock, starting to close the current system clock, and delaying to close the current system clock for N clock cycles; the power supply control module is used for generating a power supply mode switching signal at the last clock falling edge before the current system clock is closed so as to switch the system power supply from a first power consumption mode to a second power consumption mode, the current consumed by the first power consumption mode is larger than that consumed by the second power consumption mode, the power supply in the second power consumption mode is used for maintaining the states of all modules in the system so as to enable the system to recover to the first running state when a system wake-up instruction is received, and N is an integer and is more than 1.
Note that the second embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the second embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.
In order to better understand the technical solutions of the present application, the following description is given with reference to a specific example, in which details are listed mainly for the sake of understanding, and are not meant to limit the scope of protection of the present application. As shown in fig. 5 and 6, the low power consumption control system block diagram and the low power consumption control process block diagram of the present embodiment are respectively. As shown in fig. 5, the Gate output signal clkgate_out may be used to control other system module clocks except fig. 5, and is used to generate a clock Gate in the low power consumption of the entering process to reduce the dynamic power consumption of the chip first, and output 0 in the non-low power consumption by default, and is jointly controlled by the combination of the entering sleep generation Gate0, the clock control module output Gate1 and the output Gate2 of the power control module. The clock of the low-power consumption control related module comes from a clock source and is not influenced by the gating. In the following description, the controlled clock is described as FCLK. Under the lowest power consumption mode, two-stage isolation signals, namely a first-stage isolation signal (ISO 1) and a second-stage isolation signal (ISO 2), are sequentially generated, wherein ISO1 is an isolation signal actively generated before a power supply is turned off, and is used for turning off most of module signals except a clock and a power supply, ISO2 is generated when the clock and the power supply are turned off at the falling edge of the last clock, is used for isolating the power supply and a clock related control signal influenced by power failure, and is also a reset signal for a power failure domain, after the power supply detection output confirms that the power supply is established after awakening, ISO2 and ISO1 are released, a high-frequency system clock is turned on, and the system operates after the clock is stabilized.
In the low power consumption control system of the present embodiment, clock and power supply control at low power consumption is divided into four stages of modes of gradually decreasing power consumption:
firstly, the general control process of the four-stage low power consumption modes 1 to 4 comprises the following steps: generating a signal of dormancy and Gate0=1 when the execution enters low power consumption, wherein Gate0=1 controls output ClkGate_out=1 through GateCtrl combination to enable system gating, so that dynamic power consumption of the system is reduced; the low-power-consumption state indication signal is provided to the clock control module through the synchronous 1 module, the clock control module locks the synchronous 1 module, and meanwhile, the sleep maintaining module is controlled to shield the wake-up source so as to maintain in a low-power-consumption processing state, and the low-power-consumption entering state signal is output to the synchronous 2 module so as to maintain the state of Gate0=1 to be effective. The low power consumption entering process is effectively prevented from being interrupted by the awakened source through clock gate combination and low power consumption state maintaining control.
Further, the four-stage low power consumption modes 1 to 4 are specifically described as:
(1) Low power mode 1 (clock on, power hold): the clock control module does not automatically switch/close the system clock, releases the Gate0 after the synchronization 3 is processed, closes the shielding signal of the sleep maintaining module, and cancels the input low-power-consumption entering state signal of the synchronization 2 module; FCLK gating is released, at which point an interrupt wakeup signal may be received to wake the system up.
(2) Low power consumption mode 2 (clock off, power hold): the clock control module firstly performs system clock switching and other clock closing processing, and when the system clock is a PLL, the system is preferentially switched into a source clock of the PLL so as to reduce the dynamic power consumption of the system; then other clocks except the system clock are closed, and after the other clocks are closed, the current system clock is prepared to be closed; the clock is closed after the processing of the synchronous 3 module, the Gate0 is released, the shielding signal of the sleep maintaining module is closed, the input low-power-consumption entering state signal of the synchronous 2 module is cancelled, and the wake-up source signal can be received. Since the last falling edge clock is turned off when entering low power consumption, the clock control module outputs a Gate signal Gate 1=1 to control clkgate_out to keep 1; when the system is awakened, the system clock is started asynchronously, after the clock is established stably, the clock control module releases the input control GateCtrl combination control Gate1=0, FCLK gating is released, and the system responds to the awakening signal for processing.
(3) Low power mode 3 (clock off, power supply switching low power supply): the clock control module firstly performs system clock switching and other clock closing processing, and when the system clock is a PLL, the system is preferentially switched into a source clock of the PLL so as to further reduce the system power consumption; and then other clocks except the system clock are closed, and after the other clocks are closed, when the current system clock starts to be closed, a low-power-consumption cooperative processing signal is generated to ensure that the power management control and the clock closing control are kept synchronous. The clock control module and the power control module realize the simultaneous closing of the clock and the power switching through the synchronous 3 module (for example, the clock control module and the power control module are configured to carry out signal delay through a latch), the input low-power-consumption entering state signal of the synchronous 2 module is withdrawn, and the wake-up source signal can be received. The clock control module output Gate 1=1 and the power control module output Gate 2=1 hold clkgate_out at 1; when the power supply is started, the asynchronous power supply starting module is switched to a normal power supply, when the completion of power supply establishment is detected, the power supply control module releases Gate2=0, a system clock is started, after the clock establishment is stable, the clock control module releases Gate1=0, at the moment, clkGate_out=0, FCLK gating is released, and the system responds to a wake-up signal for processing.
(4) Low power mode 4 (clock off, power off): the clock control module firstly performs system clock switching and other clock closing processing, and when the system clock is a PLL, the system is preferentially switched into a source clock of the PLL so as to reduce the system power consumption; and then other clocks except the system clock are closed, and after the other clocks are closed, when the current system clock starts to be closed, a low-power-consumption cooperative processing signal is generated to ensure that the power management control and the clock closing control are kept synchronous. The clock control module and the power control module generate ISO1 through the synchronous 3 module, are used for actively isolating and closing most peripheral modules, further reduce the power consumption of the system, the synchronous 3 module generates ISO2 after generating ISO1, simultaneously closes the clock and closes the power supply, the input low-power-consumption entering state signal of the synchronous 2 module is withdrawn, the signals of the power-down part modules are isolated, and the wake-up source signal can be received. The clock control module output Gate 1=1 and the power control module output Gate 2=1 hold clkgate_out at 1; when the power supply is started asynchronously, when the completion of power supply establishment is detected, the power supply control module releases Gate 2=0, opens a system clock, and after the clock establishment is stable, the clock control module releases Gate 1=0, at the moment, clkgate_out=0, FCLK gating is released, and the system responds to the wake-up signal for processing. The synchronous 3 module generates ISO1 and ISO2 at different time points, the clock control module generates a synchronous signal when the current clock is closed after a series of clock switching closing operations are completed, and the current clock is closed and uses a plurality of triggers to delay (a clock falling edge is used), so that a simulation module which really closes the generated clock has a plurality of CLK; the power control module processes operations related to the module and power off by using the falling edge on the basis of the synchronous signal and in the time delay of the clock to turn off the effective clocks, and finally, the clock off and the power off are completed by the same falling edge.
In the low power control system of this embodiment, the reset is an unshielded signal in the process of entering low power, so when the reset except the power is removed, 1-3 and sleep are kept, the sleep signal and Gate0 are all reset immediately, but the clock control and the power control keep Gate1 and Gate2 in effect, when the power is reset, the power supply is turned on first, and when pwr_rdy=1 is output after the power is stable, the clock is turned on and Gate2 is released, and when the clock is stable, gate1 is released, and finally Gate of FCLK is released, and the system operates.
As shown in fig. 6, when the system uses the PLL clock to perform low power access, the hardware first reduces dynamic power consumption through clock gating, switches the system clock to the source clock of the PLL, and then closes the clocks opened except the current system clock, thereby further reducing dynamic power consumption caused by the clock. Finally, starting to shut down the currently used system clock and power supply (taking the internal HRC clock as an example, and taking the external OSC as a similar way), generating a first-stage isolation signal at one clock falling edge before the current system clock is shut down to shut down the peripheral module and the last clock falling edge to generate a second-stage isolation signal and generate a power off signal power_off, wherein the power off signal power_off is used for ensuring that the clock is shut down and the switching/shutting down of the power supply is synchronously completed, the clock off delay uses the falling edge of the self clock (HRC) to carry out synchronous processing, the output 0 is kept after the clock is shut down, and the falling edge shutting down processing can ensure that burrs are not generated; the receipt of the lp_sync signal by the power management module also synchronizes using the falling edge of the system clock (HRC).
If the external crystal oscillator OSC is used, clock stop may be generated in the low power consumption process, the clock state detection module detects the abnormal output osc_err_flag, and automatically opens the internal non-stop reliable clock source (HRC) of hrc_clk_en=1 through the protection logic shown in fig. 4, the oscillation stop protection logic switches the system clock to HRC, the state control of low power consumption is kept unchanged in the switching process, after the switching is successful, the HRC is used to continue to complete the low power consumption entering process and release Gate0, and because the HRC clock is forcedly opened due to the oscillation stop generation, the or Gate protection logic of hrc_clk_en and the low power consumption control signal pwr_lp_ctr is added, so that the pwr_lp=1 power supply keeps normal power supply Gate2 to release when the low power consumption mode 3 enters, and then the Gate1 is released after the clock of the system clock of the HRC is used, the system can continue to operate in response to the oscillation stop process after the low power consumption process is completed. When the abnormal low power consumption mode 4 is entered, the final HRC is forced to be turned off by ISO2 isolation due to the final power failure and isolation, so that the system is awakened by switching to the HRC clock after vibration is stopped and continuing to complete the low power consumption entering flow, and finally waiting for a wake-up signal.
The power supply control module uses the falling edge of the system clock to synchronously turn off the last power supply after the low-power consumption cooperative processing signal lp_sync is generated, an ISO1 active isolation signal is generated at the falling edge of the last clock, other modules except the clock and the power supply are turned off, the clock and the power supply are turned off at the falling edge of the last clock, and an ISO2 isolation signal is generated; with the last synchronization, the clock switching control also completes switching the system clock to select the internal HRC, and the last clk switches the HRC enable register inputs reg_hrc_en to 1, ensuring that the internal HRC clock can be used to resume system operation quickly when awake.
It should be noted that, those skilled in the art should understand that the implementation functions of the modules shown in the embodiments of the low power mode control system described above may be understood with reference to the foregoing description of the low power mode control method. The functions of the modules shown in the embodiments of the low power mode control system described above may be implemented by a program (executable instructions) running on a processor, or by a specific logic circuit. The low power mode control system according to the embodiments of the present application may also be stored in a computer readable storage medium if implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
All documents mentioned in the present application are considered to be included in the disclosure of the present application in their entirety, so that they may be subject to modification if necessary. Furthermore, it should be understood that the foregoing description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (10)
1. A low power mode control method, comprising:
receiving an instruction of the system entering a first low-power-consumption state, judging that the current system clock is a phase-locked loop clock, and if the current system clock is the phase-locked loop clock, switching the current system clock to a source clock of the phase-locked loop clock;
closing other clocks except the current system clock;
and starting to close the current system clock and delaying to close the current system clock for N clock cycles, generating a first-stage isolation signal at the last M clock falling edges before the current system clock is closed to close the peripheral module in a step-by-step mode, and respectively generating a power supply closing signal at the last clock falling edge before the current system clock is closed to close a system power supply and a second-stage isolation signal to isolate signals influenced by the closing of the system power supply, wherein M, N is an integer, N is more than 1 and M is less than or equal to N.
2. The low power mode control method of claim 1, wherein the signal affected by system power down comprises one or more of: power supply from the power down domain, control and configuration signals for the clock, reset signals from the power down domain, and configuration signals for wake-up logic and control and configuration signals for the real time clock from the non-power down domain.
3. The method of claim 1, wherein the starting shuts down the current system clock and delays shutting down the current system clock for N clock cycles, and generating a first stage isolation signal in a stepwise manner on a last mth clock falling edge before the shutdown of the current system clock to shut down the peripheral module, and generating a power down signal on a last clock falling edge before the shutdown of the current system clock to shut down the system power and a second stage isolation signal to isolate signals affected by the shutdown of the system power, respectively, further comprising:
and starting to close the current system clock and delaying to close the current system clock for N clock cycles, generating a first-stage isolation signal at the last M clock falling edge of the system clock which delays to close the N clock cycles in a step-by-step mode by utilizing an isolation circuit to close the peripheral module, and respectively generating a power-off signal at the last clock falling edge of the system clock which delays to close the N clock cycles to close the system power and a second isolation signal to isolate signals influenced by the system power-off.
4. The low power consumption mode control method according to claim 1, wherein the method further comprises:
the power supply detection and protection module receives a system wake-up instruction and asynchronously starts a system power supply; when the system power supply is detected to be built, generating and sending a power-down domain power-up completion mark signal to an isolation circuit, wherein the isolation circuit controls to release the first-stage isolation signal and the second-stage isolation signal based on an input wake-up signal and the power-down domain power-up completion mark signal, and asynchronously starting a system clock; and
the isolation circuit controls release of the first stage isolation signal and the second isolation signal based on an input reset signal.
5. The method of claim 3 or 4, wherein the isolation circuit comprises first to fourth inverters, first to third D flip-flops, first to second nor gates, and first to second or gates, wherein the input terminals of the first to fourth inverters, the second input terminal of the first nor gate, and the clock terminals of the second and third D flip-flops are used as the first, second, sixth, and seventh input terminals of the isolation circuit, respectively, for accessing a reset signal, a wake-up signal, a system clock, the third to fifth input terminals of the isolation circuit are used for accessing a power-down domain power-up completion flag signal, the output terminals of the first inverter are connected to the first input terminals of the second nor gate, the output terminals of the nor gate are connected to the clear terminals of the second and third D flip-flops, respectively, the output terminals of the second inverter are connected to the first input terminals of the first nor gate, the first output terminals of the nor gate are connected to the first D flip-flop, the second output terminals of the second nor gate are connected to the first input terminals of the first D flip-flop, the second D flip-flop, the output terminals of the second nor gate are connected to the first input terminals of the second nor gate, the first D flip-flop, and the third D flip-flop are connected to the first input terminals of the second nor gate, the first D flip-flop, and the output terminal of the first nor gate are connected to the first D flip-flop, and the first output terminal of the first D flip-flop, and the D flip-flop are connected to the first output terminal, respectively.
6. A low power mode control method, comprising:
receiving an instruction of a system in a first running state to enter a second low-power-consumption state, judging that the current system clock is a phase-locked loop clock, and if yes, switching the current system clock to a source clock of the phase-locked loop clock;
closing other clocks except the current system clock;
and starting to close the current system clock and delaying to close the current system clock for N clock cycles, and generating a power supply mode switching signal at the last clock falling edge before closing the current system clock to switch the system power supply from a first power consumption mode to a second power consumption mode, wherein the current consumed by the first power consumption mode is larger than that of the second power consumption mode, and the power supply in the second power consumption mode is used for keeping the states of all modules in the system so as to enable the system to recover to the first running state when a system wake-up instruction is received, wherein N is an integer, and N is more than 1.
7. The low power consumption mode control method according to claim 6, wherein the method further comprises:
when the current system clock is started and closed, a low-power consumption cooperative signal is generated and input to a clock control and protection circuit;
When detecting source clock abnormality as a first clock source, switching a current system clock to an internal high-frequency second clock source and generating a first clock source abnormality signal to be input to the clock control and protection circuit;
the clock control and protection circuit controls the second clock to be kept on based on the input low-power consumption cooperative signal and the first clock source abnormal signal, and outputs a power control signal under low power consumption to a power detection and protection module;
the power supply detection and protection module controls and prevents mode switching of the system power supply based on an input low-power-consumption power supply control signal.
8. The low power consumption mode control method according to claim 6, wherein the method further comprises:
when the power supply detection and protection module receives a system wake-up instruction, the system power supply is controlled to be switched from the second power consumption mode to the first power consumption mode;
and when the power supply detection and protection module detects that the first power consumption mode is switched, generating and sending a power supply completion signal, and asynchronously starting a system clock.
9. The method of claim 7, wherein the clock control and protection circuit comprises an output terminal and an and gate, a nor gate, first to fourth inverters, a delay circuit, a first nand gate, a second nand gate, and an or gate, wherein an input terminal of the first inverter, first and second input terminals of the and gate, a second input terminal of the nor gate, an input terminal of the second inverter, and a second input terminal of the or gate are respectively used as first to sixth input terminals of the clock control and protection circuit, and the first to sixth input terminals are respectively used for accessing a first clock source abnormality signal, a wake-up signal, a power-down domain power-up completion flag signal, a power-down co-processing signal, a second clock source, and a power low power consumption control signal; the output end of the OR gate is used as the output end of the clock control and protection circuit;
The output end of the first inverter is connected to the first input end of the first NAND gate, the output end of the AND gate is connected to the first input end of the NOR gate, the output end of the NOR gate is connected to the second input end of the first NAND gate, the output end of the first NAND gate is respectively connected to the input end of the second inverter and the clock end of the delay circuit, the input end of the delay circuit is connected with the output end of the third inverter, the input end of the delay circuit is connected to the fourth inverter, the output ends of the third inverter and the fourth inverter are respectively connected to the first input end and the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the first input end of the OR gate.
10. A low power mode control system, comprising:
the clock control module is used for receiving a command of the system entering the first or second low-power-consumption state, judging that the current system clock is a phase-locked loop clock, if yes, switching the current system clock to a source clock of the phase-locked loop clock, closing other clocks except the current system clock, starting to close the current system clock and delaying to close the current system clock for N clock cycles;
The power control module is used for generating a first-stage isolation signal at the last M clock falling edges before the current system clock is closed to close the peripheral module in a step-by-step mode, and respectively generating a power closing signal at the last clock falling edge before the current system clock is closed to close a system power supply and a second-stage isolation signal to isolate signals influenced by the system power supply closing, wherein M, N is an integer, N is more than 1 and M is more than 1 and less than or equal to N; or the power supply control module is used for generating a power supply mode switching signal at the last clock falling edge before the current system clock is closed so as to switch the system power supply from a first power consumption mode to a second power consumption mode, the current consumed by the first power consumption mode is larger than that of the second power consumption mode, and the power supply in the second power consumption mode is used for maintaining the states of all modules in the system so as to enable the system to recover to the first running state when a system wake-up instruction is received, wherein N is an integer, and N is more than 1.
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