CN117826484A - Display substrate and display device - Google Patents
Display substrate and display device Download PDFInfo
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- CN117826484A CN117826484A CN202211197489.7A CN202211197489A CN117826484A CN 117826484 A CN117826484 A CN 117826484A CN 202211197489 A CN202211197489 A CN 202211197489A CN 117826484 A CN117826484 A CN 117826484A
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- 239000000758 substrate Substances 0.000 title claims abstract description 106
- 239000000463 material Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 description 12
- 230000008901 benefit Effects 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
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Abstract
The invention provides a display substrate and a display device, the display substrate includes: a substrate base; the display device comprises a substrate, a plurality of grid lines and a plurality of data lines, wherein the grid lines and the data lines are arranged on the substrate, the grid lines and the data lines are crossed to define a plurality of sub-pixel areas, two columns of sub-pixel areas are arranged between two adjacent data lines, and two grid lines are arranged between two adjacent rows of sub-pixel areas; the plurality of common electrodes are arranged on the substrate and are multiplexed into touch electrodes; the plurality of public electrode leads are arranged on the substrate, the public electrode leads and the data lines have the same extending direction and are alternately arranged with the data lines, and each public electrode lead is connected with one public electrode; the pixel electrodes are arranged on the substrate and in the sub-pixel areas. In the invention, the common electrode In the display substrate of the double-gate pixel structure is multiplexed into the Touch electrode, so that the combination of the double-gate pixel structure and the In Cell Touch (In Touch) technology is realized.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display substrate and a display device.
Background
In Cell Touch (In Cell Touch) is a design In which Touch electrodes are disposed inside a display Panel (Panel). In Cell Touch panels have great advantages In terms of cost, stability, etc. over embedded Touch (On Cell Touch) panels, etc.
The Dual Gate pixel structure can reduce the number of source driving chips of the display panel, and has a great advantage in terms of cost.
How to integrate In Cell Touch In a display panel having a Dual Gate pixel structure is a problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a display substrate and a display device, which are used for solving the problem of how to integrate In Cell Touch In a display panel with a Dual Gate pixel structure.
In order to solve the technical problems, the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a display substrate, including:
a substrate base;
the grid lines and the data lines are arranged on the substrate, a plurality of sub-pixel areas are defined by the crossing of the grid lines and the data lines, two columns of sub-pixel areas are arranged between two adjacent data lines, and two grid lines are arranged between two adjacent rows of sub-pixel areas;
the public electrodes are arranged on the substrate, and the public electrodes are multiplexed into touch electrodes;
the common electrode leads are arranged on the substrate base plate, have the same extending direction with the data lines, are alternately arranged with the data lines, and are connected with one common electrode;
and the pixel electrodes are arranged on the substrate base plate and are arranged in the sub-pixel areas.
Optionally, each of the common electrodes includes a plurality of first common electrodes, each of the first common electrodes is disposed in one of the sub-pixel regions, and the plurality of first common electrodes belonging to the same common electrode are connected to each other.
Optionally, the orthographic projections of the first common electrode and the common electrode lead on the substrate are not overlapped.
Optionally, the common electrode further includes:
the plurality of public electrode auxiliary lines are arranged on the substrate, the extension directions of the public electrode auxiliary lines and the grid lines are the same, the public electrode auxiliary lines are arranged between two adjacent rows of sub-pixel areas, two public electrode auxiliary lines are arranged between the two adjacent rows of sub-pixel areas, the two public electrode auxiliary lines are respectively arranged on two sides of the two grid lines between the two adjacent rows of sub-pixel areas, each public electrode auxiliary line is disconnected at a plurality of positions, a plurality of second public electrodes are formed, and each second public electrode is connected with the first public electrode close to the second public electrode.
Optionally, the common electrode auxiliary line and the grid line are arranged in the same layer and the same material;
and/or
The common electrode lead and the data line are arranged in the same layer and the same material.
Optionally, the display substrate further includes:
a first insulating layer disposed between the second common electrode and the common electrode lead;
the second insulating layer is arranged on one side of the common electrode lead away from the substrate base plate;
a first via hole is formed in the first insulating layer, a second via hole is formed in the second insulating layer, the orthographic projection of the first via hole on the substrate is located in the orthographic projection area of the second via hole on the substrate, and the first via hole and the second via hole form a half-via hole structure;
and the crossover wire is partially arranged in the half-via structure and used for connecting the corresponding second common electrode and the common electrode lead.
Optionally, the bonding wire only includes: the lap joint structure is arranged at the position of the half-via structure and is used for connecting the corresponding second public electrode and the public electrode lead;
or,
the crossover includes:
the lap joint structure is arranged at the position of the half-via structure and is used for connecting the corresponding second public electrode and the public electrode lead;
and the connecting structure is arranged between the adjacent half-via structures and is used for being connected with the public electrode lead in parallel to reduce the resistance of the public electrode lead.
Optionally, the first common electrode is disposed on a side of the pixel electrode away from the substrate, and the bonding wire and the first common electrode are disposed on the same layer and the same material;
or alternatively
The pixel electrode is arranged on one side, far away from the substrate base plate, of the first common electrode, and the crossover line and the pixel electrode are arranged in the same layer and the same material.
Optionally, two common electrode auxiliary lines disposed between two adjacent rows of the sub-pixel regions are disconnected near a target data line or a target common electrode lead, so as to form a plurality of second common electrodes, wherein the disconnection position of one common electrode auxiliary line is located at a first side of the target data line or the target common electrode lead, and the disconnection position of the other common electrode auxiliary line is located at a second side of the target data line or the target common electrode lead.
Optionally, the distance between the disconnection position of the common electrode auxiliary line and the target data line or the target common electrode lead in the first direction is a first value;
a second common electrode overlapping the target data line or the target common electrode lead includes a first portion and a second portion connected to each other, the first portion extending from a disconnected position of the common electrode auxiliary line to the other side of the target data line or the target common electrode lead, the second portion having a width in a second direction equal to twice a width of the first portion in the second direction; the distance between the target data line or the target common electrode lead and the second part in the first direction is the first value;
the first direction is the extending direction of the common electrode auxiliary line;
the second direction is the extending direction of the target data line.
Optionally, a width of the open position of the common electrode auxiliary line in the first direction is greater than or equal to 4 μm, and the first direction is an extension direction of the common electrode auxiliary line.
Optionally, each of the first common electrodes has the same shape and size.
In a second aspect, an embodiment of the present invention provides a display device, including a display substrate as described in the first aspect.
In the embodiment of the invention, the common electrode In the display substrate of the double-gate pixel structure is multiplexed into the Touch electrode, so that the combination of the double-gate pixel structure and an In Cell Touch (In Touch) technology is realized, and the display substrate has great advantages In the aspects of cost saving, stability and the like.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a top view of a display substrate according to an embodiment of the invention;
FIG. 2 is a schematic diagram of data lines, gate lines, common electrode leads and sub-pixel regions in a display substrate according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view at A-A' in FIG. 1;
FIG. 4 is a cross-sectional view at B-B' in FIG. 1;
FIG. 5 is a cross-sectional view at C-C' in FIG. 1;
FIG. 6 is a schematic diagram of a common electrode according to an embodiment of the present invention;
FIG. 7 is a cross-sectional view at D-D' in FIG. 1;
FIG. 8 is a cross-sectional view at E-E' in FIG. 1;
fig. 9 is a top view of a partial region of a display substrate according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-6, an embodiment of the present invention provides a display substrate, including:
a substrate 101; the substrate 101 may be a glass substrate, a ceramic substrate, or the like;
a plurality of gate lines 102 and a plurality of data lines 103 disposed on the substrate 101, where the plurality of gate lines 102 and the plurality of data lines 103 intersect to define a plurality of sub-pixel regions, referring to fig. 2, two columns of the sub-pixel regions are disposed between two adjacent data lines 103, each data line 103 provides data signals for sub-pixels in the sub-pixel regions on two sides thereof, two gate lines 102 are disposed between two adjacent rows of the sub-pixel regions, two sub-pixels in two sub-pixel regions disposed between two adjacent data lines 103 and in the same row, one sub-pixel is connected to the gate line 102 on one side, the other sub-pixel is connected to the gate line 102 on the other side, and a scanning signal is provided by the gate line 102, which is a Dual gate structure;
a plurality of common electrodes 104 are disposed on the substrate 101, and the common electrodes 104 are multiplexed into Touch electrodes, i.e., the Touch electrodes are disposed inside the display substrate (i.e., in Cell Touch). In the prior art, the common electrodes in the whole display substrate are all connected, but in the embodiment of the present invention, please refer to fig. 6, in order to multiplex the common electrodes into touch electrodes, the whole common electrode in the display substrate is divided into a plurality of small blocks, each common electrode is not connected, and each common electrode is multiplexed into one touch electrode. Alternatively, in the whole display substrate, the common electrodes are arranged in a matrix manner, for example, the display substrate shown in fig. 6 has N rows and M columns of common electrodes, each common electrode is connected to the driving IC through a common electrode line, the driving IC inputs a common electrode signal and a touch signal to the common electrode in a time-sharing manner, and in a normal display period, the common electrode signal is input, and in a touch period, the touch signal is input as a touch electrode.
A plurality of common electrode leads 105 disposed on the substrate 101, wherein the common electrode leads 105 have the same extending direction as the data lines 103 and are alternately arranged with the data lines 103, and each common electrode lead 105 is connected with one common electrode 104; in an embodiment of the present invention, optionally, the number ratio of the data lines 103 to the common electrode leads 105 may be 1:1.
a plurality of pixel electrodes 1061 are disposed on the substrate 101 and disposed in the sub-pixel regions, and one pixel electrode 1061 is disposed in each sub-pixel region.
In the embodiment of the invention, the common electrode In the display substrate of the double-gate pixel structure is multiplexed into the Touch electrode, so that the combination of the double-gate pixel structure and an In Cell Touch (In Touch) technology is realized, and the display substrate has great advantages In the aspects of cost saving, stability and the like.
In the embodiment shown in fig. 1, the display substrate is of ADS (advanced dimension 1n Switch) structure, and in other embodiments of the invention, display substrates of other structures, such as TN (Twisted Nematic), VA (Vertical Alignment liquid crystal), and other structures, may be used.
In some embodiments of the present invention, each common electrode may occupy a plurality of sub-pixel regions, and the common electrodes in the plurality of sub-pixel regions may be a whole piece and not divided.
In some embodiments of the present invention, optionally, each of the common electrodes may further include a plurality of first common electrodes 1041, where each of the first common electrodes 1041 is disposed in one of the sub-pixel regions, that is, the common electrodes in the plurality of sub-pixel regions occupied by each of the common electrodes are divided and not connected, and the plurality of first common electrodes 1041 belonging to the same common electrode are connected to each other.
In the embodiment of the invention, optionally, each common electrode is square or close to square, and the side length can be 7 mm-15 mm.
In the embodiment of the present invention, each common electrode lead 105 is connected to only one common electrode, and the common electrode leads pass through other common electrodes not connected to the common electrode lead, so that the smaller the parasitic capacitance between the common electrode lead 105 and the other common electrodes not connected to the common electrode lead is, the more advantageous the touch performance is, and therefore, the first common electrode below the common electrode lead can be removed, so that the orthographic projection of the first common electrode 1041 and the common electrode lead 105 on the substrate is not overlapped, thereby reducing the parasitic capacitance between the two.
In the embodiment of the present invention, the pixel electrode 1061 is disposed opposite to the first common electrode 1041. In the embodiment shown in fig. 1, the pixel electrode 1061 is a slit electrode, i.e. a plurality of stripe-shaped slits are formed thereon. In the embodiment of the present invention, the pixel electrode 1061 is located on the side of the first common electrode 1041 away from the substrate 101, and in other embodiments, the pixel electrode 1061 may also be located on the side of the first common electrode 104 near the substrate 101, that is, the positions of the pixel electrode 1061 and the first common electrode 1041 may be interchanged.
In an embodiment of the present invention, optionally, the first common electrode and/or the pixel electrode may be made of a transparent conductive material, for example, ITO (indium tin oxide) or the like.
In an embodiment of the present invention, in order to improve the uniformity of the voltage of the common electrode, optionally, the common electrode 104 further includes:
the plurality of common electrode auxiliary lines are disposed on the substrate 101, the extending directions of the common electrode auxiliary lines and the gate lines 102 are the same, the common electrode auxiliary lines are disposed between two adjacent rows of sub-pixel regions, two common electrode auxiliary lines are disposed between two adjacent rows of sub-pixel regions, the two common electrode auxiliary lines are respectively disposed on two sides of the two gate lines 102 between the two adjacent rows of sub-pixel regions, each common electrode auxiliary line is disconnected at a plurality of positions, a plurality of second common electrodes 1042 are formed, and each second common electrode 1042 is connected with a first common electrode 1041 close to the second common electrode 1042.
By providing the common electrode auxiliary line, a common electrode network can be formed in the entire display substrate to improve the uniformity of the voltage of the common electrode.
In an embodiment of the present invention, optionally, the common electrode auxiliary line and the gate line 102 are disposed in the same layer and the same material.
In an embodiment of the present invention, optionally, the common electrode lead 105 and the data line 103 are disposed in the same layer and the same material.
In an embodiment of the present invention, optionally, the display substrate further includes:
a first insulating layer 107 disposed between the second common electrode 1042 and the common electrode lead 105;
a second insulating layer 108 disposed on a side of the common electrode lead 105 away from the substrate 101;
a first via hole is formed on the first insulating layer 107, a second via hole is formed on the second insulating layer 108, the orthographic projection of the first via hole on the substrate 101 is located in the orthographic projection area of the second via hole on the substrate, and the first via hole and the second via hole form a half via hole structure;
and a crossover line 1062 partially disposed in the half-via structure for connecting the corresponding second common electrode 1042 and the common electrode lead 105.
Optionally, in some embodiments, the crossover 1062 includes only: the lap joint structure is arranged at the position of the half-via structure and is used for connecting the corresponding second public electrode and the public electrode lead;
alternatively, in some embodiments, the crossover 1062 includes:
the lap joint structure is arranged at the position of the half-via structure and is used for connecting the corresponding second public electrode and the public electrode lead;
and the connecting structure is arranged between the adjacent half-via structures and is used for being connected with the public electrode lead in parallel to reduce the resistance of the public electrode lead.
In this embodiment of the present invention, optionally, the first insulating layer 107 may be a gate insulating layer, and may be made of SiNx.
In an embodiment of the present invention, optionally, the second insulating layer 108 may be a PVX (passivation) layer, and may be made of SiNx.
In this embodiment of the present invention, optionally, the first common electrode 1041 is disposed at a side of the pixel electrode 1061 away from the substrate 101, and the bonding wire 1062 and the first common electrode 1041 are disposed in the same layer and the same material;
or alternatively
The pixel electrode 1061 is disposed on a side of the first common electrode 1041 away from the substrate 101, and the bonding wire 1062 and the pixel electrode 1061 are disposed in the same layer and the same material.
Referring to fig. 9, in an embodiment of the present invention, optionally, two common electrode auxiliary lines disposed between two adjacent rows of the sub-pixel regions are disconnected near the target data line 103 to form a plurality of second common electrodes 1042, wherein the disconnected position of one common electrode auxiliary line is located at the first side of the target data line 103, and the disconnected position of the other common electrode auxiliary line is located at the second side of the target data line 103;
the distance between the disconnection position of the common electrode auxiliary line and the target data line 103 in the first direction is a first value a;
the second common electrode 1042 overlapping the target data line 103 includes a first portion and a second portion connected to each other, the first portion from a disconnected position of the common electrode auxiliary line to the other side of the target data line 103, and a width D of the second portion in the second direction is equal to twice a width C of the first portion in the second direction; the distance between the target data line and the second part in the first direction is the first value A;
the first direction is the extending direction of the common electrode auxiliary line;
the second direction is an extending direction of the target data line 103.
In the above embodiment, the common electrode auxiliary line is disconnected near the target data line, and in other embodiments of the invention, the common electrode auxiliary line may be connected to the data line
In other embodiments of the present invention, the common electrode auxiliary line may be disconnected in the vicinity of the target common electrode lead, that is, alternatively, two common electrode auxiliary lines disposed between two adjacent rows of the sub-pixel regions may be disconnected in the vicinity of the target common electrode lead 105 to form a plurality of the second common electrodes 1042, wherein the disconnected position of one common electrode auxiliary line is located at the first side of the target common electrode lead and the disconnected position of the other common electrode auxiliary line is located at the second side of the target common electrode lead;
the distance between the disconnection position of the public electrode auxiliary line and the target public electrode lead in the first direction is a first numerical value A;
the second common electrode 1042 overlapping the target common electrode lead includes a first portion and a second portion connected to each other, the first portion from a disconnected position of the common electrode auxiliary line to the other side of the target common electrode lead, a width D of the second portion in the second direction being equal to twice a width C of the first portion in the second direction; the distance between the target common electrode lead and the second part in the first direction is the first value A;
the first direction is the extending direction of the common electrode auxiliary line;
the second direction is an extending direction of the target common electrode lead.
The design has the advantage that when the deviation of the alignment of the SD layer (the metal layer where the data line is located) relative to the Gate layer (the Gate line and the metal layer where the second common electrode are located) is larger than A, the overlap capacitance between the data line and the second common electrode is not changed.
Referring to fig. 9, in an embodiment of the present invention, optionally, a width B of the open position of the common electrode auxiliary line in the first direction is greater than or equal to 4 μm.
The embodiment of the invention also provides a display device which comprises the display substrate in the embodiment. The display device can be a display panel, a display module comprising the display panel and a backlight module, or a display device comprising the display panel, the backlight module and a driving circuit. The display device may be an MNT (display) or a TV (television) or the like.
The embodiment of the invention also provides a manufacturing method of the display substrate, which comprises the following steps:
step S11: providing a substrate;
step S12: forming a plurality of grid lines and a plurality of data lines on the substrate, wherein the grid lines and the data lines are crossed to define a plurality of sub-pixel areas, two columns of sub-pixel areas are arranged between two adjacent data lines, and two grid lines are arranged between two adjacent rows of sub-pixel areas;
step S13: forming a plurality of common electrodes on the substrate, wherein the common electrodes are multiplexed into touch electrodes;
step S14: forming a plurality of common electrode leads on the substrate, wherein the common electrode leads have the same extending direction as the data lines and are alternately arranged with the data lines, and each common electrode lead is connected with one common electrode;
and forming a plurality of pixel electrodes on the substrate, wherein the pixel electrodes are arranged in the sub-pixel areas.
The order of execution of the steps in the above-described embodiments is not limited, and the step number is not limited, and for example, the common electrode may be formed before the data line.
Optionally, each of the common electrodes includes a plurality of first common electrodes, each of the first common electrodes is disposed in one of the sub-pixel regions, and the plurality of first common electrodes belonging to the same common electrode are connected to each other.
Optionally, the orthographic projections of the first common electrode and the common electrode lead on the substrate are not overlapped.
Optionally, the common electrode further includes:
the plurality of public electrode auxiliary lines are arranged on the substrate, the extension directions of the public electrode auxiliary lines and the grid lines are the same, the public electrode auxiliary lines are arranged between two adjacent rows of sub-pixel areas, two public electrode auxiliary lines are arranged between the two adjacent rows of sub-pixel areas, the two public electrode auxiliary lines are respectively arranged on two sides of the two grid lines between the two adjacent rows of sub-pixel areas, each public electrode auxiliary line is disconnected at a plurality of positions, a plurality of second public electrodes are formed, and each second public electrode is connected with the first public electrode close to the second public electrode.
Optionally, the common electrode auxiliary line and the grid line are arranged in the same layer and the same material, and are formed through a one-time composition process;
and/or
The common electrode lead and the data line are arranged in the same layer and the same material, and are formed through a one-time composition process.
Optionally, the method further comprises:
forming a first insulating layer disposed between the second common electrode and the common electrode lead; wherein, the first insulating layer is provided with a first via hole;
forming a second insulating layer which is arranged on one side of the common electrode lead away from the substrate base plate; the second insulating layer is provided with a second via hole, the orthographic projection of the first via hole on the substrate is positioned in the orthographic projection area of the second via hole on the substrate, and the first via hole and the second via hole form a half-via hole structure;
and forming a crossover wire, wherein the crossover wire part is arranged in the half-via structure and is used for connecting the corresponding second common electrode and the common electrode lead.
Optionally, the first common electrode is disposed on a side of the pixel electrode away from the substrate, and the bonding wire and the first common electrode are disposed on the same layer and the same material, and are formed by a one-time patterning process;
or alternatively
The pixel electrode is arranged on one side, far away from the substrate, of the first common electrode, the bonding wire and the pixel electrode are arranged on the same layer and the same material, and the pixel electrode is formed through a one-time composition process.
Optionally, two common electrode auxiliary lines arranged between two adjacent rows of the sub-pixel regions are disconnected near a target data line or a target common electrode lead to form a plurality of second common electrodes, wherein the disconnection position of one common electrode auxiliary line is positioned at a first side of the target data line or the target common electrode lead, and the disconnection position of the other common electrode auxiliary line is positioned at a second side of the target data line or the target common electrode lead;
the distance between the disconnection position of the common electrode auxiliary line and the target data line or the target common electrode lead in the first direction is a first numerical value;
a second common electrode overlapping the target data line or the target common electrode lead includes a first portion and a second portion connected to each other, the first portion extending from a disconnected position of the common electrode auxiliary line to the other side of the target data line or the target common electrode lead, the second portion having a width in a second direction equal to twice a width of the first portion in the second direction; the distance between the target data line or the target common electrode lead and the second part in the first direction is the first value;
the first direction is the extending direction of the common electrode auxiliary line;
the second direction is the extending direction of the target data line.
Optionally, a width of the open position of the common electrode auxiliary line in the first direction is greater than or equal to 4 μm.
In a specific embodiment of the present invention, optionally, the method for manufacturing the display substrate includes:
step S21: providing a substrate;
step S22: forming a 1ITO layer on the substrate base plate, and forming a first common electrode through a patterning process;
step S23: forming a Gate metal layer (Gate layer) on the substrate base plate, and forming a Gate line, a Gate electrode and a second common electrode through a patterning process;
step S24: forming a Gate Insulator (Gate Insulator), which may be formed of SiNx, for example, and forming a first via hole on the Gate Insulator through a patterning process;
step S25: forming an Active layer (Active);
step S26: forming a source drain metal layer (SD layer) and forming a data line and a common electrode lead through a patterning process;
step S27: forming a passivation layer (PVX), and forming a second via hole in the passivation layer through a patterning process, wherein the orthographic projection of the first via hole on the substrate is positioned in the orthographic projection area of the second via hole on the substrate, and the first via hole and the second via hole form a half-via hole structure;
step S28: and forming a 2ITO layer, and forming a pixel electrode and a crossover wire through a patterning process, wherein the crossover wire is partially arranged in the half-via structure and used for connecting the corresponding second common electrode and the common electrode lead.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (12)
1. A display substrate, comprising:
a substrate base;
the grid lines and the data lines are arranged on the substrate, a plurality of sub-pixel areas are defined by the crossing of the grid lines and the data lines, two columns of sub-pixel areas are arranged between two adjacent data lines, and two grid lines are arranged between two adjacent rows of sub-pixel areas;
the public electrodes are arranged on the substrate, and the public electrodes are multiplexed into touch electrodes;
the common electrode leads are arranged on the substrate base plate, have the same extending direction with the data lines, are alternately arranged with the data lines, and are connected with one common electrode;
the pixel electrodes are arranged on the substrate and in the sub-pixel areas.
2. The display substrate according to claim 1, wherein each of the common electrodes includes a plurality of first common electrodes, each of the first common electrodes is disposed in one of the sub-pixel regions, and the plurality of first common electrodes belonging to the same common electrode are connected to each other.
3. The display substrate of claim 2, wherein the orthographic projection of the first common electrode and the common electrode lead on the substrate does not overlap.
4. The display substrate of claim 2, wherein the common electrode further comprises:
the plurality of public electrode auxiliary lines are arranged on the substrate, the extension directions of the public electrode auxiliary lines and the grid lines are the same, the public electrode auxiliary lines are arranged between two adjacent rows of sub-pixel areas, two public electrode auxiliary lines are arranged between the two adjacent rows of sub-pixel areas, the two public electrode auxiliary lines are respectively arranged on two sides of the two grid lines between the two adjacent rows of sub-pixel areas, each public electrode auxiliary line is disconnected at a plurality of positions, a plurality of second public electrodes are formed, and each second public electrode is connected with the first public electrode close to the second public electrode.
5. The display substrate of claim 4, wherein,
the common electrode auxiliary line and the grid line are arranged in the same layer and the same material;
and/or
The common electrode lead and the data line are arranged in the same layer and the same material.
6. The display substrate of claim 4 or 5, further comprising:
a first insulating layer disposed between the second common electrode and the common electrode lead;
the second insulating layer is arranged on one side of the common electrode lead away from the substrate base plate;
a first via hole is formed in the first insulating layer, a second via hole is formed in the second insulating layer, the orthographic projection of the first via hole on the substrate is located in the orthographic projection area of the second via hole on the substrate, and the first via hole and the second via hole form a half-via hole structure;
and the crossover wire is partially arranged in the half-via structure and used for connecting the corresponding second common electrode and the common electrode lead.
7. The display substrate of claim 6, wherein,
the crossover only includes: the lap joint structure is arranged at the position of the half-via structure and is used for connecting the corresponding second public electrode and the public electrode lead;
or,
the crossover includes:
the lap joint structure is arranged at the position of the half-via structure and is used for connecting the corresponding second public electrode and the public electrode lead;
and the connecting structure is arranged between the adjacent half-via structures and is used for being connected with the public electrode lead in parallel to reduce the resistance of the public electrode lead.
8. The display substrate of claim 6, wherein,
the first common electrode is arranged on one side, far away from the substrate base plate, of the pixel electrode, and the bonding wire and the first common electrode are arranged in the same layer and the same material;
or alternatively
The pixel electrode is arranged on one side, far away from the substrate base plate, of the first common electrode, and the crossover line and the pixel electrode are arranged in the same layer and the same material.
9. The display substrate of claim 4, wherein,
and two common electrode auxiliary lines arranged between two adjacent rows of sub-pixel areas are disconnected near a target data line or a target common electrode lead to form a plurality of second common electrodes, wherein the disconnection position of one common electrode auxiliary line is positioned on the first side of the target data line or the target common electrode lead, and the disconnection position of the other common electrode auxiliary line is positioned on the second side of the target data line or the target common electrode lead.
10. The display substrate of claim 9, wherein,
the distance between the disconnection position of the common electrode auxiliary line and the target data line or the target common electrode lead in the first direction is a first numerical value;
a second common electrode overlapping the target data line or the target common electrode lead includes a first portion and a second portion connected to each other, the first portion extending from a disconnected position of the common electrode auxiliary line to the other side of the target data line or the target common electrode lead, the second portion having a width in a second direction equal to twice a width of the first portion in the second direction; the distance between the target data line or the target common electrode lead and the second part in the first direction is the first value;
the first direction is the extending direction of the common electrode auxiliary line;
the second direction is the extending direction of the target data line.
11. The display substrate according to claim 9, wherein a width of the open position of the common electrode auxiliary line in a first direction, which is an extending direction of the common electrode auxiliary line, is greater than or equal to 4 μm.
12. A display device comprising the display substrate according to any one of claims 1 to 11.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211197489.7A CN117826484A (en) | 2022-09-29 | 2022-09-29 | Display substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211197489.7A CN117826484A (en) | 2022-09-29 | 2022-09-29 | Display substrate and display device |
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| CN202211197489.7A Pending CN117826484A (en) | 2022-09-29 | 2022-09-29 | Display substrate and display device |
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