CN117813835A - Pixel device, image sensor, and method of operating pixel device - Google Patents

Abstract

A pixel arrangement (10) is provided which is configured for a high sensitivity mode and a low sensitivity mode, respectively. The photodiodes (20) are configured to convert electromagnetic radiation into respective charge signals, and the transfer gates (30) are configured to transfer the respective charge signals to the capacitances (40). The reset gate (50) is configured to reset the capacitance. The amplifier (60) is configured to generate a respective amplified signal, the respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively. The low sensitivity signal and the high sensitivity signal are based on a common noise level. A first capacitor (70) coupled to the first switch (90) is configured to store a high sensitivity signal and a second capacitor (80) coupled to the second switch (100) is configured to store a low sensitivity signal. Furthermore, an image sensor (200), an optoelectronic device (300) and a method for operating a pixel arrangement are provided.

Description

Pixel device, image sensor, and method of operating pixel device

Priority declaration and cross-referencing

The present patent application claims priority from U.S. provisional application No. 63/263,861, filed on 10 at 11, 2021, and German application No. 102021120779.7, filed on 10 at 8, 2021, which are incorporated herein by reference in their entireties.

Technical Field

The invention relates to a pixel device, an image sensor, an optoelectronic device and a method for operating the pixel device.

Background

CMOS image sensors are used in a wide range of applications, such as for camera modules and smart phones, tablet computers, laptop computers, and the like. For some applications, a High Dynamic Range (HDR), for example, above 85dB, is required. The Dynamic Range (DR) is limited on the one hand by the noise floor under low light conditions and on the other hand by saturation effects under high light conditions.

In order to solve the saturation problem, some methods have been developed, which can be classified into a linear response method and a nonlinear response method. For example, logarithmic compression, inflection point compression, time stamp conversion, optical frequency conversion belong to nonlinear response methods. The linear response method can be further subdivided into multiple exposure and single exposure methods. The multiple exposure method includes a method using a plurality of frames having different integration times or a method using line or pixel interleaving having different integration times. Single exposure methods include, for example, multi-gain readout or multi-sensitivity compounding.

Most available DR techniques have problems designed for rolling shutter pixels but are not friendly to global shutters. In the rolling shutter mode, the pixels of the pixel matrix are illuminated by a light source. During illumination, the pixels are sequentially exposed and read out row by row. This means that the pixel matrix is illuminated during the whole readout process. The rolling shutter mode enables high resolution of the image sensor, but may be accompanied by other drawbacks such as long illumination times and dynamic or color artifacts, especially if the rolling shutter mode is combined with one of the aforementioned DR techniques.

In the global shutter mode, all pixels of the pixel matrix are exposed during the same period of time. Therefore, a significantly shorter illumination time is required than in the rolling shutter mode. At the end of the integration time, the charge transfer operations for all rows of the pixel matrix occur simultaneously. The signal is stored in a pixel level memory and then read out. Known global shutter pixel devices including one of the aforementioned DR techniques suffer from the problem of requiring additional circuit components and having large pixel pitches.

Disclosure of Invention

An object to be achieved is to provide a pixel device with a high dynamic range and a method for operating such a pixel device. Another object is to provide an image sensor comprising an array of pixels according to a pixel arrangement and an optoelectronic device comprising such an image sensor.

These objects are achieved by the subject matter of the independent claims. Further developments and embodiments are described in the dependent claims.

Here and hereinafter, the terms "pixel device" and "pixel" refer to a light receiving element, which may be arranged in a two-dimensional array (also referred to as a matrix) together with other pixels. The pixels in the array are arranged in rows and columns. The terms "row" and "column" may be used interchangeably as they depend only on the orientation of the pixel array. The pixel may also include circuitry for controlling signals to and from the pixel. Thus, the pixels may form so-called active pixels. The pixel may receive light in any wavelength range. The term "light" may generally refer to electromagnetic radiation, including, for example, infrared (IR) radiation, ultraviolet (UV) radiation, and Visible (VIS) light.

In an embodiment, the pixel arrangement is configured to convert electromagnetic radiation in a high sensitivity mode and a low sensitivity mode, respectively. The pixel comprises at least one photodiode. The photodiodes are configured to convert electromagnetic radiation into corresponding charge signals. In particular, the pixel arrangement may form a global shutter pixel. The photodiode may specifically be a pinned photodiode. The photodiodes may be arranged in a substrate, in particular a semiconductor substrate.

The high sensitivity mode and the low sensitivity mode are operation modes of the pixel. The high sensitivity mode and the low sensitivity mode may then be performed. This may mean that the high sensitivity mode and the low sensitivity mode are performed within one frame. In particular, the low sensitivity mode may be performed before the high sensitivity mode. A low sensitivity mode of the pixel may be provided for high light conditions (i.e. high illumination). In this case the charge signal generated by the photodiode is already large and does not need to be "artificially" increased, e.g. by high gain, long exposure time, etc. If such charge signals are increased, for example, by a High Conversion Gain (HCG), saturation effects may occur. Saturation may occur, for example, because the potential well of the photodiode and/or storage element within the pixel is not large enough to carry all photo-induced charge carriers. A high sensitivity mode of the pixel may be provided for low light conditions (i.e. low illumination). In this case, the charge signal generated by the photodiode is small and should be increased, for example, by a high gain or a long exposure time, in order to obtain a good signal-to-noise ratio (SNR).

In other words, the low sensitivity mode may be an operation mode in which the exposure time of the pixel is short, particularly shorter than that of the high sensitivity mode. Alternatively, in the low sensitivity mode, a Low Conversion Gain (LCG) is applied. In a further alternative, the charge signal is kept small by means of a small photodiode region or a corresponding filter. The high sensitivity mode may be an operation mode in which the exposure time of the pixels is long, in particular longer than the exposure time of the low sensitivity mode. Alternatively, in the high sensitivity mode, the signal gain may be large. In yet another alternative, the charge signal is increased by means of a large photodiode area or the like. In yet another embodiment, the high sensitivity mode and the low sensitivity mode are implemented by barrier modulation of the transfer gate.

The pixel device further includes at least one transfer gate disposed between the photodiode and the capacitor. The transfer gate is configured to transfer a corresponding charge signal from the photodiode to the capacitor.

The transfer gate may be implemented as a transfer switch. For example, the transfer gate may be part of a transfer transistor that includes a first terminal connected to the photodiode and a second terminal connected to the capacitor. By applying a transfer signal to the transfer gate, the transfer transistor becomes electrically conductive, causing charge carriers to diffuse from the photodiode toward the capacitance. Thus, the capacitance may be implemented as a floating diffusion capacitance. The capacitance forms a memory element. The capacitance may be referred to as a floating diffusion capacitor. The capacitor may form a doped well in the semiconductor substrate. The capacitors may be configured to convert respective charge signals to respective voltage signals. It may be desirable to store signals in the voltage domain instead of the charge domain, due to dark current and reduced parasitic Photosensitivity (PLS) of the pixel.

The capacitor includes a terminal node electrically coupled to the transfer gate. Thus, the transfer gate is arranged between the photodiode and the terminal node of the capacitor. The terminal node of the capacitor may be referred to as a floating diffusion node or FD node or diffusion node. The capacitor also includes an additional terminal node that may be grounded.

The capacitance may be the capacitance of a diffusion node. The capacitance may be implemented as a pn junction. In an example, there is no discrete capacitor connected to the diffusion node. The capacitance is for example only generated by at least one parasitic capacitance. Accordingly, the terms "capacitance" and "diffusion node" are used interchangeably hereinafter.

The pixel device also includes a reset gate electrically coupled to the capacitor. Specifically, the reset gate is electrically coupled to the FD node. The reset gate is used for resetting the capacitor.

The reset gate may be implemented as a reset switch. For example, the reset gate may be part of a reset transistor that includes a first terminal connected to the pixel supply voltage and a second terminal connected to the FD node. By applying a reset signal to the reset gate, the reset transistor becomes conductive such that any redundant charge carriers are removed by applying the pixel supply voltage.

The pixel device further comprises an amplifier. The amplifier is electrically connected to the capacitor, in particular to a terminal node of the capacitor, i.e. the FD node. Specifically, the input terminal of the amplifier is electrically connected to the terminal node of the capacitor. The amplifier is configured to generate a respective amplified signal based on the respective charge signal and the sensitivity pattern. The respective amplified signal is one of a low sensitivity signal and a high sensitivity signal, respectively. The low sensitivity signal and the high sensitivity signal are based on a common noise level. This may mean that the noise levels of the low sensitivity signal and the high sensitivity signal are correlated. The common noise level may be a common noise level in the spatial or temporal domain. In particular, the common noise level may be a reset noise level.

The high sensitivity signal may be referred to as a High Conversion Gain (HCG) signal. The low sensitivity signal may be referred to as a Low Conversion Gain (LCG) signal.

The amplifier may form a common drain amplifier, also known as a source follower. The gate terminal of the source follower is connected to the FD node and serves as an input terminal of the amplifier. The common terminal may be connected to a supply voltage. A corresponding amplified signal is generated at the output terminal of the amplifier. The amplifier may be used as a voltage buffer. The amplifier may be configured to buffer the signal, thereby decoupling the FD node from the further pixel component. The amplifier may also be configured to amplify photo-induced charge carriers.

The amplified signal may be a low sensitivity signal or a high sensitivity signal depending on the respective sensitivity mode in which the pixel operates at the respective moment. The low sensitivity signal is based on the video signal and the noise level. The noise level includes temporal noise such as thermal noise and reset noise, and Fixed Pattern Noise (FPN). FPN refers to the change in signal from pixel to pixel, which is "fixed" at a certain spatial location. Thermal noise is mainly generated by random thermal agitation movements of electrons within the electrical conductor. The reset noise refers to a reset operation of the FD node that needs to be reset every frame before the start of charge integration. This reset operation may introduce sampling noise.

According to one aspect of the disclosure, the high sensitivity signal may be based on a low sensitivity signal. Thus, the high sensitivity signal is based on the same noise level as the low sensitivity signal, in particular on a common reset noise level and/or a common fixed pattern noise level. The high-sensitivity signal may include a low-sensitivity signal and an additional video signal. In other words, the noise of the high-sensitivity signal and the noise of the low-sensitivity signal are correlated. Therefore, the low-sensitivity signal can be used as a reference level of the high-sensitivity signal, so that noise of the high-sensitivity signal can be effectively eliminated. This operation may be referred to as Correlated Double Sampling (CDS). Thus, a high-sensitivity signal can be accessed with CDS, thereby obtaining a pure video signal.

The pixel device further includes a first capacitor configured to store a high sensitivity signal. The first capacitor may be implemented as a Metal Oxide Semiconductor (MOS) capacitor. Alternatively, the first capacitor is formed as a metal-insulator-metal (MIM) capacitor. The first capacitor includes a terminal node and a further terminal node. The further terminal node may be grounded or connected to a further supply voltage.

The pixel device further includes a second capacitor configured to store a low sensitivity signal. The second capacitor may be implemented as a MOS or MIM capacitor. The second capacitor includes a terminal node and a further terminal node. The further terminal node may be grounded or connected to a further supply voltage.

The pixel device further includes a first switch disposed between the output terminal of the amplifier and the first capacitor. This may mean that the first switch connects the terminal node of the first capacitor to the output terminal of the amplifier. A first switch is provided for transferring the respective amplified signal to the first capacitor. The first switch may be formed by a first switching transistor. The first switching transistor may include a gate terminal configured to receive a first switching signal by which the first switching transistor becomes conductive such that the amplified signal is transferred. The first terminal of the first switching transistor is connected to the output terminal of the amplifier. The second terminal of the first switching transistor is connected to a terminal node of the first capacitor.

The pixel device further includes a second switch disposed between the output terminal of the amplifier and the second capacitor. This may mean that the second switch connects the terminal node of the second capacitor to the output terminal of the amplifier. A second switch is provided for transferring the respective amplified signal to a second capacitor. The second switch may be formed by a second switching transistor. The second switching transistor may include a gate terminal configured to receive the second switching signal, the second switching transistor being turned on by the second switching signal such that the amplified signal is transferred. The first terminal of the second switching transistor may be connected to the output terminal of the amplifier or the second terminal of the first switching transistor. The second terminal of the second switching transistor is connected to a terminal node of the second capacitor.

Only two capacitors are required to implement the functions of the described pixel device. This allows the pixel device to be smaller. This means that the pixel pitch can be scaled in size while HDR is included, which in turn enables cost and module size to be reduced. For example, if the pixels are arranged in a matrix, the pixel pitch may be less than 2 μm. In addition, the proposed pixel device is compatible with many HDR technologies. Advantageously, the two capacitors store two different signals, namely a high sensitivity signal and a low sensitivity signal. Accordingly, the dynamic range of the pixel device can be increased. Furthermore, both the high-sensitivity signal and the low-sensitivity signal may be based on a common noise level, which in particular consists of thermal noise and reset noise. Thus, the low sensitivity signal may be used as a reference level for the high sensitivity signal. This means that a high sensitivity signal can be accessed with CDS. Thermal noise is a relevant parameter since high sensitivity signals are used in low light conditions. Advantageously, thermal noise and reset noise can be effectively suppressed by CDS. The low sensitivity signal is further processed under high light conditions. Here, thermal noise is less relevant because photon shot noise dominates at high illumination levels.

In at least one further embodiment, the high sensitivity signal comprises a low sensitivity signal and an additional video signal. This means that the high sensitivity signal is equal to the low sensitivity signal plus the additional video signal. The additional video signal may represent a pure video signal without noise. Advantageously, noise of the high-sensitivity signal is correlated with noise of the low-sensitivity signal, so that CDS can be performed. Therefore, noise of the high-sensitivity signal can be effectively eliminated.

In at least one further embodiment, the pixel arrangement further comprises at least one further amplifier. The further amplifier comprises an input terminal electrically connected to the first capacitor and/or the second capacitor, i.e. to a terminal node of the respective capacitor. The further amplifier is configured to generate a pixel output signal at an output terminal of the further amplifier.

The further amplifier may form a further common drain amplifier, i.e. a further source follower. The gate terminal of the further amplifier is connected to the terminal node of the first capacitor and/or the second capacitor. This may mean that the first capacitor and the second capacitor are arranged in parallel, such that the gate terminal of the further amplifier may be connected to both terminal nodes. Alternatively, a further amplifier is connected to the terminal node of the first capacitor and a second further amplifier is connected to the terminal node of the second capacitor. The first capacitor and the second capacitor may also be arranged in cascade such that the further amplifier is directly connected to only the terminal node of the second capacitor. The common terminal of the further amplifier is connected to the pixel supply voltage. The pixel output signal is applied at the output terminal of the further amplifier. Additional amplifiers may be used as voltage buffers. The amplifier may be configured to buffer the signal, thereby decoupling the capacitor stage from the readout circuit.

In at least one further embodiment, the pixel device further comprises a select gate between the output terminal of the further amplifier and the column bus. Select gates are provided for transferring pixel output signals to the column bus.

The select gate may be implemented as a select switch. For example, the select gate is part of a select transistor that includes a first terminal connected to the output terminal of the further amplifier and a second terminal connected to the column bus. By applying a select signal to the select gate, the select transistor becomes conductive so that the pixel output signal is forwarded to the readout circuit via the column bus. For example, the readout circuit includes an analog-to-digital converter (ADC) having a sample and hold function. The column bus may or may not be comprised by the pixel arrangement. Alternatively, the pixel includes only a portion of the column bus. Advantageously, the output signal of each pixel within the array can be accessed individually.

In at least one further embodiment, the pixel further comprises a pre-charge gate electrically coupled to the output terminal of the amplifier. The precharge gate is configured to precharge the first capacitor and the second capacitor.

The precharge gate may be implemented as a precharge switch. For example, the precharge gate is part of a precharge transistor that includes a first terminal connected to the output terminal of the amplifier and a second terminal connected to Ground (GND). By applying the precharge signal to the precharge gate, the precharge transistor becomes conductive so that the first capacitor and the second capacitor can be precharged. This may in particular mean that the first capacitor and the second capacitor are discharged in each frame before they are recharged by the amplifier to their final values. In addition, the precharge transistor may also provide a certain bias current to bias the amplifier. The precharge gate may also be implemented as a constant current source configured to provide a fixed current.

In at least one further embodiment, the at least one photodiode comprises a first photodiode for generating a first charge signal in the high sensitivity mode. Further, the at least one photodiode includes a second photodiode for generating a second charge signal in the low sensitivity mode.

The first photodiode and the second photodiode may be different. For example, the first photodiode has a larger photoactive area than the second photodiode so as to generate more charge carriers than the second photodiode. Alternatively, the second photodiode is provided with a filter in order to attenuate the second charge signal. The first photodiode and the second photodiode may share a common FD node, i.e. the same capacitance.

Thus, two photodiodes may be assigned to two respective transfer gates, wherein a first transfer gate is provided for transferring a first charge signal to a terminal node of the capacitance, and a second transfer gate is provided for transferring a second charge signal to a terminal node of the capacitance.

The first charge signal of the first photodiode results in a high sensitivity signal and the second charge signal of the second photodiode results in a low sensitivity signal. Thus, by providing a first photodiode and a second photodiode different from the first photodiode, a high dynamic range can be obtained using the corresponding charge signal.

In at least one further embodiment, the pixel device further comprises a sensitivity gate. The sensitivity gate is disposed between the reset gate and a terminal node of the capacitor. In this embodiment, the pixel device further comprises a third capacitor comprising a terminal node. A sensitivity gate is provided for shorting the terminal node of the capacitance to the terminal node of the third capacitor.

The sensitivity gate may be implemented as a gain switch. The sensitivity gate may be part of a sensitivity transistor including a first terminal electrically connected to the terminal node of the capacitor and a second terminal electrically connected to the terminal node of the third capacitor. By applying the gain signal to the sensitivity gate, the sensitivity transistor becomes conductive, shorting the FD node to the terminal node of the third capacitor. The sensitivity transistor may be referred to as a Dual Conversion Gain (DCG) transistor and the sensitivity signal may be referred to as a DCG signal or a coupled signal.

The third capacitor may be implemented as a MOS or MIM capacitor. The terminal node of the third capacitor is arranged between the reset gate and the sensitivity gate.

The third capacitor further comprises a further terminal node which may be grounded.

By shorting the FD node to the terminal node of the third capacitor, the combined capacitance is greater than the capacitance of the FD capacitance. Keeping the charge constant results in a decrease of the voltage signal. Thus, by increasing the capacitance, the gain is reduced. This means that the pixel arrangement has a reduced gain if the capacitance and the third capacitor are shorted. In other words, if the third capacitor is electrically decoupled from the capacitance through the sensitivity gate, the pixel device has an increased gain.

Typically, if the transfer gate is deactivated, the photodiode is separated from the capacitance by a potential barrier. Similarly, if the sensitivity gate is deactivated, the capacitance is separated from the third capacitor by an additional barrier. This means that charge carriers are prevented from diffusing between the photodiode and the capacitor, or between the capacitor and the third capacitor, respectively. However, in some embodiments, such charge is allowed to overflow, especially if the potential well of the photodiode or the potential well of the capacitor, respectively, is saturated. In this way, photo-induced charge carriers are not lost even during saturation, providing an increased dynamic range for the pixel device. In other words, the third capacitor stores excess charge carriers. Furthermore, the size of the photodiode and/or the capacitor may be smaller.

In at least one further embodiment, the first capacitor and the second capacitor are arranged in parallel. Both the first switch and the second switch are directly electrically connected to the output terminal of the amplifier. The terminal node of the first capacitor may be electrically connected to a further amplifier. The terminal node of the second capacitor may be electrically connected to a second further amplifier. It is also possible that the terminal node of the first capacitor and the terminal node of the second capacitor may be connected to a common further amplifier. Advantageously, the first capacitor and the second capacitor may be independently controlled by the first switch and the second switch.

In at least one further embodiment, the first capacitor and the second capacitor are arranged in cascade. In this case, the second switch is electrically connected to the output terminal of the amplifier via the first switch. In other words, the second switch is arranged between the terminal node of the first capacitor and the terminal node of the second capacitor. Advantageously, fewer components are required than in the case of a parallel arrangement of capacitors.

Further, an image sensor is provided comprising an array of pixels according to the pixel arrangement as described in one of the above embodiments. This means that all features disclosed for the pixel arrangement are also disclosed for and applicable to the image sensor and vice versa.

Further, an optoelectronic device comprising an image sensor is provided. This means that all features disclosed for the image sensor are also disclosed for and applicable to the optoelectronic device and vice versa.

The image sensor may be conveniently used in an optoelectronic device such as a smart phone, tablet computer, laptop computer or camera module. For example, the camera module is configured to operate in the visible domain for photography and/or video capture. Furthermore, the pixel arrangement is particularly suitable for operation in a global shutter mode, as the signals are stored in the pixel level memory (i.e. the first capacitor and the second capacitor). The global shutter mode is particularly suitable for infrared applications, wherein the image sensor device further comprises a light source synchronized with the pixels. Thus, optoelectronic devices comprising such image sensors may also operate in the Infrared (IR) domain, for example for 3D imaging and/or identification purposes. Image sensors with infrared sensitivity can be used in dark environments where video feed is required. Such applications are unlocked from the mobile phone face to the driver monitoring system. Both may be deployed in a luminaire in the Short Wave Infrared (SWIR) spectrum so that the telephone user/driver is not illuminated his/her light blindness.

Further, a method for operating a pixel arrangement is provided, which is configured to convert electromagnetic radiation in a high sensitivity mode and a low sensitivity mode, respectively. The above-described pixel devices may preferably be used in methods of operating the pixel devices described herein. This means that all features disclosed for the pixel arrangement and the image sensor are also disclosed for the method for operating the pixel arrangement and vice versa.

According to at least one embodiment of a method for operating a pixel device, the method comprises converting electromagnetic radiation into a corresponding charge signal by at least one photodiode. The method further includes providing a reset signal for resetting the capacitance. For example, a reset signal is applied to a reset gate electrically coupled to the capacitance. For example, by applying a reset signal, a pixel power supply voltage is applied to a terminal node of the capacitor, so that charge carriers stored on the capacitor are removed.

The method further includes providing a transfer signal for transferring a corresponding charge signal from the at least one photodiode to the capacitor. For example, a transfer signal is applied to the transfer gate between the photodiode and the terminal node of the capacitor.

The method further includes generating a respective amplified signal based on the respective charge signal and the sensitivity pattern. The respective amplified signal is one of a low sensitivity signal and a high sensitivity signal, respectively. The low sensitivity signal and the high sensitivity signal are based on a common noise level. This may mean that the noise level of the low sensitivity signal is correlated with the noise level of the high sensitivity signal. For example, the respective amplified signals are generated by an amplifier electrically connected to a capacitor at its input terminal.

The method further includes providing a first switching signal for transferring the respective amplified signal to the first capacitor. The first capacitor is configured to store a high sensitivity signal. For example, the first switching signal is applied to a first switch between a terminal node of the first capacitor and an output terminal of the amplifier.

The method further comprises providing a second switching signal for transferring the respective amplified signal to a second capacitor. The second capacitor is configured to store a low sensitivity signal. For example, the second switching signal is applied to a second switch between the terminal node of the second capacitor and the output terminal of the amplifier.

Advantageously, the two capacitors store two different signals, a high sensitivity signal and a low sensitivity signal. Accordingly, the dynamic range of the pixel device can be increased. In addition, the low sensitivity signal may be used as a reference level for the high sensitivity signal because both signals are based on a common noise level. This means that a high-sensitivity signal can be accessed using CDS, so that, for example, thermal noise and reset noise can be effectively eliminated.

In at least one further embodiment of the method, the method further comprises a first step during exposure of the pixel, wherein the pixel is operated in a low sensitivity mode. In the low sensitivity mode, a low sensitivity signal is generated and stored on the second capacitor. In a second step during pixel exposure, the pixel operates in a high sensitivity mode such that a high sensitivity signal is generated and stored on the first capacitor. The pixel exposure refers to a period of time in which the photodiode is exposed to light.

The low sensitivity signal is smaller than the high sensitivity signal. Specifically, the high sensitivity signal is equal to the low sensitivity signal plus the additional video signal. Thus, the low sensitivity signal is determined before the high sensitivity signal. Thus, advantageously, the high sensitivity signal may be based on the low sensitivity signal.

In at least one further embodiment of the method, the first and second steps during pixel exposure are performed without resetting the capacitance therebetween. If the capacitance is reset, the high-sensitivity signal will not be based on the low-sensitivity signal because the information about the low-sensitivity signal will be removed from the FD node. Advantageously, the capacitor stores information about the low sensitivity signal so that it can be reused in the high sensitivity mode. Advantageously, no additional noise is introduced.

In at least one further embodiment of the method, the low sensitivity signal is read out in a first step during pixel readout. In a second step of the readout period, the high-sensitivity signal is read out. Pixel readout refers to the period of time during which the analog signal stored on the capacitor is further processed. For example, the analog signals are transferred via a column bus to a readout circuit, where the analog signals are converted to digital signals. Advantageously, the low sensitivity signal is read out before the high sensitivity signal, so that the low sensitivity signal can be used as a reference level for the high sensitivity signal.

Reading out the high sensitivity signal may mean reading out the high sensitivity signal directly from the first capacitor. However, this may also mean that attenuated versions of the high sensitivity signal are read out. If the first capacitor and the second capacitor are arranged in cascade, the two capacitors are coupled to each other. For example, when reading out the high sensitivity signal, the high sensitivity signal may be redistributed in the first capacitor and the second capacitor. This means that the charge on the first capacitor will mix with the charge on the second capacitor. Thus, if the first capacitor is equal to the second capacitor, the high sensitivity signal on the first capacitor will be attenuated, e.g. twice.

In at least one further embodiment of the method, in a third step during pixel readout, the capacitance is reset and the reset level is read out. Resetting the capacitance is performed by applying a reset signal. The reset level refers to the non-video signal of the pixel device, i.e. no charge signal from the photodiode. By resetting the capacitance (i.e., FD node), additional noise is introduced that is uncorrelated with the noise of the high-sensitivity signal or the low-sensitivity signal. However, the reset level of the pixel device includes information about Fixed Pattern Noise (FPN). Thus, advantageously, the FPN of the pixel arrangement can be determined in a third step during pixel readout.

In at least one further embodiment, the method further comprises: during pixel readout, double delta sampling is performed by using the reset level as a reference level for the low sensitivity signal. In case of high illumination, the low sensitivity signal is further processed. Here, thermal noise is less correlated because photon shot noise dominates at high illumination. Thus, correlated double sampling to remove noise from the video signal is not required. However, it may be desirable to remove the FPN from the video signal. The FPN can be removed by performing double-up sampling (DDS), i.e., by using the reset level as a reference level for the low sensitivity signal.

In at least one further embodiment, the method further comprises: during pixel readout, correlated double sampling is performed by using the low sensitivity signal as a reference level for the high sensitivity signal. As described above, the low sensitivity signal and the high sensitivity signal are based on a common noise level. Accordingly, by performing correlated double sampling, that is, by using a low-sensitivity signal as a reference level for a high-sensitivity signal, noise can be effectively removed from the high-sensitivity signal. The removed noise includes temporal noise and fixed pattern noise.

In at least one further embodiment, the method further comprises: during pixel readout, it is determined whether to use a low sensitivity signal or a high sensitivity signal for further processing based on the corresponding amplitude level. In the case of high illumination, the high sensitivity signal may saturate. Thus, the low sensitivity signal is applied for further processing. In the case of low illumination, the low sensitivity signal may be weak and subject to noise. Thus, a high sensitivity signal is applied for further processing. Determining whether to use the low sensitivity signal or the high sensitivity signal for further processing based on the respective amplitude levels may include comparing the respective amplitude levels to respective thresholds. Advantageously, depending on the current illuminance, a low sensitivity signal or a high sensitivity signal may be used. Thus, the dynamic range increases.

In at least one further embodiment, the method further comprises: during pixel exposure in the low sensitivity mode, the conversion gain is adjusted by applying a gain signal for shorting the terminal node of the capacitor to the terminal node of the third capacitor. For example, the gain signal is applied to the sensitivity gate between the terminal node of the capacitor and the terminal node of the third capacitor. By shorting the respective terminal nodes at a given charge signal, the total capacitance increases, which in turn reduces the voltage signal. Therefore, the conversion gain of the corresponding charge signal decreases. Thus, two different conversion gains may be provided.

In at least one further embodiment of the method, converting the electromagnetic radiation into a corresponding charge signal includes generating a first charge signal by the first photodiode in a high sensitivity mode and generating a second charge signal by the second photodiode in a low sensitivity mode. In particular, the first photodiode and the second photodiode may be different such that they generate different charge signals at a given illuminance. For example, a large photodiode may be used in a high sensitivity mode for generating an increased charge signal, while a smaller photodiode may be used in a low sensitivity mode for generating a decreased charge signal and thus preventing saturation of storage elements within the pixel. By using two or at least two photodiodes, the dynamic range of the pixel device can be increased.

In at least one further embodiment of the method, converting the electromagnetic radiation into a corresponding charge signal comprises generating a first charge signal by a reduced exposure time in the low sensitivity mode and generating a second charge signal by an increased exposure time in the high sensitivity mode. The corresponding charge signal at a given illumination may be varied by different exposure times. For example, a long exposure time may be used to generate an increased charge signal in a high sensitivity mode, while a short exposure time may be used to generate a decreased charge signal in a low sensitivity mode, thereby preventing saturation. By using two or at least two exposure times, the dynamic range of the pixel device can be increased.

Other embodiments of the method will be apparent to those skilled in the art from the embodiments of the pixel arrangement described above, and vice versa.

Further, another method for operating a pixel device is provided. The above-described pixel arrangement configured to convert electromagnetic radiation in a high-sensitivity mode and a low-sensitivity mode may also be used for this method of operation. This means that all features disclosed for the pixel arrangement and the image sensor are also disclosed for the following method of operating the pixel arrangement and vice versa. In addition, aspects of the above methods are also related to the following methods. Thus, embodiments of the above-described methods are also disclosed for and applicable to the following methods.

In at least one embodiment, the method includes accumulating charge carriers with a photodiode during a first integration period. The method further includes pulsing the transfer gate to a first voltage level at the end of the first integration period to transfer a portion of the accumulated charge carriers to the capacitor, wherein the portion is configured to be depleted to a supply voltage.

The first integration period is a portion of the exposure period. This may mean that the exposure period is subdivided into several integration periods, such as a first integration period, a second integration period and a third integration period. The exposure period may be referred to as during pixel exposure. As described above, the capacitance may be the (parasitic) capacitance of the diffusion node. In other words, therefore, the accumulated charge carriers are transferred to the diffusion node by applying a transfer signal to the transfer gate. The transfer gate may be implemented as part of a transfer transistor. The first voltage level may be a voltage level lower than a threshold voltage of the transfer transistor. This may mean that the first voltage level is a partial voltage level. For example, the first voltage level is 0.8V. By applying a first voltage level to the transfer gate, the potential barrier between the photodiode and the diffusion node is reduced. Thus, excess charge carriers can overcome the reduced potential barrier to transfer from the photodiode to the diffusion node. These excess charge carriers are referred to as the portions of accumulated charge carriers. The portion is configured to be depleted to a supply voltage. This may be achieved by resetting the diffusion node. As described above, by applying a reset signal to the reset transistor connected between the diffusion node and the pixel power supply terminal, reset of the diffusion node can be achieved. The depletion of the portion may be performed, for example, during the exposure period or at the end of the exposure period or after the exposure period.

In at least one embodiment, the method further comprises continuing to accumulate charge carriers with the photodiode during the second integration period.

The second integration period is a portion of the exposure period. The second integration period is later than the first integration period. The second integration period may immediately follow the first integration period. The exposure period may include a first integration period and a second integration period. The charge carriers accumulated at the photodiode after the second integration period include the charge carriers accumulated during the first and second integration periods minus the portion of charge carriers to be depleted.

In at least one embodiment, at the end of the second integration period, the method further includes pulsing a transfer transistor to a first voltage level to transfer a first portion of the accumulated charge carriers to a capacitance, and storing a low sensitivity signal representative of the first portion of the accumulated charge carriers on at least a second capacitor (80) of a pair of capacitors electrically coupled to the capacitance.

Storing the low sensitivity signal may be performed during a storage period. The storage period may overlap with the exposure period. This may mean that the storage period starts during the exposure period. The storage period may be referred to as a frame storage period of the pixel. Transferring the first portion of the accumulated charge carriers may occur after resetting the diffusion node/capacitance to deplete the portion of the accumulated charge carriers. The first portion of the accumulated charge carriers is different from the portion of the accumulated charge carriers. However, since the first voltage level is applied to the transfer gate again, the barrier is lowered by the same amount. Thus, the first portion of accumulated charge carriers corresponds to excess charge carriers accumulated during the second integration period. A first portion of the accumulated charge carriers is not depleted but is stored on the pair of capacitors. The pair of capacitors are electrically coupled to the capacitance or the diffusion node, respectively. As described above, the pair of capacitors includes the first capacitor and the second capacitor. As described above, the capacitor may be electrically coupled to the diffusion node via the source follower. As described above, the capacitors may be arranged in parallel or in cascade. In the case of a capacitor cascade arrangement, the low sensitivity signal representing the first portion of the accumulated charge carriers may be distributed over two capacitors. In the case of a parallel arrangement of capacitors, the low sensitivity signal may be stored on one of the capacitors, for example on the second capacitor. Storing the low sensitivity signal may be achieved by applying a switching signal to the corresponding switch assigned to the capacitor. For example, as described above, a first switch is assigned to a first capacitor, and a second switch is assigned to a second capacitor.

In at least one embodiment, the method further comprises continuing to accumulate charge carriers with the photodiode during a third integration period. The third integration period is a portion of the exposure period. The third integration period is later than the second integration period. The third integration period may immediately follow the second integration period. The exposure period may include a first integration period, a second integration period, and a third integration period. The charge carriers accumulated at the photodiode after the third integration period include charge carriers accumulated during the first integration period, the second integration period, and the third integration period minus a portion of charge carriers to be depleted and minus a first portion of charge carriers to be stored on at least the second capacitor.

In at least one embodiment, at the end of the third integration period, the method further includes pulsing the transfer transistor to a second voltage level to transfer a remaining portion of the accumulated charge carriers to the capacitor, and storing a high sensitivity signal representative of the remaining portion of the accumulated charge carriers on a first capacitor of the pair of capacitors.

Pulsing the transfer transistor to the second voltage level occurs later than pulsing the transfer transistor to the first voltage level. The second voltage level may be a full voltage level. The second voltage level may be a voltage level higher than a threshold voltage level of the transfer transistor. For example, the second voltage level is 2.8V. Thus, by applying the second voltage level, the transfer transistor is in an electrically conductive state. Thus, by applying the second voltage level, the potential barrier between the photodiode and the diffusion node is lower than the potential barrier when the first voltage level is applied. In particular, the barrier can be completely dissipated. Thus, the remaining charge carriers accumulated at the photodiode are transferred to the diffusion node. The remaining portion of the accumulated charge carriers corresponds to the charge carriers accumulated during the first integration period, the second integration period and the third integration period minus the portion of charge carriers to be depleted and minus the first portion of charge carriers to be stored on at least the second capacitor.

In at least one embodiment, during the readout period, the method further comprises reading out the low sensitivity signal and the high sensitivity signal stored on the capacitor.

As described above, the readout of the corresponding signal can be performed by applying the selection signal to the selection transistor. The select signal connects a capacitor having a signal stored thereon to the column bus of the pixel. As described above, the capacitor may be electrically coupled to the column bus via a further source follower.

The described method includes barrier modulation of the transfer gate. By means of barrier modulation, the dynamic range of the pixel device can be increased. In particular, the dynamic range of a pixel device is increased by depleting a portion of the accumulated charge carriers under high light conditions. The high sensitivity signal (high conversion gain signal, HCG signal) contains the corner calibration value required during linearization of the pixel output signal. In particular, knowing the duration of the first integration period and the second integration period, respectively, and the first voltage level, the linearized signal can be reconstructed. The transfer transistor of each pixel is subject to variations and fluctuations in the manufacturing process. Therefore, the threshold voltage of the transfer transistor is different for each pixel. This may mean that the barrier between the photodiode and the diffusion node is different for each pixel when the first voltage level is applied. However, knowing the exact barrier level is relevant to removing the fixed pattern noise FPN. From the first voltage level and the HCG signal of the pixel (which corresponds to the remaining part of the charge carriers accumulated after the application of the first voltage level), information about the dependence of the output signal on the potential barrier can be derived. Further, since the first voltage level applied during the exposure period is also applied during the storage period, the ratio of the first integration period and the second integration period and the HCG signal may be used to determine how large the amount of charge carriers depleted to the power supply voltage at the end of the first integration period. Given this amount and the low sensitivity signal (low conversion gain signal, LCG signal), the pixel output signal used under high light conditions can be reconstructed.

In addition, the low sensitivity signal (LCG signal) may be used as a reference level for the high sensitivity signal (HCG signal) because both signals are based on a common noise level because the diffusion node is not reset between the storage LCG and HCG signals. Accordingly, CDS can be performed on an HCG signal used under low light conditions (in low light conditions, the LCG signal contains only noise but no video information).

In at least one embodiment, a method for operating a pixel device includes accumulating charge carriers with a photodiode in a first integration period, and pulsing a transfer gate to a first voltage level at the end of the first integration period to transfer a portion of the accumulated charge carriers to a capacitance, wherein the portion is configured to be depleted to a supply voltage. It further comprises continuing to accumulate charge carriers with the photodiode during the second integration period. It further includes pulsing the transfer gate to a first voltage level at the end of the second integration period for transferring a first portion of the accumulated charge carriers to the capacitance, and storing a low sensitivity signal representative of the first portion of the accumulated charge carriers on at least a second capacitor of a pair of capacitors electrically coupled to the capacitance. It also includes during a third integration period (T ₃ ) Continues to accumulate charge carriers using the photodiode (20). It further includes pulsing the transfer gate to a second voltage level at the end of the third integration period for transferring the remaining portion of the accumulated charge carriers to a capacitance and storing a high sensitivity signal representative of the remaining portion of the accumulated charge carriers onto a first capacitor of the pair of capacitors. The method further comprises the steps of: during the readout period, the low-sensitivity signal and the high-sensitivity signal stored on the capacitor are read out.

In at least one embodiment, the high sensitivity signal indicates a calibration level based on the remaining portion of accumulated charge carriers.

In at least one embodiment, the method further comprises adjusting the pixel output signal based on the low sensitivity signal and the high sensitivity signal depending on the pixel specific knee value determined based on the calibration level.

As described above, the remaining portion of the accumulated charge carriers corresponds to a high sensitivity signal, also referred to as an HCG signal. Knowing the first voltage level and the HCG signal, information about the transfer gate that forms the barrier can be derived. Thus, the HCG signal may be used as a calibration level for the LCG signal. This may mean that the calibration level is an HCG signal. In other words, information about the depleted portion of accumulated charge carriers is not lost, but can be reconstructed based on the first voltage level and the HCG signal as well as the integration period. In this way, depleted charge carriers can be considered. In addition, a calibration level is required in post-processing to remove the FPN caused by the change in the transfer gate.

The pixel output signal may be based on an LCG signal or an HCG signal depending on the light conditions. Under high light conditions, the LCG signal is further processed. Further processing of the LCG signal may mean adjusting the LCG signal by means of the calibration level and the relation of the first integration period and the second integration period. Thus, adjusting the pixel output signal may be referred to as pixel corner calibration. The pixel inflection point calibration may be performed separately for each pixel. Furthermore, the pixel device is self-calibrating because the barrier information is contained in the HCG signal. Thus, no additional reading is required.

Adjusting the LCG signal may also include a double-delta sampling DDS routine to remove the FPN.

In low light conditions, the HCG signal is further processed. Further processing of the HCG signal may mean adjusting the HCG signal by a correlated double sampling CDS routine.

In at least one embodiment, the first integration period is longer than the second integration period. This may mean that the duration of the first integration period is greater than the duration of the second integration period. For example, the first integration period is 1.5 to 3.0 times longer than the second integration period. For example, the first integration period is 2.0 times longer than the second integration period. In this way, saturation effects can be avoided.

In at least one embodiment, the second voltage level is greater than the first voltage level. This means that if the second voltage level is applied to the transfer gate, the barrier between the photodiode and the diffusion node is lower than if the first voltage level is applied to the transfer gate. Thus, the first voltage level may be a partial voltage level and the second voltage level may be a full voltage level. In other words, the first voltage level may be lower than the threshold voltage level and the second voltage level may be higher than the threshold voltage level. The first voltage level may be below 1.0V, for example 0.8V. For example, the second voltage level may be higher than 2.0V, such as 2.8V. By applying a partial voltage level to the transfer gate, only a portion of the accumulated charge carriers are transferred to the diffusion node. By applying a full voltage level to the transfer gate, the photodiode can be reset and the remainder of the accumulated charge carriers can be transferred to the diffusion node.

The described method using barrier modulation may also be combined with aspects of the above method:

specifically, in at least one embodiment, in a first step during pixel readout (readout period), a low-sensitivity signal can be read out, and in a second step during readout, a high-sensitivity signal can be read out, wherein in a third step during pixel readout, the capacitance is reset and the reset level is read out.

In at least one further embodiment, the reset level may be used as a reference level for the low sensitivity signal. This implements DDS.

In at least one further embodiment, correlated double sampling may be performed by using the low sensitivity signal as a reference level for the high sensitivity signal.

In at least one further embodiment, it may be determined whether to use a low sensitivity signal or a high sensitivity signal for further processing based on the respective amplitude levels. Thus, the pixel output signal may be adapted to the light conditions, which increases the dynamic range.

In at least one further embodiment, the pixel arrangement may comprise a dual conversion gain transistor as explained above. Thus, the method may include adjusting the conversion gain by applying a gain signal for shorting a terminal node of the capacitance (corresponding to the diffusion node) to a terminal node of the third capacitor. Adjusting the conversion gain may be performed during the storage period.

By the above method of operating a pixel device, HDR in a voltage domain global shutter (VGS) pixel can be achieved without affecting the pipeline mode (i.e., pipelining the signal to a storage capacitor). Furthermore, only two capacitors are required, which means that the pixel device can have a low area. The latter method utilizes self-calibrating barrier modulation, which means that the calibration value is included in one of the signals, in particular in the HCG signal. Typically, the calibration value must be obtained by additional reading.

Other embodiments of the method will be apparent to those skilled in the art from the embodiments of the pixel arrangement described above, and vice versa. The pixel arrangement may form a voltage domain global shutter pixel. Alternatively, the pixel arrangement forms a rolling shutter pixel.

Drawings

The following description of the drawings may further illustrate and explain aspects of a pixel device and a method of operating such a pixel device. Components and portions of the pixel device that are functionally identical or have the same effect are denoted by the same reference numerals. The same or effectively the same components and portions may be described with respect to only the drawing in which they first appear. Their description is not necessarily repeated in successive figures.

Fig. 1 shows the dynamic range of a pixel device.

Fig. 2A shows an exemplary embodiment of a pixel device.

Fig. 2B shows an exemplary signal timing of the pixel arrangement according to fig. 2A.

Fig. 3 shows a further exemplary embodiment of a pixel arrangement.

Fig. 4A shows a further exemplary embodiment of a pixel arrangement.

Fig. 4B shows an exemplary signal timing of the pixel arrangement according to fig. 4A.

Fig. 5 shows a further exemplary embodiment of a pixel arrangement.

Fig. 6 shows a schematic diagram of an optoelectronic device comprising an image sensor comprising a pixel arrangement.

Fig. 7 shows further exemplary signal timings of the pixel arrangement according to fig. 2A.

Fig. 8 shows an exemplary operation performed by the pixel device according to fig. 2A.

Fig. 9 shows exemplary characteristics of the pixel device.

Fig. 10 shows further exemplary signal timings of the pixel arrangement according to fig. 2A.

Detailed Description

Fig. 1 shows a photo-induced charge signal Q of a pixel device 10 (not shown) plotted against illuminance I. It can be seen that there is a linear or near linear relationship between the charge signal Q and the illuminance I. For small values of the charge signal Q, the signal is dominated by the noise floor 998, making it challenging to obtain a usable video signal from the noise charge signal Q. If the charge signal is well above the noise floor level 998, then the available video signal may be determined. However, for a high charge signal Q, a saturation region 999 may be reached. This means that the photodiodes or storage elements in the pixel arrangement 10 can only handle a certain number of photo-induced charge carriers, since the corresponding potential wells are not large enough to accumulate more charge. Therefore, in the typical pixel device 10, an appropriate video signal for very low light conditions and very high light conditions cannot be obtained. The light conditions in between, i.e. those that can obtain an appropriate video signal, define the dynamic range DR of the pixel arrangement 10. It is desirable to increase the dynamic range of the pixel device 10.

In fig. 2A, an exemplary embodiment of the pixel device 10 is shown. The pixel arrangement 10 shown may be operated to achieve a High Dynamic Range (HDR). The pixel arrangement 10 is configured to convert electromagnetic radiation in a high sensitivity mode and a low sensitivity mode, respectively.

The pixel arrangement 10 comprises at least one photodiode 20 configured to convert electromagnetic radiation into a corresponding charge signal. The photodiode 20 includes an anode terminal and a cathode terminal. The anode terminal of the photodiode 20 is connected to a negative pixel power supply voltage VSS, which may also be Ground (GND). The photodiode 20 can convert light of any wavelength, such as visible light, infrared light, and/or ultraviolet light.

The pixel further includes a transfer gate 30 between the photodiode 20 and a capacitor 40. In the embodiment shown in fig. 1, the transfer gate 30 is implemented as part of a transfer transistor that acts as a switch. A first terminal of the transfer transistor is electrically connected to the cathode terminal of the photodiode 20. A second terminal of the transfer transistor is electrically connected to a terminal node 42 of the capacitor 40. The terminal node 42 is hereinafter referred to as a (floating) diffusion (FD) node 42. The capacitance 40 may be implemented as a capacitor, and may be referred to as an FD capacitor. The transfer gate 30 of the transfer transistor is configured to receive a transfer signal TX for transferring a corresponding charge signal from the photodiode 20 to the capacitor 40. The capacitor 40 is configured to convert a corresponding charge signal to a corresponding voltage signal. The other terminal node 44 of the capacitor 40 may be connected to VSS.

The pixel device 10 also includes a reset gate 50 electrically coupled to the capacitor 40 for resetting the capacitor 40. In the embodiment shown in fig. 1, the reset gate 50 is implemented as part of a reset transistor that acts as a switch. The first terminal of the reset transistor is electrically connected to the pixel power supply voltage VDD. A second terminal of the reset transistor is electrically connected to a terminal node 42 of the capacitor 40. The reset gate 30 of the reset transistor is configured to receive a reset signal RST for resetting the capacitance 40 by application of the pixel supply voltage VDD and thereby removing any redundant charge carriers.

The pixel device 10 further includes an amplifier 60, the amplifier 60 being electrically connected to the capacitor 40 and configured to generate a respective amplified signal based on the respective charge signal and the sensitivity pattern. The corresponding amplified signals are respectively low-sensitivity signals or high-sensitivity signals. The low sensitivity signal and the high sensitivity signal are based on a common noise level. As shown in fig. 2, the amplifier 60 may form a common drain amplifier, also referred to as a source follower. The gate terminal 62 of the source follower is connected to the FD node 42 and serves as the input terminal 62 of the amplifier 60. The common terminal is connected to a power supply voltage VDD. A corresponding amplified signal is generated at the output terminal 64 of the amplifier 60.

The pixel device 10 further includes a first capacitor 70 configured to store a high sensitivity signal and a second capacitor 80 configured to store a low sensitivity signal. The first capacitor 70 includes a terminal node 72 and a further terminal node 74. Additional terminal nodes 74 may be connected to VSS as shown in fig. 1. Further, the second capacitor 80 comprises a terminal node 82 and a further terminal node 84. Additional terminal nodes 84 may be connected to VSS as shown in fig. 2.

The pixel device 10 further comprises a first switch 90 between the output terminal 64 of the amplifier 60 and the first capacitor 70. A first switch 90 is provided for transferring the respective amplified signal to the first capacitor 70. The first switch 90 may be formed of a first switching transistor. The first switching transistor comprises a gate terminal 90, the gate terminal 90 being configured to receive the first switching signal S1. A first terminal of the first switching transistor is connected to the output terminal 64 of the amplifier 60. A second terminal of the first switching transistor 90 is connected to a terminal node 71 of the first capacitor 70.

The pixel device 10 further comprises a second switch 100 arranged between the output terminal 64 of the amplifier 60 and the second capacitor 80. A second switch 100 is provided for transferring the corresponding amplified signal to the second capacitor 80. The second switch 100 may be formed of a second switching transistor. The second switching transistor may include a gate terminal 100, the gate terminal 100 being configured to receive the second switching signal S2. The first terminal of the second switching transistor is connected to the second terminal of the first switching transistor and to the terminal node 72 of the first capacitor 70. A second terminal of the second switching transistor is connected to a terminal node 82 of the second capacitor 80.

The pixel device 10 according to fig. 2A may operate as follows: in a first step during pixel exposure, the photodiode 20 is exposed Yu Guangda for a first exposure time T ₁ So that a first charge signal is generated and converted into a low sensitivity signal. By applying the respective switching signals S1, S2, the low sensitivity signal is transferred and stored on the second capacitor 80. In a second step during pixel exposure, the photodiode 20 isExposure to light for a second exposure time T ₂ Which is longer than the first exposure time T ₁ So that a second charge signal is generated and converted into a high sensitivity signal. By applying the respective switching signals S1, S2, the high sensitivity signal is transferred and stored on the first capacitor 70. The floating diffusion capacitance 40 may not be reset between the first step and the second step. Thus, the high sensitivity signal is based on or comprises a low sensitivity signal. This means that both signals are based on a common noise level. Thus, during pixel readout, the low-sensitivity signal can be used as a reference level for the high-sensitivity signal, so that Correlated Double Sampling (CDS) can be performed. Thus, noise in the high-sensitivity signal can be eliminated.

In a further step during pixel readout, the reset level of the pixel device 10 is sampled by applying a reset signal RST to the reset gate 50. The reset level may be used as a reference level for the low sensitivity signal so that double incremental sampling (DDS) may be performed. Accordingly, fixed Pattern Noise (FPN) in the low sensitivity signal can be eliminated. During pixel readout, it may be determined whether to use a low sensitivity signal with DDS or a high sensitivity signal with CDS for further processing based on the corresponding amplitude level.

The pixel device 10 shown in fig. 2A includes additional components, however, additional components may be omitted in other embodiments. The pixel device 10 according to fig. 2A further comprises a precharge gate 160 electrically coupled to the output terminal 64 of the amplifier 60. The precharge gate 160 may be provided for precharging the first capacitor 70 and the second capacitor 80, which may in particular mean that the capacitors 70, 80 are discharged before the new signal is stored. As shown in fig. 2A, the precharge gate 160 may be part of a precharge transistor that includes a first terminal connected to the output terminal 64 of the amplifier 60 and a second terminal connected to VSS. By applying the precharge signal PC to the precharge gate 160, the precharge transistor becomes conductive, so that the first capacitor 70 and the second capacitor 80 are discharged.

The pixel arrangement 10 according to fig. 2A further comprises a further amplifier 110, the further amplifier 110 comprising an input terminal 112 electrically connected to the second capacitor 80, and the further amplifier 110 being configured to generate a pixel output signal at an output terminal 114 of the further amplifier 110. Similar to amplifier 60, the further amplifier may be implemented as a source follower, wherein gate 112 serves as input terminal 112 and the common terminal is connected to VDD.

The pixel device 10 further comprises a select gate 120 between the output 114 of the further amplifier 110 and the column bus 130 for transferring the pixel output signal to the column bus 130. As shown, select gate 120 may be part of a select transistor that includes a first terminal connected to output terminal 114 of further amplifier 110 and a second terminal connected to column bus 130. By applying a select signal SEL to select gate 120, the pixel output signal is forwarded to column bus 130.

In fig. 2B, the operation of the pixel arrangement 10 according to fig. 2A is shown in more detail and with respect to signal timing. It should be noted, however, that the signal timing shown is more of an example and may vary. Furthermore, the scaling of the time interval should not be seen as an accurate indication.

It can be seen that the operating pixel arrangement 10 can be divided into two time intervals, wherein the first time interval T, respectively _ex Is provided for pixel exposure and frame storage, and a second time interval T _r0 Is provided for pixel readout or row readout. In this context, a row read out may mean a read out of a single row. The rows can be read out sequentially, wherein all rows require the same time interval T _ro . Since the pixel arrangement 10 may be a global shutter pixel, the pixel exposure and frame store may be global operations, i.e. the pixel exposure and frame store may affect each pixel of the pixel array simultaneously. However, reading pixels may be a local operation, as the pixels or rows of the pixel array may be read one after the other. Furthermore, in the pixel device 10 of the illustrated embodiment, the first time interval T _ex Is subdivided into a first (short) exposure time T ₁ And a second (long) exposure time T ₂ As described above.

Fig. 2B shows timings of the transfer signal TX, the reset signal RST, the first switching signal S1, the second switching signal S2, the precharge signal PC, and the selection signal SEL. These signals may be in an active state (high state) or in a deactivated state (low state). Applying the corresponding signal may mean that the signal is switched to an active state. Hereinafter, the timing is explained in more detail using selected time points t1 to t8 shown in the drawings.

At a first exposure time T ₁ At the end, a transfer signal TX is applied at time t1, such that the corresponding charge signal is transferred from photodiode 20 to capacitor 40. Furthermore, this results in a low sensitivity signal being transferred to the second capacitor 80, because the switching signals S1, S2 controlling the first switch 90 and the second switch 100 are both in an active state. By deactivating the second switching signal S2 at time t2, a low sensitivity signal is stored on the second capacitor 80.

At a second exposure time T ₂ At the end, the transfer signal TX is applied again at time t3, so that the corresponding charge signal is transferred from the photodiode 20 to the capacitor 40. In this case, this results in a high sensitivity signal that is transferred to the first capacitor 70 because the switching signal S1 is still in an active state. By deactivating the first switching signal S1 at time t4, a high sensitivity signal is stored on the first capacitor 70. It should be noted that between time t1 and time t3, the reset signal RST remains deactivated, which means that the capacitor 40 is not reset, such that the high sensitivity signal and the low sensitivity signal are based on a common noise level. At time t5, the reset signal RST is activated. This is to prevent imaging problems such as halation. The reset signal RST is activated after storing the high sensitivity signal.

The pixel readout starts by applying the selection signal SEL at time t 6. At this time, the low sensitivity signal stored on the second capacitor 80 is read out. The high sensitivity signal stored on the first capacitor 70 is read out by applying the second switching signal S2 at time t 7. From time t8, the reset level is read out by deactivating the reset signal RST. Subsequently, the first switching signal S1, the second switching signal S2, and the precharge signal PC are activated, so that the signal corresponding to the reset level is transferred to the readout circuit, and the capacitors 70, 80 are discharged. After that, the pixel device 10 is ready for the next frame.

In fig. 3, a further embodiment of the pixel arrangement 10 is shown. The embodiment according to fig. 3 differs from the embodiment according to fig. 2 in that the capacitors 70, 80 are not arranged in cascade, but in parallel. This means that the second switch 100 coupled to the second capacitor 80 is directly connected to the output terminal 64 of the amplifier 60, instead of being connected to the output terminal 64 of the amplifier 60 via the first switch 90 as in fig. 2. It should be noted that the precharge gate 160 may also be implemented as a constant current source configured to provide a fixed current. Furthermore, the embodiment according to fig. 3 further comprises a further select gate 120 'and a second further amplifier 110' coupled to the second capacitor 80, while the further amplifier 110 and the select gate 120 are coupled to the first capacitor 70. It should be noted, however, that the illustrated embodiment shows a parallel arrangement of capacitors 70, 80 by way of example only. Other arrangements are possible. For example, the capacitors 70, 80 arranged in parallel may share a common further amplifier 110 through additional switches. The parallel arrangement has the advantage that the high-sensitivity signal and the low-sensitivity signal can be stored and read independently, at the cost of requiring additional components. Those skilled in the art will understand how to achieve similar signal timing as shown in fig. 2B. However, the signal timing may be slightly changed during both pixel exposure and pixel readout, as the first switch and the second switch may be operated independently.

In fig. 4A, another embodiment of the pixel device 10 is shown. The embodiment according to fig. 4 differs from the embodiment according to fig. 2 in that the pixel device further comprises a second photodiode 20 'connected to the FD node 42 via a second transfer gate 30'. This means that the first photodiode 20 and the second photodiode 20' are arranged in parallel. The first photodiode 20 is configured to generate a first charge signal in a high sensitivity mode and the second photodiode 20' is configured to generate a second charge signal in a low sensitivity mode. The first photodiode 20 and the second photodiode 20' may be different, which may mean that at a given illuminance the corresponding charge signal is different. The manner in which such a pixel device 10 is operated may be similar to the embodiment of fig. 2A, however, the exposure times of the respective photodiodes 20, 20' may be equal.

In fig. 4B, the operation of the pixel device 10 according to fig. 4A is shown in more detail with respect to signal timing. Also, it should be noted that the illustrated signal timing is more examples and may vary. Scaling of the time interval should not be seen as an accurate indication. The timing of the respective signals is similar to that in the example of fig. 2B, except that the first transfer signal TX1 controls the difference of the first transfer gate 30 and the second transfer signal TX2 controls the second transfer gate 30'. Thus, at time t1, the corresponding charge signal is transferred from the second photodiode 20' to the capacitor 40 by activating the second transfer signal TX2, and at time t3, the corresponding charge signal is transferred from the first photodiode 20 to the capacitor 40 by activating the first transfer signal TX 1. For further explanation of fig. 4B, reference is made to the description above with respect to fig. 2B.

In fig. 5, another embodiment of the pixel arrangement 10 is shown. The embodiment according to fig. 5 differs from the embodiment according to fig. 2A in that it further comprises a sensitivity gate 140 between the capacitor 40 and the reset gate 50. Thus, in this embodiment, reset gate 50 is electrically coupled to capacitor 40 via sensitivity gate 140. Further, the pixel device 10 includes a third capacitor 150. The third capacitor 150 includes a terminal node 152 and a further terminal node 154. The further terminal node 154 of the third capacitor 150 may be connected to VSS as indicated. The sensitivity gate 140 may be part of a sensitivity transistor that includes a first terminal connected to the FD node 42 of the capacitance 40 and a second terminal connected to the terminal node 152 of the third capacitance 150. By applying a gain signal to the sensitivity gate 140, the sensitivity transistor becomes conductive, shorting the FD node 42 to the terminal node 152 of the third transistor 150. Thus, the total capacitance can be increased, and the conversion gain can be reduced.

The mode of operation of this embodiment is similar to the mode of operation of the embodiment according to fig. 2A. Here, however, the pixel 10 does not have to be exposed twice. The charge signal of the photodiode 20 is first converted with a low conversion gain by applying a gain signal to the sensitivity gate 140, thereby obtaining a low sensitivity signal. Then, the charge signal is converted at a high conversion gain by deactivating the gain signal, thereby obtaining a high-sensitivity signal. As in the previously mentioned embodiment, the capacitor 40 is not reset between the generation of the high sensitivity signal and the low sensitivity signal. Those skilled in the art will understand how to implement similar signal timing as shown in fig. 2B and 4B. However, the signal timing may vary slightly, at least during pixel exposure.

In fig. 6, an optoelectronic device 300 comprising an image sensor 200 is schematically shown, the image sensor 200 comprising a pixel arrangement 10. The pixels 10 of the image sensor 200 may be arranged in a two-dimensional array, as indicated in fig. 6. The optoelectronic device 300 or the image sensor 200 may comprise further components, such as other circuit elements or light sources, which are synchronized with the pixels 10. The pixel device 10 is used, for example, in a voltage domain global shutter pixel (abbreviated VGS pixel). The pixel arrangement 10 is implemented as, for example, a rolling shutter pixel.

Fig. 7 shows another exemplary timing diagram performed by the pixel apparatus 10 shown in fig. 2A, for example. However, with a small modification, the timing chart can also be applied to the pixel device 10 according to fig. 3 (the first switching signal S1 is omitted). The following signals are shown as a function of time: a transfer signal TX, a reset signal RST, a first switching signal S1, and a second switching signal S2. It should be noted that the illustrated signal timing is more examples and may vary. Furthermore, the scaling of the time interval should not be seen as an accurate indication.

Fig. 7 shows a reset period T _rst Exposure period T _ex And (frame) storage period T _FS . The readout period T is not shown _r0 . Readout period T _r0 Will follow the storage period T _FS . Storage period T _FS And exposure period T _ex Overlapping. Exposure period T _ex In the reset period T _rst After that, the process is performed.

Exposure period T _ex Including a first integration period T1, a second integration period T2, and a third integration period T3. The third integration period follows the second integration period. Second integration periodT2 follows the first integration period T1. Storage period T _FS Including a first storage phase FS1 and a second storage phase FS2. The second storage phase FS2 follows the first storage phase FS 1.

Storage period T _FS May be a global storage period for each pixel within the pixel array. The readout period T can be performed separately for each row _r0 . Thus, in the second storage stage FS2 and the readout period T _r0 There may be a time gap between them.

In the reset period T _rst During this period, the reset signal RST and the transfer signal TX are applied. This may mean that the reset gate 50 and transfer transistor 30 are pulsed, resulting in the removal of any redundant charge carriers by connecting the photodiode 20 and diffusion node 42 to the pixel supply voltage VDD. The transfer gate may be pulsed to a full voltage level, i.e., to a second voltage level V2. The reset signal RST may remain high until the second TX is pulsed to the first voltage level V1, as shown by the dashed line.

During the first integration period T1, charge carriers are accumulated by the photodiode 20. The amount of accumulated charge carriers depends on the duration of the first integration period T1. At the end of the first integration period T1, the transfer gate 30 is pulsed to a first voltage level V1. This results in a portion of the accumulated charge carriers being transferred to either the capacitor 40 or the diffusion node 42, respectively. The portion is configured to be depleted to the pixel supply voltage VDD. This is done via a reset signal RST that is used to connect the diffusion node 42 to the pixel supply voltage VDD.

After said pulsing of the transfer gate 30, charge carriers continue to accumulate through the photodiode 20 in the second integration period T2. The second integration period T2 may be shorter than the first integration period T1. The amount of charge carriers accumulated in the second integration period T2 depends on the duration of the second integration period T2.

In the illustrated example, the reset pulse RST is applied to the reset gate 50 during the second integration period T2. This removes any redundant charge carriers from the diffusion node 42, especially the portion of the accumulated charge carriers that are transferred during the V1 pulse. Thus, the portion is depleted to the pixel supply voltage VDD.

At the end of the second integration period T2, the transfer gate 30 is again pulsed to the first voltage level V1. This results in a first portion of the accumulated charge carriers being transferred to diffusion node 42. A low sensitivity signal representing the first portion of accumulated charge carriers is configured to be stored on a capacitor (70, 80), as described below.

During the third integration period T3, charge carriers continue to be accumulated by the photodiode 20. The amount of accumulated charge carriers depends on the duration of the third integration period T3. At the end of the third integration period T3, the transfer gate 30 is pulsed to the second voltage level V2. This results in the transfer of the remaining portion of the accumulated charge carriers to diffusion node 42. A high sensitivity signal representing the remainder of the accumulated charge carriers is configured to be stored on a capacitor (70, 80), as described below.

Storage period T _FS The first storage stage FS1 of (1) uses pulsing to a first voltage level V1 that causes a first portion of the accumulated charge carriers to transfer to the capacitor 40 or the diffusion node 42, respectively. The first portion may correspond to charge carriers accumulated during the second integration period T2. Then, the first switching signal S1 and the second switching signal S2 are applied to store a low sensitivity signal representing a first portion of the accumulated charge carriers on a pair of capacitors 70, 80 electrically coupled to the capacitance 40 via the source follower 60. The low sensitivity signal may be redistributed across the first capacitor 70 and the second capacitor 80.

The second storage phase FS2 is followed by pulsing using a second voltage level V2, which results in the transfer of the remaining part of the accumulated charge carriers to the capacitor 40 or the diffusion node 42, respectively. The remaining portion may correspond to charge carriers accumulated during the first to third integration periods T1 to T3 (minus the depletion portion and the first portion). The second voltage level V2 may be a full voltage level such that all remaining charge carriers are transferred. Then, the first switch signal S1 is applied to the first switch 90 for storing a high sensitivity signal representing the remaining part of the accumulated charge carriers on the first capacitor 70. Alternatively, the first switching signal S1 may remain high from the first pulsing to the second pulsing, as indicated by the dashed line.

Fig. 8 illustrates exemplary operations performed by the pixel device 10 illustrated in fig. 2A, 3, or 5. In fig. 8, the operations are shown in blocks. A method for operating the pixel device 10 includes, for example, the following blocks, which may be referred to as processes or steps:

block 350: exposure starts: the photodiode 20 converts electromagnetic radiation into charge carriers. This means that charge carriers accumulate in the photodiode 20. This stage may be referred to as exposure period T _ex . Exposure period T _ex Can be subdivided into several subsequent integration periods T ₁ And T ₂ . The number of integration periods may be two.

Block 351: modifying the transfer barrier based on the system input: the transfer signal TX supplied to the transfer transistor 30 controls the potential barrier between the photodiode 20 and the FD node 42. At the end of the first integration period T1, the transfer gate 30 is pulsed to a first voltage level V1 of the transfer signal TX. The first voltage level V1 of the transfer signal TX is selected such that the barrier to the flow of charge carriers between the photodiode 20 and the FD node 42 is reduced. This means that a portion of the accumulated charge carriers are transferred to FD node 42. This is followed by a second integration period T2 and a third integration period T3, in which charge carriers continue to accumulate.

A portion of the accumulated charge carriers will be depleted to the pixel supply voltage. Depletion of the portion to the pixel supply voltage may be performed by applying a reset signal RST (and a coupling signal DCG, if applicable) such that FD node 42 is electrically connected to the pixel supply voltage VDD.

Block 352: a first portion of the charge carriers accumulated by the photodiode 20 are transferred to the FD node 42. At the end of the second integration period T2, the transfer gate 30 is again pulsed to the first voltage level V1 of the transfer signal TX. This means that a first portion of the accumulated charge carriers is transferred to FD node 42. The first portion of the charge carriers corresponds to charge carriers accumulated in the second integration period T2. The charge carriers at FD node 42 generate a capacitance voltage at input 62 of amplifier 60.

Block 353: in the storage period T _FS In the first stage FS1 of (a) a first portion of charge carriers is stored on the first capacitor 70 and the second capacitor 80: the first switching transistor 90 and the second switching transistor 100 are set to an on state for transferring a first portion of charge carriers from the FD node 42 to the second capacitor 80. This may mean that an amplified capacitance voltage is applied to the first capacitor 70 and the second capacitor 80. The second switching signal S2 may have a short pulse for equalizing the voltages at the first capacitor 70 and the second capacitor 80. This may mean that the signal is redistributed over the first capacitor 70 and the second capacitor 80. The amplified capacitor voltage corresponds to a Low Conversion Gain (LCG) signal.

Block 354: in the readout period T _r0 In the first stage of (a) the second capacitor 80 is read out: the output voltage tapped at the second capacitor 80 is amplified by a further amplifier 110. In the sense period T at the select transistor 120 _r0 With the first sense phase set to an on state, the amplified output voltage is provided to the column line 130 for digitizing. A first digitized value is generated as a function of a first value of the output voltage, for example by an evaluation circuit. Said first value of the output voltage corresponds to the LCG signal.

Block 355: the remaining charge carriers are transferred to FD node 42: at the end of the third integration period T3, the transfer gate 30 is pulsed to the second voltage level V2 of the transfer signal TX. This means that the remaining portion of the accumulated charge carriers are transferred to FD node 42. Thus, the transfer gate 30 is pulsed to different voltage levels V1, V2, thereby modifying the potential barrier.

By pulsing to the second voltage level, the potential barrier between the photodiode 20 and the FD node 42 is minimized or removed. The first voltage level V1 of the transfer signal results in a higher potential barrier than the second voltage level V2. In an example, V1< V2.

Block 356: in the storage period T _FS In the second stage FS2 of (2), the residual charge to be accumulated by the photodiode 20The carriers are stored on the first capacitor 70. This may mean that the capacitance voltage VC tapped at the FD node 42 is amplified by the amplifier 60. The amplified capacitance voltage is supplied to the first capacitor 70 by supplying the pulse of the first switching signal S1 to the first switching transistor 90. The amplified capacitor voltage corresponds to a High Conversion Gain (HCG) signal.

Block 357: in the readout period T _r0 In the second stage RO2 of (2), the first capacitor 70 is read out: after the output voltage at the second capacitor 80 is sensed in block 354 in the first sensing stage RO1, the second switching transistor 100 is set to an on state. Thus, the voltages at the first capacitor 70 and the second capacitor 80 are equalized. Since the capacitance voltage is still amplified by the amplifier 60, the output voltage at the second capacitor 80 is equal to the amplified capacitance voltage. The output voltage is amplified by a further amplifier 110. When the select transistor 120 is set to the on state in the second sensing phase RO2 of the sensing phase RO, the amplified output voltage is provided to the column line 130 for digitizing. A second digitized value is generated by the evaluation circuit as a function of the second value of the output voltage. The second value of the output voltage corresponds to the HCG signal.

Generally, the steps of blocks 352, 353, 355, 356 are at frame storage period T _FS Is executed in the middle. In the readout period T _r0 Steps of blocks 354, 357 are performed.

Block 358: the voltage of the second capacitor 80 or the digitized value of the voltage of the second capacitor 80 is subtracted from the voltage of the first capacitor 70 or the digitized value of the voltage of the first capacitor 70: the output signal representing the illuminance IL of the photodiode 20 is a function of the first digitized value (generated by block 353) and the second digitized value (generated by block 357). In an example, the first digitized value (generated by block 353) is subtracted from the second digitized value (generated by block 357) by an evaluation circuit. By this operation, the HCG signal can be accessed with Correlated Double Sampling (CDS) because the first (digitized) value and the second (digitized) value are based on a common noise level consisting of thermal noise and reset noise, in particular. This means that the LCG signal can be used as a reference level for the HCG signal. Since HCG signals are used in low light conditions, thermal noise is a relevant parameter. Therefore, thermal noise and reset noise can be effectively suppressed by CDS. Under high light conditions, the LCG signal is further processed. Here, the thermal noise is less correlated because photon shot noise dominates.

Block 359: increasing the LCG signal. This may mean that the LCG signal is adjusted. In particular, the LCG signal may be amplified. Adjusting or amplifying the LCG signal may be performed by an evaluation circuit. This step may occur particularly if the pixel device 10 includes a dual conversion transistor 140 and a third capacitor 150. In this case, the LCG signal may be sampled with a lower gain to increase dynamic range. To correct the gain adjustment, the LCG signal is increased in block 359. However, if the pixel apparatus 10 does not include the dual conversion gain process, this step may be omitted. Furthermore, the LCG signal may be accessed using double incremental sampling (DDS). LCG signals are used in high illumination situations where thermal noise is less correlated because photon shot noise dominates. Thus, correlated double sampling to remove noise from the video signal is not required. However, it may be desirable to remove Fixed Pattern Noise (FPN) from the video signal. By performing double upsampling (DDS), the FPN can be removed from the LCG signal. The DDS may be performed by subtracting a reset level from the LCG signal, wherein a readout period T after the second readout phase may be _r0 The reset level is read out in the third stage of (a).

Block 360: per pixel inflection point calibration: the HCG signal contains a first calibration level required in post-processing to remove FPN caused by variations in the transfer transistors affecting the threshold voltage. Since the same first voltage level V1 applied for barrier modulation after the first integration period T1 is also applied during readout, the HCG signal includes inflection point calibration values required for the linearization period and the FPN correction period. The inflection point calibration is performed separately for each pixel. Block 360 is optional.

Block 361: linearization. The linearized pixel output signal, i.e. the pixel output signal linearly dependent on the illumination level, can be reconstructed. Reconstructing the pixel output signal may depend on the light conditions:

in low light conditions, pulsing to the first voltage level V1 does not affect the photodiode charge. Reconstruction can be achieved by reading the HCG signal with CDS.

In high light conditions, both pulses to the first voltage level V1 affect the photodiode charge. For reconstruction, the LCD signal is used with DDS. For linearization, multiply it by exposure ratio T ₀ T1, wherein T0 represents the total exposure time.

In the mid-light case, only the second pulsing to the first voltage level V1 affects the photodiode charge. For reconstruction, the HCG signal (with CDS) and the LCG signal (with DDS) are summed in the digital domain.

The pulsed voltage level V1 used for barrier modulation of transfer transistor 30 may optionally be used to reconstruct the pixel output signal.

Fig. 9 illustrates exemplary characteristics of the pixel device 10, such as that shown in fig. 2A and operating according to the methods of fig. 7 and 8. The response signal SIG in artificial units is shown as a function of the illuminance I in artificial units. The signal SIG1 (dotted line) is a signal generated by the first integration period T1. It saturates for higher exposure levels because pulsing transfer gate 30 to first voltage level V1 results in depletion of excess charge carriers to pixel supply voltage VDD.

The signal SIG2 (dotted line) is a signal generated from the second integration period T2. The slope of the signal SIG2 is not steeper than the slope of the signal SIG1 because the integration period T2 may be shorter than the integration period T1. Alternatively or additionally, the slope of signal SIG2 is less steep than the slope of signal SIG1, because both signals are obtained at different conversion gains. For example, the signal SIG1 is obtained at a high conversion gain (up to the inflection point). For example, the signal SIG2 is obtained at a low conversion gain. Thus, the slope depends on, for example, the value of the capacitance 40 and the capacitance value of the third capacitor 150. The slope difference depends on the gain ratio. In case the size of the photodiode 20 is too small, the signal SIG2 may saturate for very high illumination levels.

The output signal SIG3 (solid line) is a signal obtained by combining the signal SIG1 and the signal SIG 2. Further, the output signal SIG3 may be a function of the signal SIG1, the signal SIG2, and a reset signal (not shown). By combining the signals SIG1 and SIG2, the dynamic range of the pixel apparatus 10 can be increased. The exact saturation level of the signal SIG1 may be determined from the HCG signal because the HCG signal corresponds to the remaining charge carriers after pulsing to the first voltage level V1.

Fig. 10 shows another exemplary timing diagram performed by the pixel apparatus 10 shown in fig. 2A, for example. The timing according to fig. 10 differs from the timing according to fig. 7 in that the exposure period is defined differently. Specifically, the exposure period T _ex Is not in association with a storage period T _FS Overlapping. As shown in fig. 7, the exposure may be stopped after the second integration period T2. This may mean that the exposure comprises or consists of a first integration period T1 and a second integration period T2. At the end of the second integration period T2 a reset pulse RST is applied to remove any redundant charge carriers from the diffusion node 42, especially the portion of accumulated charge carriers transferred during V1 pulsing.

In this embodiment, the method for operating the pixel device 10 includes: in exposure period T _ex During which charge carriers are accumulated with the photodiode 20 in a first integration period T1, the transfer gate 30 is pulsed to a first voltage level V1 at the end of the first integration period T1 to transfer a portion of the accumulated charge carriers to the capacitor 40, wherein the portion is configured to be depleted to the supply voltage VDD, and charge carriers continue to be accumulated with the photodiode 20 in a second integration period T2. In the storage period T _FS During the period:

the transfer gate 30 is pulsed to a first voltage level V1 for transferring a first portion of the accumulated charge carriers to the capacitance 40, a low sensitivity signal representing the first portion of the accumulated charge carriers is stored on a pair of capacitors 70, 80 electrically coupled to the capacitance 40, the transfer gate 30 is pulsed to a second voltage level V2 for transferring the remaining portion of the accumulated charge carriers to the capacitance 40, and a high sensitivity signal representing the remaining portion of the accumulated charge carriers is stored on a first capacitor 70 of the pair of capacitors 70, 80. In the readout period T _r0 During the period: read out and store in electricityLow sensitivity signals and high sensitivity signals on the containers 70, 80.

For further details, refer to the description of fig. 7. The features disclosed in connection with fig. 7 can also be applied to the embodiment according to fig. 10.

In order to familiarize the reader with novel aspects of the concept, embodiments of the pixel device 10 and methods of operating such a pixel device 10 disclosed herein have been discussed. While the preferred embodiments have been shown and described, many changes, modifications, equivalents and substitutions of the disclosed concepts may be made by those skilled in the art without departing unnecessarily from the scope of the claims.

It is to be understood that the present disclosure is not limited to the embodiments disclosed and the details specifically shown and described above. Rather, the features recited in the individual dependent claims or in the description may be advantageously combined. Further, the scope of the present disclosure includes those changes and modifications that will be apparent to those skilled in the art and that fall within the scope of the appended claims.

Within the scope of the claims or the specification, the term "comprising" does not exclude other elements or steps of the corresponding features or processes. Where the terms "a" or "an" are used in conjunction with a feature, they do not exclude a plurality of such features. Furthermore, any reference signs in the claims shall not be construed as limiting the scope.

Reference numerals

10. Pixel device

20. Photodiode having a high-k-value transistor

30. Transfer gate

40. Capacitance device

42. Terminal node of capacitor

44. Additional terminal node of capacitor

50. Reset gate

60. Amplifier

62. Input terminal of amplifier

64. Output terminal of amplifier

70. First capacitor

72. Terminal node of first capacitor

74. Additional terminal node of first capacitor

80. Second capacitor

82. Terminal node of second capacitor

84. Additional terminal node of second capacitor

90. First switch

100. Second switch

110. Additional amplifier

112. Input terminal of further amplifier

114. Output terminal of additional amplifier

120. Select gate

130. Column bus

140. Sensitivity grid

150. Third capacitor

152. Terminal node of third capacitor

154. Additional terminal node of third capacitor

160. Pre-charged grid

200. Image sensor

300. Optoelectronic device

350-361 frame

998. Noise floor

999. Saturation region

DR dynamic range

FS1, FS2 storage phase

I illuminance

PC precharge signal

Q charge

RST reset signal

S1, S2 switch signal

SIG1-SIG3 signals

SEL select signal

time points t1-t8

T1, T2, T3 integration period

T _ex Pixel exposure, exposure period

T _FS Storage period

T _ro Pixel readout, readout period

T _rst Reset period

TX, TX1, TX2 transfer signals

V1, V2 voltage level

VSS negative pixel supply voltage, GND

VDD pixel supply voltage

Claims (20)

1. A pixel arrangement (10) configured to convert electromagnetic radiation in a high sensitivity mode and a low sensitivity mode, respectively, the pixel arrangement (10) comprising:

at least one photodiode (20) configured to convert electromagnetic radiation into a corresponding charge signal,

a transfer gate (30) between the photodiode (20) and a capacitance (40) for transferring the respective charge signal to the capacitance (40),

a reset gate (50) electrically coupled to the capacitor (40) for resetting the capacitor (40),

an amplifier (60) electrically connected to the capacitor (40) and configured to generate a respective amplified signal based on the respective charge signal and the sensitivity pattern, the respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively, wherein the low sensitivity signal and the high sensitivity signal are based on a common noise level,

A first capacitor (70) configured to store the high sensitivity signal,

a second capacitor (80) configured to store the low sensitivity signal,

-a first switch (90) between the output terminal (64) of the amplifier (60) and the first capacitor (70), and

-a second switch (100) between the output terminal (64) of the amplifier (60) and the second capacitor (80).

2. Pixel device (10) according to the preceding claim, wherein the high sensitivity signal comprises the low sensitivity signal and an additional video signal.

3. A pixel device (10) according to any one of the preceding claims, further comprising:

-at least one further amplifier (110) comprising an input terminal (112) electrically connected to the first capacitor (70) and/or the second capacitor (80) and configured to generate a pixel output signal at an output terminal (114) of the further amplifier (110), and

-a select gate (120) between the output terminal (114) of the further amplifier (110) and a column bus (130) for transferring the pixel output signal to the column bus (130).

4. A pixel device (10) according to any one of the preceding claims, wherein the at least one photodiode (20) comprises a first photodiode (20) for generating a first charge signal in the high sensitivity mode and a second photodiode (20') for generating a second charge signal in the low sensitivity mode.

5. A pixel device (10) according to any one of the preceding claims, further comprising a sensitivity gate (140) between the reset gate (50) and the capacitance (40), the sensitivity gate (140) being for shorting a terminal node (42) of the capacitance (40) with a terminal node (152) of a third capacitance (150).

6. A pixel device (10) according to any one of the preceding claims, wherein the first capacitor (70) and the second capacitor (80) are arranged in parallel or in cascade.

7. An image sensor (200) comprising an array of pixels of the pixel arrangement (10) according to any of the preceding claims.

8. A method for operating a pixel arrangement (10), the pixel arrangement (10) being configured to convert electromagnetic radiation in a high sensitivity mode and a low sensitivity mode, respectively, the method comprising:

converting electromagnetic radiation into a corresponding charge signal by means of at least one photodiode (20),

providing a Reset Signal (RST) for resetting the capacitance (40),

providing a transfer signal (TX) for transferring the respective charge signal from the at least one photodiode (20) to the capacitance (40),

generating a respective amplified signal based on the respective charge signal and the sensitivity pattern, the respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively, wherein the low sensitivity signal and the high sensitivity signal are based on a common noise level,

-providing a first switching signal (S1) for transferring the respective amplified signal to a first capacitor (70), the first capacitor (70) being configured to store the high sensitivity signal, and

-providing a second switching signal (S2) for transferring the respective amplified signal to a second capacitor (80), the second capacitor (80) being configured to store the low sensitivity signal.

9. Method according to the preceding claim, wherein the pixel exposure (T _ex ) In a first step of the period, the pixel arrangement (10) is operated in the low sensitivity mode such that the low sensitivity signal is generated and stored on the second capacitor (80), and wherein, in a pixel exposure (T _ex ) In a second step of the period, the pixel arrangement (10) is operated in the high sensitivity mode such that the high sensitivity signal is generated and stored in the first capacitor (70) And wherein, after pixel exposure (T _ex ) The first and second steps of the period are performed without resetting the capacitor (40) therebetween.

10. The method of any of claims 8 to 9, wherein converting electromagnetic radiation into a corresponding charge signal comprises: a first charge signal is generated by the first photodiode (20) in the high sensitivity mode and a second charge signal is generated by the second photodiode (20') in the low sensitivity mode.

11. The method according to any one of claims 8 to 9, wherein converting electromagnetic radiation into a corresponding charge signal comprises in the low sensitivity mode with a reduced exposure time (T ₁ ) Generating a first charge signal and in the high sensitivity mode with an increased exposure time (T ₂ ) A second charge signal is generated.

12. A method for operating a pixel device (10), the method comprising:

accumulating charge carriers with the photodiode (20) in a first integration period (T1),

at the end of the first integration period (T1), pulsing the transfer gate (30) to a first voltage level (V1) to transfer a portion of accumulated charge carriers to the capacitor (40), wherein the portion is configured to be depleted to a supply Voltage (VDD),

continuing to accumulate charge carriers with the photodiode (20) in a second integration period (T2),

-pulsing the transfer gate (30) to the first voltage level (V1) at the end of the second integration period (T2) to transfer a first portion of accumulated charge carriers to the capacitance (40), and storing a low sensitivity signal representative of the first portion of accumulated charge carriers on at least a second capacitor (80) of a pair of capacitors (70, 80) electrically coupled to the capacitance (40),

Continuing to accumulate charge carriers with the photodiode (20) in a third integration period (T3),

-pulsing the transfer gate (30) to a second voltage level (V2) at the end of the third integration period (T3) to transfer the remaining portion of accumulated charge carriers to the capacitance (40), and storing a high sensitivity signal representative of the remaining portion of accumulated charge carriers on a first capacitor (70) of the pair of capacitors (70, 80), and

-during a readout period (T _ro ) During this time, the low sensitivity signal and the high sensitivity signal stored on the capacitors (70, 80) are read out.

13. The method of claim 12, wherein the high sensitivity signal is indicative of a calibration level based on the remaining portion of accumulated charge carriers, and wherein the method further comprises: the pixel output signal is adjusted based on the low sensitivity signal and the high sensitivity signal depending on the pixel specific knee value determined based on the calibration level.

14. The method according to any one of claims 12 to 13, wherein the first integration period (T1) is longer than the second integration period (T2).

15. The method according to any one of claims 12 to 14, wherein the second voltage level (V2) is greater than the first voltage level (V1).

16. A method according to any one of claims 8 to 15, wherein the pixel read-out (T _ro ) In a first step of the period, the low sensitivity signal is read out, and wherein, in the reading out (T _ro ) In a second step of the period, the high sensitivity signal is read out, and wherein, in a pixel readout (T _ro ) In the third step of the period, the capacitor (40) is reset and the reset level is read out.

17. The method according to the preceding claim, further comprising: double delta sampling is performed by using the reset level as a reference level for the low sensitivity signal.

18. The method of any of claims 8 to 17, further comprising: correlated double sampling is performed by using the low sensitivity signal as a reference level for the high sensitivity signal.

19. The method of any of claims 8 to 18, further comprising: whether to use the low sensitivity signal or the high sensitivity signal for further processing is determined based on the respective amplitude level.

20. The method of any of claims 8 to 19, further comprising: the conversion gain is adjusted by applying a gain signal for shorting the terminal node (42) of the capacitor (40) to the terminal node (152) of the third capacitor (150).