CN117811547A - External clock detection circuit, clock synchronization circuit and power management chip - Google Patents
External clock detection circuit, clock synchronization circuit and power management chip Download PDFInfo
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Abstract
The application provides an external clock detection circuit, a clock synchronization circuit and a power management chip, wherein the external clock detection circuit comprises a voltage detection module, an inverter, a clock detection module and a logic module; the voltage detection module outputs a first detection signal according to the input signal and the bias current; the inverter inverts the first detection signal to generate a second detection signal; the clock detection module generates a clock detection signal according to the first detection signal and the second detection signal, when the clock detection signal is at a high level, the input signal is a clock signal, and when the clock detection signal is at a low level, the input signal is a voltage signal; the logic module generates an external clock signal according to the clock detection signal and the second detection signal. The external clock detection circuit can accurately identify the input signals and control the output of the external clock detection circuit according to different input signals so as to avoid the problem of false triggering.
Description
Technical Field
The present application relates to the field of electronic circuit technology, and more particularly, to an external clock detection circuit, a clock synchronization circuit, and a power management chip.
Background
An internal clock signal is generally provided in a circuit to control a switching frequency or other devices in the circuit according to the internal clock signal, however, the internal clock signal has a certain jitter, and an external clock signal is generally provided in order to ensure control reliability of controlling the switching frequency or other devices in the circuit.
In the related art, a logic circuit is generally used to generate an external clock signal, however, the logic circuit has a complex structure, and the logic circuit cannot accurately identify an input signal, which may cause a false triggering problem.
Disclosure of Invention
For solving the above-mentioned problem, the application provides an external clock detection circuit, clock synchronization circuit and power management chip, and the external clock detection circuit that this application provided can carry out accurate discernment to the input signal to according to the output of different input signal control external clock detection circuit, with the problem of avoiding the false triggering. And the structure is simple, and the manufacturing cost is lower.
In a first aspect, the present application provides an external clock detection circuit, including a voltage detection module, an inverter, a clock detection module, and a logic module; the voltage detection module is used for outputting a first detection signal according to the input signal and the bias current; wherein the input signal comprises a voltage signal or a clock signal; the input end of the inverter is connected with the output end of the voltage detection module and is used for generating a second detection signal by inverting the first detection signal; the first input end of the clock detection module is connected with the output end of the voltage detection module and the input end of the inverter, the second input end of the clock detection module is connected with the output end of the inverter, the clock detection module is used for generating a clock detection signal according to the first detection signal and the second detection signal, when the clock detection signal is at a high level, the input signal is a clock signal, the clock detection signal is at a low level, and the input signal is a voltage signal; and the logic module is used for generating an external clock signal according to the clock detection signal and the second detection signal.
The external clock detection circuit provided by the embodiment of the application can accurately detect the input signal, so that when the input signal is a clock signal, the corresponding external clock signal is externally output through the logic module, when the input signal is a voltage signal, the external clock signal is not externally output, and therefore the problem of false triggering is avoided, and the reliability of the external clock detection circuit in outputting the external clock signal is ensured. And the external clock detection circuit has simple structure and lower manufacturing cost.
In one possible design, the voltage detection module includes: the first resistor, the first capacitor, the second resistor and the first switch tube; the first end of the first resistor is used for accessing a voltage signal; the first polar plate is connected with the second end of the first resistor; the first end of the second resistor is connected with the second pole plate of the first capacitor, and the second end of the second resistor is used for being grounded; the controlled end of the first switch tube is connected with the second polar plate of the first capacitor and the first end of the second resistor, the first end of the first switch tube is connected with the input end of the inverter, and the second end of the first switch tube is used for being grounded; when the input signal is a clock signal, the first switch tube is conducted, the output of the first end of the first switch tube is pulled down, and the first detection signal is in a low level; when the input signal is a voltage signal, the first switch tube is turned off, and the first detection signal is at a high level.
In one possible design, the voltage detection module further includes: and one end of the protection unit is connected with the second polar plate of the first capacitor and the first end of the second resistor, and the other end of the protection unit is connected with the controlled end of the first switch tube.
In one possible design, the clock detection module includes a second capacitor, a first current source, a second switching tube and a third switching tube; the first polar plate is used for grounding; one end of the first current source is connected with the power supply voltage; a second current source, one end of which is grounded; the controlled end of the second switch tube is connected with the output end of the inverter and is used for accessing a second detection signal, the first end of the second switch tube is connected with the other end of the first current source, and the second end of the second switch tube is connected with the second plate of the second capacitor; the controlled end of the third switching tube is connected with the output end of the voltage detection module and the input end of the inverter and is used for accessing a first detection signal, the first end of the third switching tube is connected with the other end of the second current source, and the second end of the third switching tube is connected with the second end of the second switching tube and the second plate of the second capacitor; when the input signal is a clock signal, the first detection signal is low level, the third switch tube is turned off, the second detection signal is high level, the second switch tube is turned on to charge the second capacitor, the clock detection signal is high level, and the external clock detection circuit outputs an external clock signal; when the input signal is a voltage signal, the first detection signal is high level, the third switch tube is conducted, the second detection signal is low level, the second switch tube is turned off, the second capacitor discharges, the clock detection signal is low level, and the external clock detection circuit does not output an external clock signal.
In one possible design, the external clock detection circuit further includes a first mirror unit and a second mirror unit; the first mirror image unit is characterized in that a first input end is connected with a first enabling signal, a second input end is connected with a second enabling signal, a third input end is connected with a power supply voltage, and a first output end is used for grounding; the first input end of the second mirror image unit is connected with a first enabling signal, the second input end of the second mirror image unit is connected with the second output end of the first mirror image unit, the third input end of the second mirror image unit is used for being connected with a power supply voltage, and the output end of the third mirror image unit is connected with the second input end of the voltage detection module; the first enable signal is high level, and the second mirror unit outputs bias current when the second enable signal is low level.
In one possible embodiment, the first mirror unit comprises a third current source, a third resistor, a fourth switching tube, a first current mirror and a fifth switching tube; one end of the third current source is connected with the power supply voltage; the first end of the third resistor is connected with the other end of the third current source; the controlled end of the fourth switching tube is used for accessing a first enabling signal, and the first end of the fourth switching tube is connected with the second end of the third resistor; the first end of the first current mirror is connected with the first end of the fourth switching tube, the second end of the first current mirror is used for being grounded, the third end of the first current mirror is connected with the second end of the fourth switching tube, and the fourth end of the first current mirror is connected with the second input end of the second mirror image unit; and the controlled end of the fifth switching tube is used for accessing a second enabling signal, the first end of the fifth switching tube is connected with the third end of the first current mirror, and the second end of the fifth switching tube is grounded.
In one possible embodiment, the second mirror unit comprises a second current mirror and a sixth switching tube; the first end of the second current mirror is connected with the fourth end of the first current mirror, the second end of the second current mirror is used for being connected with power supply voltage, and the output end of the second current mirror is connected with the second input end of the voltage detection module; and the controlled end of the sixth switching tube is used for being connected with a first enabling signal, the first end of the sixth switching tube is used for being connected with a power supply voltage, and the second end of the sixth switching tube is connected with the third end of the second current mirror.
In one possible design manner, the external clock detection circuit further includes a seventh switching tube, the controlled end is used for accessing a second enabling signal, the first end is connected with the output end of the clock detection module, and the second end is used for being grounded; when the input signal is a clock signal, the second enabling signal is low level, the seventh switching tube is turned off, the clock detection signal is high level, and the external clock detection circuit outputs an external clock signal; when the input signal is a voltage signal, the second enabling signal is high level, the seventh switch tube is conducted, the clock detection signal is low level, and the external clock detection circuit does not output an external clock signal.
In one possible design, the logic module includes: a NAND gate and a driving unit; the first input end of the NAND gate is connected with the output end of the clock detection module and used for being connected with a clock detection signal, and the second input end of the NAND gate is connected with the output end of the inverter and used for being connected with a second detection signal; and the input end of the driving unit is connected with the output end of the NAND gate, and the output end is used for outputting an external clock signal.
In a second aspect, the present application provides a clock synchronization circuit, including an external clock detection circuit, an internal clock generation circuit, and a clock selection circuit as described in any of the optional manners of the first aspect; the external clock detection circuit is used for outputting an external clock signal; an internal clock generation circuit for outputting an internal clock signal; the clock selection circuit is connected with the external clock detection circuit at a first input end and the internal clock generation circuit at a second input end; when the input signal is a clock signal and the external clock signal and the internal clock signal are in phase synchronization, the clock selection circuit is used for outputting the external clock signal, and when the input signal is a voltage signal, the clock selection circuit is also used for outputting the internal clock signal.
Drawings
Fig. 1 is a schematic diagram of a module structure of an external clock detection circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a circuit structure of an external clock detection circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram II of a circuit structure of an external clock detection circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram III of a circuit structure of an external clock detection circuit according to an embodiment of the present application;
Fig. 5 is a schematic diagram of a circuit structure of an external clock detection circuit according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram II of a module structure of an external clock detection circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a circuit structure of an external clock detection circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a circuit structure of an external clock detection circuit according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram seven of a circuit structure of an external clock detection circuit according to an embodiment of the present application.
Wherein, each reference sign in the figure:
1. an external clock detection circuit; 11. a voltage detection module; 111. a protection unit; 12. a clock detection module; 13. a logic module; 131. a driving unit; 14. a first shaping module; 15. a second shaping module; 16. a first mirror unit; 161. a first current mirror; 17. a second mirror unit; 171. a second current mirror; 2. an internal clock generating circuit; 3. a clock selection circuit;
INV, inverter; bias, bias current; VIN, input signal; r1, a first resistor; r2, a second resistor; r3, a third resistor; c1, a first capacitor; c2, a second capacitor; c3, a third capacitor; q1, a first switching tube; q2, a second switching tube; q3, a third switching tube; q4, a fourth switching tube; q5, a fifth switching tube; q6, a sixth switching tube; q7, a seventh switching tube; D. a diode; i1, a first current source; i2, a second current source; i3, a third current source; NAND and NAND gates; EN1, a first enable signal; EN2, a second enable signal; VDD, supply voltage; q, a switching tube; EN, enable pin.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, and circuits are omitted so as not to obscure the description of the present application with unnecessary detail.
Currently, internal and external clock signals are typically provided in a circuit to control the switching frequency or other devices in the circuit. However, there is some jitter in the internal clock signal, resulting in an inability to accurately control the switching frequency or other devices. For this reason, a logic circuit that can generate an external clock signal to output the external clock signal to control a switching frequency or other devices in the circuit when the internal clock signal is dithered is proposed in the related art. However, the logic circuit has a complex structure, and the logic circuit cannot accurately recognize the input signal, which may cause a false triggering problem. Here, it should be noted that, when the input signal to which the logic circuit is connected is not a clock signal, but is a voltage signal, the logic circuit may also output an external clock signal, so that there is a problem of false triggering, and the external clock signal at this time is abnormal and cannot be synchronized with the internal clock signal, so that the normal use of the circuit may be affected due to the abnormality of the switching frequency or other devices controlled by the external clock signal.
Therefore, the embodiment of the application provides an external clock detection circuit, a clock synchronization circuit and a power management chip, wherein the external clock detection circuit can accurately identify input signals and control the output of the external clock detection circuit according to different input signals so as to avoid the problem of false triggering. And the structure is simple, and the manufacturing cost is lower.
The external clock detection circuit, the clock synchronization circuit and the power management chip provided in the present application are exemplarily described below with reference to the accompanying drawings.
As shown in fig. 1, the embodiment of the application provides an external clock detection circuit 1, which comprises a voltage detection module 11, an inverter INV, a clock detection module 12 and a logic module 13, wherein the output end of the voltage detection module 11 is connected with the input end of the inverter INV, the output end of the inverter INV is connected with the second input end of the clock detection module 12, the first input end of the clock detection module 12 is connected with the output end of the voltage detection module 11 and the input end of the inverter INV, the output end of the clock detection module 12 is connected with the first input end of the logic module 13, and the second input end of the logic module 13 is connected with the output end of the inverter INV.
The first input end of the voltage detection module 11 is used for accessing the input signal VIN, the second input end of the voltage detection module 11 is used for accessing the Bias current Bias, and the voltage detection module 11 can output a first detection signal according to the input signal VIN and the Bias current Bias. Here, it should be noted that, at this time, the input signal VIN includes a voltage signal or a clock signal, the voltage detection module 11 may output different first detection signals to the inverter INV according to the different input signals VIN, the inverter INV may invert the first detection signals to generate second detection signals and output the second detection signals to the clock detection module 12, so that the clock detection module 12 may know whether the input signal VIN is a clock signal based on the second detection signals and the first detection signals, and generate corresponding clock detection signals and output the generated clock detection signals to the logic module 13. The logic module 13 may generate a corresponding external clock signal from the clock detection signal and the second detection signal.
Here, it should be noted that the external clock signal output by the logic module 13 is the same as the frequency of the input signal VIN input by the voltage detection module 11.
When the clock detection signal is at a high level, it represents that the input signal VIN is a clock signal at this time, and when the clock detection signal is at a low level, it represents that the input signal VIN is a voltage signal at this time. Specifically, when the input signal VIN detected by the voltage detection module 11 is a clock signal, the output first detection signal may be at a low level, the output second detection signal corresponding to the inverter INV is at a high level, the first detection signal received by the clock detection module 12 is at a low level, the second detection signal is at a high level, based on the two control signals, the clock detection module 12 can learn that the input signal VIN accessed by the external clock detection circuit 1 at this time is a clock signal, the clock detection signal corresponding to the output of the clock detection module 12 is at a high level, and the logic module 13 can output the external clock signal after receiving the clock detection signal at the high level.
When the input signal VIN detected by the voltage detection module 11 is a voltage signal, the output first detection signal may be at a high level, and the second detection signal corresponding to the inverter INV is at a low level, at this time, the first detection signal received by the clock detection module 12 is at a high level, and the second detection signal is at a low level, based on the two control signals, the clock detection module 12 may learn that the input signal VIN accessed by the external clock detection circuit 1 is at the voltage signal, which indicates that no clock signal is input, so that the clock detection signal corresponding to the clock detection module 12 is at a low level, and the logic module 13 does not output the external clock signal after receiving the clock detection signal at the low level, i.e., at this time, the output of the logic module 13 may be a low level signal.
Here, it is understood that the clock detection signal is a signal obtained from the first detection signal and the second detection signal.
In order to avoid the problem that the external clock detection circuit 1 causes false triggering to the external output signal when the input signal VIN is a voltage signal, the first input end of the logic module 13 is connected to the output end of the clock detection module 12, and the second input end of the logic module 13 is connected to the output end of the inverter INV, that is, the logic module 13 may generate the external clock signal according to the clock detection signal and the second detection signal. When the input signal VIN is a clock signal, the first detection signal output by the voltage detection module 11 is at a low level, the second detection signal output by the inverter INV is at a high level, and the clock detection signal output by the clock detection module 12 is at a high level, at this time, the logic module 13 outputs an external clock signal after receiving both signals at the high level. When the input signal VIN is a voltage signal, the first detection signal output by the voltage detection module 11 is at a high level, the second detection signal output by the inverter INV is at a low level, and the clock detection signal output by the clock detection module 12 is at a low level, at this time, the logic module 13 does not output an external clock signal after receiving both signals at the low level, i.e. the output of the logic module 13 is 0.
Here, it can be understood that when the input signal VIN is a clock signal, the second detection signal at this time may be an external clock signal, and the clock detection signal at this time is at a high level, so that the logic module 13 may output the external clock signal. When the input signal VIN is a voltage signal, the second detection signal is a level signal, and in order to avoid the problem of false triggering caused by outputting the level signal, the clock detection signal is at a low level, so that the logic module 13 does not output the level signal. In this way, the logic module 13 can generate the external clock signal according to the clock detection signal and the second detection signal, so as to avoid the problem of false triggering, and ensure the reliability of the output signal of the external clock detection circuit 1.
Thus, the external clock detection circuit 1 provided in this embodiment of the present application may accurately detect the input signal VIN, so that when the input signal VIN is a clock signal, the logic module 13 outputs a corresponding external clock signal to the outside, so that when the input signal VIN is a voltage signal, the external clock signal is not output to the outside, thereby avoiding the problem of false triggering, and ensuring the reliability of the external clock detection circuit 1 in outputting the external clock signal. The external clock detection circuit 1 has a simple structure and low manufacturing cost.
When the input signal VIN is a voltage signal, the voltage detection module 11 provided herein may further implement low-voltage and high-voltage input, and in an example, as shown in fig. 2, the voltage detection module 11 may include a first resistor R1, a first capacitor C1, a second resistor R2, and a first switching tube Q1, where a first end of the first resistor R1 is used for accessing the input signal VIN, a second end of the first resistor R1 is connected to a first plate of the first capacitor C1, a controlled end of the first switching tube Q1 is connected to a second plate of the first capacitor C1 and a first end of the second resistor R2, a second end of the second resistor R2 is used for grounding, a first end of the first switching tube Q1 is connected to an input end of the inverter INV, and a second end of the first switching tube Q1 is used for grounding.
In this example, when the input signal VIN is a clock signal, the first switching tube Q1 is turned on, and at this time, the output of the first end of the first switching tube Q1 is pulled down, and the first detection signal output by the voltage detection module 11 is at a low level. When the input signal VIN is a voltage signal, the first switching tube Q1 is turned off, and the first detection signal output by the voltage detection module 11 is at a high level. The highest voltage input by the voltage detection module 11 may depend on the withstand voltage of the first capacitor C1, that is, different high voltage inputs may be satisfied by selecting the first capacitor C1 with different withstand voltages.
Alternatively, the first switching transistor Q1 may be an N-type metal-Oxide-Semiconductor (NMOS), PMOS, triode, or other device or circuit with a switching function, which is not particularly limited in this application.
In order to ensure the reliability of the first detection signal output by the voltage detection module 11, as shown in fig. 2, in one example, the voltage detection module 11 may further include a protection unit 111, where one end of the protection unit 111 is connected to the second electrode plate of the first capacitor C1 and the first end of the second resistor R2, and the other end of the protection unit 111 is connected to the controlled end of the first switching tube Q1.
Optionally, as shown in fig. 2, the protection unit 111 may include two diodes D connected in series, where an anode of one diode D and a cathode of the other diode D are connected to the second electrode plate of the first capacitor C1 and the first end of the second resistor R2, and other devices or circuits with protection function may be used for the protection unit 111.
In one example, as shown in fig. 3, the clock detection module 12 may include a second capacitor C2, a first current source I1, a second current source I2, a second switching tube Q2, and a third switching tube Q3, where a first polar plate of the second capacitor C2 is used for grounding, one end of the first current source I1 is connected to the power supply voltage VDD, one end of the second current source I2 is grounded, a controlled end of the second switching tube Q2 is connected to an output end of the inverter INV and is used for accessing a second detection signal, a first end of the second switching tube Q2 is connected to the other end of the first current source I1, and a second end of the second switching tube Q2 is connected to a second polar plate of the second capacitor C2. The controlled end of the third switching tube Q3 is connected with the output end of the voltage detection module 11 and the input end of the inverter INV, and is used for accessing a first detection signal, the first end of the third switching tube Q3 is connected with the other end of the second current source I2, and the second end of the third switching tube Q3 is connected with the second end of the second switching tube Q2 and the second plate of the second capacitor C2.
In this example, when the input signal VIN is a clock signal, the corresponding first detection signal is at a low level, the second detection signal is at a high level, the third switching tube Q3 is turned off, the second switching tube Q2 is turned on, at this time, the second capacitor C2 is charged, the clock detection module 12 detects that the clock signal is connected, and the output clock detection signal is at a high level, so that the logic module 13 may output an external clock signal based on the clock detection signal, that is, the output external clock signal may be at a high level at this time. When the input signal VIN is a voltage signal, the corresponding first detection signal is at a high level, the second detection signal is at a low level, the third switching tube Q3 is turned on, the second switching tube Q2 is turned off, at this time, the second capacitor C2 discharges, the clock detection module 12 detects that no clock signal is connected, and the output clock detection signal is at a low level, so that the external clock detection circuit 1 does not output an external clock signal, that is, the output signal at this time may be at a low level.
In this way, the second detection signal and the first detection signal are respectively connected to the second switching tube Q2 and the third switching tube Q3, so as to control the charge and discharge of the second capacitor C2 based on different signals, thereby detecting whether a clock signal is connected, and outputting a corresponding clock detection signal according to the detection result, so that the logic module 13 can output an external clock signal based on the clock detection signal. The clock detection module 12 has a simple structure and high detection accuracy, and avoids the problem that when the input signal VIN accessed by the external clock detection circuit 1 is not a clock signal but a voltage signal, the external clock detection circuit 1 can also output an external clock signal externally, thereby causing false triggering.
In order to ensure the stability of the first detection signal output by the voltage detection module 11 and the clock detection signal output by the clock detection module 12, in one example, as shown in fig. 4, the external clock detection circuit 1 may further include a first shaping module 14 and a second shaping module 15, where an input end of the first shaping module 14 is connected to an output end of the voltage detection module 11 to shape and output the first detection signal, and an input end of the second shaping module 15 is connected to an output end of the clock detection module 12 to shape and output the clock detection signal.
Alternatively, the first shaping module 14 and the second shaping module 15 may be schmitt triggers, or may be other devices or circuits with shaping effects, which are not limited in this application.
In one example, as shown in fig. 5, the logic module 13 may include: the first input end of the NAND gate NAND is connected to the output end of the clock detection module 12, and when the external clock detection circuit 1 is provided with the second shaping module 15, the first input end of the NAND gate NAND is connected to the output end of the second shaping module 15, and is used for accessing the shaped clock detection signal, and the second input end of the NAND gate NAND is connected to the output end of the inverter INV, and is used for accessing the second detection signal. For example, when the input signal VIN is a clock signal, the second detection signal connected to the NAND gate NAND outputs an external clock signal when the clock detection signal is at a high level, and when the input signal VIN is at a low level, the second detection signal connected to the NAND gate NAND does not output an external clock signal, that is, the output of the NAND gate NAND is 0, so as to avoid the problem of false triggering caused by the NAND gate NAND outputting a signal when the input signal VIN is at a level.
In order to improve the driving capability of the output external clock signal, in one example, as shown in fig. 5, the logic module 13 may further include a driving unit 131, an input terminal of the driving unit 131 is connected to an output terminal of the NAND gate NAND, and an output terminal of the driving unit 131 is used to output the external clock signal with improved driving capability.
Alternatively, as shown in fig. 5, the driving unit 131 may include a plurality of inverters INV connected in series, or may include other devices or circuits with improved driving capability, which is not particularly limited in this application.
The Bias current Bias in the present application may be provided by an external circuit or may be provided by the external clock detection circuit 1 in the present application, and in one example, as shown in fig. 6, the external clock detection circuit 1 may further include: the first mirror unit 16 and the second mirror unit 17, the first input terminal of the first mirror unit 16 is connected to the first enable signal EN1, the second input terminal of the first mirror unit 16 is connected to the second enable signal EN2, the third input terminal of the first mirror unit 16 is connected to the power supply voltage VDD, and the first output terminal of the first mirror unit 16 is grounded. The first input end of the second mirror unit 17 is connected to the first enable signal EN1, the second input end of the second mirror unit 17 is connected to the second output end of the first mirror unit 16, the third input end of the second mirror unit 17 is used to access the power supply voltage VDD, and the output end of the second mirror unit 17 is connected to the second input end of the voltage detection module 12.
In this example, whether the first and second mirror units 16 and 17 generate the Bias current Bias may be controlled by controlling the first and second enable signals EN1 and EN 2. For example, when the first enable signal EN1 is at a high level and the second enable signal EN2 is at a low level, the first and second mirroring units 16 and 17 are turned on to mirror currents, so that the second mirroring unit 17 may output the bias current Bais to provide the bias current Bais to the voltage detecting module 11, so that the voltage detecting module 11 may operate.
As shown in fig. 7, the first mirror unit 16 may include a third current source I3, a third resistor R3, a fourth switching tube Q4, a first current mirror 161, and a fifth switching tube Q5, where one end of the third current source I3 is connected to the power supply voltage VDD, a first end of the third resistor R3 is connected to the other end of the third current source I3, a controlled end of the fourth switching tube Q4 is connected to the first enable signal EN1, a first end of the fourth switching tube Q4 is connected to the second end of the third resistor R3, a first end of the first current mirror 161 is connected to the first end of the fourth switching tube Q4, a second end of the first current mirror 161 is connected to the ground, a third end of the first current mirror 161 is connected to the second end of the fourth switching tube Q4, a fourth end of the first current mirror 161 is connected to the second input end of the second mirror 17, a controlled end of the fifth switching tube Q5 is connected to the second enable signal EN1, and a first end of the fifth switching tube Q5 is connected to the fourth end of the fourth switching tube Q5.
In this example, when the Bias current Bias needs to be supplied from the external clock detection circuit 1, the first enable signal EN1 is controlled to be high level, and the second enable signal EN2 is controlled to be low level, so that the first current mirror 161 can mirror the current to the second mirror unit 17, so that the second mirror unit 17 can output the Bias current Bias to the voltage detection module 11. When the external clock detection circuit 1 is not required to supply the Bias current Bias, the first enable signal EN1 is controlled to be low and the second enable signal EN2 is controlled to be high.
Alternatively, the first current mirror 161 may be formed by a plurality of switching transistors Q connected in a common gate, or may be formed by other devices or circuits having a mirror function, which is not particularly limited in this application.
As shown in fig. 7, the second mirroring unit 17 may include a second current mirror 171 and a sixth switching tube Q6, wherein a first end of the second current mirror 171 is connected to a fourth end of the first current mirror 171, a second end of the second current mirror 171 is connected to the power supply voltage VDD, an output end of the second current mirror 171 is connected to a second input end of the voltage detection module 11 (i.e., a first end of the first switching tube Q1 shown in fig. 7), a controlled end of the sixth switching tube Q6 is connected to the first enable signal EN1, a first end of the sixth switching tube Q6 is connected to the power supply voltage VDD, and a second end of the sixth switching tube Q6 is connected to a third end of the second current mirror 171.
In this example, the first enable signal EN1 connected to the controlled terminal of the sixth switching tube Q6 and the first enable signal EN1 connected to the controlled terminal of the fourth switching tube Q4 are the same enable signal, so when the Bias current Bias needs to be provided by the external clock detection circuit 1, by controlling the first enable signal EN1 to be at a high level and the second enable signal EN2 to be at a low level, the first current mirror 161 can mirror the current to the second current mirror 171, so that the second current mirror 171 can output the Bias current Bias to the voltage detection module 11. When the external clock detection circuit 1 is not required to supply the Bias current Bias, the first enable signal EN1 is controlled to be low and the second enable signal EN2 is controlled to be high. Simple structure and simple operation.
Alternatively, the second current mirror 171 may be formed by a plurality of switching transistors Q connected in common, or may be formed by other devices or circuits having a mirror function, which is not particularly limited in this application.
When the external clock detection circuit 1 is not required to output an external clock signal, in an example, as shown in fig. 8, the external clock detection circuit 1 may further include a seventh switching tube Q7, a controlled end of the seventh switching tube Q7 is used for accessing the second enable signal EN2, a first end of the seventh switching tube Q7 is connected to an output end of the clock detection module 13, and a second end of the seventh switching tube Q7 is used for grounding. Here, it may be understood that the second enable signal EN2 connected to the controlled terminal of the seventh switching tube Q7 and the second enable signal EN2 connected to the fifth switching tube Q5 are the same enable signal, so when the external clock detection circuit 1 is not required to output the external clock signal, the second enable signal EN2 may be controlled to be at a high level, and the seventh switching tube Q7 is turned on, and the clock detection signal is at a low level, so that the external clock detection circuit 1 does not output the external clock signal, or the external clock signal output by the external clock detection circuit 1 may be understood to be at a low level. When the second enable signal EN2 is at a high level, the fifth switch tube Q5 is turned on, and the first mirror unit 16 will stop working, so that no additional control signal is needed, the second enable signal EN2 can control the first mirror unit 16 not to mirror, and meanwhile, the external clock detection circuit 1 is controlled not to output an external clock signal, no additional control signal is needed to control different switch tubes, and the control cost is simplified.
In this example, specifically, when the external clock detection circuit 1 is required to output an external clock signal and the input signal VIN is a clock signal, the second enable signal EN2 is controlled to be at a low level, so that the seventh switching tube Q7 is turned off, and at this time, the clock detection signal is at a high level, and the external clock detection circuit 1 outputs the external clock signal. When the external clock detection circuit 1 is required to output an external clock signal and the input signal VIN is a voltage signal, the second enable signal EN2 is kept at a high level, the seventh switching tube Q7 is turned on, so that the clock detection signal is at a low level, the external clock detection circuit 1 does not output the external clock signal, and the second enable signal EN2 is controlled to be at a low level until the input signal VIN is a clock signal, so as to output the external clock signal, thereby avoiding the problem of false triggering. When the external clock signal is not required to be output by the external clock detection circuit 1, the second enable signal EN2 is controlled to be kept at a high level, and thus, a detailed description thereof will be omitted.
In summary, the external clock detection circuit 1 provided in the embodiment of the present application can accurately detect the input signal VIN, when the input signal VIN is a clock signal, the corresponding external clock signal is externally output, and when the input signal VIN is a voltage signal, the external clock signal is not externally output, so as to avoid the problem of false triggering. Meanwhile, when the input signal VIN is a voltage signal, the voltage detection module 11 can also realize the input of high-voltage and low-voltage signals, and the external clock detection circuit 1 has a simple structure and low manufacturing cost.
As shown in fig. 9, the embodiment of the present application further provides a clock synchronization circuit, which includes the external clock detection circuit 1, the internal clock generation circuit 2, and the clock selection circuit 3 described in any of the foregoing optional manners, where the external clock detection circuit 1 outputs an external clock signal when detecting that the input signal VIN is a clock signal, and the internal clock generation circuit is configured to generate an internal clock signal. A first input terminal of the clock selection circuit 3 is connected to the external clock detection circuit 1, and a second input terminal of the clock selection circuit 3 is connected to the internal clock generation circuit 2. When the input signal VIN is a clock signal and the external clock signal and the internal clock signal are phase-synchronized, the clock selection circuit 3 outputs the external clock signal, and when the input signal VIN is a voltage signal, the clock selection circuit 3 outputs the internal clock signal.
The power management chip provided in the embodiment of the present application has the external clock detection circuit 1 of the above embodiment, and thus has all the advantages of the external clock detection circuit 1. The external clock detection circuit 1 is described in detail above, and thus will not be described here again.
The embodiment of the application also provides a power management chip, which comprises the clock synchronization circuit in any optional mode, and the power management chip provided by the embodiment of the application has the clock synchronization circuit in the embodiment, so that the power management chip has all the beneficial effects of the clock synchronization circuit. And thus are not described in detail herein.
Here, it should be noted that, the enable pin EN of the power management chip in the present application may be multiplexed with the enable pin EN of the external clock detection circuit 1, so that no additional input pin is required, and the manufacturing cost is reduced.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. An external clock detection circuit, characterized by being applied to a clock synchronization circuit, comprising:
the voltage detection module is used for outputting a first detection signal according to the input signal and the bias current; wherein the input signal comprises a voltage signal or a clock signal;
the input end of the inverter is connected with the output end of the voltage detection module and is used for generating a second detection signal by inverting the first detection signal;
The first input end of the clock detection module is connected with the output end of the voltage detection module and the input end of the inverter, the second input end of the clock detection module is connected with the output end of the inverter, the clock detection module is used for generating a clock detection signal according to the first detection signal and the second detection signal, when the clock detection signal is in a high level, the input signal is the clock signal, and when the clock detection signal is in a low level, the input signal is the voltage signal; the method comprises the steps of,
the logic module is used for generating an external clock signal according to the clock detection signal and the second detection signal, and the frequency of the external clock signal is the same as that of the input signal.
2. The external clock detection circuit of claim 1, wherein the voltage detection module comprises:
the first end of the first resistor is used for accessing the input signal;
the first polar plate is connected with the second end of the first resistor;
the first end of the second resistor is connected with the second pole plate of the first capacitor, and the second end of the second resistor is used for being grounded; the method comprises the steps of,
The controlled end of the first switch tube is connected with the second polar plate of the first capacitor and the first end of the second resistor, the first end of the first switch tube is connected with the input end of the inverter, and the second end of the first switch tube is used for being grounded;
when the input signal is the clock signal, the first switching tube is conducted, the output of the first end of the first switching tube is pulled down, and the first detection signal is in a low level; when the input signal is the voltage signal, the first switch tube is turned off, and the first detection signal is at a high level.
3. The external clock detection circuit of claim 2, wherein the voltage detection module further comprises:
and one end of the protection unit is connected with the second polar plate of the first capacitor and the first end of the second resistor, and the other end of the protection unit is connected with the controlled end of the first switch tube.
4. The external clock detection circuit of claim 1, wherein the clock detection module comprises:
the first polar plate is used for grounding;
one end of the first current source is connected with the power supply voltage;
a second current source, one end of which is grounded;
the controlled end of the second switch tube is connected with the output end of the inverter and is used for accessing the second detection signal, the first end of the second switch tube is connected with the other end of the first current source, and the second end of the second switch tube is connected with the second plate of the second capacitor; the method comprises the steps of,
The controlled end of the third switching tube is connected with the output end of the voltage detection module and the input end of the inverter and is used for accessing the first detection signal, the first end of the third switching tube is connected with the other end of the second current source, and the second end of the third switching tube is connected with the second end of the second switching tube and the second plate of the second capacitor;
when the input signal is the clock signal, the first detection signal is low level, the third switch tube is turned off, the second detection signal is high level, the second switch tube is turned on to charge the second capacitor, the clock detection signal is high level, and the external clock detection circuit outputs the external clock signal; when the input signal is the voltage signal, the first detection signal is at a high level, the third switching tube is turned on, the second detection signal is at a low level, the second switching tube is turned off, the second capacitor discharges, the clock detection signal is at a low level, and the external clock detection circuit does not output the external clock signal.
5. The external clock detection circuit of any one of claims 1-4, wherein the external clock detection circuit further comprises:
The first mirror image unit is characterized in that a first input end is connected with a first enabling signal, a second input end is connected with a second enabling signal, a third input end is connected with the power supply voltage, and a first output end is used for being grounded; the method comprises the steps of,
the first input end of the second mirror image unit is connected with the first enabling signal, the second input end of the second mirror image unit is connected with the second output end of the first mirror image unit, the third input end of the second mirror image unit is used for being connected with the power supply voltage, and the output end of the third mirror image unit is connected with the second input end of the voltage detection module;
and when the first enabling signal is in a high level and the second enabling signal is in a low level, the second mirror unit outputs the bias current.
6. The external clock detection circuit of claim 5, wherein the first mirroring unit comprises:
one end of the third current source is connected with the power supply voltage;
the first end of the third resistor is connected with the other end of the third current source;
the controlled end of the fourth switching tube is used for being connected with the first enabling signal, and the first end of the fourth switching tube is connected with the second end of the third resistor;
the first end of the first current mirror is connected with the first end of the fourth switching tube, the second end of the first current mirror is used for being grounded, the third end of the first current mirror is connected with the second end of the fourth switching tube, and the fourth end of the first current mirror is connected with the second input end of the second mirror unit; the method comprises the steps of,
And the controlled end of the fifth switch tube is used for being connected with the second enabling signal, the first end of the fifth switch tube is connected with the third end of the first current mirror, and the second end of the fifth switch tube is grounded.
7. The external clock detection circuit of claim 6, wherein the second mirroring unit comprises:
the first end of the second current mirror is connected with the fourth end of the first current mirror, the second end of the second current mirror is used for being connected with the power supply voltage, and the output end of the second current mirror is connected with the second input end of the voltage detection module; the method comprises the steps of,
and the controlled end of the sixth switching tube is used for being connected with the first enabling signal, the first end of the sixth switching tube is used for being connected with the power supply voltage, and the second end of the sixth switching tube is connected with the third end of the second current mirror.
8. The external clock detection circuit of claim 7, wherein the external clock detection circuit further comprises:
the controlled end of the seventh switching tube is used for accessing the second enabling signal, the first end of the seventh switching tube is connected with the output end of the clock detection module, and the second end of the seventh switching tube is used for being grounded;
when the input signal is the clock signal, the second enabling signal is low level, the seventh switching tube is turned off, the clock detection signal is high level, and the external clock detection circuit outputs the external clock signal; when the input signal is the voltage signal, the second enabling signal is high level, the seventh switching tube is conducted, the clock detection signal is low level, and the external clock detection circuit does not output the external clock signal.
9. The external clock detection circuit of claim 8, wherein the logic module comprises:
the first input end of the NAND gate is connected with the output end of the clock detection module and used for accessing the clock detection signal, and the second input end of the NAND gate is connected with the output end of the inverter and used for accessing the second detection signal; the method comprises the steps of,
and the input end of the driving unit is connected with the output end of the NAND gate, and the output end is used for outputting the external clock signal.
10. A clock synchronization circuit, comprising:
the external clock detection circuit according to any one of claims 1 to 9, for outputting the external clock signal;
an internal clock generation circuit for outputting an internal clock signal; the method comprises the steps of,
the first input end of the clock selection circuit is connected with the external clock detection circuit, and the second input end of the clock selection circuit is connected with the internal clock generation circuit; the clock selection circuit is used for outputting the external clock signal when the input signal is the clock signal and the external clock signal and the internal clock signal are in phase synchronization, and is also used for outputting the internal clock signal when the input signal is the voltage signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311868614.7A CN117811547A (en) | 2023-12-29 | 2023-12-29 | External clock detection circuit, clock synchronization circuit and power management chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311868614.7A CN117811547A (en) | 2023-12-29 | 2023-12-29 | External clock detection circuit, clock synchronization circuit and power management chip |
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| CN117811547A true CN117811547A (en) | 2024-04-02 |
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| CN202311868614.7A Pending CN117811547A (en) | 2023-12-29 | 2023-12-29 | External clock detection circuit, clock synchronization circuit and power management chip |
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