CN117810232A - Avalanche diode sensor based on address distribution mechanism control - Google Patents

Abstract

The invention provides an avalanche diode sensor based on address distribution mechanism control, which comprises a two-dimensional array of SPAD pixels prepared on a sensor chip, wherein the two-dimensional array of SPAD pixels comprises: SPAD pixels arranged on the sensor chip; the AFE centralized placement area is used for intensively placing a plurality of SPAD pixel control detection circuits; the sensor chip is characterized by further comprising a plurality of address selectors arranged on the sensor chip, wherein the address selectors are arranged corresponding to one or more rows of the two-dimensional array of SPAD pixels and are configured to select a plurality of addresses from n addresses in a total set of addresses as an address packet, and the addresses in the address packet are distributed to the AFE centralized placement area through more than one address line; and the AFE centralized placement area controls corresponding multiple rows of pixels based on multiple address lines. The invention can effectively utilize the area of the non-photosensitive area to carry out wiring while realizing the control of a plurality of rows of pixels by adding an address distribution mechanism, and can reduce the wiring in a multiplexing mode and the like.

Description

Avalanche diode sensor based on address distribution mechanism control

Technical Field

The invention relates to the technical field of semiconductors, in particular to an avalanche diode sensor based on address distribution mechanism control.

Background

Avalanche diodes include APDs and SPADs. Where APD is an abbreviation for avalanche photodiode (Avalanche Photodiode), SPAD is an acronym for single photon avalanche diode (Single Photon Avalanche Diode). The basic working principle is that an APD or SPAD is reversely biased above an avalanche voltage Vbd, so that the avalanche phenomenon occurs. By this phenomenon, rapid amplification of the optical signal is achieved.

In operation, SPAD corresponds to a reverse biased PN junction. The reverse bias voltage is of a magnitude such that an overload voltage Vex is superimposed on the avalanche voltage Vbd. This PN junction then operates in Geiger mode. Figure 1 shows 3 states of SPAD operation. The initial state 1 is an OFF state of SPAD after the bias voltage is applied. When this state is triggered (Trigger) avalanche breakdown occurs, and SPAD then enters the high current ON state 2. When SPAD is operated in geiger mode, the optical gain is infinite. The infinite gain is caused by a collision ionization phenomenon (impact ionization) within the semiconductor. The large current generated by this phenomenon is called breakdown, but since a large number of electrons do not destroy the crystal structure, there is no damage to the device. Finally, this large current will lower the bias voltage of SPAD, bringing SPAD to state 3.

Fig. 2 shows an example of a circuit included in the AFE of SPAD. After avalanche occurs, the charge across the diode decreases with avalanche current. SPAD is brought to state 3, which is an annealing process. After the annealing is finished, the SPAD needs to be added with the overvoltage Vex again, and the process is a reset process. Typically, a reset circuit is required to connect Vex and SPAD. And this reset circuit may have an active reset circuit and a passive reset circuit. For the reset circuit, the annealing function needs to be considered in design. Annealing circuitry is sometimes added according to design requirements. Fig. 2 (a) and (b) show two different connections of SPAD, respectively, signal can be either connected from the negative electrode (Cathode) or from the positive electrode (Anode).

The avalanche diode requires a large reverse bias voltage during operation, and an isolation region is required between the control circuit and the avalanche diode, which reduces the photosensitive area ratio of the sensor chip. Meanwhile, in the traditional image sensor, the pixel output is an analog signal, and the pixel and the control circuit cannot be far away in order to avoid interference. The SPAD outputs digital signals, which are not limited by the SPAD, so that the SPAD control circuit can be arranged in a centralized way. Therefore, in order to increase the photosensitive area occupation ratio of the chip as much as possible, the control circuits can be intensively arranged so as to reduce the occupied area of the control circuits and the isolation areas.

However, the following problems still exist in centralized placement of control circuits:

because the control circuits are arranged in a centralized way, the control circuits in one area need to control a plurality of rows of pixels, and therefore, a plurality of address lines need to be configured, so that the manufacturing difficulty and the cost are increased, the area of the pixels of the chip is limited, and the photosensitive area occupation ratio of the chip is improved.

Disclosure of Invention

The invention solves the technical problem of providing an avalanche diode sensor based on address distribution mechanism control, and by adding the address distribution mechanism, each row distributes an address packet containing a plurality of address lines so as to realize the purpose of controlling a plurality of rows of pixels. The method is realized by the following technical scheme:

an avalanche diode sensor based on address distribution mechanism control, comprising a two-dimensional array of SPAD pixels prepared on a sensor chip, the two-dimensional array of SPAD pixels comprising:

SPAD pixels arranged on the sensor chip;

the AFE centralized placement area is used for intensively placing a plurality of SPAD pixel control detection circuits;

the sensor chip is characterized by further comprising a plurality of address selectors arranged on the sensor chip, wherein the address selectors are arranged corresponding to one or more rows of the two-dimensional array of SPAD pixels and are configured to select a plurality of addresses from n addresses in a total set of addresses as an address packet, and the addresses in the address packet are distributed to the AFE centralized placement area through more than one address line;

and the AFE centralized placement area controls corresponding multiple rows of pixels based on multiple address lines.

In some embodiments, the address packet is configured corresponding to each row of the two-dimensional array of SPAD pixels, and the address packet of at least one row or all rows distributes the address to more than two rows of AFE centralized placement areas through the address lines.

In some embodiments, address packets of at least one row or all rows distribute addresses to AFE centrally located areas in the row or adjacent rows via address lines configured for the row.

In some embodiments, the pels controlled by each AFE set placement region include a plurality of pels located in discrete rows.

In some embodiments, control circuitry configured in the AFE centralized placement area receives addresses distributed by two or more address packets over address lines.

In some embodiments, control circuitry in the same AFE centralized placement area receives addresses distributed by two adjacent address packets over address lines.

In some embodiments, the sensor chip further includes a level conversion unit disposed on the sensor chip, and coupled between the address selector and the corresponding address line, for performing level conversion in different power domains.

In some embodiments, the address selector is implemented based on a metal wire; and selecting a designated address from the address total set to form an address packet, and connecting the address packet to a corresponding address line through the metal connection line.

In some embodiments, the address selector is implemented based on a number of multiplexers having inputs coupled to a total set of addresses and outputs coupled to respective address lines.

In some embodiments, the two-dimensional array of SPAD pixels is prepared based on an FSI process, and address lines in the address packet are configured in a non-photosensitive region of SPAD pixels.

In some embodiments, the two-dimensional array of SPAD pixels is prepared based on BSI technology, and address lines in the address packet are configured at any position of the corresponding SPAD pixels.

The beneficial technical effects of the invention are as follows:

for the avalanche diode sensor of the centralized placement control circuit, an address distribution mechanism is added, so that one address packet is distributed to each row in the two-dimensional array of SPAD pixels, the area of a non-photosensitive area can be effectively utilized for wiring while the control of a plurality of rows of pixels is realized, and the wiring can be reduced in a multiplexing mode and the like, thereby reducing the area of a chip and improving the occupation ratio of the photosensitive area.

Drawings

Fig. 1 is a schematic diagram of SPAD operation modes and three state transitions.

FIG. 2 is a schematic diagram of circuitry and two different connections involved in the AFE of the prior art SPAD.

Fig. 3 is a schematic diagram of a conventional arrangement of SPADs and corresponding control detection circuits (AFEs) on a sensor chip.

Fig. 4 is a schematic diagram of a conventional sensor chip uplink arrangement.

Fig. 5 is a schematic diagram showing several exemplary examples of centralized placement of SPAD-corresponding control detection circuits (AFEs) in an embodiment of the present invention.

FIG. 6 is a schematic diagram showing a hybrid placement of SPAD and AFE based on two placement modes in an embodiment of the invention.

FIG. 7 is a schematic diagram showing the arrangement of SPAD and AFE on a sensor chip based on a centralized placement pattern in an embodiment of the present invention.

FIG. 8 is a schematic diagram showing the arrangement of SPAD and AFE on a sensor chip based on a centralized mixed placement mode in an embodiment of the present invention.

FIG. 9 is a schematic diagram of conventional routing in the SPAD and AFE based centralized placement mode in an illustrative embodiment of the invention.

Fig. 10 is a schematic diagram of a sensor chip array configured with an address selector in an embodiment of the invention.

FIG. 11 is a schematic diagram of an address selector in an embodiment of the invention.

Fig. 12 is a schematic diagram showing an example of one cycle wiring in the illustrated embodiment of the present invention.

Fig. 13 is a schematic diagram showing an example of an address packet generated by the address selector in the embodiment of the present invention.

Fig. 14 is a schematic diagram showing an example in which the address selector is configured with a level shift module in the embodiment of the present invention.

Fig. 15 is a schematic diagram showing a specific example of an address selector in the embodiment of the present invention.

Fig. 16 is another specific example schematic diagram of an address selector in the illustrated embodiment of the present invention.

FIG. 17 is a schematic diagram of an address trace based on FSI process in an illustrative embodiment of the present invention.

Fig. 18 is a schematic diagram of address routing based on BSI process in an embodiment of the present invention.

Fig. 19 is a schematic view showing an application example of the avalanche diode sensor of the present invention.

Fig. 20 is a schematic diagram of another application example of the avalanche diode sensor of the present invention.

Detailed Description

For a further understanding of the present invention, preferred embodiments of the invention are described below in conjunction with the examples, but it should be understood that these descriptions are merely intended to illustrate further features and advantages of the invention, and are not limiting of the claims of the invention.

In one or more embodiments described below, a positive bias indicates that the bias voltage is positive or higher relative to the power ground (of the chip), and a negative bias indicates that the bias voltage is negative or lower relative to the power ground (of the chip).

As described in the background section above, for FSI and BSI but non-pel level connected processes, the control circuitry (AFE) needs to be on the same chip as the SPAD pels. Because of the high reverse voltage required for SPAD pixels, an isolation region is required between the AFE and SPAD, as shown in fig. 3. The isolation region has less influence on the Fill factor (the area occupied by the SPAD pixel region reaches the sum of the area of the SPAD pixel and the control circuit) when the pixel area is large (say, 50um,30 um). But when the area of the picture element is small, say 15um,10um or even smaller, this has a large influence on the Fill factor. Resulting in waste of chip area.

As shown in fig. 4, for the conventional sensor, because the AFEs are independently placed, a control mode of one row and one line is generally adopted, so that control of each row of the array can be realized.

Because the control circuit of the avalanche diode at least comprises a reset circuit and a signal detection circuit, in the traditional sensor, the circuits occupy a large area of a chip, the chip cost is increased, and complex functions are difficult to integrate. In order to solve the above problem, the area occupied by the isolation area between the pixel and the control circuit can be reduced by the method of respectively carrying out centralized layout on the control circuit and the SPAD pixel, thereby reducing the chip area and improving the Fill factor. Fig. 5 illustrates several ways in which the picture elements are centrally placed:

in the example of the arrangement mode shown in fig. 5 (a), the array comprises a pixel group formed by arranging 6 SPAD pixels 10 in sequence along the longitudinal direction, and an AFE centralized arrangement area 20 corresponding to the pixel group, which comprises a control detection circuit arrangement area 20a and an isolation area 20b arranged around the control detection circuit arrangement area. The control detection circuits of all the pixels in the pixel group are arranged in the AFE centralized placement area 20a in a centralized manner. In this example, the pixel group and the AFE centralized placement area 20 together form a strip area, so that the SPAD and the AFE occupy only one column of area on the whole, and are convenient to repeatedly place in an array manner on the whole chip, thereby forming a SPAD pixel two-dimensional array with a higher filling coefficient.

The placement examples shown in fig. 5 (b) and fig. 5 (c) are similar to those in fig. 5 (a), except that the AFE centralized placement area corresponding to the pixel group in fig. 5 (b) is configured between two parts of pixels, and 6 SPAD pixels in the pixel group in fig. 5 (c) are placed in two rows, and the AFE centralized placement area and the isolation area corresponding to the pixel group are configured at the bottom of the pixel area, so that a relatively regular rectangular area is integrally formed.

In the examples shown in fig. 5 (d) and 5 (e), SPAD pixels in a pixel group are placed separately from AFE concentrated placement of the corresponding pixel group. Wherein, in fig. 5 (d), 6 SPAD pixels are divided into two groups to be placed separately, and the AFE centralized placement area is positioned at the bottom of the lower pixel group; in fig. 5 (e), 3 SPAD pixels are placed separately from the corresponding AFE set placement. By adopting the two placing modes, the placing mode of the pixel group is more flexible, and the pixel group is convenient to be combined and placed on the whole chip to form an array.

In the above example, 6 or 3 pixels share the AFE concentrated placement area in one AFE concentrated placement area. This can significantly reduce the area of the isolation region. If the area of each AFE centralized placement area is equal to the area of one SPAD pixel, the overall filling coefficient can reach 6/7. According to the conservation estimation, if the AFE of 2 SPAD pixels is put in an AFE centralized placement area which is equal to the area of the SPAD pixels, at least 2/3 of the Fill factor can be achieved.

Further, referring to fig. 6, the two placement modes shown in fig. 6 (a) and fig. 6 (b) are combined together to form two pixel groups which are integrally located on a column and are staggered and arranged and corresponding AFE centralized placement areas as shown in fig. 6 (c). Wherein, the first part of pixels 101 of the first pixel group are sequentially placed along the longitudinal direction, then the first AFE centralized placement area 111 corresponding to the first pixel group is placed, then the first part of pixels 103 of the second pixel group, the second part of pixels 102 of the first pixel group, the second AFE centralized placement area 112 corresponding to the second pixel group, and the second part of pixels 104 of the second pixel group are sequentially placed along the longitudinal direction. The arrangement mode increases the degree of freedom of circuit layout design and is beneficial to the design of pixel scanning control. The distance between the SPAD pixel and the AFE region can be reduced by placing the SPAD pixel at two ends of the AFE region than at one side, so that the uniformity of the performance of the SPAD pixel is better.

In the example shown in fig. 7, the AFE concentrated placement areas 20 are arranged periodically and dispersedly, wherein the dispersion means that the space period of the AFE unit is larger than the interval between the centers of two adjacent SPAD pixels 10. The regular layout of the period makes the preparation convenient, and the distributed AFE unit arrangement avoids the generation of a large-area detection blind area in the detection array due to the excessive aggregation of the AFE units.

As an improvement, in the example shown in fig. 8, the array contains two or more SPAD-AFE centralized placement modes, so that the flexibility of increasing the control of the array circuit is further increased. It should be noted that SPADs and AFEs identified by different patterns in the drawings are only used for distinguishing the placement and connection relationships, and are not substantially different.

As shown in fig. 9, for the sensor with the centralized control circuit in the above example, if a conventional control mode of one address line in one row is used, in order to control multiple rows of pixels, a longitudinal wiring on the detection array is required, which increases the complexity of wiring. Moreover, for FSI processes, address traces, if running in the photosensitive area of the pixel, can affect the performance of the pixel. The area of the pixel non-photosensitive area is very limited, and only a small amount of wiring can be supported.

Based on the background, the invention provides an avalanche diode sensor based on address distribution mechanism control, which realizes the control of a plurality of rows of pixels on a sensor chip in a wiring mode which is as concise as possible under the condition of intensively placing a control circuit and SPAD pixels.

The following is a further detailed description of the present invention by way of specific examples.

In one or more embodiments described below, a two-dimensional array of SPAD pixels is fabricated based on a BSI process of FSI or non-pixel level interconnects.

Example 1

As shown in fig. 10, an example of an avalanche diode sensor controlled based on an address distribution mechanism in the present invention is shown, which includes a two-dimensional array of SPAD pixels fabricated on a sensor chip, the two-dimensional array of SPAD pixels including a pixel arrangement region formed by at least two SPAD pixels arranged in succession; and the AFE centralized placing area is used for intensively placing the plurality of SPAD pixel control detection circuits and comprises a control detection circuit placing area and an isolation area which is arranged around the control detection circuit placing area.

Specifically, in the two-dimensional array of SPAD pixels shown in fig. 10, the two-dimensional array of SPAD pixels includes a plurality of AFE centralized placement areas 21 of upwardly adjacent pixels, a plurality of AFE centralized placement areas 22 of downwardly adjacent pixels, a plurality of SPAD pixels 11 controlled by the AFE centralized placement areas 22 of downwardly adjacent pixels, and a plurality of SPAD pixels 12 controlled by the AFE centralized placement areas 22 of upwardly adjacent pixels; and a plurality of top AFE concentrated placement areas 23 and a plurality of bottom AFE concentrated placement areas 24 of downward adjacent pixels and upward adjacent pixels at the edge portions, a plurality of SPAD pixels 13 controlled by the top AFE concentrated placement areas 23, and a plurality of SPAD pixels 14 controlled by the bottom AFE concentrated placement areas 24. The downward adjacent and the upward adjacent refer to the corresponding relation between the control circuits arranged in the AFE centralized placement area and the corresponding SPAD pixels, namely, the corresponding SPAD pixels are controlled by the control circuits arranged in the AFE centralized placement area. The squares marked by the same pattern in the figure represent the same type of AFE centralized placement area or SPAD pixels.

Meanwhile, in order to solve the wiring problem in the centralized placement mode, the sensor of the invention further comprises an address selector arranged on the sensor chip, wherein the address selector is arranged corresponding to one or more rows of the two-dimensional array of SPAD pixels (in the embodiment, corresponding to each row), is configured to select a plurality of addresses from n addresses in the total set of addresses as an address packet, and distributes the addresses in the address packet to the AFE centralized placement area through more than one address line;

and the AFE centralized placement area controls corresponding multiple rows of pixels based on multiple address lines.

Referring to fig. 11, the address selector is configured to select m addresses from n addresses of the total set of addresses, and distribute the m addresses as one address packet to each row.

In this embodiment, the purpose of controlling a plurality of rows of pixels can be achieved by adding an address selector to each row in the array, and selecting m addresses from n addresses in the total set of addresses as an address packet to be distributed to each row.

It should be noted that, the AFE centralized placement areas 20 shown in fig. 10 and other subsequent drawings include a control detection circuit placement area and an isolation area disposed around the control detection circuit placement area, which are only for clarity and brevity of illustration, and are not clearly distinguished in the drawings; the actual arrangement may be seen with reference to fig. 5.

Example 2

The present embodiment shows an example of one cycle wiring of the avalanche diode sensor controlled based on the address distribution mechanism on the basis of the above-described embodiment 1.

Referring to FIG. 12, in this example, the two-dimensional array of SPAD pixels includes 15 rows (Top AFE, row <1> -Row <14 >) of Top AFE, and the address selector also generates 15 address packets (Row_EN shown on the left side of the figure) by corresponding selection. Wherein, the first address packet row_en <1,2,3> corresponds to three address lines 1,2,3 on the Top Row (Top AFE), the second address packet row_en <5,6> corresponds to two address lines 5,6 on the first Row (Row <1 >), and the third address packet row_en <6,7> corresponds to two address lines 6,7 on the second Row (Row <2 >); and so on; the last address packet row_en <8,9,15,16> corresponds to the upper 8,9,15,16 address lines of the fourteenth Row (Row <14 >). Correspondingly, the row where the SPAD pixels controlled by the AFE centralized placement area of each row are located is shown on the right side of the figure. For example, the SPAD pixels controlled by the downward adjacent top AFE are located in rows 1,2,3 (Row <1,2,3 >), the SPAD pixels controlled by the upward adjacent pixel AFE located in the fourth Row are located in rows 1,2,3,8,9,10 (Row <1,2,3,8,9,10 >), and the SPAD pixels controlled by the downward adjacent pixel AFE located in Row 9 are located in rows 3,4,5,10,11,12 (Row <3,4,5,10,11,12 >); the rest of the rows are so analogized that no further description is given.

Example 3

The present embodiment further shows an example in which the address selector generates an address packet on the basis of embodiment 2 described above.

Referring to fig. 13, in this embodiment, three address selectors are included, each of which selects four addresses from 28 addresses (row_en <1:28 >) of the total set of addresses to form three address packets corresponding to a fourth Row (Row <4 >), a fifth Row (Row <5 >) and a sixth Row (Row <6 >), and each of the three address packets is coupled to a corresponding AFE concentrated placement area (dark area in the figure) in each Row through four address lines corresponding to the fourth Row (Row <4 >), the fifth Row (Row <5 >) and the sixth Row (Row <6 >) of the pixel array. In the figure, each AFE centralized placement area can control 6 pixels corresponding to the AFE centralized placement area in the column, wherein the 6 pixels comprise three pixels adjacent to the AFE centralized placement area above and three pixels separately placed below. In order to realize that the AFE centralized placement area controls 6 pixels, 2 address lines are multiplexed from address lines corresponding to the next row of address packets and are connected to the AFE centralized placement area through longitudinal connection lines. (where the vertical lines are above the AFE centralized placement area or the pixel non-photosensitive area, for clarity of illustration and ease of illustration, the blank is shown in the figure with an arc arrow.)

By adopting the mode, the multiplexing of the address lines corresponding to each address packet can be realized, so that the wiring number of the address lines is effectively saved.

It should be noted that, for clarity, only a part of the AFE centralized placement area and the corresponding pixels controlled by the control circuit in the AFE centralized placement area related to the foregoing description are shown in fig. 13, and the pixels in the rest area or the AFE centralized placement area in the pixel array are omitted and not shown. The actual placement can be seen with reference to fig. 12.

Example 4

The present embodiment further shows an example in which the address selector includes a level conversion unit on the basis of embodiment 3 described above.

Referring to fig. 14, in the present embodiment, the address selector is further configured with a plurality of level conversion units coupled between the address selector and the corresponding address lines for performing level conversion in different power domains, such as converting signals of the VDDL power domain into signals of the VDDH power domain.

Example 5

This embodiment shows a specific implementation example of the address selector in the present invention.

Referring to fig. 15, in the present embodiment, the address selector is implemented based on a metal wiring; and selecting a designated address from the address total set to form an address packet, and connecting the address packet to a corresponding address line through a metal wire.

Example 6

This embodiment shows another specific implementation example of the address selector in the present invention.

Referring to fig. 16, in this embodiment, the address selector is implemented based on a plurality of multiplexers, and the multiplexers have input terminals coupled to the address aggregate and output terminals coupled to corresponding address lines. By applying a control signal to the multiplexer, the input signal is selectively output, and a specified address can be selected to constitute an address packet.

Example 7

The embodiment mainly shows a schematic diagram of address routing arrangement on a chip based on different processes in the invention.

As shown in fig. 17, for the FSI process, because the address trace is on the same side of the substrate as the picture element, the address trace may be routed to a non-photosensitive region of the picture element.

As shown in fig. 18, for BSI processes, the address traces may run anywhere on the picture elements because the address traces are on a different side of the substrate than the picture elements.

Example 8

As shown in fig. 19, the present exemplary embodiment is a schematic diagram of the present invention in which the avalanche diode control circuit is applied to a laser radar.

Example 9

As shown in fig. 20, the present exemplary embodiment is a schematic diagram of the present invention in which the avalanche diode control circuit is applied to an automobile radar.

The above description of the embodiments is only for aiding in the understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.

Claims (11)

1. An avalanche diode sensor based on address distribution mechanism control, which is characterized by comprising a two-dimensional array of SPAD pixels prepared on a sensor chip, wherein the two-dimensional array of SPAD pixels comprises:

SPAD pixels arranged on the sensor chip;

the AFE centralized placement area is used for intensively placing a plurality of SPAD pixel control detection circuits;

the sensor chip is characterized by further comprising a plurality of address selectors arranged on the sensor chip, wherein the address selectors are arranged corresponding to one or more rows of the two-dimensional array of SPAD pixels and are configured to select a plurality of addresses from n addresses in a total set of addresses as an address packet, and the addresses in the address packet are distributed to the AFE centralized placement area through more than one address line;

and the AFE centralized placement area controls corresponding multiple rows of pixels based on multiple address lines.

2. The avalanche diode sensor according to claim 1, wherein the address packets are configured for each row of the two-dimensional array of SPAD pixels, the address packets of at least one or all rows distributing addresses to more than two rows of AFE concentrated placement areas via address lines.

3. The avalanche diode sensor according to claim 2, wherein the address packets of at least one or all of the rows distribute addresses to the AFE concentrated placement areas in the row or adjacent rows via address lines configured for the row.

4. The avalanche diode sensor according to any one of claims 1-3, wherein the picture elements controlled by each AFE focus placement area comprise a plurality of picture elements located in discrete rows.

5. The avalanche diode sensor according to claim 1, wherein the control circuit arranged in the AFE hub placement area receives addresses distributed by two or more address packets via address lines.

6. The avalanche diode sensor according to claim 5, wherein the control circuit in the same AFE centralized placement area receives addresses distributed by two adjacent address packets via address lines.

7. The avalanche diode sensor according to claim 1, further comprising a level shifting unit disposed on the sensor chip, the level shifting unit being coupled between the address selector and a corresponding address line for level shifting in different power domains.

8. The avalanche diode sensor according to claim 1, wherein said address selector is implemented based on metal wiring; and selecting a designated address from the address total set to form an address packet, and connecting the address packet to a corresponding address line through the metal connection line.

9. The avalanche diode sensor according to claim 1, wherein said address selector is implemented based on a number of multiplexers having inputs coupled to a total set of addresses and outputs coupled to respective address lines.

10. The avalanche diode sensor according to claim 1, wherein the two-dimensional array of SPAD pixels is prepared based on FSI process, and the address lines in the address packet are arranged in the non-photosensitive area of SPAD pixels.

11. The avalanche diode sensor according to claim 1, wherein the two-dimensional array of SPAD pixels is prepared based on BSI technology, and the address lines in the address packet are arranged at any position of the corresponding SPAD pixels.