CN117806417A - Training circuit and training method suitable for write equalization - Google Patents

Abstract

The invention provides a training circuit and a training method suitable for write equalization, wherein in a picosecond training mode, a picosecond training circuit is used for controlling a master clock generating circuit to generate a first master clock signal to be aligned and controlling a write clock generating circuit to generate a first write clock signal to be aligned based on the current working frequency and a reference clock signal, and a control delay circuit is used for delaying the first write clock signal to be aligned until training is finished sequentially based on different delay gears; in the UI level training mode, based on the current working frequency and the reference clock signal, the master clock generating circuit is controlled to generate a second master clock signal to be aligned and the write clock generating circuit is controlled to generate a second clock signal to be aligned, the control delay circuit delays the second clock signal to be aligned based on different delay gears in sequence until training is finished, and the aligned CK signal and the aligned WCK signal can be obtained rapidly under different working frequencies, so that write balance training is realized.

Description

Training circuit and training method suitable for write equalization

Technical Field

The invention relates to the technical field of clock adjustment, in particular to a training circuit and a training method suitable for write equalization.

Background

In the LPDDR5 (Low Power Double Data Rate 5) specification, a new Clock signal named Write Clock (WCK) is introduced for timing control of Write operations, while the instruction set has one reference Clock, the master Clock CK (Clock), at the same time. The write clock signal WCK for writing data must be aligned with the master clock signal CK for subsequent read and write operations of the LPDDR5 memory, as specified by the LPDDR5 specification. Such alignment can ensure coordination and synchronization between the memory controller and the memory chip, thereby effectively improving stability and reliability of data transmission. Therefore, a training circuit and training method suitable for write equalization is needed to keep the write clock signal WCK aligned with the master clock signal CK.

Disclosure of Invention

The invention provides a training circuit and a training method suitable for write equalization, which are used for realizing the alignment of a write clock signal WCK and a master clock signal CK.

The invention provides a training circuit suitable for write equalization, comprising:

the system comprises a training control circuit, a picosecond training circuit, a master clock generation circuit, a write clock generation circuit and a delay circuit;

the training control circuit is used for controlling to enter a picosecond training mode when the current working frequency is smaller than a first preset frequency, and determining whether the picosecond training mode is ended or not based on a sampling signal returned by a data input/output loop of the storage device;

The picosecond training circuit is used for controlling the master clock generating circuit to generate a first to-be-aligned master clock signal and controlling the writing clock generating circuit to generate a first to-be-aligned writing clock signal based on the current working frequency and a reference clock signal in a picosecond training mode, controlling the delay circuit to delay the first to-be-aligned writing clock signal based on different delay gears in sequence to obtain a first delayed writing clock signal, and transmitting the first to-be-aligned master clock signal and the first delayed writing clock signal to a storage device until the training control circuit determines that the picosecond training mode is finished based on a sampling signal returned by a data input/output loop of the storage device.

According to the training circuit suitable for write equalization, when the current working frequency is smaller than the second preset frequency, the frequency of the first main clock signal to be aligned is the same as the frequency of the reference clock signal, and the first clock signal to be aligned is generated after a write clock control interface signal is set as WCK fast-toggle; when the current working frequency is greater than the second preset frequency and less than the first preset frequency, the frequency of the first to-be-aligned master clock signal is 1/2 of the frequency of the reference clock signal, and the first to-be-aligned write clock signal is generated after setting a write clock control interface signal as WCK toggle.

According to the training circuit suitable for write equalization provided by the invention, the training control circuit is specifically used for:

judging whether a sampling signal returned by a data input/output loop of the storage device contains 0 to 1 or 1 to 0 jump, and if the sampling signal contains 0 to 1 or 1 to 0 jump, determining that the picosecond training mode is ended.

According to the training circuit suitable for write equalization, the training circuit further comprises a UI-level training circuit;

the training control circuit is further used for controlling to enter a UI level training mode when the current working frequency is larger than the first preset frequency, and determining whether the UI level training mode is finished or not based on a sampling signal returned by a data input/output loop of the storage device;

the UI level training circuit is used for controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the writing clock generating circuit to generate a second writing clock signal to be aligned based on the current working frequency and a reference clock signal in a UI level training mode, controlling the delay circuit to delay the second writing clock signal to be aligned based on different delay gears in sequence to obtain a second delayed writing clock signal, and transmitting the second master clock signal to be aligned and the second delayed writing clock signal to the storage device until the training control circuit determines that the UI level training mode is finished based on sampling signals returned by a data input and output loop of the storage device; wherein the frequency of the second master clock signal to be aligned is less than the frequency of the reference clock signal.

According to the training circuit suitable for write equalization provided by the invention, the UI-level training circuit is specifically used for:

a signal generation step: setting a value of a phase difference counter based on a current preset phase difference, and controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the write clock generating circuit to generate a second write clock signal to be aligned based on a current working frequency, a reference clock signal and the phase difference counter; the phase difference between the second write clock signal to be aligned and the second master clock signal to be aligned is equal to the current preset phase difference;

an iteration delay step: the delay circuit is controlled to delay the second clock signal to be aligned based on different delay gears in sequence to obtain a second delay write clock signal, and the second clock signal to be aligned and the second delay write clock signal are transmitted to the storage device until an iteration stopping condition is reached; the iteration stopping condition is that the training control circuit determines that a UI level training mode is ended or UI level training fails;

updating: if the iteration stopping condition is UI level training failure, updating the current preset phase difference, and repeating the signal generating step and the iteration delaying step.

According to the training circuit suitable for write equalization provided by the invention, the control of the master clock generating circuit to generate a second master clock signal to be aligned and the control of the write clock generating circuit to generate a second write clock signal to be aligned based on the current working frequency, a reference clock signal and the phase difference counter specifically comprise:

dividing the frequency of the reference clock signal based on a first configurable counter to obtain a frequency-divided clock signal, and controlling the master clock generating circuit to select the frequency-divided clock signal as the second master clock signal to be aligned; the value of the first configurable counter is determined based on the current operating frequency;

and configuring the values of a second configurable counter and a third configurable counter based on the values of the first configurable counter, and alternately starting the second configurable counter and the third configurable counter when the phase difference counter indicates that the phase difference condition is met, so as to alternately set a write clock control interface signal as WCK stable high and WCK stable low based on the second configurable counter and the third configurable counter, and obtain the second write clock signal to be aligned.

According to the training circuit suitable for write equalization provided by the invention, the training control circuit is specifically used for:

judging whether a sampling signal returned by a data input/output loop of the storage device contains 0 to 1 or 1 to 0 jump, and if the sampling signal contains 0 to 1 or 1 to 0 jump, determining that the UI level training mode is ended.

According to the training circuit suitable for the write equalization, the training control circuit is further used for controlling to enter the UI-level training mode after the picosecond-level training mode is determined to be ended.

The invention also provides a training method of the training circuit suitable for write equalization, which comprises the following steps:

based on the training control circuit, when the current working frequency is smaller than a first preset frequency, controlling to enter a picosecond training mode;

based on a picosecond training circuit, in a picosecond training mode, based on a current working frequency and a reference clock signal, after a master clock generating circuit is controlled to generate a first to-be-aligned master clock signal and a write clock generating circuit is controlled to generate a first to-be-aligned write clock signal, a control delay circuit sequentially delays the first to-be-aligned write clock signal based on different delay gears to obtain a first delayed write clock signal, and the first to-be-aligned master clock signal and the first delayed write clock signal are transmitted to a storage device until the training control circuit determines that the picosecond training mode is finished based on a sampling signal returned by a data input/output loop of the storage device.

According to the training method provided by the invention, based on the training control circuit, when the current working frequency is greater than the first preset frequency, the UI level training mode is controlled to be entered;

based on a UI level training circuit, in a UI level training mode, based on the current working frequency and a reference clock signal, controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the writing clock generating circuit to generate a second writing clock signal to be aligned, controlling the delay circuit to delay the second writing clock signal to be aligned sequentially based on different delay gears to obtain a second delayed writing clock signal, and transmitting the second master clock signal to be aligned and the second delayed writing clock signal to the storage device until the training control circuit determines that the UI level training mode is finished based on sampling signals returned by a data input and output loop of the storage device; wherein the frequency of the second master clock signal to be aligned is less than the frequency of the reference clock signal.

According to the training circuit and the training method suitable for write equalization, in a picosecond training mode, based on the current working frequency and a reference clock signal, a master clock generating circuit is controlled to generate a first master clock signal to be aligned, and after the first clock signal to be aligned is controlled to be written into the master clock generating circuit, a delay circuit is controlled to delay the first clock signal to be aligned sequentially based on different delay gears, so that a first delay write clock signal is obtained, the first master clock signal to be aligned and the first delay write clock signal are transmitted to a storage device, and until the training control circuit determines that the picosecond training mode is finished based on a sampling signal returned by a data input/output loop of the storage device; in the UI level training mode, after the master clock generating circuit is controlled to generate a second master clock signal to be aligned and the write clock generating circuit is controlled to generate a second write clock signal to be aligned based on the current working frequency and the reference clock signal, the control delay circuit delays the second write clock signal to be aligned based on different delay gears in sequence to obtain a second delay write clock signal, and the second master clock signal to be aligned and the second delay write clock signal are transmitted to the storage device until the training control circuit determines that the UI level training mode is finished based on sampling signals returned by a data input and output loop of the storage device, so that aligned CK signals and WCK signals can be obtained quickly under different working frequencies, and write balance training is realized.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a training circuit suitable for write equalization according to the present invention;

FIG. 2 is a schematic diagram of a training circuit suitable for write equalization according to a second embodiment of the present invention;

FIG. 3 is a schematic flow chart of the training method according to the present invention;

FIG. 4 is a second flow chart of the training method according to the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Fig. 1 is a schematic structural diagram of a training circuit suitable for write equalization according to the present invention, as shown in fig. 1, the training circuit includes:

a training control circuit 110, a picosecond training circuit 120, a master clock generation circuit 130, a write clock generation circuit 140, and a delay circuit 150.

The training control circuit 110 is configured to control to enter a picosecond training mode when the current operating frequency is less than a first preset frequency, and determine whether the picosecond training mode is ended based on a sampling signal returned by a data input/output loop of the storage device 200;

the picosecond training circuit 120 is configured to, in a picosecond training mode, control the master clock generating circuit 130 to generate a first to-be-aligned master clock signal and control the write clock generating circuit 140 to generate a first to-be-aligned write clock signal based on a current operating frequency and a reference clock signal, control the delay circuit 150 to delay the first to-be-aligned write clock signal based on different delay steps sequentially, obtain a first delayed write clock signal, and transmit the first to-be-aligned master clock signal and the first delayed write clock signal to the memory device 200 until the training control circuit 110 determines that the picosecond training mode is finished based on a sampling signal returned by a data input/output loop of the memory device 200.

Specifically, when the current operating frequency of the link is less than a first preset frequency (e.g., 6400), control enters a picosecond training mode to train with the picosecond training circuit 120 to obtain the aligned master clock signal CK and write clock signal WCK.

Specifically, in the picosecond training mode, the picosecond training circuit 120 may control the master clock generation circuit 130 to generate the first to-be-aligned master clock signal and the write clock generation circuit 140 to generate the first to-be-aligned write clock signal based on the current operating frequency and the reference clock signal. The picosecond training circuit 120 may generate a CK signal with a frequency meeting the scene requirement based on a clock configuration register 1211 (a dram_ck register or a dram_clk register, etc., where the specific naming of the register depends on the type of the memory controller), and control the master clock generating circuit 130 to select the CK signal and perform a parallel-serial operation on the CK signal, to obtain a first master clock signal to be aligned, and generate a WCK signal with a frequency meeting the scene requirement by configuring a write clock control interface signal (dfi_ WCK _toggle or dfi_ WCK _toggle_pn, etc.), and control the write clock generating circuit 140 to select the WCK signal and perform a parallel-serial operation on the WCK signal, to obtain the first write clock signal to be aligned.

In some embodiments, when the current operating frequency is less than the second preset frequency (e.g., 3200), no down-clocking of the reference clock signal is required, so the value of clock configuration register 1211 may be set to "4b'1010" to generate the first to-be-aligned master clock signal having the same frequency as the reference clock signal. Meanwhile, the picosecond training circuit 120 may set the write clock control interface signal to WCK fast-toggle based on the first configuration unit 1221, and the clock generating circuit of the memory controller may be correspondingly adjusted to generate a WCK signal satisfying the WCK fast-toggle mode based on the reference clock signal, and the picosecond training circuit 120 controls the write clock generating circuit 140 to select the WCK signal generated in the mode and perform parallel-serial conversion, so as to obtain the first write clock signal to be aligned. When the reference clock signal is greater than the second preset frequency and less than the first preset frequency, the reference clock signal needs to be downshifted, so the value of the clock configuration register 1211 may be set to "4b'1100" to generate the first master clock signal to be aligned with a frequency of 1/2 of the frequency of the reference clock signal. Meanwhile, the picosecond training circuit 120 may set the write clock control interface signal to WCK toggle based on the second configuration unit 1222, and the clock generating circuit of the memory controller may be correspondingly adjusted to generate a WCK signal satisfying the WCK toggle mode based on the reference clock signal, and the picosecond training circuit 120 controls the write clock generating circuit 140 to select the WCK signal generated in the mode and perform parallel-serial conversion, thereby obtaining the first write clock signal to be aligned. It should be noted that the frequency ratio of the first to-be-aligned master clock signal and the first to-be-aligned write clock signal generated in the above manner conforms to the LPDDR5 specification.

Subsequently, the picosecond training circuit 120 controls the delay circuit 150 to delay the first write clock signal to be aligned based on different delay gear sequentially, so as to obtain a first delayed write clock signal. After each delay, the first to-be-aligned master clock signal and the first delayed write clock signal obtained by the delay are transmitted to the memory device 200 through the CK Pad and the WCK Pad, respectively, the memory device 200 returns corresponding sampling signals through the data input/output loop to describe the phase relationship between the first to-be-aligned master clock signal and the first delayed write clock signal obtained by the delay, and the training control circuit 110 may determine whether the first to-be-aligned master clock signal and the first delayed write clock signal obtained by the delay are aligned based on the sampling signals returned by the data input/output loop of the memory device 200, so as to determine whether the picosecond training mode is ended. If the delay circuit 150 delays the first to-be-aligned write clock signal based on any delay gear, and the training control circuit 110 determines that the picosecond training mode is finished based on the sampling signal returned by the data input/output loop of the memory device 200, it indicates that the first delayed write clock signal obtained by this delay is aligned with the first to-be-aligned master clock signal in the picosecond training mode, so that the aligned CK signal and WCK signal are obtained.

In some embodiments, the training control circuit 110 may determine whether the sampling signal returned by the data input/output loop of the memory device 200 includes a transition from 0 to 1 or from 1 to 0, and if the sampling signal includes a transition from 0 to 1 or from 1 to 0, determine that the picosecond training mode is over.

In other embodiments, as shown in FIG. 2, the training circuit further includes a UI-level training circuit 160.

The training control circuit 110 is further configured to control entering a UI level training mode when the current operating frequency is greater than a first preset frequency, and determine whether the UI level training mode is ended based on a sampling signal returned by the data input/output loop of the storage device 200;

the UI level training circuit 160 is configured to, in the UI level training mode, control the master clock generating circuit 130 to generate a second master clock signal to be aligned and the control write clock generating circuit 140 to generate a second write clock signal to be aligned based on the current operating frequency and the reference clock signal, control the delay circuit 150 to delay the second write clock signal to be aligned based on different delay steps in sequence, obtain a second delayed write clock signal, and transmit the second master clock signal to be aligned and the second delayed write clock signal to the storage device 200 until the training control circuit 110 determines that the UI level training mode is finished based on the sampling signal returned by the data input/output loop of the storage device 200; wherein the frequency of the second to-be-aligned master clock signal is less than the frequency of the reference clock signal.

Specifically, when the current operating frequency of the link is greater than a first preset frequency (e.g., 6400), control enters a UI level training mode to train with the UI level training circuit 160 to obtain the aligned master clock signal CK and write clock signal WCK.

In the UI level training mode, the UI level training circuit 160 may control the master clock generating circuit 130 to generate the second to-be-aligned master clock signal and the write clock generating circuit 140 to generate the second to-be-aligned write clock signal based on the current operating frequency and the reference clock signal. The current working frequency of the link is higher, and the reference clock signal needs to be reduced to different degrees to obtain the second main clock signal to be aligned, wherein the degree of the reduction depends on the current working frequency and the specifications of the memory controller and the memory device, so that the frequency of the second main clock signal to be aligned is smaller than that of the reference clock signal. In addition, the frequency ratio of the second to-be-aligned write clock signal to the second to-be-aligned master clock signal must satisfy the LPDDR5 specification, so the second to-be-aligned write clock signal whose frequency satisfies the requirement of the LPDDR5 specification can be generated based on the frequency of the second to-be-aligned master clock signal.

Subsequently, similar to the picosecond level training circuit 120, the ui level training circuit 160 may control the delay circuit 150 to sequentially delay the second write clock signal to be aligned based on different delay stages, resulting in a second delayed write clock signal. After each delay, the second master clock signal to be aligned and the second delayed write clock signal obtained by the delay are transmitted to the memory device 200 through the CK Pad and the WCK Pad, respectively, the memory device 200 returns corresponding sampling signals through the data input/output loop to describe the phase relationship between the second master clock signal to be aligned and the second delayed write clock signal obtained by the delay, and the training control circuit 110 may determine whether the second master clock signal to be aligned and the second delayed write clock signal obtained by the delay are aligned based on the sampling signals returned by the data input/output loop of the memory device 200, so as to determine whether the UI level training mode is ended. If the delay circuit 150 delays the second write clock signal to be aligned based on any delay gear, and the training control circuit 110 determines that the UI level training mode is finished based on the sampling signal returned by the data input/output loop of the storage device 200, it indicates that the second write clock signal delayed this time is aligned with the second master clock signal to be aligned in the UI level training mode, so that the aligned CK signal and WCK signal are obtained.

In some embodiments, the training control circuit 110 may determine whether the sampling signal returned by the data input/output loop of the storage device 200 includes a transition from 0 to 1 or from 1 to 0, and if the sampling signal includes a transition from 0 to 1 or from 1 to 0, determine that the UI level training mode is ended.

In other embodiments, to improve the success rate of the UI level training, the UI level training circuit 160 may specifically be configured to perform the following steps:

a signal generation step: setting the value of the phase difference counter 1621 based on the current preset phase difference, and controlling the master clock generation circuit 130 to generate a second master clock signal to be aligned and controlling the write clock generation circuit 140 to generate a second write clock signal to be aligned based on the current operating frequency, the reference clock signal, and the phase difference counter 1621; the phase difference between the second to-be-aligned write clock signal and the second to-be-aligned master clock signal is equal to the current preset phase difference;

an iteration delay step: the control delay circuit 150 sequentially delays the second clock signal to be aligned based on different delay gears to obtain a second delayed write clock signal, and transmits the second master clock signal to be aligned and the second delayed write clock signal to the storage device 200 until reaching a stop iteration condition; the stop iteration condition is that the training control circuit 110 determines that the UI level training mode ends or the UI level training fails;

Updating: if the iteration stopping condition is that the UI level training fails, the current preset phase difference is updated, and the signal generating step and the iteration delaying step are repeated.

In the iterative delay step, if the delay circuit 150 attempts all delay steps, the training control circuit 110 determines that the UI level training mode is not ended (i.e. the sampling signal returned by the data input/output loop of the storage device 200 does not include a transition from 0 to 1 or from 1 to 0 all the time), and determines that the UI level training fails. At this time, the current preset phase difference is modified and the value of the phase difference counter 1621 is updated, and the phase difference between the second to-be-aligned write clock signal and the second to-be-aligned master clock signal is changed, so that a new training process is entered.

In some embodiments, the UI stage training circuit 160 may divide the reference clock signal based on the first configurable counter 1611 to obtain a divided clock signal, and control the master clock generating circuit 130 to select the divided clock signal and perform parallel-serial conversion to obtain a second master clock signal to be aligned. Wherein the value of the first configurable counter 1611 is used to control the division ratio, which may be determined based on the current operating frequency. For example, the higher the current operating frequency, the higher the frequency division ratio may be set; in addition, the selectable operating frequency may be divided into a plurality of frequency ranges, and corresponding frequency dividing ratios may be set for the respective frequency ranges, so that the current frequency dividing ratio is determined based on the frequency range in which the current operating frequency is located.

In addition, the UI level training circuit 160 may configure the values of the second configurable counter 1622 and the third configurable counter 1623 based on the value of the first configurable counter 1611, and when the phase difference counter 1621 indicates that the phase difference condition is satisfied (for example, the value of the phase difference counter 1621 becomes 0), alternately turn on the second configurable counter 1622 and the third configurable counter 1623 to alternately set the write clock control interface signal to be WCK stable high and WCK stable low through the third configuration unit 1624 and the fourth configuration unit 1625 based on the second configurable counter 1622 and the third configurable counter 1623, generate corresponding WCK signals, and further obtain the second write clock signal to be aligned after parallel-to-serial. Wherein, the time of writing the clock control interface signal to WCK static high depends on the value of the second configurable counter 1622, and the time of writing the clock control interface signal to WCK static low depends on the value of the third configurable counter 1623.

Here, the periodic second to-be-aligned write clock signal may be obtained by alternately turning on the second and third configurable counters 1622 and 1623 several times (e.g., 8 times) to alternately set the write clock control interface signal to WCK stable high and WCK stable low based on the second and third configurable counters 1622 and 1623, thereby alternately generating a high level and a low level. Wherein the duration of the high level depends on the value of the second configurable counter 1622 and the duration of the low level depends on the value of the third configurable counter 1623. It can be seen that the frequency of the second write clock signal to be aligned can be set by the values of the second matable counter 1622 and the third matable counter, and the values of the second matable counter 1622 and the third matable counter are set based on the value of the first matable counter 1611, so that the frequency ratio of the second write clock signal to be aligned to the second master clock signal to be aligned can be ensured to meet the requirement of the LPDDR5 specification.

In other embodiments, the training control circuit is further configured to control entry into the UI level training mode after determining that the picosecond level training mode is over. When the UI level training mode is entered after the picosecond level training mode is ended, the operation mode of the UI level training circuit 160 is similar to that given in the above embodiment, and will not be described here. In this case, when the UI level training circuit 160 sequentially delays the second to-be-aligned write clock signal based on different delay levels, the UI level training circuit may test the delay level with a delay level corresponding to the delay circuit as a start value.

In summary, in the training circuit provided by the embodiment of the invention, in the picosecond training mode, the picosecond training circuit is used for controlling the master clock generating circuit to generate the first master clock signal to be aligned and controlling the write clock generating circuit to generate the first write clock signal to be aligned based on the current working frequency and the reference clock signal, and then controlling the delay circuit to delay the first write clock signal to be aligned based on different delay gears in sequence, so as to obtain the first delay write clock signal, and transmitting the first master clock signal to be aligned and the first delay write clock signal to the storage device until the training control circuit determines that the picosecond training mode is finished based on the sampling signal returned by the data input output loop of the storage device; in the UI level training mode, after the master clock generating circuit is controlled to generate a second master clock signal to be aligned and the write clock generating circuit is controlled to generate a second write clock signal to be aligned based on the current working frequency and the reference clock signal, the control delay circuit delays the second write clock signal to be aligned based on different delay gears in sequence to obtain a second delay write clock signal, and the second master clock signal to be aligned and the second delay write clock signal are transmitted to the storage device until the training control circuit determines that the UI level training mode is finished based on sampling signals returned by a data input and output loop of the storage device, so that aligned CK signals and WCK signals can be obtained quickly under different working frequencies, and write balance training is realized.

The training method provided by the invention is described below, and the training method described below and the training circuit described above can be referred to correspondingly.

Based on any of the above embodiments, fig. 3 is a schematic flow chart of a training method provided by the present invention, where the method is based on the training circuit provided by the above embodiment, and as shown in fig. 3, the method includes:

step 310, controlling to enter a picosecond training mode when the current working frequency is smaller than a first preset frequency based on the training control circuit;

step 320, based on the picosecond training circuit, in the picosecond training mode, based on the current working frequency and the reference clock signal, after the master clock generating circuit is controlled to generate a first to-be-aligned master clock signal and the write clock generating circuit is controlled to generate a first to-be-aligned write clock signal, the control delay circuit sequentially delays the first to-be-aligned write clock signal based on different delay gears to obtain a first delayed write clock signal, and the first to-be-aligned master clock signal and the first delayed write clock signal are transmitted to the storage device until the training control circuit determines that the picosecond training mode is finished based on the sampling signal returned by the data input/output loop of the storage device.

Based on any of the above embodiments, when the current operating frequency is less than a second preset frequency, the frequency of the first to-be-aligned master clock signal is the same as the frequency of the reference clock signal, and the first to-be-aligned write clock signal is generated after setting a write clock control interface signal to WCK fast-toggle; when the current working frequency is greater than the second preset frequency and less than the first preset frequency, the frequency of the first to-be-aligned master clock signal is 1/2 of the frequency of the reference clock signal, and the first to-be-aligned write clock signal is generated after setting a write clock control interface signal as WCK toggle.

Based on any of the above embodiments, the training control circuit determines that the picosecond training mode is finished based on the sampling signal returned by the data input/output loop of the storage device, and specifically includes:

judging whether a sampling signal returned by a data input/output loop of the storage device contains 0 to 1 or 1 to 0 jump, and if the sampling signal contains 0 to 1 or 1 to 0 jump, determining that the picosecond training mode is ended.

Based on any of the above embodiments, as shown in fig. 4, the training method further includes:

step 410, controlling to enter a UI-level training mode when the current working frequency is greater than the first preset frequency based on the training control circuit;

Step 420, based on a UI level training circuit, in a UI level training mode, based on a current working frequency and a reference clock signal, controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the write clock generating circuit to generate a second write clock signal to be aligned, controlling the delay circuit to delay the second write clock signal to be aligned based on different delay gears in sequence, obtaining a second delay write clock signal, and transmitting the second master clock signal to be aligned and the second delay write clock signal to the storage device until the training control circuit determines that the UI level training mode is finished based on a sampling signal returned by a data input/output loop of the storage device; wherein the frequency of the second master clock signal to be aligned is less than the frequency of the reference clock signal.

Based on any one of the foregoing embodiments, after controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the write clock generating circuit to generate a second write clock signal to be aligned based on the current operating frequency and the reference clock signal, controlling the delay circuit to delay the second write clock signal to be aligned based on different delay gears in turn, to obtain a second delayed write clock signal, and transmitting the second master clock signal to be aligned and the second delayed write clock signal to the storage device until the training control circuit determines that the UI level training mode is finished based on the sampling signal returned by the data input/output loop of the storage device, including:

A signal generation step: setting a value of a phase difference counter based on a current preset phase difference, and controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the write clock generating circuit to generate a second write clock signal to be aligned based on a current working frequency, a reference clock signal and the phase difference counter; the phase difference between the second write clock signal to be aligned and the second master clock signal to be aligned is equal to the current preset phase difference;

an iteration delay step: the delay circuit is controlled to delay the second clock signal to be aligned based on different delay gears in sequence to obtain a second delay write clock signal, and the second clock signal to be aligned and the second delay write clock signal are transmitted to the storage device until an iteration stopping condition is reached; the iteration stopping condition is that the training control circuit determines that a UI level training mode is ended or UI level training fails;

updating: if the iteration stopping condition is UI level training failure, updating the current preset phase difference, and repeating the signal generating step and the iteration delaying step.

Based on any one of the foregoing embodiments, the controlling the master clock generating circuit to generate the second to-be-aligned master clock signal and the controlling the write clock generating circuit to generate the second to-be-aligned write clock signal based on the current operating frequency, the reference clock signal, and the phase difference counter specifically includes:

dividing the frequency of the reference clock signal based on a first configurable counter to obtain a frequency-divided clock signal, and controlling the master clock generating circuit to select the frequency-divided clock signal as the second master clock signal to be aligned; the value of the first configurable counter is determined based on the current operating frequency;

and configuring the values of a second configurable counter and a third configurable counter based on the values of the first configurable counter, and alternately starting the second configurable counter and the third configurable counter when the phase difference counter indicates that the phase difference condition is met, so as to alternately set a write clock control interface signal as WCK stable high and WCK stable low based on the second configurable counter and the third configurable counter, and obtain the second write clock signal to be aligned.

Based on any of the above embodiments, the training control circuit determines that the UI level training mode is finished based on the sampling signal returned by the data input/output loop of the storage device, and specifically includes:

Judging whether a sampling signal returned by a data input/output loop of the storage device contains 0 to 1 or 1 to 0 jump, and if the sampling signal contains 0 to 1 or 1 to 0 jump, determining that the UI level training mode is ended.

Based on any of the above embodiments, the training method further includes:

after the end of the picosecond training mode is determined, control enters the UI training mode.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A training circuit adapted for write equalization, comprising:

the system comprises a training control circuit, a picosecond training circuit, a master clock generation circuit, a write clock generation circuit and a delay circuit;

the training control circuit is used for controlling to enter a picosecond training mode when the current working frequency is smaller than a first preset frequency, and determining whether the picosecond training mode is ended or not based on a sampling signal returned by a data input/output loop of the storage device;

the picosecond training circuit is used for controlling the master clock generating circuit to generate a first to-be-aligned master clock signal and controlling the writing clock generating circuit to generate a first to-be-aligned writing clock signal based on the current working frequency and a reference clock signal in a picosecond training mode, controlling the delay circuit to delay the first to-be-aligned writing clock signal based on different delay gears in sequence to obtain a first delayed writing clock signal, and transmitting the first to-be-aligned master clock signal and the first delayed writing clock signal to a storage device until the training control circuit determines that the picosecond training mode is finished based on a sampling signal returned by a data input/output loop of the storage device.

2. The training circuit adapted for write equalization as defined in claim 1, wherein when said current operating frequency is less than a second predetermined frequency, said first to-be-aligned master clock signal is the same frequency as said reference clock signal, said first to-be-aligned write clock signal being generated after setting a write clock control interface signal to WCK fast-toggle; when the current working frequency is greater than the second preset frequency and less than the first preset frequency, the frequency of the first to-be-aligned master clock signal is 1/2 of the frequency of the reference clock signal, and the first to-be-aligned write clock signal is generated after setting a write clock control interface signal as WCK toggle.

3. Training circuit suitable for write equalization according to claim 1, characterized in that the training control circuit is specifically adapted to:

judging whether a sampling signal returned by a data input/output loop of the storage device contains 0 to 1 or 1 to 0 jump, and if the sampling signal contains 0 to 1 or 1 to 0 jump, determining that the picosecond training mode is ended.

4. Training circuit suitable for write equalization as defined in claim 1, further comprising a UI level training circuit;

The training control circuit is further used for controlling to enter a UI level training mode when the current working frequency is larger than the first preset frequency, and determining whether the UI level training mode is finished or not based on a sampling signal returned by a data input/output loop of the storage device;

the UI level training circuit is used for controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the writing clock generating circuit to generate a second writing clock signal to be aligned based on the current working frequency and a reference clock signal in a UI level training mode, controlling the delay circuit to delay the second writing clock signal to be aligned based on different delay gears in sequence to obtain a second delayed writing clock signal, and transmitting the second master clock signal to be aligned and the second delayed writing clock signal to the storage device until the training control circuit determines that the UI level training mode is finished based on sampling signals returned by a data input and output loop of the storage device; wherein the frequency of the second master clock signal to be aligned is less than the frequency of the reference clock signal.

5. Training circuit suitable for write equalization as claimed in claim 4, characterized in that said UI level training circuit is specifically adapted to:

A signal generation step: setting a value of a phase difference counter based on a current preset phase difference, and controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the write clock generating circuit to generate a second write clock signal to be aligned based on a current working frequency, a reference clock signal and the phase difference counter; the phase difference between the second write clock signal to be aligned and the second master clock signal to be aligned is equal to the current preset phase difference;

an iteration delay step: the delay circuit is controlled to delay the second clock signal to be aligned based on different delay gears in sequence to obtain a second delay write clock signal, and the second clock signal to be aligned and the second delay write clock signal are transmitted to the storage device until an iteration stopping condition is reached; the iteration stopping condition is that the training control circuit determines that a UI level training mode is ended or UI level training fails;

updating: if the iteration stopping condition is UI level training failure, updating the current preset phase difference, and repeating the signal generating step and the iteration delaying step.

6. The training circuit adapted for write equalization as defined in claim 5 wherein said controlling said master clock generation circuit to generate a second master clock signal to be aligned and said writing clock generation circuit to generate a second write clock signal to be aligned based on a current operating frequency, a reference clock signal and said phase difference counter comprises:

dividing the frequency of the reference clock signal based on a first configurable counter to obtain a frequency-divided clock signal, and controlling the master clock generating circuit to select the frequency-divided clock signal as the second master clock signal to be aligned; the value of the first configurable counter is determined based on the current operating frequency;

and configuring the values of a second configurable counter and a third configurable counter based on the values of the first configurable counter, and alternately starting the second configurable counter and the third configurable counter when the phase difference counter indicates that the phase difference condition is met, so as to alternately set a write clock control interface signal as WCK stable high and WCK stable low based on the second configurable counter and the third configurable counter, and obtain the second write clock signal to be aligned.

7. Training circuit suitable for write equalization according to claim 4, characterized in that said training control circuit is specifically adapted to:

judging whether a sampling signal returned by a data input/output loop of the storage device contains 0 to 1 or 1 to 0 jump, and if the sampling signal contains 0 to 1 or 1 to 0 jump, determining that the UI level training mode is ended.

8. The training circuit adapted for write equalization as defined in claim 4, wherein said training control circuit is further adapted to control entry into a UI level training mode upon determining that a picosecond level training mode is complete.

9. Training method based on a training circuit suitable for write equalization according to any of the claims 1 to 8, characterized in that it comprises:

based on the training control circuit, when the current working frequency is smaller than a first preset frequency, controlling to enter a picosecond training mode;

based on a picosecond training circuit, in a picosecond training mode, based on a current working frequency and a reference clock signal, after a master clock generating circuit is controlled to generate a first to-be-aligned master clock signal and a write clock generating circuit is controlled to generate a first to-be-aligned write clock signal, a control delay circuit sequentially delays the first to-be-aligned write clock signal based on different delay gears to obtain a first delayed write clock signal, and the first to-be-aligned master clock signal and the first delayed write clock signal are transmitted to a storage device until the training control circuit determines that the picosecond training mode is finished based on a sampling signal returned by a data input/output loop of the storage device.

10. The training method of claim 9, wherein the training method further comprises:

based on the training control circuit, when the current working frequency is greater than the first preset frequency, controlling to enter a UI-level training mode;

based on a UI level training circuit, in a UI level training mode, based on the current working frequency and a reference clock signal, controlling the master clock generating circuit to generate a second master clock signal to be aligned and controlling the writing clock generating circuit to generate a second writing clock signal to be aligned, controlling the delay circuit to delay the second writing clock signal to be aligned sequentially based on different delay gears to obtain a second delayed writing clock signal, and transmitting the second master clock signal to be aligned and the second delayed writing clock signal to the storage device until the training control circuit determines that the UI level training mode is finished based on sampling signals returned by a data input and output loop of the storage device; wherein the frequency of the second master clock signal to be aligned is less than the frequency of the reference clock signal.