CN117805567A - FPGA-based cable partial discharge simulation generation device - Google Patents
FPGA-based cable partial discharge simulation generation device Download PDFInfo
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- CN117805567A CN117805567A CN202311844396.3A CN202311844396A CN117805567A CN 117805567 A CN117805567 A CN 117805567A CN 202311844396 A CN202311844396 A CN 202311844396A CN 117805567 A CN117805567 A CN 117805567A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention belongs to the technical field of electronic circuits, and particularly discloses a cable partial discharge simulation generating device based on an FPGA. The invention can be directly connected with the high-voltage cable to simulate the partial discharge defect, ensures that the partial discharge characteristic parameters are controllable, and the simulation experiment result can be reproduced, thereby being beneficial to the storage and the analysis of the cable partial discharge simulation experiment data.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a cable partial discharge simulation generating device based on an FPGA.
Background
The partial discharge defect simulation generating device (Partial Discharge Fault Simulation Device) is a device for simulating partial discharge defects that may occur in an electrical apparatus. Partial discharge refers to a partial shock discharge phenomenon occurring in electrical equipment, typically caused by damage or failure of the insulation system of the equipment.
In the operation process of the power equipment, the problems of aging of an insulation system, dielectric breakdown and the like can be caused due to long-term voltage and current effects, so that partial discharge defects are caused. Such defects are generally tiny discharges and often cannot be directly observed inside the device, and therefore need to be simulated and detected by a special device.
The partial discharge defect simulation generating device can evaluate and test the insulation performance of the electrical equipment by simulating and generating specific partial discharge defects. It is generally composed of a high voltage generator, a discharge electrode, a signal acquisition system, a data analysis system, etc.
In actual operation, the device is first supplied with the appropriate voltage by a high voltage generator and then simulated with a discharge electrode to create a partial discharge defect. The discharge electrode is a very important component of the device, and is usually installed inside the equipment to be tested, and induces a partial discharge phenomenon by generating a high voltage electric field. Meanwhile, the signal acquisition system can monitor and record relevant data such as current, voltage, discharge characteristics and the like in real time.
The partial discharge defect simulation generating device plays an important role in maintenance and operation of the power equipment. The device can help engineers to timely detect and analyze partial discharge defects existing in equipment, prevent potential faults, and improve the reliability and safety of the power equipment. Meanwhile, the method can also provide important reference data for the design and research and development of the power equipment, and promote the progress and development of the power equipment technology.
However, the existing partial discharge simulation generating device cannot be directly connected to a high-voltage cable for use, and the partial discharge defect simulation generating device simulates a high-frequency discharge phenomenon, which usually occurs randomly, and its characteristic parameters may also change with time and conditions, so that the existing partial discharge simulation generating device has difficulty in reproducing experimental results and accurately measuring partial discharge characteristic parameters.
Disclosure of Invention
The invention aims to provide a cable partial discharge simulation generating device based on an FPGA, which is used for solving the problems in the prior art.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the invention provides a cable partial discharge simulation generating device based on an FPGA, which comprises an FPGA processor, a DAC module and an RC circuit which are sequentially connected, wherein the FPGA processor is used for generating a digital control signal and transmitting the digital control signal to the DAC module, the DAC module is used for receiving the digital control signal, converting the digital control signal into an analog control signal and transmitting the analog control signal to the RC circuit, and the RC circuit is used for receiving the analog control signal and outputting the partial discharge analog signal to a high-voltage cable.
In one possible design, the device further includes a host computer, where the host computer is connected to the FPGA processor and is configured to send a control command to the FPGA processor, so that the FPGA processor generates a digital control signal according to the control command after receiving the control command.
In one possible design, the upper computer uses a single-chip microcomputer.
In one possible design, the apparatus further comprises a power module for providing operating power to the FPGA processor, the DAC module, and the RC circuit.
In one possible design, the FPGA processor employs an XC6SLX16-2CSG324C type FPGA chip.
In one possible design, the DAC module includes a DAC chip and a filter amplifier circuit connected to the DAC chip, where the filter amplifier circuit has multiple paths.
In one possible design, the DAC chip employs an AD9767 type dual-channel DAC chip, and the filter amplification circuit includes a low frequency filter circuit and a two-stage operational amplifier employing an AD8065 type operational amplifier.
In one possible design, the RC circuit includes a signal source, a first high-voltage capacitor, a second high-voltage capacitor, a first resistor and a second resistor, where an input end of the signal source is connected with the DAC module, an output end of the signal source is sequentially connected with the first high-voltage capacitor, the second high-voltage capacitor and the first resistor in series, another output end of the signal source is connected with the first output terminal, the second resistor is connected in parallel between the first high-voltage capacitor and the second high-voltage capacitor, the other end of the second resistor is connected with the first output terminal in parallel, and the other end of the first resistor is connected with the second output terminal, where the first output terminal and the second output terminal are used for connecting the high-voltage cable.
The beneficial effects are that: according to the invention, the FPGA processor can generate corresponding digital control signals and transmit the digital control signals to the DAC module, the DAC module can convert the digital control signals into analog control signals and transmit the analog control signals to the RC circuit, the RC circuit can receive the analog control signals to perform pulse generation processing, and finally, corresponding partial discharge analog signals are output to the high-voltage cable, so that the partial discharge defect simulation of the high-voltage cable is realized. The invention can be directly connected with the high-voltage cable to simulate the partial discharge defect, ensures that the partial discharge characteristic parameters are controllable, and the simulation experiment result can be reproduced, thereby being beneficial to the storage and the analysis of the cable partial discharge simulation experiment data.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a device architecture according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a DAC module according to an embodiment;
FIG. 3 is a schematic diagram of an AD9767 DAC chip according to an embodiment;
FIG. 4 is a schematic diagram of a filter amplifier circuit according to an embodiment;
FIG. 5 is a schematic diagram of a 40-pin AD data output expansion port in an embodiment;
fig. 6 is a schematic circuit diagram of a portion of a power module according to an embodiment.
Detailed Description
It should be noted that the description of these examples is for aiding in understanding the present invention, but is not intended to limit the present invention. Specific structural and functional details disclosed herein are merely representative of example embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It will be appreciated that the term "coupled" is to be interpreted broadly, and may be a fixed connection, a removable connection, or an integral connection, for example, unless explicitly stated and limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in the embodiments can be understood by those of ordinary skill in the art according to the specific circumstances.
In the following description, specific details are provided to provide a thorough understanding of example embodiments. However, it will be understood by those of ordinary skill in the art that the example embodiments may be practiced without these specific details. For example, a system may be shown in block diagrams in order to avoid obscuring the examples with unnecessary detail. In other embodiments, well-known processes, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.
Examples:
the embodiment provides a cable partial discharge simulation generating device based on an FPGA, which comprises an FPGA processor, a DAC module and an RC circuit, wherein the FPGA processor, the DAC module and the RC circuit are sequentially connected, the FPGA processor is used for generating digital control signals and transmitting the digital control signals to the DAC module, the DAC module is used for receiving the digital control signals, converting the digital control signals into analog control signals and transmitting the analog control signals to the RC circuit, the RC circuit is used for receiving the analog control signals and outputting the partial discharge analog signals to a high-voltage cable, and the device further comprises an upper computer, wherein the upper computer is connected with the FPGA processor and is used for sending control commands to the FPGA processor so that the FPGA processor can generate the digital control signals according to the control commands after receiving the control commands.
In the implementation, the upper computer can send a control command to the FPGA processor, so that the FPGA processor can generate a digital control signal according to the control command after receiving the control command, and then the digital control signal is transmitted to the DAC module, and the upper computer and the FPGA processor can establish communication butt joint in a wired or wireless mode. The DAC module can convert the digital control signal into an analog control signal, the analog control signal is transmitted to the RC circuit, the RC circuit can receive the analog control signal to perform pulse generation processing, and finally, the corresponding partial discharge analog signal is output to the high-voltage cable, so that the partial discharge defect simulation of the high-voltage cable is realized. The upper computer can adopt a singlechip or a computer and the like. The FPGA (Field Programmable Gate Array) processor adopts an XC6SLX16-2CSG324C type FPGA chip.
As shown in fig. 2 to 4, the DAC module includes a DAC chip and a filter amplifier circuit connected to the DAC chip, where the filter amplifier circuit is provided with multiple paths. The DAC chip adopts an AD9767 type dual-channel DAC chip, and has the characteristics of high precision, high resolution, low power consumption and the like. The DAC chip may be connected to the FPGA processor through a 40-pin AD data out expansion port as shown in FIG. 5. The filtering and amplifying circuit comprises a low-frequency filtering circuit and a two-stage operational amplifier, the low-frequency filtering circuit can be obtained by connecting corresponding capacitors and resistors in parallel, the operational amplifier adopts an AD8065 operational amplifier, and finally, an analog control signal between-5V and +5V is output at a DAC module output interface DACOUT. The device also comprises a power supply module, wherein the power supply module is used for providing working power supply for the FPGA processor, the DAC module and the RC circuit, and as shown in fig. 6, the power supply module can provide 3.3V working power supply for the DAC chip.
As shown in fig. 1, the RC circuit includes a signal source, a first high-voltage capacitor, a second high-voltage capacitor, a first resistor and a second resistor, where an input end of the signal source is connected with the DAC module, an output end of the signal source is sequentially connected with the first high-voltage capacitor, the second high-voltage capacitor and the first resistor in series, another output end of the signal source is connected with a first output terminal, the second resistor is connected between the first high-voltage capacitor and the second high-voltage capacitor in parallel, another end of the second resistor is connected with the first output terminal in parallel, another end of the first resistor is connected with the second output terminal, and the first output terminal and the second output terminal are used for connecting a high-voltage cable. The high-voltage capacitor and the resistor can form a first-order differential circuit to generate corresponding pulses, and the high-voltage capacitor can effectively isolate and protect devices connected to the high-voltage cable.
In the process of carrying out partial discharge simulation by the cable partial discharge simulation generating device, a corresponding partial discharge detection method can be adopted to detect a partial discharge simulation signal, and a pulse current method can be adopted to carry out partial discharge detection for example. The pulse current method is one of the earlier detection methods for partial discharge, and is used for detecting signals from neutral points or grounding points of power equipment through rogowski coils or detecting impedance at the coupling capacitor side, and is one of detection methods widely applied to online and offline monitoring, and the generation device can simulate and detect partial discharge signals at different positions by combining the pulse current method. The partial discharge type can be divided into air gap discharge, tip discharge and surface discharge, and the three types of discharge all have different voltage pulse waveforms, the partial discharge corresponding amplitude can be obtained according to a PRPD spectrogram, the two-dimensional discrete probability distribution of the partial discharge can be obtained by an actual PRPD spectrogram data set, then the random amplitude is generated according to the probability distribution, and then the random amplitude and the waveform are combined into a complete pulse waveform, so that the simulation of the partial discharge of different types and different positions of the cable can be realized.
The FPGA-based cable partial discharge simulation generating device provided by the embodiment can simulate the partial voltage signals when defects occur at different positions of different types, provides calibration for subsequent experiments, can store experimental data, has reproducibility, simultaneously avoids data errors of an actual cable caused by discharge aging, and provides a good simulation generating device for cable partial discharge measurement in the future.
Finally, it should be noted that: the foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. The cable partial discharge simulation generating device based on the FPGA is characterized by comprising an FPGA processor, a DAC module and an RC circuit which are sequentially connected, wherein the FPGA processor is used for generating digital control signals and transmitting the digital control signals to the DAC module, the DAC module is used for receiving the digital control signals, converting the digital control signals into analog control signals and transmitting the analog control signals to the RC circuit, and the RC circuit is used for receiving the analog control signals and outputting the partial discharge analog signals to a high-voltage cable.
2. The device for generating the cable partial discharge simulation based on the FPGA according to claim 1, further comprising an upper computer, wherein the upper computer is connected with the FPGA processor and is used for sending a control command to the FPGA processor so that the FPGA processor can generate a digital control signal according to the control command after receiving the control command.
3. The FPGA-based cable partial discharge simulation generating device according to claim 2, wherein the upper computer is a single-chip microcomputer.
4. The FPGA-based cable partial discharge simulation generation device of claim 1, further comprising a power module for providing operating power to the FPGA processor, the DAC module, and the RC circuit.
5. The FPGA-based cable partial discharge simulation generating device according to claim 1, wherein the FPGA processor is an XC6SLX16-2CSG324C type FPGA chip.
6. The FPGA-based cable partial discharge analog generation device according to claim 1, wherein the DAC module comprises a DAC chip and a filter amplification circuit connected to the DAC chip, and the filter amplification circuit is provided with multiple paths.
7. The FPGA-based cable partial discharge analog generation device according to claim 6, wherein the DAC chip is an AD9767 type dual-channel DAC chip, the filter amplification circuit comprises a low-frequency filter circuit and a two-stage operational amplifier, and the operational amplifier is an AD8065 type operational amplifier.
8. The FPGA-based cable partial discharge simulation generation device according to claim 1, wherein the RC circuit comprises a signal source, a first high-voltage capacitor, a second high-voltage capacitor, a first resistor and a second resistor, the input end of the signal source is connected with the DAC module, one output end of the signal source is sequentially connected with the first high-voltage capacitor, the second high-voltage capacitor and the first resistor in series, the other output end of the signal source is connected with a first output terminal, the second resistor is connected between the first high-voltage capacitor and the second high-voltage capacitor in parallel, the other end of the second resistor is connected with a first output terminal in parallel, the other end of the first resistor is connected with a second output terminal, and the first output terminal and the second output terminal are used for connecting a high-voltage cable.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311844396.3A CN117805567A (en) | 2023-12-28 | 2023-12-28 | FPGA-based cable partial discharge simulation generation device |
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| CN202311844396.3A CN117805567A (en) | 2023-12-28 | 2023-12-28 | FPGA-based cable partial discharge simulation generation device |
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| CN213813840U (en) * | 2020-11-04 | 2021-07-27 | 苏州热工研究院有限公司 | Multifunctional cable main insulation fault and partial discharge simulation device |
| CN214201650U (en) * | 2020-11-10 | 2021-09-14 | 武汉中成智创科技有限公司 | Distributed power cable partial discharge signal simulation device capable of networking |
| CN117092573A (en) * | 2023-01-18 | 2023-11-21 | 特变电工山东鲁能泰山电缆有限公司 | Partial discharge analog signal generating device and partial discharge detection system |
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2023
- 2023-12-28 CN CN202311844396.3A patent/CN117805567A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104635124A (en) * | 2015-01-22 | 2015-05-20 | 深圳供电局有限公司 | Simulator for partial discharge modes |
| KR20190020233A (en) * | 2017-08-17 | 2019-02-28 | 한국전력공사 | Simulated signal generating Apparatus and method for partial discharge simulation |
| CN111999537A (en) * | 2020-09-29 | 2020-11-27 | 广东电网有限责任公司江门供电局 | Miniature built-in signal generator and cable partial discharge simulation method thereof |
| CN112363098A (en) * | 2020-10-29 | 2021-02-12 | 国网湖南省电力有限公司 | Programmable cable partial discharge calibration simulation device and calibration method |
| CN213813840U (en) * | 2020-11-04 | 2021-07-27 | 苏州热工研究院有限公司 | Multifunctional cable main insulation fault and partial discharge simulation device |
| CN214201650U (en) * | 2020-11-10 | 2021-09-14 | 武汉中成智创科技有限公司 | Distributed power cable partial discharge signal simulation device capable of networking |
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