CN117092573A - Partial discharge analog signal generating device and partial discharge detection system - Google Patents
Partial discharge analog signal generating device and partial discharge detection system Download PDFInfo
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- CN117092573A CN117092573A CN202310074160.XA CN202310074160A CN117092573A CN 117092573 A CN117092573 A CN 117092573A CN 202310074160 A CN202310074160 A CN 202310074160A CN 117092573 A CN117092573 A CN 117092573A
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- G—PHYSICS
- G01—MEASURING; TESTING
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Abstract
The invention provides a partial discharge analog signal generating device and a partial discharge detection system, and relates to the technical field of partial discharge detection. The generation device of the partial discharge analog signal comprises an upper computer, a Field Programmable Gate Array (FPGA) control module and a digital-to-analog converter (DAC) output module. And the upper computer is used for sending the discharge mode parameters. The FPGA control module is connected with the upper computer and is used for receiving the discharge mode parameters, extracting a phase spectrogram matched with the discharge mode parameters from the discharge mode library and outputting one path of discharge pulse signals and one path of synchronous phase signals of the phase spectrogram. The DAC module is connected with the FPGA control module and is used for respectively converting one path of discharge pulse signal and one path of synchronous phase signal of the phase spectrogram into corresponding analog signals and outputting the analog signals. At least to solve the problem that it is difficult to obtain different types of real partial discharge analog signals in the related art.
Description
Technical Field
The present invention relates to the field of partial discharge detection technologies, and in particular, to a partial discharge analog signal generating device and a partial discharge detection system.
Background
The partial discharge analog signal generator is a common tool in partial discharge test and power department training work.
The partial discharge simulator built based on the simulation circuit has single discharge type, and the discharge signal after a period of use can be changed, so that the verification requirement of the partial discharge detector and various training works can not be met.
Disclosure of Invention
The invention aims to solve the technical problems of the prior art, and provides a partial discharge analog signal generating device and a partial discharge detection system, which at least solve the problems that different types of real partial discharge analog signals are difficult to obtain in the related art.
In a first aspect, the invention provides a generating device of partial discharge analog signals, which comprises an upper computer, a Field Programmable Gate Array (FPGA) control module and a digital-to-analog converter (DAC) output module.
And the upper computer is used for sending the discharge mode parameters.
The FPGA control module is connected with the upper computer and is used for receiving the discharge mode parameters, extracting a phase spectrogram matched with the discharge mode parameters from the discharge mode library and outputting one path of discharge pulse signals and one path of synchronous phase signals of the phase spectrogram.
The DAC module is connected with the FPGA control module and is used for respectively converting one path of discharge pulse signal and one path of synchronous phase signal of the phase spectrogram into corresponding analog signals and outputting the analog signals.
Preferably, the FPGA control module comprises a control unit, and a phase accumulation counter is arranged in the control unit.
The control unit is used for extracting the phase value and the discharge quantity amplitude of the discharge signal in the phase spectrogram, and when the output value of the phase accumulation counter is equal to the phase value of the discharge signal, the discharge pulse waveform of the discharge quantity amplitude corresponding to the output phase value is used for controlling as one path of discharge pulse signal.
The control unit is also used for controlling the output sine waveform as one synchronous phase signal.
Preferably, the upper computer comprises upper computer software and a network port communication module.
The upper computer software sends the discharge mode parameters to the FPGA control module through the network port communication module.
Preferably, the FPGA control module further comprises a storage unit.
And the storage unit is used for storing the phase spectrograms and the discharge pulse waveforms matched with the various discharge mode parameters so as to form a discharge mode library.
Preferably, the FPGA control module further comprises an updating unit.
And the updating unit is connected with the storage unit and used for receiving the new phase spectrogram and the discharge pulse waveform sent by the upper computer software so as to update the discharge mode library.
Preferably, the discharge pattern comprises one or any combination of corona discharge, levitation discharge, internal discharge.
In a second aspect, the present invention further provides a partial discharge detection system, which includes a partial discharge detector, a verification device, and a generation device of the partial discharge analog signal in the first aspect.
The generation device of the partial discharge analog signal is used for outputting an analog signal corresponding to a phase spectrogram matched with the discharge mode parameter.
The partial discharge detector is connected with the generation device of the partial discharge analog signal, and is used for receiving the analog signal, carrying out characteristic recognition on a phase map corresponding to the analog signal and outputting a recognition result.
The verification device is respectively connected with the partial discharge detector and the generation device of the partial discharge analog signal and is used for verifying the consistency of the identification result and the analog signal so as to detect the quality of the partial discharge detector.
According to the partial discharge analog signal generating device and the partial discharge detection system, the analog signals corresponding to the matched phase spectrograms are extracted and output based on the FPGA control module according to the discharge mode parameters sent by the upper computer, so that the real partial discharge analog signals are obtained. And because a plurality of discharging modes are stored in the discharging mode library of the FPGA control module, different types of real partial discharging analog signals can be obtained according to the instructions sent by the upper computer.
Drawings
Fig. 1 is a schematic structural diagram of a partial discharge analog signal generating device according to embodiment 1 of the present invention;
fig. 2A is a schematic diagram of a phase spectrogram of a corona discharge in discharge mode 1 according to embodiment 1 of the present invention;
fig. 2B is a schematic diagram of a phase spectrogram of discharge mode 2 floating discharge according to embodiment 1 of the present invention;
fig. 2C is a schematic diagram of a phase spectrogram of the internal discharge in the discharge mode 3 according to embodiment 1 of the present invention;
fig. 2D is a schematic diagram of a phase spectrogram of the discharge mode 4 internal discharge superimposed corona discharge of the embodiment 1 of the present invention;
fig. 2E is a schematic diagram of a phase spectrogram of discharge mode 5 floating discharge superposition internal discharge according to embodiment 1 of the present invention;
fig. 2F is a schematic diagram of a phase spectrogram of the discharge mode 6 floating discharge superposition internal discharge and corona discharge of example 1 of the present invention;
FIG. 3 is a schematic diagram of a partial discharge analog signal generating device according to embodiment 2 of the present invention;
fig. 4 is a schematic diagram of a partial discharge detection system according to embodiment 3 of the present invention.
Detailed Description
In order to make the technical scheme of the present invention better understood by those skilled in the art, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings.
It is to be understood that the specific embodiments and figures described herein are merely illustrative of the invention, and are not limiting of the invention.
It is to be understood that the various embodiments of the invention and the features of the embodiments may be combined with each other without conflict.
It is to be understood that only the portions relevant to the present invention are shown in the drawings for convenience of description, and the portions irrelevant to the present invention are not shown in the drawings.
It should be understood that each unit and module in the embodiments of the present invention may correspond to only one physical structure, may be formed by a plurality of physical structures, or may be integrated into one physical structure.
It will be appreciated that, without conflict, the functions and steps noted in the flowcharts and block diagrams of the present invention may occur out of the order noted in the figures.
It is to be understood that the flowcharts and block diagrams of the present invention illustrate the architecture, functionality, and operation of possible implementations of systems, apparatuses, devices, methods according to various embodiments of the present invention. Where each block in the flowchart or block diagrams may represent a unit, module, segment, code, or the like, which comprises executable instructions for implementing the specified functions. Moreover, each block or combination of blocks in the block diagrams and flowchart illustrations can be implemented by hardware-based systems that perform the specified functions, or by combinations of hardware and computer instructions.
It should be understood that the units and modules related in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, for example, the units and modules may be located in a processor.
Example 1:
the generation device of the partial discharge analog signal is generally used as an analog signal source of a partial discharge detection instrument and is used for verifying or detecting the identification capability and the waveform identification capability of the partial discharge detection instrument to the discharge spectrum characteristics.
As shown in fig. 1, the present embodiment provides a generating device for partial discharge analog signals, which includes an upper computer 11, a field programmable gate array FPGA (Field Programmable Gate Array) control module 12, and a DAC output module 13.
The upper computer 11 is used for sending the discharge mode parameters.
The FPGA control module 12 is connected with the upper computer 11, and is used for receiving the discharge mode parameters, extracting a phase spectrogram matched with the discharge mode parameters from a discharge mode library, and outputting one path of discharge pulse signals and one path of synchronous phase signals of the phase spectrogram.
The DAC module 13 is connected with the FPGA control module 12 and is used for respectively converting one path of discharge pulse signal and one path of synchronous phase signal of the phase spectrogram into corresponding analog signals and outputting the analog signals.
In this embodiment, the upper computer 11 refers to a computer or a single chip microcomputer that can directly send an operation instruction, and generally provides a user operation interactive interface and displays feedback data to a user. Typical device types for the host computer 11 are computers, cell phones, tablets, panels, touch screens, etc. The discharge pattern parameters include a discharge pattern identification or a discharge pattern name or other discharge pattern related parameter, such as a specific discharge pattern superimposed interference signal. The discharge pattern includes one or any combination of corona discharge, levitation discharge, and internal discharge. Examples of a variety of different types of discharge patterns are provided as shown in fig. 2A-2F, corona discharge, levitation discharge, internal discharge superimposed corona discharge, levitation discharge superimposed internal discharge, and corona discharge, respectively. For example, the upper computer 11 sends the discharge pattern 5, the FPGA control module 12 connected with the upper computer 11 receives the instruction of the discharge pattern 5, extracts a phase spectrogram matched with the discharge pattern 5 (i.e. a phase spectrogram of floating discharge and internal discharge is superimposed) from the discharge pattern library, outputs a path of discharge pulse signal and a path of synchronous phase signal of the phase spectrogram, and converts the two paths of signals into corresponding analog signals respectively through the DAC module 13, thereby obtaining partial discharge analog signals. The FPGA control module 12 of the present embodiment can extract a corresponding phase spectrogram according to the instruction of the upper computer 11, and convert the phase spectrogram into a corresponding analog signal, and then output the corresponding analog signal, so as to obtain different types of real partial discharge analog signals according to requirements.
Optionally, the upper computer 11 includes upper computer software and a network port communication module.
The upper computer software sends the discharge mode parameters to the FPGA control module 12 through the network port communication module.
In this embodiment, the upper computer software refers to software for completing operation interaction of the upper computer.
Optionally, the FPGA control module 12 includes a control unit.
The control unit is internally provided with a phase accumulation counter.
The control unit is used for extracting the phase value and the discharge quantity amplitude of the discharge signal in the phase spectrogram, and when the output value of the phase accumulation counter is equal to the phase value of the discharge signal, the discharge pulse waveform of the discharge quantity amplitude corresponding to the output phase value is used for controlling as one path of discharge pulse signal. The control unit is also used for controlling the output sine waveform as one synchronous phase signal.
In this embodiment, as seen from a phase spectrogram of a certain discharge mode, there is a corresponding discharge magnitude at certain phase values, so the control unit is configured to extract the phase value and the discharge magnitude of the discharge signal in the phase spectrogram, and when the output value of the phase accumulation counter is equal to the phase value of the discharge signal, control the discharge pulse waveform of the discharge magnitude corresponding to the output phase value as a path of discharge pulse signal. Meanwhile, the control unit is also used for controlling the output sine waveform as one synchronous phase signal. For example, a sinusoidal waveform with a frequency of 50Hz may be output as one synchronous phase signal. The discharge mode parameters issued by the upper computer software can indicate a plurality of single discharge modes to be overlapped or indicate a specific discharge mode to overlap an interference signal, so that signals corresponding to the phase spectrogram output by the control unit comprise overlapped plurality of discharge signals or interference signals, and the type of partial discharge analog signals can be increased by obtaining discharge pulse waveforms and synchronous phases of overlapped plurality of discharge sources or interference signals through the generating device of the embodiment. Further, as the interference signal is superimposed on the discharge signal, the obtained partial discharge analog signal is more consistent with the real signal, and finally the detection quality of the partial discharge detection instrument is improved.
Optionally, the FPGA control module 12 further includes a memory unit.
And the storage unit is used for storing the phase spectrograms and the discharge pulse waveforms matched with the various discharge mode parameters so as to form a discharge mode library.
Optionally, the FPGA control module 12 further comprises an updating unit.
And the updating unit is connected with the storage unit and used for receiving the new phase spectrogram and the discharge pulse waveform sent by the upper computer software so as to update the discharge mode library.
In this embodiment, the type of the partial discharge signal can be further increased by updating the discharge pattern library by the updating unit.
According to the generation device of the partial discharge analog signals, the corresponding phase spectrogram is extracted according to the upper computer instruction based on the FPGA control module and converted into the corresponding analog signals to be output, so that different types of real partial discharge analog signals can be obtained according to requirements. Further, the discharge mode parameters issued by the upper computer software can indicate that a plurality of single discharge modes are overlapped or indicate that a specific discharge mode is overlapped with an interference signal, so that signals corresponding to the phase spectrogram output by the control unit comprise overlapped various discharge signals or interference signals, and the generation device of the embodiment can obtain discharge pulse waveforms and synchronous phases of overlapped various discharge sources or interference signals, and can increase types of partial discharge analog signals. Further, as the interference signal is superimposed on the discharge signal, the obtained partial discharge analog signal is more consistent with the real signal, and finally the detection quality of the partial discharge detection instrument is improved. In addition, the type of the partial discharge signal can be further increased by updating the discharge pattern library by the updating unit.
Example 2:
as shown in fig. 3, the embodiment provides a generating device of a partial discharge analog signal, which includes upper computer software, a network port communication module, an FPGA control module, and a 2-channel DAC output module.
And the upper computer software transmits the discharge mode parameters to the FPGA control module through the network port communication module.
And the FPGA control module stores phase spectrograms and discharge pulse waveforms matched with various discharge modes, the matched phase spectrograms are found according to discharge mode parameters set by upper computer software, and the phase value and discharge quantity amplitude of a discharge signal in the phase spectrograms are extracted. In addition, a phase accumulation counter is maintained in the FPGA control module, when the phase accumulation counter is equal to the phase value of the discharge signal, the FPGA control module outputs a discharge pulse waveform with equal proportion amplitude as a 1-path discharge signal, and the FPGA control module also outputs a 50Hz sine waveform as a 1-path synchronous signal.
Optionally, the FPGA control module may further receive a new phase spectrogram and a discharge pulse waveform issued by the upper computer software, so as to update the discharge pattern library. And the 2-channel DAC output module converts the 1-channel discharge signal and the 1-channel synchronous signal into analog signals and outputs the analog signals.
According to the generation device of the partial discharge analog signals, different types of partial discharge analog signals can be output by setting different discharge mode parameters through upper computer software. The generating device can update the discharging mode library to increase a new discharging mode, and has the characteristics of intelligence, flexibility and variability.
Example 3:
as shown in fig. 4, the present embodiment provides a partial discharge detection system including a partial discharge detector 41, a verification device 42, and a generation device 43 of a partial discharge analog signal described in embodiment 1 or embodiment 2.
The generation device 43 of the partial discharge analog signal is configured to output an analog signal corresponding to a phase spectrogram matched with the discharge mode parameter.
The partial discharge detector 41 is connected to the generation device 43 of the partial discharge analog signal, and is configured to receive the analog signal, perform feature recognition on a phase map corresponding to the analog signal, and output a recognition result.
The verifying device 42 is connected to the partial discharge detector 41 and the generating device 43 of the partial discharge analog signal, respectively, and is used for verifying the consistency of the identification result and the analog signal so as to detect the quality of the partial discharge detector.
According to the partial discharge detection system provided by the embodiment, as the interference signal is superimposed on the discharge signal output by the partial discharge analog signal generating device, the obtained partial discharge analog signal is more matched with the real signal, and finally the detection quality of the partial discharge detector is improved.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (7)
1. A generating device of partial discharge analog signals is characterized by comprising an upper computer, a field programmable gate array FPGA control module and a digital-to-analog converter DAC output module,
the upper computer is used for sending the discharge mode parameters,
the FPGA control module is connected with the upper computer and used for receiving the discharge mode parameters, extracting a phase spectrogram matched with the discharge mode parameters from a discharge mode library, outputting a discharge pulse signal and a synchronous phase signal of the phase spectrogram,
the DAC module is connected with the FPGA control module and is used for respectively converting one path of discharge pulse signal and one path of synchronous phase signal of the phase spectrogram into corresponding analog signals and outputting the analog signals.
2. The apparatus for generating partial discharge analog signals according to claim 1, wherein the FPGA control module comprises a control unit,
a phase accumulation counter is arranged in the control unit,
the control unit is used for extracting the phase value and the discharge quantity amplitude of the discharge signal in the phase spectrogram, when the output value of the phase accumulation counter is equal to the phase value of the discharge signal, the discharge pulse waveform used for controlling the discharge quantity amplitude corresponding to the output phase value is used as one path of discharge pulse signal,
the control unit is also used for controlling the output sine waveform as one synchronous phase signal.
3. The device for generating partial discharge analog signals according to claim 1, wherein the upper computer comprises upper computer software and a network port communication module,
the upper computer software sends the discharge mode parameters to the FPGA control module through the network port communication module.
4. The apparatus for generating a partial discharge analog signal according to claim 3, wherein the FPGA control module further comprises a memory unit,
and the storage unit is used for storing the phase spectrograms and the discharge pulse waveforms matched with the various discharge mode parameters so as to form a discharge mode library.
5. The apparatus for generating a partial discharge analog signal according to claim 4, wherein the FPGA control module further comprises an updating unit,
and the updating unit is connected with the storage unit and used for receiving the new phase spectrogram and the discharge pulse waveform sent by the upper computer software so as to update the discharge mode library.
6. The partial discharge analog signal generating device according to claim 1, wherein the discharge pattern comprises one or any combination of corona discharge, levitation discharge, internal discharge.
7. A partial discharge detection system comprising a partial discharge detector, a verification device, and a partial discharge analog signal generating device according to any one of claims 1 to 6,
the generation device of the partial discharge analog signal is used for outputting an analog signal corresponding to a phase spectrogram matched with the discharge mode parameter,
the partial discharge detector is connected with the generation device of the partial discharge analog signal and is used for receiving the analog signal, carrying out characteristic recognition on a phase map corresponding to the analog signal, outputting a recognition result,
the verification device is respectively connected with the partial discharge detector and the generation device of the partial discharge analog signal and is used for verifying the consistency of the identification result and the analog signal so as to detect the quality of the partial discharge detector.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104238753A (en) * | 2014-09-21 | 2014-12-24 | 长春吉大博硕科技有限责任公司 | Pulse voltage signal generating device for representation of electrostatic force touch |
| CN104753502A (en) * | 2015-04-23 | 2015-07-01 | 成都理工大学 | FPGA (field-programmable gate array)-based DDS (direct digital synthesizer) signal generator and implementation method thereof |
| CN110673074A (en) * | 2019-08-29 | 2020-01-10 | 国网江西省电力有限公司电力科学研究院 | Partial discharge check signal generator based on digital up-conversion |
| CN110794329A (en) * | 2019-11-08 | 2020-02-14 | 国网湖北省电力有限公司电力科学研究院 | Method for testing defect recognition capability of partial discharge live detector of combined electrical apparatus and switch cabinet |
| CN111596188A (en) * | 2020-05-28 | 2020-08-28 | 南京华乘电气科技有限公司 | Signal generator simulation device and high-frequency current partial discharge signal simulation method |
| CN112946444A (en) * | 2021-05-17 | 2021-06-11 | 中国电力科学研究院有限公司 | Method and system for reproducing partial discharge characteristic signals of insulation defects of high-voltage cross-linked cable system |
-
2023
- 2023-01-18 CN CN202310074160.XA patent/CN117092573A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104238753A (en) * | 2014-09-21 | 2014-12-24 | 长春吉大博硕科技有限责任公司 | Pulse voltage signal generating device for representation of electrostatic force touch |
| CN104753502A (en) * | 2015-04-23 | 2015-07-01 | 成都理工大学 | FPGA (field-programmable gate array)-based DDS (direct digital synthesizer) signal generator and implementation method thereof |
| CN110673074A (en) * | 2019-08-29 | 2020-01-10 | 国网江西省电力有限公司电力科学研究院 | Partial discharge check signal generator based on digital up-conversion |
| CN110794329A (en) * | 2019-11-08 | 2020-02-14 | 国网湖北省电力有限公司电力科学研究院 | Method for testing defect recognition capability of partial discharge live detector of combined electrical apparatus and switch cabinet |
| CN111596188A (en) * | 2020-05-28 | 2020-08-28 | 南京华乘电气科技有限公司 | Signal generator simulation device and high-frequency current partial discharge signal simulation method |
| CN112946444A (en) * | 2021-05-17 | 2021-06-11 | 中国电力科学研究院有限公司 | Method and system for reproducing partial discharge characteristic signals of insulation defects of high-voltage cross-linked cable system |
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