CN117804514A - Ultrasonic detection device, ultrasonic control circuit and driving method thereof - Google Patents

Abstract

The present disclosure provides an ultrasonic detection device, an ultrasonic control circuit, and a driving method thereof. The ultrasonic control circuit includes: the bias sub-circuit is used for controlling the bias signal end to be connected with the first node under the control of the potential of the first control end; the first node is connected with the ultrasonic sensor; the first acquisition sub-circuit is used for controlling the potential of the second node according to the potential of the first node; the second acquisition sub-circuit is used for controlling the potential of the third node according to the potential of the first node; the conversion sub-circuit is used for outputting a first current signal according to the potential of the second node and outputting a second current signal according to the potential of the third node; the subtracting sub-circuit is used for outputting a third current signal according to the first current signal and the second current signal, and the third current signal is the difference value of the first current signal and the second current signal; the output sub-circuit is used for transmitting the third current signal to the signal output terminal. The present disclosure can improve detection accuracy.

Description

Ultrasonic detection device, ultrasonic control circuit and driving method thereof

Technical Field

The present disclosure relates to the field of ultrasonic detection technologies, and in particular, to an ultrasonic detection device, an ultrasonic control circuit, and a driving method thereof.

Background

The ultrasonic detection device is widely applied to the fields of industrial nondestructive inspection, distance measurement and thickness measurement, agricultural ultrasonic breeding, ultrasonic seedling culture and ultrasonic induced spawning, biomedical diagnosis and operation, fingerprint identification in consumer electronic products and the like. The ultrasonic detection device comprises an ultrasonic sensor and an ultrasonic control circuit. The ultrasonic control circuit has low detection accuracy.

Disclosure of Invention

The invention aims to provide an ultrasonic detection device, an ultrasonic control circuit and a driving method thereof, which can improve detection accuracy.

According to one aspect of the present disclosure, there is provided an ultrasonic control circuit comprising:

the bias voltage subcircuit is connected with a bias voltage signal end, a first control end and a first node and is used for controlling the bias voltage signal end to be connected with the first node under the control of the potential of the first control end; the first node is connected with an ultrasonic sensor;

the first acquisition sub-circuit is connected with the first node and the second node and is used for controlling the potential of the second node according to the potential of the first node;

the second acquisition sub-circuit is connected with the first node and the third node and is used for controlling the potential of the third node according to the potential of the first node;

the conversion sub-circuit is connected with the second node and the third node and is used for outputting a first current signal according to the potential of the second node and outputting a second current signal according to the potential of the third node;

a subtracting sub-circuit for receiving the first current signal and the second current signal and outputting a third current signal according to the first current signal and the second current signal, wherein the third current signal is a difference value between the first current signal and the second current signal;

and the output subcircuit is used for transmitting the third current signal to a signal output end.

Further, the subtracting sub-circuit includes:

the control electrode of the first transistor is connected with the fourth node, the first electrode of the first transistor is used for receiving the first current signal, and the second electrode of the first transistor is connected with the first power supply end;

and the control electrode of the second transistor is connected with the fourth node, the first electrode of the second transistor is used for receiving the second current signal, and the second electrode of the second transistor is connected with the first power supply end.

Further, the output sub-circuit includes:

and a third transistor, a control electrode of the third transistor is connected with the scanning signal end, a first electrode of the third transistor is connected with a first electrode of the first transistor, and a second electrode of the third transistor is connected with the signal output end.

Further, the conversion sub-circuit includes:

a control electrode of the fourth transistor is connected with the second node, a first electrode of the fourth transistor is connected with a second power supply end, and a second electrode of the fourth transistor is used for outputting the first current signal;

and a control electrode of the fifth transistor is connected with the third node, a first electrode of the fifth transistor is connected with the second power supply end, and a second electrode of the fifth transistor is used for outputting the second current signal.

Further, the first acquisition sub-circuit includes:

a first switching device connected between the first node and the second node;

the first energy storage element is connected between the third power end and the second node.

Further, the first switching device includes:

and the control electrode of the sixth transistor is connected with the second control end, the first electrode of the sixth transistor is connected with the second node, and the second electrode of the sixth transistor is connected with the first node.

Further, the second acquisition sub-circuit includes:

a second switching device connected between the first node and the third node;

and the second energy storage element is connected between the third power supply end and the third node.

Further, the second switching device includes:

and a control electrode of the seventh transistor is connected with the third control end, a first electrode of the seventh transistor is connected with the third node, and a second electrode of the seventh transistor is connected with the first node.

Further, the bias subcircuit includes:

and the control electrode of the eighth transistor is connected with the first control end, the first electrode of the eighth transistor is connected with the first node, and the second electrode of the eighth transistor is connected with the bias signal end.

Further, the ultrasonic control circuit further includes:

and the third acquisition sub-circuit is connected with the output end of the output sub-circuit and is used for converting the output signal of the output sub-circuit into a voltage signal.

Further, the third acquisition sub-circuit includes:

the non-inverting input end of the operational amplifier is connected with the reference voltage end, and the inverting input end of the operational amplifier is connected with the output end of the output sub-circuit;

and the resistor is connected between the inverting input end of the operational amplifier and the output end of the operational amplifier.

According to one aspect of the present disclosure, there is provided an ultrasonic detection apparatus including:

the ultrasonic control circuit is used for controlling the ultrasonic wave;

and the ultrasonic sensor is connected with the first node of the ultrasonic control circuit.

According to an aspect of the present disclosure, there is provided a driving method of an ultrasonic control circuit, the driving method employing the ultrasonic control circuit, the driving method including:

the bias sub-circuit controls the bias signal terminal to be connected with the first node under the control of the potential of the first control terminal;

enabling the first acquisition sub-circuit to control the potential of the second node according to the potential of the first node;

enabling the second acquisition sub-circuit to control the potential of the third node according to the potential of the first node;

the conversion sub-circuit is enabled to output a first current signal according to the potential of the second node, and is enabled to output a second current signal according to the potential of the third node;

causing the subtracting sub-circuit to receive the first current signal and the second current signal and to output a third current signal according to the first current signal and the second current signal, the third current signal being a difference between the first current signal and the second current signal;

and enabling the output sub-circuit to transmit the third current signal to a signal output terminal.

The first acquisition sub-circuit is used for controlling the potential of the second node according to the potential of the first node; the second acquisition sub-circuit is used for controlling the potential of the third node according to the potential of the first node; the conversion sub-circuit is used for outputting a first current signal according to the potential of the second node and outputting a second current signal according to the potential of the third node; the subtracting sub-circuit is used for outputting a third current signal according to the first current signal and the second current signal, wherein the third current signal is the difference value of the first current signal and the second current signal, so that signal noise can be reduced, and detection accuracy is improved.

Drawings

Fig. 1 is a schematic diagram of an ultrasonic control circuit in the related art.

Fig. 2 is a block diagram of an ultrasound control circuit of an embodiment of the present disclosure.

Fig. 3 is a circuit diagram of an ultrasound control circuit of an embodiment of the present disclosure.

Fig. 4 is another circuit diagram of an ultrasound control circuit of an embodiment of the present disclosure.

Fig. 5 is a timing diagram of the operation of the ultrasound control circuit of an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of the structure of an ultrasonic control circuit of an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of the operation of an ultrasound control circuit of an embodiment of the present disclosure.

Fig. 8 is a schematic diagram of an arrangement with a plurality of ultrasonic sensors in an embodiment of the disclosure.

Reference numerals illustrate: 1. a bias subcircuit; 2. a first acquisition sub-circuit; 3. a second acquisition sub-circuit; 4. a conversion sub-circuit; 5. a subtracting sub-circuit; 6. an output sub-circuit; 7. a third acquisition sub-circuit; 8. a signal acquisition sub-circuit; 100. an ultrasonic control circuit; 200. a cover plate; vss, a first power supply terminal; vdd, a second power supply terminal; GND, the third power supply end; gate (n), scanning signal terminal; GND, the third power supply end; vrst, first control end; vbias, bias signal terminal; vclose1, the second control end; vclose2, the third control end; vout, signal output; vref1, reference voltage terminal; PF, ultrasonic sensor; 101. a first electrode; 102. a piezoelectric material layer; 103. a second electrode; r1, resistance; u1, an operational amplifier; ip, first current signal; in, a second current signal; Δi, third current signal; s1, a first switching device; s2, a second switching device; n1, a first node; n2, a second node; n3, a third node; n4, a fourth node; n5, a fifth node; n6, a sixth node; t1, a first transistor; t2, a second transistor;

t3, third transistor; t4, fourth transistor; t5, fifth transistor; t6, sixth transistor; t7, seventh transistor; t8, eighth transistor; t9, bias transistor.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus consistent with some aspects of the disclosure as detailed in the accompanying claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

Transistors used in the present disclosure may be transistors, thin film transistors, or field effect transistors or other devices of the same characteristics. In the embodiments of the present disclosure, in order to distinguish between two poles of a transistor except for a control pole, one of the poles is referred to as a first pole and the other pole is referred to as a second pole.

In actual operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

In actual operation, when the transistor is a thin film transistor, the thin film transistor may include a P-type thin film transistor that is turned on when the gate is at a low level, and an N-type thin film transistor that is turned off when the gate is at a high level, and is turned on when the gate is at a low level.

In the related art, as shown in fig. 1, the ultrasonic control circuit includes a bias transistor T9 and a signal acquisition sub-circuit 8. The bias transistor T9 is connected to the bias signal terminal Vbias, the first control terminal Vrst, and the first node N1, and is configured to control the bias signal terminal Vbias to be connected to the first node N1 under the control of the potential of the first control terminal Vrst. The first node N1 is connected to an ultrasonic sensor PF. The signal acquisition sub-circuit 8 is configured to output according to the potential of the first node N1. The ultrasonic control circuit may generate noise during operation. The noise of the ultrasonic control circuit includes reset noise, optical noise, thermal noise, 1/f noise, broadband noise, and noise generated by electromagnetic interference and crosstalk. The reset noise is noise caused by signal voltage jump when the first control terminal Vrst performs switching operation. The ultrasonic sensor PF is made of glass, light transmittance is strong, and a transistor in an ultrasonic control circuit is made of a polysilicon semiconductor, which is extremely susceptible to light and heat, so that on or off current fluctuates to generate optical noise and thermal noise. Due to the semiconductor material properties, the transistor has a high noise power density at low frequencies, and the noise gradually tends to smoothly form broadband noise up to 1/f frequency. The ultrasonic sensor PF may be noisy by electromagnetic interference in the environment.

The disclosed embodiments provide an ultrasonic control circuit. As shown in fig. 2 and 4, the ultrasound control circuit may include a bias voltage sub-circuit 1, a first acquisition sub-circuit 2, a second acquisition sub-circuit 3, a conversion sub-circuit 4, a subtraction sub-circuit 5, and an output sub-circuit 6, wherein:

the bias sub-circuit 1 is connected to a bias signal terminal Vbias, a first control terminal Vrst and a first node N1, and is configured to control the bias signal terminal Vbias to be connected to the first node N1 under the control of the potential of the first control terminal Vrst. The first node N1 is connected to an ultrasonic sensor PF. The first collecting sub-circuit 2 is connected to the first node N1 and the second node N2, and is configured to control the potential of the second node N2 according to the potential of the first node N1. The second acquisition sub-circuit 3 is connected to the first node N1 and the third node N3, and is configured to control the potential of the third node N3 according to the potential of the first node N1. The conversion sub-circuit 4 is connected to the second node N2 and the third node N3, and is configured to output a first current signal Ip according to the potential of the second node N2 and also configured to output a second current signal In according to the potential of the third node N3. The subtracting sub-circuit 5 is configured to receive the first current signal Ip and the second current signal In, and output a third current signal Δi according to the first current signal Ip and the second current signal In, where the third current signal Δi is a difference between the first current signal Ip and the second current signal In. The output sub-circuit 6 is arranged to transmit a third current signal Δi to the signal output Vout.

The ultrasonic control circuit of the embodiment of the present disclosure, the first acquisition sub-circuit 2 is configured to control the potential of the second node N2 according to the potential of the first node N1; the second acquisition sub-circuit 3 is used for controlling the potential of the third node N3 according to the potential of the first node N1; the conversion sub-circuit 4 is configured to output a first current signal Ip according to the potential of the second node N2, and is also configured to output a second current signal In according to the potential of the third node N3; the subtracting sub-circuit 5 is configured to output a third current signal Δi according to the first current signal Ip and the second current signal In, where the third current signal Δi is a difference between the first current signal Ip and the second current signal In, so that noise can be reduced, and detection accuracy can be improved.

The following describes each part of the ultrasonic control circuit of the embodiment of the present disclosure in detail:

as shown in fig. 2, the bias sub-circuit 1 is connected to a bias signal terminal Vbias, a first control terminal Vrst and a first node N1, and is configured to control the bias signal terminal Vbias to be connected to the first node N1 under the control of the potential of the first control terminal Vrst. The first node N1 is connected to an ultrasonic sensor PF. For example, as shown in fig. 4, the bias sub-circuit 1 may include an eighth transistor T8. The control electrode of the eighth transistor T8 is connected to the first control terminal Vrst, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is connected to the bias signal terminal Vbias.

As shown in fig. 3, the first collecting sub-circuit 2 may include a first switching device S1 and a first energy storage element. The first switching device S1 may be connected between the first node N1 and the second node N2. The first energy storage element is connected between the third power source GND and the second node N2. For example, as shown in fig. 4, the first switching device S1 may include a sixth transistor T6. The control electrode of the sixth transistor T6 is connected to the second control terminal Vclose1, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the first node N1. The first energy storage element may be a first capacitor C1, where one polar plate of the first capacitor C1 is connected to the third power supply end GND, and the other polar plate is connected to the second node N2. The third power terminal GND may be a ground terminal. After turning off the sixth transistor T6 through the second control terminal Vclose1, the potential of the second node N2 can be latched.

As shown in fig. 3, the second acquisition sub-circuit 3 may include a second switching device S2 and a second energy storage element. The second switching device S2 may be connected between the first node N1 and the third node N3. The second energy storage element may be connected between the third power source GND and the third node N3. For example, as shown in fig. 4, the second switching device S2 may include a seventh transistor T7. The control electrode of the seventh transistor T7 is connected to the third control terminal Vclose2, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the first node N1. The second energy storage element may be a second capacitor C2, where one electrode plate of the second capacitor C2 is connected to the third power supply end GND, and the other electrode plate is connected to the third node N3. After the seventh transistor T7 is turned off by the third control terminal Vclose2, the potential of the third node N3 can be latched. The distance between the first capacitor C1 and the second capacitor C2 in the present disclosure is tens of micrometers, so that the electromagnetic interference intensity is approximately equal, and thus the induced currents (noise) generated are approximately equal, so that the ultrasonic control circuit of the present disclosure can reduce the noise generated by the electromagnetic interference.

As shown In fig. 2 to 4, the conversion sub-circuit 4 is connected to the second node N2 and the third node N3, and is configured to output the first current signal Ip according to the potential of the second node N2 and further configured to output the second current signal In according to the potential of the third node N3. For example, the conversion sub-circuit 4 may include a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second power supply terminal Vdd, and the second electrode of the fourth transistor T4 is configured to output the first current signal Ip. The control electrode of the fifth transistor T5 is connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second power supply terminal Vdd, and the second electrode of the fifth transistor T5 is configured to output the second current signal In. The bias signal terminal Vbias may provide a bias voltage for the turn-on of the fourth transistor T4 and the fifth transistor T5. The second power supply terminal Vdd is used for providing a dc voltage to the fourth transistor T4 and the fifth transistor T5.

As shown In fig. 2-4, the subtracting sub-circuit 5 is configured to receive the first current signal Ip and the second current signal In, and output a third current signal Δi according to the first current signal Ip and the second current signal In, where the third current signal Δi is a difference between the first current signal Ip and the second current signal In. For example, the subtracting sub-circuit 5 may include a first transistor T1 and a second transistor T2. The control electrode of the first transistor T1 is connected to the fourth node N4, the first electrode of the first transistor T1 is configured to receive the first current signal Ip, and the second electrode of the first transistor T1 is connected to the first power supply terminal Vss. The control electrode of the second transistor T2 is connected to the fourth node N4, the first electrode of the second transistor T2 is configured to receive the second current signal In, and the second electrode of the second transistor T2 is connected to the first power supply terminal Vss. It is known that the subtracting sub-circuit 5 is a mirrored current source circuit. The first power supply terminal Vss can provide a negative dc signal.

As shown in fig. 4, for the subtracting sub-circuit 5 described above, the first current signal Ip output from the fourth transistor T4 flows to the sixth node N6, and is divided into two current signals from the sixth node N6, one of which flows to the first pole of the first transistor T1, and the other flows to the output sub-circuit 6 as the third current signal Δi; the second current signal In output by the fifth transistor T5 flows to the fifth node N5, and is divided into two current signals from the fifth node N5, one current signal Ic flows to the first pole of the second transistor T2, and the other current signal Ib flows to the fourth node N4, where in=ic+ib; since the voltages of the control electrodes of the second transistor T2 and the first transistor T1 are the same, ic=id, and since the resistances of the control electrodes of the second transistor T2 and the first transistor T1 are very large, reaching the order of several hundred megaohms, the value of Ib is small, and thus in=ic+ib≡ic=id, so that the third current signal Δi flowing from the fifth node N5 to the output sub-circuit 6 is equal to (Ip-In).

As shown in fig. 2-4, the output sub-circuit 6 is configured to transmit a third current signal Δi to the signal output terminal Vout. For example, the output sub-circuit 6 may include a third transistor T3. The control electrode of the third transistor T3 is connected to the scan signal terminal Gate (n), the first electrode of the third transistor T3 is connected to the first electrode of the first transistor T1, and the second electrode of the third transistor T3 is connected to the signal output terminal Vout.

As shown in fig. 2 and 4, the ultrasound control circuit of the embodiments of the present disclosure may further include a third acquisition sub-circuit 7. The third acquisition sub-circuit 7 may be connected to the output of the output sub-circuit 6 and is adapted to convert the output signal of the output sub-circuit 6 into a voltage signal. For example, the third acquisition sub-circuit 7 may include an operational amplifier U1 and a resistor R1. The non-inverting input terminal of the operational amplifier U1 is connected to the reference voltage terminal Vref1, and the inverting input terminal of the operational amplifier U1 is connected to the output terminal of the output sub-circuit 6. The resistor R1 is connected between the inverting input terminal of the operational amplifier U1 and the output terminal of the operational amplifier U1, i.e., one end of the resistor R1 is connected with the inverting input terminal of the operational amplifier U1, and the other end of the resistor R1 is connected with the output terminal of the operational amplifier U1.

The embodiment of the disclosure also provides a driving method of the ultrasonic control circuit. The driving method adopts the ultrasonic control circuit of any one of the embodiments. The driving method may include:

the bias sub-circuit 1 is connected with a first node N1 by controlling a bias signal terminal Vbias under the control of the potential of a first control terminal Vrst;

the first acquisition sub-circuit 2 is enabled to control the potential of the second node N2 according to the potential of the first node N1;

causing the second acquisition sub-circuit 3 to control the potential of the third node N3 according to the potential of the first node N1;

causing the conversion sub-circuit 4 to output a first current signal Ip according to the potential of the second node N2, and also causing the conversion sub-circuit 4 to output a second current signal In according to the potential of the third node N3;

causing the subtracting sub-circuit 5 to receive the first current signal Ip and the second current signal In and to output a third current signal Δi according to the first current signal Ip and the second current signal In, the third current signal Δi being a difference value of the first current signal Ip and the second current signal In;

the output sub-circuit 6 is caused to transmit the third current signal Δi to the signal output terminal Vout.

The operation of the ultrasonic control circuit in fig. 4 will be described in detail with reference to the operation timing diagram of the ultrasonic control circuit shown in fig. 5, and the above-mentioned all transistors are N-type thin film transistors, and the on-levels of all the transistors are high. The echo signal is received by the ultrasonic sensor PF, converted into an electrical signal, and the signal is acquired at the falling edge of the first control terminal Vrst. RGD in the timing diagram indicates a time interval, specifically, a time taken from the start of ultrasonic wave generation to the reception of a return wave.

As shown In fig. 5, in the first stage, when the third control terminal Vclose2 and the first control terminal Vrst become high at the same time, the seventh transistor T7 and the eighth transistor T8 are both turned on, and after an RGD time interval passes from the start time of the first stage, the first control terminal Vrst enters a falling edge, the second acquisition sub-circuit 3 acquires the first signal at the falling edge of the first control terminal Vrst, the acquired first signal is a system base value, the acquired first signal is written into the third node N3 and held by the second capacitor C2, and the fifth transistor T5 converts the first signal into the second current signal In. The second control terminal Vclose1 is in a low state in the first stage, and the sixth transistor T6 is always turned off.

As shown in fig. 5, in the second stage, there is an echo signal, the third control terminal Vclose2 is in a low level state, and the seventh transistor T7 is turned off; when the second control terminal Vclose1 and the first control terminal Vrst become high at the same time, the sixth transistor T6 and the eighth transistor T8 are both turned on, and the first control terminal Vrst enters a falling edge after an RGD time interval from a start time of the second stage, the first collecting sub-circuit 2 collects a second signal at the falling edge of the first control terminal Vrst, the second signal is an echo peak signal, the collected second signal is written into the second node N2 and is held by the first capacitor C1, and the fourth transistor T4 converts the second signal into the first current signal Ip. The first current signal Ip and the second current signal In are subtracted by the subtracting sub-circuit 5, and the subtracting sub-circuit 5 outputs a third current signal Δi. When the scan signal terminal Gate (n) is at a high level, the third current signal Δi is read out through the third transistor T3 and the third acquisition sub-circuit 7.

In the related art, in order to acquire a system base value and an echo signal, two frames of data are required, one frame is the system base value corresponding to the RGD time, the other frame is the echo signal corresponding to the RGD time, and the two frames of data are required to be acquired, converted and transmitted and subjected to image processing (subtraction processing) in an upper computer. By adopting the ultrasonic control circuit and the time sequence, two frames are changed into one frame, the time of the image processing step of the upper computer is reduced, the data throughput is greatly reduced, and the transmission frame rate is improved.

Simulation test

1. Voltage simulation

When the voltages of the gates of the fourth transistor T4 and the fifth transistor T5 are 3V, the voltage output from the signal output terminal Vout is-1V, wherein the signal input from Vref1 to the operational amplifier U1 is-1V, and Δi is equal to about 0A by the formula "vout=ref- Δi×r1".

When the voltage of the gate electrode of the fourth transistor T4 is 3.1V and the voltage of the gate electrode of the fifth transistor T5 is 3V, the voltage outputted from the signal output terminal Vout is approximately equal to-1.59V, and Δi is 5.9 μa.

2. Current simulation

When the gate voltage of the fourth transistor T4 is 3.1V and the gate voltage of the fifth transistor T5 is 3V, the values of Ic and Id are both 160 μa, the first current signal Ip is 165.9 μa, Δi=ip-in=5.9 μa, and the current simulation result matches the voltage simulation result.

The embodiment of the disclosure also provides an ultrasonic detection device. As shown in fig. 2 and 6, the ultrasonic detection device may include an ultrasonic sensor PF and the ultrasonic control circuit 100 of any of the above embodiments. The ultrasonic sensor PF is connected to a first node N1 of the ultrasonic control circuit 100. As shown in fig. 6, the ultrasonic sensor PF includes a first electrode 101 and a second electrode 103 disposed opposite to each other, and a piezoelectric material layer 102 between the first electrode 101 and the second electrode 103. One of the first electrode 101 and the second electrode 103 may be grounded, and the other may serve as an echo receiving terminal. The material of the piezoelectric material layer 102 may be PVDF film type piezoelectric material, or may be other inorganic or organic piezoelectric material such as AlN, PZT, znO. The ultrasound control circuit 100 may be provided on a side of the layer 102 of piezoelectric material facing away from the first electrode 101. The ultrasonic detection device may also include a cover plate 200. The cover 200 may be provided on a side of the ultrasound control circuit 100 facing away from the first electrode 101. The cover 200 may be a glass cover. Fig. 7 shows the operation of the ultrasonic probe. The PZT piezoelectric ceramic sound source generates large energy, and the PZT piezoelectric ceramic sound source is used to emit an excitation signal, and when the sound wave is reflected to the piezoelectric material layer 102, the excitation signal is converted into an Alternating Current (AC) voltage, and the electrode serving as the echo receiving end outputs a corresponding signal.

As shown in fig. 8, the ultrasonic detection device of the present disclosure may include a plurality of ultrasonic sensors PF distributed in an array to constitute a plurality of sensor rows. The number of the ultrasonic control circuits 100 is also plural, and is connected to the plural ultrasonic sensors PF in one-to-one correspondence. When the ultrasonic control circuit 100 is used to acquire the signals of the plurality of ultrasonic sensors PF, the gate of the third transistor T3 may be turned on line by line in a line scanning manner, that is, on line by line. Taking N as 1000 in fig. 8 as an example, a progressive scanning method is adopted, and about 1.3s is required. For a single ultrasound control circuit 100, the signals stored at the second node N2 and the third node N3 will decrease over time within 1.6 s. The first capacitor C1 and the second capacitor C2 have good uniformity, and the leakage is approximately equal. As the signals of the second node N2 and the third node N3 decrease continuously over time, the third current signal Δi is equal to (Ip-In), and since (Ip-In) is approximately unchanged, the ultrasound control circuit 100 of the present disclosure is not affected by the voltage holding capability, thereby realizing the voltage drop compensation function.

The ultrasonic detection device, the ultrasonic control circuit and the driving method of the ultrasonic control circuit provided by the embodiment of the disclosure belong to the same inventive concept, and descriptions of related details and beneficial effects can be referred to each other, and are not repeated.

The foregoing disclosure is not intended to be limiting, but rather is to be construed as limited to the preferred embodiments, and is intended to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.

Claims (13)

1. An ultrasonic control circuit, comprising:

the bias voltage subcircuit is connected with a bias voltage signal end, a first control end and a first node and is used for controlling the bias voltage signal end to be connected with the first node under the control of the potential of the first control end; the first node is connected with an ultrasonic sensor;

the first acquisition sub-circuit is connected with the first node and the second node and is used for controlling the potential of the second node according to the potential of the first node;

the second acquisition sub-circuit is connected with the first node and the third node and is used for controlling the potential of the third node according to the potential of the first node;

the conversion sub-circuit is connected with the second node and the third node and is used for outputting a first current signal according to the potential of the second node and outputting a second current signal according to the potential of the third node;

a subtracting sub-circuit for receiving the first current signal and the second current signal and outputting a third current signal according to the first current signal and the second current signal, wherein the third current signal is a difference value between the first current signal and the second current signal;

and the output subcircuit is used for transmitting the third current signal to a signal output end.

2. The ultrasound control circuit of claim 1, wherein the subtraction sub-circuit comprises:

the control electrode of the first transistor is connected with the fourth node, the first electrode of the first transistor is used for receiving the first current signal, and the second electrode of the first transistor is connected with the first power supply end;

and the control electrode of the second transistor is connected with the fourth node, the first electrode of the second transistor is used for receiving the second current signal, and the second electrode of the second transistor is connected with the first power supply end.

3. The ultrasonic control circuit of claim 2, wherein the output sub-circuit comprises:

and a third transistor, a control electrode of the third transistor is connected with the scanning signal end, a first electrode of the third transistor is connected with a first electrode of the first transistor, and a second electrode of the third transistor is connected with the signal output end.

4. The ultrasound control circuit of claim 1 or 2, wherein the conversion sub-circuit comprises:

a control electrode of the fourth transistor is connected with the second node, a first electrode of the fourth transistor is connected with a second power supply end, and a second electrode of the fourth transistor is used for outputting the first current signal;

and a control electrode of the fifth transistor is connected with the third node, a first electrode of the fifth transistor is connected with the second power supply end, and a second electrode of the fifth transistor is used for outputting the second current signal.

5. The ultrasound control circuit of claim 1, wherein the first acquisition sub-circuit comprises:

a first switching device connected between the first node and the second node;

the first energy storage element is connected between the third power end and the second node.

6. The ultrasonic control circuit of claim 5, wherein the first switching device comprises:

and the control electrode of the sixth transistor is connected with the second control end, the first electrode of the sixth transistor is connected with the second node, and the second electrode of the sixth transistor is connected with the first node.

7. The ultrasound control circuit of claim 1, wherein the second acquisition sub-circuit comprises:

a second switching device connected between the first node and the third node;

and the second energy storage element is connected between the third power supply end and the third node.

8. The ultrasonic control circuit of claim 7, wherein the second switching device comprises:

and a control electrode of the seventh transistor is connected with the third control end, a first electrode of the seventh transistor is connected with the third node, and a second electrode of the seventh transistor is connected with the first node.

9. The ultrasonic control circuit of claim 1, wherein the bias sub-circuit comprises:

and the control electrode of the eighth transistor is connected with the first control end, the first electrode of the eighth transistor is connected with the first node, and the second electrode of the eighth transistor is connected with the bias signal end.

10. The ultrasonic control circuit of claim 1, wherein the ultrasonic control circuit further comprises:

and the third acquisition sub-circuit is connected with the output end of the output sub-circuit and is used for converting the output signal of the output sub-circuit into a voltage signal.

11. The ultrasound control circuit of claim 10, wherein the third acquisition sub-circuit comprises:

the non-inverting input end of the operational amplifier is connected with the reference voltage end, and the inverting input end of the operational amplifier is connected with the output end of the output sub-circuit;

and the resistor is connected between the inverting input end of the operational amplifier and the output end of the operational amplifier.

12. An ultrasonic detection device, comprising:

the ultrasound control circuit of any one of claims 1-11;

and the ultrasonic sensor is connected with the first node of the ultrasonic control circuit.

13. A driving method of an ultrasonic control circuit, characterized in that the driving method employs the ultrasonic control circuit according to any one of claims 1 to 11, the driving method comprising:

the bias sub-circuit controls the bias signal terminal to be connected with the first node under the control of the potential of the first control terminal;

enabling the first acquisition sub-circuit to control the potential of the second node according to the potential of the first node;

enabling the second acquisition sub-circuit to control the potential of the third node according to the potential of the first node;

the conversion sub-circuit is enabled to output a first current signal according to the potential of the second node, and is enabled to output a second current signal according to the potential of the third node;

causing the subtracting sub-circuit to receive the first current signal and the second current signal and to output a third current signal according to the first current signal and the second current signal, the third current signal being a difference between the first current signal and the second current signal;

and enabling the output sub-circuit to transmit the third current signal to a signal output terminal.