CN117795684A

CN117795684A - Semiconductor device with shielding element

Info

Publication number: CN117795684A
Application number: CN202380013133.XA
Authority: CN
Inventors: 孙超; 江宁; 刘威
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-01-28
Filing date: 2023-02-14
Publication date: 2024-03-29
Also published as: US20230245980A1; EP4437591A1

Abstract

A semiconductor device is provided. For example, the semiconductor device may include a plurality of transistors arranged in an array in an X-Y plane. Each of the transistors may include a channel extending in the Z-direction. The semiconductor device may further include a plurality of word lines. Each of the word lines may electrically connect adjacent ones of the transistors arranged in columns in the X-direction at lateral walls of a channel of the transistor. The semiconductor device may further include one or more electromagnetic shielding elements. At least one of the electromagnetic shielding elements may be disposed between adjacent two of the transistors disposed in a row in the Y direction.

Description

Semiconductor device with shielding element

Cross Reference to Related Applications

This application claims priority from chinese application No. 2022101083896 filed on 28, 1, 2022, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to semiconductor memories, and more particularly, to semiconductor devices having shielding elements.

Background

As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers have continually sought techniques for stacking memory cells in multiple planes to achieve greater memory capacity and lower cost per bit. A 3D NAND memory device is an exemplary device that stacks multiple planes of memory cells to achieve greater storage capacity and lower cost per bit. The 3D NAND memory device may include a stack of alternating insulating layers and word line layers over a substrate and a slit structure.

Disclosure of Invention

Aspects of the present disclosure provide a method for manufacturing a semiconductor device. For example, the method may include: a plurality of transistors arranged in an array in an X-Y plane is formed. Each of the transistors may include a channel extending in the Z-direction. The method may further comprise: a plurality of word lines are formed. Each of the word lines may electrically connect adjacent ones of the transistors at lateral walls of a channel of the transistors. Adjacent ones of the transistors may be arranged in columns in the X-direction. The method may further comprise: one or more electromagnetic shielding elements are formed. Each of the electromagnetic shielding elements may be disposed between adjacent two of the transistors disposed in a row in the Y direction.

In an embodiment, each of the transistors may further include a source electrode disposed on a first end of the channel and a drain electrode disposed on a second end of the channel, and the electromagnetic shielding element may have a projection onto the channel in the Y direction, the projection not overlapping the source and drain electrodes. In another embodiment, the electromagnetic shielding element may be shorter than the channels of the two adjacent transistors in the Z-direction. In some embodiments, the electromagnetic shielding element may also be disposed between two adjacent ones of the transistors disposed in a column.

In an embodiment, each of the channels of the transistor may be rectangular columnar, and each of the word lines may be formed at a lateral wall of a corresponding one of the rectangular columnar channels. For example, the lateral walls of rectangular pillar-shaped channels of two adjacent transistors on which the word lines are formed may face in opposite directions.

In an embodiment, the method may further comprise: an electromagnetic shield contact pad connected to one of the electromagnetic shield elements is formed, and a word line contact pad connected to one of the word lines adjacent to the electromagnetic shield element is formed. The electromagnetic shield contact pads and the word line contact pads may be disposed on opposite sides of the array in the X-direction. In an embodiment, the electromagnetic shielding element and the word line may be formed by: forming a first recess in a substrate of the semiconductor device on a back side thereof for forming a contact pad in the first recess, and filling the first recess with an oxide, forming a second recess and a third recess in the substrate for forming a word line and an electromagnetic shielding element in the second recess and the third recess, respectively, the third recess being in contact with the first recess, filling the second recess with a first conductor for forming the word line, thinning the back side of the semiconductor device to expose the oxide filled in the first recess, recessing the oxide to expose a lateral wall of the third recess, and filling the third recess and the first recess with a second conductor for forming the electromagnetic shielding element and the contact pad, respectively.

Aspects of the present disclosure also provide a semiconductor device. For example, the semiconductor device may include: a plurality of transistors arranged in an array in an X-Y plane. Each of the transistors may include a channel extending in the Z-direction. The semiconductor device may further include a plurality of word lines. Each of the word lines may electrically connect adjacent ones of the transistors arranged in columns in the X-direction at lateral walls of a channel of the transistor. The semiconductor device may further include one or more electromagnetic shielding elements. Each of the electromagnetic shielding elements may be disposed between two adjacent ones of the transistors that are disposed in a row in the Y direction.

In an embodiment, the semiconductor device may further include: an electromagnetic shield contact pad connected to one of the electromagnetic shield elements and a word line contact pad connected to one of the word lines adjacent to the electromagnetic shield element. The electromagnetic shield contact pads and the word line contact pads may be disposed on opposite sides of the array in the X-direction.

In an embodiment, at least one of the electromagnetic shielding elements may comprise a plurality of electromagnetic shielding segments spaced apart from each other. For example, the electromagnetic shielding segments may be arranged in the X-direction, the Y-direction, and/or the Z-direction.

In an embodiment, at least one of the electromagnetic shielding elements may be applied with a first voltage that is less than a second voltage applied to a corresponding one of the channels. In some embodiments, at least one of the electromagnetic shielding elements may be applied with a voltage such that a first transistor of the two adjacent transistors between which the electromagnetic shielding element is disposed is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element and a second electromagnetic field generated by a second transistor of the two adjacent transistors.

Aspects of the present disclosure also provide a memory system. For example, the memory system may include a semiconductor device and control circuitry coupled to the semiconductor device. The control circuitry may be configured to control operation of the semiconductor device. The semiconductor device may include a plurality of transistors arranged in an array in an X-Y plane. Each of the transistors may include a channel extending in the Z-direction. The semiconductor device may further include a plurality of word lines. Each of the word lines may electrically connect adjacent ones of the transistors arranged in columns in the X-direction at lateral walls of a channel of the transistor. The semiconductor device may further include one or more electromagnetic shielding elements. Each of the electromagnetic shielding elements may be disposed between adjacent two of the transistors disposed in a row in the Y direction.

Drawings

Aspects of the disclosure may be understood from the following detailed description when read in conjunction with the accompanying drawings. Note that the various features are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

FIG. 1A is a schematic diagram of a planar transistor;

FIG. 1B is a schematic diagram of a buried channel transistor;

fig. 2 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

fig. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

fig. 4A is a top view illustrating formation of a pillar-shaped channel of a semiconductor device according to some embodiments of the present disclosure;

fig. 4B is a schematic diagram illustrating formation of a pillar-shaped channel of a semiconductor device according to some embodiments of the present disclosure;

fig. 4C is a top view illustrating the formation of an insulating layer of a semiconductor device according to some embodiments of the present disclosure;

fig. 4D is a top view illustrating formation of a second recess and a third recess of a semiconductor device according to some embodiments of the present disclosure;

fig. 4E is a top view illustrating the formation of a gate oxide layer of a semiconductor device according to some embodiments of the present disclosure;

fig. 4F is a top view illustrating the formation of electromagnetic shielding elements and word lines of a semiconductor device according to some embodiments of the present disclosure;

fig. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

Fig. 6A is a top view illustrating formation of a pillar-shaped channel of a semiconductor device according to some embodiments of the present disclosure;

fig. 6B is a top view illustrating the formation of an insulating layer of a semiconductor device according to some embodiments of the present disclosure;

fig. 6C is a top view illustrating formation of a second recess and a third recess of a semiconductor device according to some embodiments of the present disclosure;

fig. 6D is a top view illustrating the formation of a gate oxide layer of a semiconductor device according to some embodiments of the present disclosure;

fig. 6E is a top view illustrating the formation of a metal layer and a gate of a semiconductor device according to some embodiments of the present disclosure;

fig. 7 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

fig. 8 is a top view illustrating the formation of contact pads of a semiconductor device according to some embodiments of the present disclosure;

fig. 9 is a top view illustrating the formation of another contact pad of a semiconductor device in accordance with some embodiments of the present disclosure;

fig. 9A is a top view illustrating the formation of yet another contact pad of a semiconductor device in accordance with some embodiments of the present disclosure;

fig. 10A-10H are cross-sectional views of semiconductor devices having electromagnetic shielding elements of various configurations according to some embodiments of the present disclosure;

Fig. 11A-11E are various cross-sectional views of a semiconductor device having electromagnetic shielding elements of various configurations according to some embodiments of the present disclosure;

fig. 12A to 12C are cross-sectional views illustrating fabrication of a semiconductor device according to some embodiments of the present disclosure; and is also provided with

Fig. 13 illustrates a block diagram of a memory system, according to some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Although specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. One skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be employed in a variety of other applications.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a" or "an" may also be understood to convey a singular usage or a plural usage, depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to convey a set of exclusive factors, but rather may allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only "directly on something" but also includes "on something" with intermediate features or layers therebetween. Furthermore, "above … …" or "over … …" not only means "above" or "over" something, but may also include its meaning "above" or "over" something without intermediate features or layers therebetween (i.e., directly on something).

Further, spatially relative terms such as "under … …," "below … …," "lower," "above … …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated. In addition to the orientations depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use or process steps. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where the semiconductor device is formed, and thus, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive and contact layers in which contacts, interconnect lines, and/or vertical interconnect VIAs (VIA) are formed, and one or more dielectric layers.

As used herein, the term "nominal" refers to desired or target values, as well as ranges of values above and/or below desired values, of a property or parameter set for a component or process step during a design phase of a product or process. As used herein, a range of values may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given amount of value that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a given amount of a value that varies within, for example, 10-30% of the value (e.g., ±10%, ±20% or ±30% of the value).

In this disclosure, the term "horizontal/lateral/transverse" means nominally parallel to the lateral surface of the substrate, and the term "vertical/vertical" means nominally perpendicular to the lateral surface of the substrate.

As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having vertically oriented memory cell transistor strings (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate.

In the related art, array transistors of the mainstream memory include a planar array transistor and a Buried Channel Array Transistor (BCAT). Fig. 1A and 1B are schematic diagrams showing a planar array transistor 100A and a BCAT 100B, respectively. As shown in fig. 1A, the transistor of the planar array transistor 100A includes a gate G, and a source S (/ D) and a drain D (/ S) formed on two substantially horizontal sides of the gate G. As shown in fig. 1B, the transistor of the BCAT 100B includes a gate G, and a source S (/ D) and a drain D (/ S) also formed on two substantially horizontal sides of the gate G. Since the source S (/ D) and the drain D (/ S) occupy positions that do not overlap the gate G, both the planar array transistor 100A and the BCAT 100B have large areas.

In the planar array transistor 100A and the BCAT 100B, since the source S (/ D) and the drain D (/ S) are located at two substantially horizontal sides of the gate G, the Bit Line (BL) and the capacitor of the memory must be located at the same side as the gate G. In a subsequent process, BL, transistor and capacitor must be connected to each other, and the transistor must also be connected to a Word Line (WL). Therefore, both the planar array transistor 100A and the BCAT 100B have a complicated circuit layout and are difficult to manufacture.

In the planar array transistor 100A in fig. 1A and the BCAT 100B in fig. 1B, only one transistor is shown. The planar array transistor 100A and BCAT 100B may include any number of transistors in accordance with the present disclosure.

Aspects of the present disclosure provide a semiconductor device. Referring to fig. 2, fig. 2 is a schematic diagram of a semiconductor device 200 according to some embodiments of the present disclosure. The semiconductor device 200 may include a plurality of transistors 210 arranged in an array in an X-Y plane. For example, the array may include a plurality of rows arranged along a first direction (e.g., an X-direction) and a plurality of columns intersecting the rows and arranged along a second direction (e.g., a Y-direction). Each of the transistors 210 may include a channel 211, and the channels 211 of the transistors 210 are arranged in an array along a first direction and a second direction. In an embodiment, each of the channels 211 may be in the shape of a pillar and may extend in a third direction (e.g., a Z direction) perpendicular to a plane defined by the first and second directions. For example, the post may have a cross-section in the shape of a rectangle, a circle, a diamond, or any other polygon. In an embodiment, the pillar-shaped channel 211 located in each of the columns of the array may be sequentially formed with an oxide layer 215 and a word line 214 at lateral walls thereof, and thus may be connected to each other by the word line 214, both the oxide layer 215 and the word line 214 extending in a first direction (e.g., X-direction). In an embodiment, the source electrode 212 and the drain electrode 213 may be respectively formed at both ends of each of the pillar-shaped channels 211. In some embodiments, the source 212 and drain 213 are interchangeable. Since the source electrode 212 and the drain electrode 213 are formed at both ends of each of the pillar-shaped channels 211, instead of at both sides of each of the word lines (i.e., the gate electrodes) 214, the semiconductor device 200 has a greater transistor density as compared to a semiconductor device including the planar semiconductor device 100A or the BCAT 100B, as shown in fig. 1A and 1B, each of the planar semiconductor device 100A or the BCAT 100B includes a transistor having a source electrode and a drain electrode formed at substantially horizontal sides of the gate electrode.

In the semiconductor device 200, where each of the word lines 214 is formed on only one lateral wall of a corresponding one of the pillar trenches 211, any one of the pillar trenches 211 (e.g., rectangular pillar trench 211 ') that is coupled to an unselected word line 214 (e.g., word line 214') adjacent to the selected word line (e.g., word line 214 ") will be affected by the selected word line 214". For example, the activity of an adjacent selected word line 214 "may change the charge accumulated in a transistor including a channel 211 'connected to an unselected word line 214', and the information stored in the transistor may be affected by the so-called row hammer effect (Row Hammer Effect).

Referring to fig. 3, fig. 3 is a cross-sectional view of the semiconductor device 200 in fig. 2 along a cutting line BB'. When the selected word line WL1 connected to the rectangular pillar channel CH1 is activated, another rectangular pillar channel CH2 adjacent to the pillar channel CH1 will be disturbed, and thus, the performance of the semiconductor device 200 is affected. Further improvements in the semiconductor device 200 are therefore desirable.

Aspects of the present disclosure provide a method for manufacturing a semiconductor device. Fig. 4 is a flowchart of a method 400 for manufacturing a semiconductor device (e.g., semiconductor device 400A shown in fig. 4A-4F or semiconductor device 500 shown in fig. 5) according to some embodiments of the present disclosure. The method 400 may include steps S410 to S440.

At step S410, a plurality of transistors (e.g., transistors of the semiconductor device 400A) are formed on a surface of a wafer (e.g., wafer 409 shown in fig. 4A). In an embodiment, the transistors may be arranged in an array, and the array may include a plurality of rows arranged along a first direction (e.g., an X-direction) parallel to the surface of the wafer 409 and a plurality of columns intersecting the rows and arranged along a second direction (e.g., a Y-direction) parallel to the surface of the wafer 409. For example, the first direction and the second direction may include an included angle of less than or equal to 90 degrees. Each of the transistors may include a channel (e.g., channel 401 shown in fig. 4A) extending in a third direction (e.g., Z-direction) perpendicular to the first direction, the second direction, and the surface of wafer 409. In some embodiments, at least one of the channels 401 may be in the shape of a pillar. In embodiments, the post may have a cross-section in the shape of a rectangle, diamond, circle, or any other polygon. For example, the columnar channels 401 may extend in a third direction perpendicular to a plane defined by the first direction and the second direction (e.g., a surface of the wafer 409).

At step S420, a plurality of word lines (e.g., word line 407 shown in fig. 4F) are formed on the lateral walls of the pillar channel 401 of the transistor. In an embodiment, each of the word lines 407 may electrically connect one or more of the transistors adjacent to each other and arranged in columns in a first direction (e.g., X-direction) at a lateral wall of the transistor. In an embodiment, the word lines 407 each extend in the X-direction and are parallel to the X-direction, and are arranged in the Y-direction.

At step S430, an electromagnetic shielding element (e.g., electromagnetic shielding element 408 shown in fig. 4F) is formed between at least adjacent two of the columnar channels 401 of the transistors arranged in a row in the Y direction. In an embodiment, the electromagnetic shielding element 408 may extend in the X-direction.

At step S440, a source and a drain (e.g., source 504 and drain 503 shown in fig. 5) are formed at both ends of each of the pillar-shaped channels 401 of the transistor. In some embodiments, the electromagnetic shielding element 504 has a projection onto the channel 211 in the Y-direction that does not overlap with the source 212 and drain 213.

In an embodiment, the wafer 409 may be a single crystal silicon material, e.g., a single crystal silicon ingot, used to fabricate the semiconductor device 400A. A single crystal silicon ingot (e.g., in the shape of a cylinder) may be ground, polished, and sliced to form a plurality of circular silicon plates (i.e., wafers). In another embodiment, wafer 409 may have two opposing rounded surfaces, one of which is the above-mentioned surface of wafer 409, and the other of which may be referred to as the backside surface of wafer 409, according to some embodiments of the present disclosure.

Fig. 4A-4F illustrate fabrication of a semiconductor device (e.g., semiconductor device 400A) at an intermediate stage according to some embodiments of the present disclosure. In the semiconductor device 400A, word lines are formed on lateral walls of any two adjacent transistors (or channels) facing in different directions.

Fig. 4A is a top view of a semiconductor device 400A illustrating the formation of a channel of a transistor of the semiconductor device 400A, in accordance with some embodiments of the present disclosure. As shown in fig. 4A, a plurality of channels 401 arranged in an array in an X-Y plane are formed on the surface of a wafer 409, for example. For example, the array may include a plurality of rows arranged along a first direction (e.g., an X-direction) and a plurality of columns intersecting the rows and arranged along a second direction (e.g., a Y-direction). In an embodiment, as shown in fig. 4B, fig. 4B is a schematic diagram illustrating formation of pillar-shaped trenches 401 of a semiconductor device 400A according to some embodiments of the present disclosure, each of the trenches 401 may be in the shape of a pillar (e.g., a rectangular pillar), and each of the rectangular pillar-shaped trenches 401 may extend in a third direction (e.g., a Z-direction) perpendicular to a plane defined by the first and second directions.

In some embodiments, columnar channels 401 may be formed on the surface of wafer 409 by: a mask (not shown) covering a certain region of the wafer 409 for forming the columnar channels 401 is used to cover the wafer 409; etching the wafer 409 to a depth (which is less than the thickness of the wafer 409) to form the first recess 402; and the mask is removed to form the columnar channels 401 whose lateral walls are exposed. In some embodiments, wafer 409 may be etched by using Photolithography (PH) or dry Etching (ET), such as electron beam lithography, plasma etching, and Reactive Ion Etching (RIE).

Fig. 4C is a top view illustrating the formation of an insulating layer of a semiconductor device 400A according to some embodiments of the present disclosure. In some embodiments, an insulating material (e.g., siO ₂ ) Is deposited in the first recess 402 to form an insulating layer 403 covering the first recess 402 and the lateral walls of the pillar-shaped channel 401. In some embodiments, chemical Mechanical Polishing (CMP) may then be employed to polish and remove the remaining insulating material to expose the top surfaces of the pillar-shaped channels 401.

Fig. 4D is a top view illustrating formation of second and third grooves of a semiconductor device 400A according to some embodiments of the present disclosure. In an embodiment, the insulating layer 403 may be etched to form a second groove 404 and a third groove 405, the second groove 404 exposing one of the lateral walls of each of the columnar channels 401 (e.g., rectangular columnar channels 401), and each of the third grooves 405 being disposed in a row in the Y direction between two adjacent transistors (i.e., two adjacent rectangular columnar channels 401). In some embodiments, each of the second grooves 404 may expose lateral walls of the pillar-shaped channels 401 of transistors adjacent to each other and arranged in columns in the X-direction. In an embodiment, as shown in fig. 4D, the lateral walls of two adjacent rectangular columnar channels 401 exposed by corresponding two of the second grooves 404 may face in opposite directions. In another embodiment, the lateral walls of two adjacent rectangular columnar channels 401 exposed by corresponding two of the second grooves 404 may face the same direction. In some embodiments, as shown in fig. 4D, a third groove 405 and each of two second grooves 404 (between which the third groove 405 is disposed) are disposed at opposite lateral walls of the rectangular columnar channel 401.

Fig. 4E is a top view illustrating the formation of a gate oxide layer of a semiconductor device 400A according to some embodiments of the present disclosure. In an embodiment, the lateral walls of the rectangular columnar channels 401 exposed by the second grooves 404 may be oxidized, for example, by direct oxidation, basic oxidation, or acidic oxidation, to form gate oxide layers 406 on the exposed lateral walls of the rectangular columnar channels 401. For example, the lateral walls of the rectangular columnar channels 401 exposed by the second grooves 404 may be directly heated and oxidized such that silicon in the lateral walls reacts with air containing an oxidized material at a high temperature, thereby forming a silicon oxide film, i.e., a gate oxide layer 460, on the lateral walls of the rectangular columnar channels 401. In some embodiments, the gate oxide layer 406 may include an insulating material, such as silicon dioxide (SiO ₂ )。

Fig. 4F is a top view illustrating the formation of electromagnetic shielding elements and word lines of a semiconductor device 400A according to some embodiments of the present disclosure. In an embodiment, the third recess 405 and the second recess 404 may be filled with a metal material to form the electromagnetic shielding element 408 and the word line (or gate) 407, respectively. Thus, the word line 407 and the electromagnetic shielding element 408 can be formed in a single deposition step. In a certain embodiment, the metallic material may include, but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other suitable metallic materials. In an embodiment, the electromagnetic shielding element 408 may be made of polysilicon. In an embodiment, each of the word lines 407 may electrically connect adjacent ones of the transistors arranged in columns in the X-direction at lateral walls of the pillar channel 401 of the transistor. In an embodiment, a gate oxide layer 406 is disposed between the pillar channel 401 and the word line 407 to isolate the word line 407 from the pillar channel 401 and prevent charge leakage. In an embodiment, as shown in fig. 4F, the lateral walls of two adjacent rectangular pillar-shaped channels 401 where the word lines 407 are disposed may face in opposite directions. In another embodiment, the lateral walls of two adjacent rectangular pillar-shaped channels 401 where the word lines 407 are disposed may face the same direction. In some embodiments, as shown in fig. 4F, each of the electromagnetic shielding element 408 and the two word lines 407 (between which the electromagnetic shielding element 408 is disposed) are disposed at opposite lateral walls of the rectangular columnar channel 401. The electromagnetic shielding element 408 can prevent adjacent pillar trenches 410 from interfering with each other and reduce coupling effects that occur between the word line 407 and the pillar trench 401. The word line 407 may be applied with a word line voltage, and a transistor connected to the word line 407 may be enabled or disabled.

In some embodiments, a bit line may be formed to connect the source or drain of a transistor. The storage capacitor is further formed to store data written into the semiconductor device 400A. Each of the storage capacitors has a first electrode connected to a drain or source of a corresponding one of the transistors and a second electrode connected to a common terminal. In an embodiment, the common terminal may be connected to a low voltage, for example, 0.5V. In another embodiment, the common terminal may be grounded. In an embodiment, the electromagnetic shielding element 408 may be made of a metallic material having a high work function, such that the electromagnetic shielding element 408 is capable of having an even lower voltage.

In an embodiment, at least one of the electromagnetic shielding elements 408 may be applied with a first voltage that is less than a second voltage applied to a corresponding one of the channels 401. In another embodiment, the electromagnetic shielding element 408 may be disposed in an intermediate region between two adjacent transistors, and the first voltage may be less than half of the second voltage. In some embodiments, at least one of the electromagnetic shielding elements may be applied with a voltage such that a first transistor of the two adjacent transistors between which the electromagnetic shielding element 408 is disposed is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element 408 and a second electromagnetic field generated by a second transistor of the two adjacent transistors.

In an embodiment, the electromagnetic shielding element 408 may be connected to a common terminal. In another embodiment, the electromagnetic shielding element 408 may be disconnected from the common terminal and independently supplied with a voltage.

In some embodiments, the second recess 404 may be greater in etch depth than the third recess 405. The etch depths of the second grooves 404 and the third grooves 405 may be controlled by determining various etch parameters (e.g., etch time, gas flow rate, gas flow ratio, pressure, and temperature). For example, at a constant etching rate, the longer the etching time, the deeper the groove formed in the third direction (e.g., Z direction) becomes. In an embodiment, the second groove 404 may have a greater etching depth than the third groove 405 by controlling the etching parameters. The second grooves 404 and the third grooves 405 may be formed by dry etching (e.g., plasma etching).

In some embodiments, the first direction and the second direction may include an included angle of less than or equal to 90 degrees.

Fig. 5 is a cross-sectional view of a semiconductor device 500 according to some embodiments of the present disclosure. The semiconductor device 500 may be manufactured by the method 400. In an embodiment, the semiconductor device 500 may include a plurality of transistors arranged in an array in an X-Y plane, and each of the transistors may include a channel, for example, a pillar channel 501. For example, the array may include a plurality of rows arranged along a first direction (e.g., an X-direction) and a plurality of columns intersecting the rows and arranged along a second direction (e.g., a Y-direction). Each of the transistors may include a channel 501, and the channels 501 of the transistors are arranged in an array along a first direction and a second direction. In an embodiment, each of the channels 501 may be in the shape of a pillar and extend in a third direction (e.g., Z-direction) perpendicular to a plane defined by the first and second directions. For example, the posts may have a cross-section that is rectangular, circular, diamond-shaped, or any other polygonal shape. In an embodiment, the pillar-shaped channel 501 located in each of the columns of the array may be sequentially formed with an oxide layer 506 and a word line 507 at lateral walls thereof, and thus may be connected to each other by the word line 507, both the oxide layer 506 and the word line 507 extending in a first direction (e.g., X direction). In an embodiment, the source 504 and the drain 503 may be formed at both ends of each of the pillar-shaped channels 501, respectively. In some embodiments, the source 504 and drain 503 are interchangeable. In an embodiment, the electromagnetic shielding element 508 may be disposed between two adjacent ones of the transistors that are arranged in a row in the Y direction and extend in the X direction. For example, the electromagnetic shielding element 508 may be parallel to the word line 507.

In some embodiments, as shown in fig. 5, the projection of at least one of the electromagnetic shielding elements 508 onto a corresponding one of the columnar channels 501 in the Y-direction does not overlap the source 504 and the drain 503. For example, the electromagnetic shielding element 508 extends in the Z direction less than the length of the columnar channel 501 and is equal to or greater than one third of the length.

In some embodiments, as shown in fig. 5, word lines 507 of adjacent two of the columnar trenches 501 are formed on lateral walls of the columnar trenches facing in opposite directions, and one of electromagnetic shielding elements 508 is disposed between the two columnar trenches 501 at a lateral wall of the columnar trench opposite to the lateral wall where the corresponding word line 507 is formed.

In a certain embodiment, the semiconductor apparatus 500 may further include: a bit line 510 connected to the drain 503 of the transistor; and a storage capacitor 509 connected to the source 504 at a first terminal thereof and to a common terminal (not shown) at a second terminal thereof via a storage capacitor pad 505 for storing data written to the semiconductor device 500.

In some embodiments, the electromagnetic shielding element 508 may be connected to a common terminal, and thus a voltage applied to the common terminal may be provided to the electromagnetic shielding element 508.

Fig. 6A-6E illustrate the fabrication of a semiconductor device 600 according to some embodiments of the present disclosure. In the semiconductor device 600, word lines are formed on lateral walls of any two adjacent transistors (or channels) facing in the same direction.

Fig. 6A is a top view illustrating the formation of a pillar-shaped channel of a semiconductor device 600 according to some embodiments of the present disclosure. As shown in fig. 6A, a plurality of channels 601 arranged in an array in an X-Y plane are formed on the surface of a wafer (not shown), for example. For example, the array may include a plurality of rows arranged along a first direction (e.g., an X-direction) and a plurality of columns intersecting the rows and arranged along a second direction (e.g., a Y-direction). In an embodiment, each of the channels 601 may be in the shape of a pillar (e.g., a rectangular pillar), and each of the rectangular pillar-shaped channels 401 may extend in a third direction (e.g., a Z-direction) perpendicular to a plane defined by the first and second directions.

In some embodiments, columnar channels 601 may be formed on the surface of the wafer by: a mask (not shown) covering a certain region of the wafer for forming the column-shaped channel 601 is used to cover the wafer; etching the wafer to a depth (which is less than the thickness of the wafer) to form first grooves 602 disposed between the columnar channels 601; and the mask is removed to form the columnar channels 601 whose lateral walls are exposed. In some embodiments, the wafer may be etched by using Photolithography (PH) or dry Etching (ET), such as electron beam lithography, plasma etching, and Reactive Ion Etching (RIE).

Fig. 6B is a top view illustrating the formation of an insulating layer of a semiconductor device 600 according to some embodiments of the present disclosure. In some embodiments, an insulating material (e.g., siO ₂ ) Is deposited in the first recess 602 to form an insulating layer 603 covering the first recess 602 and the lateral walls of the columnar channels 601. In some embodiments, chemical Mechanical Polishing (CMP) may then be employed to polish and remove the remaining insulating material to expose the top surfaces of the pillar trenches 601.

Fig. 6C is a top view illustrating formation of second and third grooves of a semiconductor device 600 according to some embodiments of the present disclosure. In an embodiment, the insulating layer 603 may be etched to form a second groove 604 and a third groove 605, the second groove 604 exposing one of the lateral walls of each of the columnar channels 601 (e.g., rectangular columnar channels 601), and each of the third grooves 605 being disposed in a row in the Y direction between two adjacent transistors (i.e., two adjacent rectangular columnar channels 601). In some embodiments, each of the second grooves 604 may expose lateral walls of the pillar-shaped channels 601 of transistors adjacent to each other and arranged in columns in the X-direction. In an embodiment, as shown in fig. 6C, the lateral walls of two adjacent rectangular columnar channels 601 exposed by corresponding two of the second grooves 604 may face the same direction. In another embodiment, the lateral walls of two adjacent rectangular columnar channels 601 exposed by corresponding two of the second grooves 604 may face in opposite directions. In some embodiments, as shown in fig. 6C, a third groove 605 and each of two second grooves 604 (between which the third groove 605 is disposed) are disposed at opposite lateral walls of the rectangular columnar channel 601.

In some embodiments, the second recess 604 may be greater in etch depth than the third recess 605. The etch depths of the second grooves 604 and the third grooves 605 may be controlled by determining various etch parameters (e.g., etch time, gas flow rate, gas flow ratio, pressure, and temperature). For example, at a constant etching rate, the longer the etching time, the deeper the groove formed in the third direction (e.g., Z direction) becomes. In an embodiment, the second groove 604 may have a greater etch depth than the third groove 605 by controlling the etch parameters. The second grooves 604 and the third grooves 605 may be formed by dry etching (e.g., plasma etching).

Fig. 6D is a top view illustrating the formation of a gate oxide layer of a semiconductor device 600 according to some embodiments of the present disclosure. In an embodiment, the lateral walls of the rectangular columnar channels 601 exposed by the second grooves 604 may be oxidized, for example, by direct oxidation, basic oxidation, or acidic oxidation, to form gate oxide layers 606 on the exposed lateral walls of the rectangular columnar channels 601. For example, the lateral walls of the rectangular columnar channels 601 exposed by the second grooves 604 may be directly heated and oxidized such that silicon in the lateral walls reacts with air containing an oxidized material at a high temperature, thereby forming a silicon oxide film, i.e., a gate oxide layer 660, on the lateral walls of the rectangular columnar channels 601. In some embodiments, the gate oxide layer 606 may include an insulating material, such as two Silicon oxide (SiO) ₂ )。

Fig. 6E is a top view illustrating the formation of electromagnetic shielding elements and word lines of a semiconductor device 600 according to some embodiments of the present disclosure. In an embodiment, the third groove 605 and the second groove 604 may be filled with a metal material to form an electromagnetic shielding element 608 and a word line (or gate) 607, respectively. Thus, the word line 607 and the electromagnetic shielding element 608 can be formed in a single deposition step. In another embodiment, the word line 607 and the electromagnetic shielding element 608 may be formed sequentially in two process steps. In a certain embodiment, the metallic material may include, but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other suitable metallic materials. In an embodiment, each of the word lines 607 may electrically connect adjacent ones of the transistors arranged in columns in the X-direction at lateral walls of the pillar channel 601 of the transistor. In an embodiment, a gate oxide layer 606 is disposed between the pillar channel 601 and the word line 607 to isolate the word line 607 from the pillar channel 601 and prevent leakage of charge. In an embodiment, as shown in fig. 6E, the lateral walls of two adjacent rectangular pillar-shaped channels 601 where the word lines 607 are disposed may face in the same direction. In another embodiment, the lateral walls of two adjacent rectangular pillar-shaped channels 601 where the word lines 607 are disposed may face in opposite directions. In some embodiments, as shown in fig. 6E, an electromagnetic shielding element 608 and each of two word lines 607 (with the electromagnetic shielding element 608 disposed therebetween) are disposed at opposite lateral walls of a rectangular columnar channel 601. The electromagnetic shielding element 608 can prevent adjacent pillar trenches 601 from interfering with each other and reduce a coupling effect occurring between the word line 607 and the pillar trench 601. The word line 607 may be applied with a word line voltage, and a transistor connected to the word line 607 may be enabled or disabled.

In some embodiments, a bit line may be formed to connect the drains of the transistors. The storage capacitor is further formed to store data written into the semiconductor device 600. Each of the storage capacitors has a first electrode connected to a source of a corresponding one of the transistors and a second electrode connected to a common terminal. In an embodiment, the common terminal may be connected to a low voltage, for example, 0.5V. In another embodiment, the common terminal may be grounded.

In an embodiment, the electromagnetic shielding element 608 may be connected to a common terminal. In another embodiment, the electromagnetic shielding element 608 may be disconnected from the common terminal and independently supplied with a voltage. In some embodiments, the electromagnetic shielding element 608 may be grounded.

Fig. 7 is a cross-sectional view of a semiconductor device 700 according to some embodiments of the present disclosure. The semiconductor device 700 may be manufactured by the method 400. The semiconductor device 700 may include a plurality of transistors arranged in an array in an X-Y plane defined by a first direction (e.g., an X-direction) and a second direction (e.g., a Y-direction), each of the transistors including a channel 701 (e.g., a rectangular columnar channel) extending in a third direction (e.g., a Z-direction) perpendicular to the X-Y plane. A gate oxide layer 706 and a word line 707 are formed in turn at one of the lateral walls of each of the rectangular columnar channels 701. The gate oxide layer 706 is thus disposed between the rectangular columnar channel 701 and the word line 707 to isolate the word line 707 from the rectangular columnar channel 701 and prevent leakage of charge. Each of the word lines 707 may extend in a first direction (e.g., an X-direction) and connect at least some of the transistors arranged in columns in the X-direction. Electromagnetic shielding element 708 may be disposed between at least two adjacent transistors arranged in a row in the Y-direction. In an embodiment, the electromagnetic shielding element 708 may extend in the X-direction. In one embodiment, the word line 707 and the electromagnetic shielding element 708 are parallel. A source electrode 704 and a drain electrode 703 are formed at both ends of each of the columnar channels 701, respectively.

In an embodiment, as shown in fig. 7, the electromagnetic shielding element 708 has a length greater than the word line 707 in the direction in which the columnar channel 701 extends (for example, the Z direction). The length of the electromagnetic shielding element 708 and the length of the word line 707 may be determined by controlling the etching depths of the third groove (e.g., the third groove 605) and the second groove (e.g., the second groove 604), respectively. The etch depths of the second grooves 604 and the third grooves 605 may be controlled by determining various etch parameters (e.g., etch time, gas flow rate, gas flow ratio, pressure, and temperature). In an embodiment, the length of the electromagnetic shielding element 708 along the direction in which the columnar channel 701 extends (e.g., the Z direction) is greater than one third of the length of the word line 707 in the Z direction.

In a certain embodiment, the semiconductor apparatus 700 may further include: a bit line 710, the bit line 710 being connected to the drain 703 of the transistor; and a storage capacitor 709, the storage capacitor 709 being connected to the source electrode 704 at a first terminal thereof and to a common terminal (not shown) at a second terminal thereof via a storage capacitor pad 705 for storing data written to the semiconductor device 700.

In an embodiment, the electromagnetic shielding element 708 may be connected to a common terminal, and thus a voltage applied to the common terminal may be provided to the electromagnetic shielding element 708. In another embodiment, the electromagnetic shielding element 708 may be disconnected from the common terminal and independently supplied with a voltage.

Fig. 8 is a top view illustrating the formation of contact pads of a semiconductor device 800 in accordance with some embodiments of the present disclosure. For example, bit line 810 is connected to the drains of a plurality of transistors arranged in an array in the X-Y plane. Each of the transistors has a channel 809, e.g., a rectangular columnar channel, extending in a direction perpendicular to the X-Y plane (e.g., the Z-direction). The semiconductor device 800 may include a plurality of word lines 807 and one or more electromagnetic shielding elements 808. Each of the word lines 807 may electrically connect adjacent ones of the transistors arranged in columns in the X direction at lateral walls of the transistors. Each of the electromagnetic shielding elements 808 may be disposed between two adjacent ones of the transistors that are disposed in a row in the Y direction. In an embodiment, the lateral walls of rectangular pillar channels 809 of two adjacent transistors, on which word lines 807 are formed, face in opposite directions. The semiconductor device 800 may further include a word line contact pad 801 connected to the word line 807 and an electromagnetic shield contact pad 802 connected to the electromagnetic shield element 808. In an embodiment, since the word line contact pads 801 and the electromagnetic shield contact pads 802 may be larger in size than the word line 807 and the electromagnetic shield element 808, respectively, any adjacent two of the word line contact pads 801 may be disposed on two opposite sides of the array in the X-direction, and any one of the electromagnetic shield contact pads 802 and an adjacent one of the word line contact pads 801 may be staggered with respect to each other, thereby preventing the word line 807 and the electromagnetic shield element 808 from contacting each other.

Fig. 9 is a top view illustrating the formation of contact pads of a semiconductor device 900 according to some embodiments of the present disclosure. For example, bit line 910 is connected to the sources or drains of a plurality of transistors arranged in an array in the X-Y plane. Each of the transistors has a channel 909 (e.g., a rectangular columnar channel) extending in a direction perpendicular to the X-Y plane (e.g., the Z direction). The semiconductor device 900 may include a plurality of word lines 907 and one or more electromagnetic shielding elements 908. Each of the word lines 907 may electrically connect adjacent ones of the transistors arranged in columns in the X-direction at lateral walls of the transistors. Each of the electromagnetic shielding elements 908 may be disposed between two adjacent ones of the transistors that are arranged in a row in the Y-direction. In an embodiment, the lateral walls of the rectangular pillar channels 909 of two adjacent transistors, where the word lines 907 are formed, may face in the same direction. The semiconductor device 900 may further include a word line contact pad 901 connected to the word line 907 and an electromagnetic shield contact pad 902 connected to the electromagnetic shield element 908. In some embodiments, the word line contact pads 901 and the electromagnetic shield contact pads 902 are disposed on the same side of the array in the X-direction, and any one of the electromagnetic shield contact pads 902 is staggered with respect to an adjacent one of the word line contact pads 901.

Fig. 9A is a top view illustrating the formation of contact pads of a semiconductor device 900A according to some embodiments of the present disclosure. For example, bit line 910A is connected to the sources or drains of a plurality of transistors arranged in an array in the X-Y plane. Each of the transistors has a channel 909A, e.g., a rectangular columnar channel, extending in a direction perpendicular to the X-Y plane (e.g., the Z direction). The semiconductor device 900A may include a plurality of word lines 907A and one or more electromagnetic shielding elements 908A. Each of the word lines 907A may electrically connect adjacent ones of the transistors arranged in columns in the X direction at lateral walls of the transistors. Each of the electromagnetic shielding elements 908A may be disposed between two adjacent ones of the transistors that are arranged in a row in the Y-direction. In an embodiment, the lateral walls of rectangular pillar channels 909A of two adjacent transistors, where word lines 907A are formed, may face in the same direction. The semiconductor device 900A may further include a word line contact pad 901A connected to the word line 907A and an electromagnetic shield contact pad 902A connected to the electromagnetic shield element 908A. In some embodiments, any adjacent two of the word line contact pads 901A and the electromagnetic shield contact pads 902A are disposed on opposite sides of the array in the X-direction, thereby preventing the word line 907A and the electromagnetic shield element 908 from contacting each other. For example, as shown in fig. 9A, the electromagnetic shield contact pad 902A is disposed on the back side of the array in the X direction, and the word line contact pad 901A adjacent to the electromagnetic shield contact pad 902A is disposed on the front side of the array in the X direction.

Fig. 10A-10H are cross-sectional views of semiconductor devices 1000A-1000H having electromagnetic shielding elements 1008A-1008H of various configurations according to some embodiments of the present disclosure. The semiconductor device 1000A/1000B/1000C/1000D/1000E/1000F/1000G/1000H includes: a plurality of transistors arranged in an X-Y plane, for example, each of the transistors includes a channel 1001A/1001B/1001C/1001D/1001E/1001F/1001G/1001H (for example, a rectangular columnar channel) extending in a Z direction and a source 1004A/1004B/1004C/1004D/1004E/1004F/1004G/1004H and a drain 1003A/1003B/1003C/1003D/1003E/1003F/1003G/1003H formed at both ends of the columnar channel 1001A/1001B/1001C/1001D/1001E/1001F/1001G/1001H, respectively; a plurality of word lines 1007A/1007B/1007C/1007D/1007E/1007F/1007G/1007H, each of which electrically connects adjacent ones of the transistors arranged in columns in the X direction at lateral walls of the column channels 1001A/1001B/1001C/1001D/1001E/1001F/1001G/1001H; one or more electromagnetic shielding elements

1008A/1008B/1008C/1008D/1008E/1008F/1008G/1008H, wherein each electromagnetic shielding element is disposed between two adjacent ones of the transistors that are aligned in the Y-direction. The electromagnetic shielding elements may have projections onto the columnar channels in the Y-direction and may be equal in length to the columnar channels (e.g., electromagnetic shielding element 1008A) or smaller in length than the columnar channels (e.g., electromagnetic shielding elements 1008B, 1008C, and 1008D), and electromagnetic shielding elements 1008B, 1008C, and 1008D may be disposed in the middle, upper, and lower regions, respectively, relative to columnar channels 1001B, 1001C, and 1001D. The electromagnetic shielding elements may have a cross-section in the shape of a rectangle (e.g., electromagnetic shielding elements 1008A-1008E, 1008G, and 1008H) or an ellipse (e.g., electromagnetic shielding element 1008F). The electromagnetic shielding elements may each include a plurality of electromagnetic shielding segments that are spaced apart from each other and arranged in the Z-direction (e.g., electromagnetic shielding element 1008G) and/or the Y-direction (e.g., electromagnetic shielding element 1008H).

Fig. 11A-11E are cross-sectional views of semiconductor devices 1100A-1100E having electromagnetic shielding elements 1108A-1108E of various configurations in accordance with some embodiments of the present disclosure. The semiconductor device 1100A/1100B/1100C/1100D/1100E includes: a plurality of transistors arranged in an X-Y plane, for example, each of the transistors includes a channel 1101A/1101B/1101C/1101D/1101E (for example, a rectangular columnar channel) extending in a Z direction and a source and a drain (not shown) formed at both ends of the columnar channel 1101A/1101B/1101C/1101D/1101E, respectively; a plurality of word lines 1107A/1107B/1107C/1107D/1107E, each of which electrically connects adjacent ones of the transistors arranged in columns in the X-direction at lateral walls of the pillar-shaped channels 1101A/1101B/1101C/1101D/1101E; and one or more electromagnetic shielding elements 1108A/1108B/1108C/1108D/1108E, wherein each electromagnetic shielding element is disposed between two adjacent ones of the transistors that are aligned in the Y-direction. As shown in fig. 11C and 11D, respectively, the electromagnetic shielding elements may each include a plurality of electromagnetic shielding segments spaced apart from each other and arranged in the Y direction (e.g., electromagnetic shielding element 1108E) or in the X direction (e.g., electromagnetic shielding elements 1108C and 1108D), and the electromagnetic shielding segments of the electromagnetic shielding elements may extend in the X direction and/or the Y direction. Electromagnetic shielding elements may also be disposed between adjacent two of the transistors disposed in a column in the X direction, for example, electromagnetic shielding elements 1108B and 1108E.

Fig. 12A to 12C are cross-sectional views illustrating fabrication of semiconductor devices according to some embodiments of the present disclosure. In an embodiment, the electromagnetic shielding element and the word line may be formed simultaneously in a single process. For example, as shown in fig. 12A, a vertical gate groove (or trench) VG (e.g., second groove 404) and an isolation groove (or trench) ISO (e.g., third groove 405) narrower than the vertical gate groove VG may be formed in the substrate, an oxide layer (e.g., gate oxide layer 406) may be formed on exposed lateral walls of the vertical gate groove VG and isolation groove ISO, and a conductor (e.g., a metal material or polysilicon) may be simultaneously deposited in the vertical gate groove VG and isolation groove ISO to form a word line WL (e.g., word line 407) and an electromagnetic shielding element ESE (e.g., electromagnetic shielding element 408) of the semiconductor device 1200A, respectively.

In another embodiment, as shown in fig. 12B, the word line WL and the electromagnetic shielding element ESE of the semiconductor device 1200B may be sequentially formed. For example, vertical gate grooves VG may be formed in the substrate, an oxide layer may be formed on exposed lateral walls of the vertical gate grooves VG, and a first conductor may be deposited in the vertical gate grooves VG to form word lines WL; and isolation trenches ISO may be etched and formed in the substrate, an oxide liner may be deposited on exposed lateral walls of the isolation trenches ISO, and a second conductor may be deposited to fill the isolation trenches ISO, thereby forming electromagnetic shielding elements ESE.

In some embodiments, as shown in fig. 12C, the word line WL and the electromagnetic shielding element ESE of the semiconductor device 1200C may be separately formed. For example, the recess in which the contact pad (e.g., the electromagnetic shielding contact pad 902A shown in fig. 9A) is to be formed may be formed and filled with oxide, and for example, the vertical gate recess VG and isolation recess ISO may then be etched by self-aligned double patterning (SADP). Accordingly, a portion of the isolation groove ISO where the electromagnetic shielding contact pad will be formed on the back side of the semiconductor device 1200C may be deeper than the vertical gate groove VG, and the remaining portion of the isolation groove ISO may be as deep as the vertical gate groove VG. Subsequently, an oxide layer and a first conductor may be sequentially formed in the vertical gate groove VG to form the word line WL, the backside of the semiconductor device 1200C may be thinned to expose the oxide filled in the isolation groove ISO, then the oxide may be recessed, an oxide liner may be deposited on the exposed lateral walls of the isolation groove ISO, and a second conductor may fill the isolation groove ISO and a space formed after the oxide recess to form the electromagnetic shielding element ESE and the electromagnetic shielding contact pad, respectively.

Fig. 13 illustrates a block diagram of a memory system 1300, according to some embodiments of the present disclosure. The memory system 1300 may include one or more semiconductor devices 1301 to 1304, for example, semiconductor devices 400A, 500, 600, 700, 800, 900A, 1000A-1000H, 1100A-1100E, and 1200A-1200C. In some embodiments, the memory system 1300 may be a Solid State Drive (SSD) or a memory module.

The memory system 1300 may include other suitable components. For example, the memory system 1300 may include an interface (or main interface circuitry) 1310 and a main controller (or control circuitry) 1320 coupled to each other. The memory system 1300 may also include a bus 1330 that couples the main controller 1320 with the semiconductor devices 1301 to 1304. Further, a main controller 1320 is connected to the semiconductor devices 1301 through 1304, respectively, as shown by corresponding control lines 1340-1370, for example.

The interface 1310 is suitably mechanically and electrically configured to connect between the memory system 1300 and a host device, and may be used to transfer data between the memory system 1300 and the host device.

The main controller 1320 is configured to connect the respective semiconductor devices 1301 to 1304 to an interface 1310 for data transmission. For example, the main controller 1320 may be configured to provide enable/disable signals to the semiconductor devices 1301 to 1304, respectively, to activate one or more of the semiconductor devices 1301 to 1304 for data transmission.

The main controller 1320 is responsible for completing the various instructions within the memory system 1300. For example, the main controller 1320 may perform bad block management, error check and correction, garbage collection, and the like. In some embodiments, the main controller 1320 may be implemented using a processor chip. In some examples, master controller 1320 may be implemented using multiple Master Control Units (MCUs).

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a plurality of transistors arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z-direction;

Forming a plurality of word lines, each of the word lines electrically connecting adjacent ones of the transistors at lateral walls of the channel of the transistors, the adjacent ones of the transistors being arranged in columns in an X-direction; and

one or more electromagnetic shielding elements are formed, at least one of which is disposed between adjacent two of the transistors arranged in a row in the Y direction.

2. The method of claim 1, wherein each of the transistors further comprises a source disposed on a first end of the channel and a drain disposed on a second end of the channel, and the electromagnetic shielding element has a projection onto the channel in a Y-direction that does not overlap the source and the drain.

3. The method of claim 1, wherein the electromagnetic shielding element is shorter in the Z-direction than the channels of the adjacent two transistors.

4. The method of claim 1, wherein the electromagnetic shielding element is further disposed between two adjacent ones of the transistors disposed in a column.

5. The method of claim 1, wherein each of the channels of the transistor is rectangular-columnar and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular-columnar channels.

6. The method of claim 5, wherein the lateral walls of the rectangular pillar channels of the adjacent two transistors, on which the word lines are formed, face in opposite directions.

7. The method of claim 1, further comprising:

forming an electromagnetic shield contact pad connected to one of the electromagnetic shield elements; and

forming a word line contact pad connected to one of the word lines adjacent to the electromagnetic shielding element,

wherein the electromagnetic shield contact pads and the word line contact pads are disposed on opposite sides of the array in the X-direction.

8. The method of claim 7, wherein the electromagnetic shielding element and the word line are formed by:

forming a first recess in a substrate of the semiconductor device on a back side thereof for forming a contact pad in the first recess, and filling the first recess with an oxide;

Forming a second groove and a third groove in the substrate for forming the word line and the electromagnetic shielding element in the second groove and the third groove, respectively, the third groove being in contact with the first groove;

filling the second recess with a first conductor to form the word line;

thinning the backside of the semiconductor device to expose the oxide filled in the first recess;

recessing the oxide to expose lateral walls of the third recess; and

the third recess and the first recess are filled with a second conductor to form the electromagnetic shielding element and the contact pad, respectively.

9. A semiconductor device, comprising:

a plurality of transistors arranged in an array in an X-Y plane, each of the transistors including a channel extending in a Z-direction;

a plurality of word lines, each of the plurality of word lines electrically connecting adjacent ones of the transistors arranged in columns in an X-direction at lateral walls of the channel of the transistor; and

one or more electromagnetic shielding elements, at least one of which is disposed between two adjacent ones of the transistors that are disposed in a row in the Y direction.

10. The semiconductor device according to claim 9, wherein each of the transistors further comprises a source electrode provided on a first end of the channel and a drain electrode provided on a second end of the channel, and wherein the electromagnetic shielding element has a projection onto the channel in a Y direction, the projection not overlapping the source electrode and the drain electrode.

11. The semiconductor device according to claim 9, wherein the electromagnetic shielding element is shorter than the channels of the adjacent two transistors in a Z direction.

12. The semiconductor device according to claim 9, wherein the electromagnetic shielding element is further provided between adjacent two transistors arranged in a column among the transistors.

13. The semiconductor device of claim 9, wherein each of the channels of the transistor is rectangular-columnar and each of the word lines is formed at a lateral wall of a corresponding one of the rectangular-columnar channels.

14. The semiconductor device of claim 13, wherein the lateral walls of the rectangular pillar channels of the adjacent two transistors on which the word lines are formed face in opposite directions.

15. The semiconductor device according to claim 9, further comprising:

an electromagnetic shielding contact pad connected to one of the electromagnetic shielding elements; and

a word line contact pad connected to one of the word lines adjacent to the electromagnetic shielding element,

16. The semiconductor device of claim 9, wherein at least one of the electromagnetic shielding elements comprises a plurality of electromagnetic shielding segments spaced apart from one another.

17. The semiconductor device of claim 16, wherein the electromagnetic shield segments are arranged in an X-direction, a Y-direction, and/or a Z-direction.

18. The semiconductor device according to claim 9, wherein at least one of the electromagnetic shielding elements is applied with a first voltage that is smaller than a second voltage applied to a corresponding one of the channels.

19. The semiconductor device according to claim 9, wherein at least one of the electromagnetic shielding elements is applied with a voltage such that a first transistor of the adjacent two transistors between which the electromagnetic shielding element is disposed is less affected by a combination of a first electromagnetic field generated by the electromagnetic shielding element and a second electromagnetic field generated by a second transistor of the adjacent two transistors.

20. A memory system, comprising:

a semiconductor device, the semiconductor device comprising:

one or more electromagnetic shielding elements, at least one of which is provided between two adjacent ones of the transistors that are arranged in a row in the Y direction; and

control circuitry coupled to the semiconductor device, the control circuitry configured to control operation of the semiconductor device.