CN117790422A

CN117790422A - Dielectric layer for nanoplatelet protection and method of forming the same

Info

Publication number: CN117790422A
Application number: CN202310428920.2A
Authority: CN
Inventors: 林政颐; 陈书涵; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-11-22
Filing date: 2023-04-20
Publication date: 2024-03-29

Abstract

The present disclosure relates to dielectric layers for nanoplatelet protection and methods of forming the same. One device includes a gate stack having a top and a stack structure located below the top of the gate stack. The stacked structure includes a plurality of semiconductor nanostructures, an upper nanostructure of the plurality of semiconductor nanostructures overlapping a corresponding lower nanostructure. The stack structure further includes a plurality of gate structures, each gate structure including a lower portion of the gate stack. Each gate structure of the plurality of gate structures is located between two semiconductor nanostructures of the plurality of semiconductor nanostructures. A dielectric layer extends over the top surface and sidewalls of the stacked structure. The dielectric layer includes a lower sub-layer including a first dielectric material and an upper sub-layer over the lower sub-layer and formed of a second dielectric material different from the first dielectric material. The gate spacer is located on the dielectric layer. The source/drain regions are located beside the gate stack.

Description

Dielectric layer for nanoplatelet protection and method of forming the same

Technical Field

The present disclosure relates to dielectric layers for nanoplatelet protection and methods of forming the same.

Background

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: insulating or dielectric, conductive, and semiconductor layers of material are deposited sequentially over a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems that need to be solved arise.

Disclosure of Invention

According to one embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a protruding semiconductor stack, the semiconductor stack comprising: a plurality of sacrificial layers; and a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are alternately arranged; depositing a dielectric layer on sidewalls and a top surface of the protruding semiconductor stack, wherein the dielectric layer comprises: a lower sub-layer; and an upper sub-layer over the lower sub-layer, wherein the lower sub-layer and the upper sub-layer comprise different dielectric materials; forming a dummy gate electrode layer on the dielectric layer; patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer serves as an etch stop layer; forming a gate spacer on an additional sidewall of the dummy gate electrode; removing the dummy gate electrode; etching the dielectric layer to reveal the protruding semiconductor stack; removing the plurality of sacrificial layers; and forming a replacement gate stack filling the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

According to another embodiment of the present disclosure, there is provided a semiconductor device including: a gate stack including a top; a stack structure located below a top of the gate stack, the stack structure comprising: a plurality of semiconductor nanostructures, an upper nanostructure of the plurality of semiconductor nanostructures overlapping a lower nanostructure of the plurality of semiconductor nanostructures; and a plurality of gate structures, each gate structure comprising a lower portion of the gate stack, wherein each gate structure of the plurality of gate structures is located between two semiconductor nanostructures of the plurality of semiconductor nanostructures; a dielectric layer extending over the top surface and sidewalls of the stacked structure, wherein the dielectric layer comprises: a lower sub-layer comprising a first dielectric material; and an upper sub-layer over the lower sub-layer, wherein the upper sub-layer comprises a second dielectric material different from the first dielectric material; a gate spacer on the dielectric layer; and source/drain regions located beside the gate stack.

According to still another embodiment of the present disclosure, there is provided a semiconductor device including: a semiconductor substrate; a first dielectric isolation region and a second dielectric isolation region, including at least some portions in the semiconductor substrate; a protruding structure protruding above a top surface of the dielectric isolation region, wherein the protruding structure is located laterally between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure comprises: a plurality of semiconductor layers; and a plurality of gate stack portions, wherein the plurality of semiconductor layers and the plurality of gate stack portions are alternately placed; a plurality of internal spacers comprising a plurality of pairs, each pair being located on opposite sides of one of the plurality of gate stack portions; and a dielectric layer comprising: a top over the protruding structure, wherein the top has a first thickness; and a sidewall portion in contact with one of the plurality of inner spacers, wherein the sidewall portion has a second thickness different from the first thickness.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-3, 4A, 4B, 5-7, 8A, 8B, 8C, 8D, 8E, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, 13A, 13B, 13C, 13D, 13E, 14A, 14B, 15A, 15B, 15C, and 15D illustrate perspective, cross-sectional, and top views of intermediate stages in forming a Gate All Around (GAA) transistor according to some embodiments.

Figure 16 illustrates a process flow for forming GAA transistors according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "lower," "above," "higher," etc.) herein are used to facilitate a description of a relationship of one element or feature to another element(s) or feature(s) shown in the figures. These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A Gate All-Around (GAA) transistor with an improved dummy Gate dielectric and method of forming the same are provided. According to some embodiments, the forming of the GAA transistor includes: a composite dummy gate dielectric is deposited that includes two or more layers formed of different dielectric materials, thereby reducing damage to the underlying silicon nanostructure. The dummy gate dielectric may be a non-conformal layer having a top portion with a thickness greater than the thickness of the sidewall portions. The embodiments discussed herein are intended to provide examples to enable the subject matter of the present disclosure to be made or used, and modifications that remain within the intended scope of the different embodiments will be readily appreciated by those of ordinary skill in the art. In the various views and illustrative embodiments, like reference numerals are used to indicate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Fig. 1-3, 4A, 4B, 5-7, 8A, 8B, 8C, 8D, 8E, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, 13A, 13B, 13C, 13D, 13E, 14A, 14B, 15A, 15B, 15C, and 15D illustrate perspective, cross-sectional, and top views of intermediate stages in forming GAA transistors according to some embodiments. The corresponding process is also schematically reflected in the process flow shown in fig. 16.

Referring to fig. 1, a perspective view of a wafer 10 including a substrate 20 is shown. A multilayer structure including a multilayer stack 22 is formed on the substrate 20. According to some embodiments, substrate 20 is (or includes) a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., but other substrates and/or structures may be used, such as, for example, semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments it may be doped as an n-type semiconductor.

According to some embodiments, the multi-layer stack 22 is formed by a series of epitaxial processes for depositing alternating materials. The corresponding process is shown as process 202 in process flow 200 shown in fig. 16. According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material. Because of epitaxy, the first layer 22A and the second layer 22B have the same lattice direction as the substrate 20.

According to some embodiments, the first layer 22A of the first semiconductor material is formed of or includes: siGe, ge, si, gaAs, inSb, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, etc. forms or includes SiGe, ge, si, gaAs, inSb, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., siGe) is by epitaxial growth, and the corresponding deposition method may be Vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), chemical Vapor Deposition (CVD), low Pressure CVD (LPCVD), atomic Layer Deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced Pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed at aboutAnd about->A first thickness in the range between. However, any suitable thickness may be used while remaining within the scope of the embodiments.

Once the first layer 22A has been deposited over the substrate 20, the second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, e.g., si, siGe, ge, gaAs, inSb, gasB, inAlAs, inGaAs, gasB, gaAsSB, combinations thereof, etc., and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, and vice versa. It should be appreciated that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.

According to some embodiments, second layer 22B is epitaxially grown on first layer 22A using a deposition technique similar to that used to form first layer 22A. According to some embodiments, the second layer 22B is formed to a similar thickness as the first layer 22A. The second layer 22B may also be formed to be different from the thickness of the first layer 22A.

Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same thickness as the second layer 22B or a different thickness than the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

According to some embodiments, the pad oxide layer 12 and the hard mask 14 are formed over the multi-layer stack 22. Liner oxide layer 12 may comprise silicon oxide, silicon carbide, etc., while hard mask layer 14 may comprise silicon nitride, and other materials may be used. The pad oxide layer 12 and the hard mask layer 14 are patterned to form a plurality of elongated strips, which are also referred to as pad oxide and hard mask.

Referring to fig. 2, a portion of the underlying substrate 20 and the multi-layer stack 22 are patterned in an etching process (es) such that trenches (filled with isolation regions 26) are formed. The trenches extend into the substrate 20. The remainder of the multi-layer stack is hereinafter referred to as multi-layer stack 22'. The corresponding process is shown as process 204 in process flow 200 shown in fig. 16. Portions of the underlying multilayer stack 22', substrate 20 are left behind and are hereinafter referred to as substrate strips 20'. The multilayer stack 22' includes a semiconductor layer 22A and a semiconductor layer 22B. The semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is hereinafter alternatively referred to as a nanostructure. The portions of the multi-layer stack 22 'and underlying substrate strip 20' are collectively referred to as semiconductor strips 27.

In the above embodiments, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithographic processes (including double patterning processes or multiple patterning processes) may be used to pattern the structures. Typically, a double patterning process or a multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns, for example, having a pitch smaller than that obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA structure.

Next, isolation regions 26 are formed, the isolation regions 26 may also be referred to as Shallow Trench Isolation (STI) regions throughout the specification. The corresponding process is shown as process 206 in process flow 200 shown in fig. 16. STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of substrate 20. Liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high Density Plasma Chemical Vapor Deposition (HDPCVD), CVD, or the like. STI region 26 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on, HDPVCD, or the like. A planarization process (e.g., a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process) may then be performed to level the top surface of the dielectric material, for example, with the top surface of the hard mask layer 14, and the remainder of the dielectric material is STI regions 26.

Referring to fig. 3, sti regions 26 are recessed such that the top of semiconductor strips 24 protrudeA top surface 26T is raised above the remainder of the STI region 26 to form protruding fins (structures) 28 (also referred to as nanoplatelets). The corresponding process is shown as process 208 in process flow 200 shown in fig. 16. Protruding fins 28 include some top of substrate strip 20 'and multi-layer stack 22'. The recessing of STI regions 26 may be performed by a dry etching process, wherein, for example, NF ₃ And NH ₃ Is used as the etching gas. During the etching process, a plasma may be generated. Argon may also be included. In accordance with an alternative embodiment of the present disclosure, the recessing of STI regions 26 is performed by a wet etching process. For example, the etching chemistry may include HF. The pad oxide layer 12 and the hard mask 14 are removed.

Referring to fig. 4A and 4B, a dielectric layer 32 is deposited on the sidewalls and top surfaces of protruding fins 28, as well as on the top surfaces of STI regions 26. The corresponding process is shown as process 210 in process flow 200 shown in fig. 16. Fig. 4A shows a perspective view, and fig. 4B shows a vertical cross section 4B-4B shown in fig. 4A. According to some embodiments, the dielectric layer 32 is a single (homogenous) layer, the entire dielectric layer 32 being formed of the same material and having the same composition. Throughout the specification, when two layers are referred to as having the same composition, it means that the two layers have the same elements, and the percentages of the corresponding elements in the two layers are the same as each other. Conversely, when two layers are referred to as having different compositions, it means that at least one of the two layers has at least one element that is not in the other layer, or that the two layers have the same element, but the percentages of the elements in the two layers are different from each other.

According to alternative embodiments, the dielectric layer 32 is a composite layer comprising two or more sub-layers. For example, fig. 4A and 4B illustrate a composite layer 32, the composite layer 32 including a lower sub-layer 32A and an upper sub-layer 32B above the lower sub-layer 32A. A dashed line (interface) is drawn between the lower sub-layer 32A and the upper sub-layer 32B to indicate that the dielectric layer 32 may be a single layer (in these embodiments, no interface is formed therein) or may be a composite layer. In the case of a composite layer, dielectric layer 32 may comprise two layers, three layers, or multiple layers, with adjacent layers being formed of different dielectric materials.

According to some embodiments in which the dielectric layer 32 is a single layer, the dielectric layer 32 may be formed of a material having a lower etch rate than silicon oxide, wherein the etch rate is responsive to an etch chemistry used to remove and clean the subsequently formed dummy gate electrode 34 (fig. 13A-13E). According to some embodiments, cleaning is performed using HF, and the dielectric layer 32 may include elements other than oxygen (e.g., carbon and/or nitrogen). For example, dielectric layer 32 may be formed from or include the following: siC (SiC) _x (x is in the range between about 0.8 and about 1), siO _x C _y (x and y are in the range between about 0.8 and about 1), siO _x N _y 、SiC _x N _y 、SiN _x (x is in the range between about 0.8 and about 1.33), siO _x C _y N _z (x and y are in the range between about 0.1 and about 0.3, and z is in the range between about 0.4 and about 0.6), and the like.

According to alternative embodiments in which dielectric layer 32 is a composite layer, lower sub-layer 32A may be made of SiO _x Formed, (x is in the range between about 0.8 and about 2.0, or in the range between about 0.8 and 1.33). Lower sublayer 32A may also be made of non-SiO _x A dielectric material formed of non-SiO _x The dielectric material may be the material described above that has a lower etch rate than silicon oxide in the subsequent removal and cleaning of the dummy gate electrode 34. For example, other than SiO _x The dielectric material may be formed of or include the following: siC (SiC) _x 、SiO _x C _y 、SiO _x N _y 、SiC _x N _y 、SiN _x 、SiO _x C _y N _z Etc.

According to yet another alternative embodiment, in which dielectric layer 32 is a composite layer, each of lower sub-layer 32A and upper sub-layer 32B may be composed of non-SiO _x Dielectric material forming or including non-SiO _x A dielectric material. Although the materials of the lower sub-layer 32A and the upper sub-layer 32B are different from each other, each of the lower sub-layer 32A and the upper sub-layer 32B may be formed of a material (described above) having a lower etching rate than silicon oxide in the subsequent removal and cleaning of the dummy gate electrode 34. For example, each of the lower sub-layer 32A and the upper sub-layer 32B May be selected from the same candidate material group, which may include SiC _x 、SiO _x C _y 、SiO _x N _y 、SiC _x N _y 、SiN _x 、SiO _x C _y N _z Etc.

According to yet another alternative embodiment, in which the dielectric layer 32 is a composite layer, each of the lower sub-layer 32A and the upper sub-layer 32B may have a uniform composition. When dielectric layer 32 is a single layer, the entire dielectric layer 32 may be deposited to have a uniform composition. According to an alternative embodiment, the dielectric layer 32 has a gradually changing composition, different portions including the same elements (e.g., silicon, oxygen, and nitrogen), while the percentage of elements is gradually changed from bottom to top. For example, the bottom of the dielectric layer 32 may include SiO _x While the top may include SiAE _y (or SiOAE) _y ) Where "AE" represents an alternative element such as C, N or any combination including two or three of C, N and O. The atomic percent y of AE increases gradually from the bottom of the dielectric layer 32 to the top of the dielectric layer 32. This can be achieved, for example, by gradually changing the flow rate of the precursor when CVD is used. As will be discussed in subsequent paragraphs, the upper sub-layer 32B may act as a firewall to prevent sheet damage when formed of a different material than the lower sub-layer 32A.

According to some embodiments, the dielectric layer 32 is formed using an Atomic Layer Deposition (ALD) process, which includes a plurality of ALD cycles. Each ALD cycle may include a first stage and a subsequent second stage. The first stage may include: the first precursor is introduced (also referred to as pulsing or feeding) into the ALD chamber, the first precursor is purged, and the plasma is turned on. The plasma may be turned off during the pulsing and initial cleaning phases in the first phase. The second stage may include: a second precursor is introduced into the ALD chamber, the second precursor is purged, and a plasma is turned on. During the pulsing and initial cleaning phases in the second phase, the plasma may be turned off. The plasma may also be turned on in the second stage, but may not be turned on in the first stage. The purge gas may include N ₂ Ar, ne, kr, he, etc., or combinations thereof. EtcThe ion treatment may be performed to include N ₂ 、Ar、Ne、Kr、He、O ₂ 、NH ₃ 、N ₂ O, or the like, or combinations thereof.

According to some embodiments, the first precursor comprises a silicon-containing precursor, which may include silane, disilane, aminosilane, di-sec-butylaminosilane (DSBAS), di (tert-butylamino) silane (BTBAS), and the like, or a combination thereof. The second precursor may include another element(s), e.g., C, N and/or O. For example, when N is to be included in the dielectric layer, the second precursor may include ammonia. The resulting dielectric layer 32 may include SiC, siN, siO, siCN, siOCN, siON, the like, or a combination thereof.

According to alternative embodiments, other deposition methods, such as CVD, may be used to form dielectric layer 32. The composition of dielectric layer 32 may be controlled by adjusting the flow rates of the corresponding precursors. According to some embodiments in which the composition of dielectric layer 32 is gradually changed, the flow rate and flow rate ratio of the precursor may be gradually changed as deposition of dielectric layer 32 is performed.

According to some embodiments, as shown in fig. 5 and 6, which are shown later, the dummy gate electrode layer 34 is patterned in an anisotropic etching process, and the patterning process is performed using the dielectric layer 32 as an etch stop layer. Because of process variations, the top of the dielectric layer 32 on top of the protruding fin 28 may be damaged and may also have more loss than the vertical portions of the dielectric layer 32 on the sidewalls of the protruding fin 28. When the top of the dielectric layer 32 is damaged or removed due to process variations, the top nanostructures 22B may be exposed and subject to loss. This results in process degradation and bias. Thus, the dielectric layer 32 may be formed to have a top thickness that is greater than the sidewall thickness, thereby providing a greater process margin for top nanostructure loss.

Fig. 4B shows the vertical cross-section of fig. 4A-4B. Dielectric layer 32 includes a top portion 32T directly above protruding fin 28, and the top thickness of the top portion is denoted as T1 (including T1A, T B and T1C). The thickness T1 may be measured at the middle vertical line of the corresponding protruding fin 28. According to some embodiments, the top portion 32T has a uniform thickness. For example, fig. 4B shows that thickness T1A, thickness T1B, and thickness T1C may be the same, varying by less than about 10% or less.

The dummy gate dielectric layer 32 also includes sidewall portions 32S on the sidewalls of the protruding fins 28, and horizontal portions 32H that overlap and contact the top surfaces of the STI regions 26. The thickness T3 of the horizontal portion 32H may be equal to the thickness T2, with both the thickness T2 and the thickness T3 being less than the thickness T1. Thus, the dielectric layer 32 is a non-conformal layer. According to some embodiments, each of the thickness ratio T1/T2 and the thickness ratio T1/T3 is greater than about 1.5, and may be greater than about 2.0 (e.g., in a range between about 2 and about 5). When one or more of the lower and upper sublayers 32A, 32B are non-conformal, the thickness ratio T1'/T2' and the thickness ratio T1"/T2" may also be greater than about 1.5, and may be greater than about 2.0, for example, in a range between about 2 and about 5. Thickness T1 'and thickness T2' are the top thickness and sidewall thickness, respectively, of lower sub-layer 32A. Thickness T1 "and thickness T2" are the top thickness and sidewall thickness, respectively, of upper sub-layer 32B.

According to some embodiments, the top thickness T1 may be aboutAnd about->Within a range between. Sidewall thickness T2 and bottom thickness T3 may be +.>And about->Within a range between.

According to some embodiments in which dielectric layer 32 comprises two or more dielectric layers, zero, one, or more sub-layers in dielectric layer 32 may have non-conformal profiles of any combination described above, while other sub-layer(s), if any, may be conformal. For example, when there are two sub-layers, the lower sub-layer 32A may have a conformal profile, while the upper sub-layer 32B may have a non-conformal profile. This profile allows the upper sub-layer 32A to stop etching in subsequent patterning of the dummy gate electrode layer. According to alternative embodiments, the lower sub-layer 32A may have a non-conformal profile, while the upper sub-layer 32B may have a conformal profile. According to yet another alternative embodiment, both the lower sub-layer 32A and the upper sub-layer 32B have non-conformal profiles.

To achieve a non-conformal profile of the dielectric layer 32, a CVD-mode ALD process is employed, wherein ALD process conditions are adjusted to achieve a thicker top thickness than sidewall thickness. Adjustment of process conditions may include reducing precursor introduction time (feed time) such that precursor diffusion time to the bottom of the trench between protruding fins 28 is less, and precursor adsorption time is less. Adjustment of the process conditions may also include increasing the pressure of the precursor during precursor introduction. Adjustment of process conditions may also include reducing the plasma on-time (hereinafter referred to as plasma processing time) so that fewer reactions occur.

According to some embodiments, the precursor introduction time may be in a range between about 0.01 seconds and about 0.2 seconds in an ALD cycle for forming the non-conformal dielectric layer 32. The pressure may be in a range between about 2 torr and about 3.5 torr. The plasma treatment time may be in a range between about 0.1 seconds and about 3 seconds.

It should be appreciated that the profile of the dielectric layer 32 may be a result of a combination of various factors. Thus, experiments can be conducted to find a desired combination of process conditions to achieve a desired profile. The experiment may include forming a plurality of sample dielectric layers 32 on a plurality of sample wafers. In formation, multiple sample dielectric layers are formed using multiple different combinations of process conditions (e.g., pressure, precursor introduction time, plasma processing time, etc.). The profile of the sample dielectric layer is measured to determine a correlation between the process conditions and the profile of the dielectric layer. Thus, the desired process conditions may be selected as conditions that result in a desired profile of the dielectric layer 32.

It should be appreciated that in a related process, the dummy dielectric layer may be formed simultaneously with the gate oxide of the IO transistor. According to the embodiment of the present disclosure, since the material and structure of the dielectric layer 32 are different from those of the gate oxide of the IO transistor, the formation of the dielectric layer 32 and the formation of the gate oxide of the IO transistor are decoupled and formed in separate processes and have different structures. For example, the gate oxide of the IO transistor may be formed of silicon oxide and may be conformal, while the dielectric layer 32 of the GAA transistor may be formed of the above-described materials and may be non-conformal.

Referring to fig. 5, a dummy gate electrode layer 34 is deposited. The corresponding process is shown as process 212 in process flow 200 shown in fig. 16. A planarization process is then performed to level the top surface of the dummy gate electrode layer 34. For example, the dummy gate electrode layer 34 may be formed using polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used. A hard mask layer(s) 36 is also formed over the dummy gate electrode layer 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a plurality of layers thereof.

Referring to fig. 6, the hard mask layer 36 and the dummy gate electrode layer 34 are patterned in an etching process 39 to form a dummy gate stack 37, the dummy gate stack 37 including the hard mask 36 and the dummy gate electrode 34. The corresponding process is shown as process 214 in process flow 200 shown in fig. 16. The resulting structure is shown in fig. 6. According to some embodiments, the patterning process is performed by an anisotropic etching process. The etching gas may include fluorine (F ₂ ) Chlorine (Cl) ₂ ) Hydrogen chloride (HCl), hydrogen bromide (HBr), bromine (Br) ₂ )，C ₂ F ₆ ，CF ₄ ，SO ₂ ，HBr、Cl ₂ And O ₂ Or a combination thereof. Etching is performed using the dielectric layer 32 as an etch stop layer. According to some embodiments, the etch rate of dielectric layer 32 is lower than the etch rate of silicon oxide by selecting an appropriate combination of the material and etch chemistry of dielectric layer 32. As a result, the dielectric layer 32 in embodiments of the present disclosure stops etching better than silicon oxide, which may also be the gate oxide of the IO transistor (which may be formed in the same wafer/die as the GAA transistor).

Because the etching process 39 is anisotropic, the top of the dielectric layer 32 suffers more loss from the sidewall portions. As the top of dielectric layer 32 gets thicker, the likelihood of completely removing the top of dielectric layer 32 by patterning process 39 decreases. Thus, the underlying top nanostructure 22B is less likely to be etched, or lost if etched. For example, during the patterning process 39, siO _x And SiO _x C _y N _Z May be in the range ofPer minute and about->An etching rate in a range between/min. On the other hand, siC _x And SiC (SiC) _x N _y Can have a significantly lower etch rate, which can be at about +.>Per minute and about->In the range between/min. SiN (SiN) _x May also have a significantly lower etch rate, which may be at about +.>Per minute and about->In the range between/min.

According to some embodiments in which dielectric layer 32 is a composite layer, one, but not both, of upper sub-layer 32B and lower sub-layer 32A are non-conformal, and the etch rate of the non-conformal sub-layer (in patterning process 39) may also be lower than the etch rate of the conformal sub-layer to minimize the possibility of completely removing the top of dielectric layer 32.

Next, fig. 7 shows that gate spacers 38 are formed on the sidewalls of the dummy gate stack 37. The corresponding process is shown as process 216 in process flow 200 shown in fig. 16.According to some embodiments, gate spacer layer 38 is formed of a dielectric material (e.g., silicon nitride (SiN), silicon dioxide (SiO) ₂ ) Silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like), and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The process of forming the gate spacer 38 may include: one or more dielectric layers are deposited and then an anisotropic etching process(s) is performed on the dielectric layer(s). The remainder of the dielectric layer(s) is gate spacers 38.

Fig. 8A, 8B, and 8E illustrate the formation of the recess 42, with the epitaxial region being formed from the recess 42. Fig. 8A and 8B show cross-sectional views of the structure shown in fig. 8E. Fig. 8A shows a vertical cross-section A-A in fig. 8E cut through the portion of protruding fin 28 not covered by dummy gate stack 37 and gate spacers. Fig. 8A also shows fin spacers 38' located on the sidewalls of protruding fins 28. Fig. 8B shows a reference cross section B-B in fig. 8E, which is parallel to the longitudinal direction of the projecting wing 28.

Fig. 8A, 8B, and 8E illustrate the exposed portions of dielectric layer 32 being etched. The corresponding process is shown as process 218 in process flow 200 shown in fig. 16. Portions of the dummy gate stack 37 and gate spacers 38 directly under the dielectric layer 32 and protruding fins 28 remain after the etching process. The corresponding process is shown as process 220 in process flow 200 shown in fig. 16. The remaining portion of the dielectric layer 32 is considered part of the dummy gate stack 37. According to some embodiments, the etching process includes using C ₂ F ₆ ，CF ₄ ，SO ₂ ，HBr、Cl ₂ And O ₂ HBr, cl ₂ 、O ₂ And CH (CH) ₂ F ₂ A dry etching process performed to etch the multi-layer semiconductor stack 22 'and underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multi-layer semiconductor stack 22', or may be lower than the bottom of the multi-layer semiconductor stack 22'. The etching may be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the recess 42 are vertical and straight.

Referring to fig. 8B, the sacrificial semiconductor layer 22A is laterally recessed to form lateral recesses 41, the lateral recesses 41 being recessed from the edges of the respective overlying and underlying nanostructures 22B. The corresponding process is shown as process 222 in process flow 200 shown in fig. 16. The lateral recessing of the sacrificial semiconductor layer 22A may be achieved by a wet etching process that uses an etchant that is more selective to the material of the sacrificial semiconductor layer 22A, e.g., silicon germanium (SiGe), than to the material of the nanostructures 22B and the substrate 20, e.g., silicon (Si). For example, in embodiments where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructures 22B are formed of silicon, a wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etch process may be performed using a dipping process, a spraying process, etc., and may be performed using any suitable process temperature (e.g., between about 400 ℃ and about 600 ℃) and suitable process time (e.g., between about 100 seconds and about 1000 seconds). According to an alternative embodiment, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

Fig. 8C and 8D show top views of the structure shown in fig. 8B, wherein the top views are taken from horizontal planes through the sacrificial semiconductor layer 22A and the nanostructures 22B, respectively. Referring to fig. 8C and 8D, the edges of the nanostructures 22B may be aligned with the inner edges of the gate spacers 38. Fig. 8C shows that the edge of the sacrificial semiconductor layer 22A is laterally recessed. As a result, some internal portions of the lower sub-layer 32A of the dielectric layer 32 may be exposed.

Damage may be caused to the lower sub-layer 32A during the lateral recessing of the sacrificial semiconductor layer 22A and subsequent cleaning process. This may result in a through channel (air gap) 43 being formed in the lower sub-layer 32A. According to some embodiments, upper sub-layer 32B is resistant to chemicals used in the lateral recessing of sacrificial semiconductor layer 22A and the subsequent cleaning process, and thus through channel 43 will be blocked by upper sub-layer 32B. In other words, the etching rate of the upper sub-layer 32B is lower than that of the lower sub-layer 32A.

Fig. 9A and 9B illustrate the formation of the inner spacer 44.The corresponding process is shown as process 224 in process flow 200 shown in fig. 16. The forming process includes depositing a spacer layer extending into the recess 41 and performing an etching process to remove portions of the inner spacer layer outside the recess 41, thereby leaving the inner spacer layer 44 in the recess 41. The inner spacer 44 may be formed of SiOCN, siON, siOC, siCN or the like or include SiOCN, siON, siOC, siCN or the like. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process, wherein the etching chemistry may include H ₂ SO ₄ Diluted HF, ammonia solution (NH) ₄ OH, aqueous ammonia), and the like, or combinations thereof.

Fig. 10A, 10B, and 10C show cross-sectional and perspective views of forming source/drain regions 48 in recesses 42 by epitaxy. The corresponding process is shown as process 226 in process flow 200 shown in fig. 16. The source/drain region(s) may refer to either a source or a drain, either individually or collectively depending on the context. According to some embodiments, the source/drain regions 48 may stress the nanostructures 22B (the nanostructures 22B serve as channels for corresponding GAA transistors), thereby improving performance.

According to some embodiments, the corresponding transistor is n-type, so the epitaxial source/drain regions 48 are formed n-type by doping with n-type dopants. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown to form epitaxial source/drain regions 48. According to an alternative embodiment, the corresponding transistor is p-type, so the epitaxial source/drain regions 48 are formed p-type by doping with p-type dopants. For example, silicon boron (SiB), silicon germanium boron (SiGeB), and the like may be grown to form epitaxial source/drain regions 48. After filling recess 42 with epitaxial region 48, further epitaxial growth of epitaxial region 48 results in horizontal expansion of epitaxial region 48, and facets may be formed. Further growth of epitaxial regions 48 may also cause adjacent epitaxial regions 48 to merge with one another, thus forming voids 49 (fig. 10C).

After the epitaxial process, the epitaxial region 48 may be further implanted with p-type impurities or n-type impurities to form source and drain regions, which are also indicated with reference numeral 48. According to an alternative embodiment of the present disclosure, the implantation process is skipped when epitaxial region 48 is in-situ doped with n-type impurities or p-type impurities during epitaxy and epitaxial region 48 is also a source/drain region.

Fig. 11A, 11B, and 11C show cross-sectional and perspective views of the structure after formation of a Contact Etch Stop Layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is shown as process 228 in process flow 200 shown in fig. 16. FIG. 11A shows a cross section 11A-11A of FIG. 11B. The CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 52 may comprise a dielectric material formed using, for example, FCVD, spin-on, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), or the like.

Fig. 12A and 12B to 15A and 15B illustrate a process for forming a replacement gate stack and a contact plug. In fig. 12A and 12B, a planarization process (e.g., a CMP process or a mechanical polishing process) may be performed to level the top surface of ILD 52. According to some embodiments, the planarization process may remove the hard mask 36 to reveal the dummy gate electrode 34, as shown in fig. 12A. The corresponding process is shown as process 230 in process flow 200 shown in fig. 16. According to alternative embodiments, the planarization process may reveal the hard mask 36 and be stopped on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), gate spacer 38, and ILD 52 are horizontal within process variations.

Next, in the process shown in fig. 13A, 13B, and 13C, the dummy gate electrode 34 (and hard mask 36 if remaining) is removed in one or more etching processes, thereby forming a recess 58, as shown in fig. 13A and 13B. The corresponding process is shown as process 232 in process flow 200 shown in fig. 16. The portion of gate dielectric 32 in recess 58 is exposed.

According to some In embodiments, the removal of the dummy gate electrode 34 may be performed by a dry and/or wet etching process. For example, when dry etching is performed, the etching gas may include F ₂ 、Cl ₂ 、HCl、HBr、Br ₂ 、C ₂ F ₆ 、CF ₄ 、SO ₂ Etc., or a combination thereof. After removing the dummy gate electrode 34, a cleaning process may be performed, which may be performed by using a dry etching process such as HF.

Fig. 13D and 13E show top views of the structure shown in fig. 13A, 13B and 13C, taken from the same horizontal plane as shown in fig. 8C and 8D, respectively. As can be seen from fig. 13E, if the through channel 43 penetrates the entire dielectric layer 32, chemicals used to etch the dummy gate electrode 34 and subsequent cleaning processes may pass through the opening 58 and through the channel 43 to the nanostructure 22B, which nanostructure 22B may be formed of or include silicon. Thus, the nanostructure 22B may be damaged, thus forming the void 43E. According to embodiments of the present disclosure, upper sub-layer 32B advantageously blocks through-channel 43 from extending into it, and thus through-channel 43 will not be able to penetrate the entire dielectric layer 32. The chemicals in the recess 58 will not reach and damage the nanostructure 22B.

Referring to fig. 14A and 14B, the exposed portions of gate dielectric 32 are etched. The corresponding process is shown as process 234 in process flow 200 shown in fig. 16. On the other hand, the portion of the gate dielectric 32 directly under the gate spacer 38 is protected from being removed.

The sacrificial layer 22A is then removed to extend the recesses 58 between the nanostructures 22B. The corresponding process is shown as process 236 in process flow 200 shown in fig. 16. The sacrificial layer 22A may be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective to the material of the sacrificial layer 22A, while the nanostructures 22B, substrate 20, STI regions 26, and remaining gate dielectric 32 are relatively unetched as compared to the sacrificial layer 22A. According to some embodiments, wherein the sacrificial layer 22A comprises SiGe, for example, the nanostructure 22B comprises silicon or carbon doped silicon, for example. Such asTetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) ₄ OH), or the like, may be used to remove the sacrificial layer 22A.

Referring to fig. 15A, 15B, and 15C, a gate stack 70 is formed. The corresponding process is shown as process 238 in process flow 200 shown in fig. 16. Gate dielectric 62 is first formed. According to some embodiments, each of the gate dielectrics 62 includes an interfacial layer 64 and a high-k dielectric layer 66 on the interfacial layer 64. The interface layer 64 may be formed of or include silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD. According to some embodiments, high-k dielectric layer 66 includes one or more dielectric layers. For example, the high-k dielectric layer 66 may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

A gate electrode 68 is formed over the gate dielectric 62. In the formation process, a conductive layer is first formed on high-k dielectric layer 66 to fill the remainder of recess 58. The gate electrode 68 may include a metal-containing material, for example, tiN, taN, tiAl, tiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and/or multilayers thereof. The gate electrode 68 may also include a filler metal such as cobalt, tungsten, or the like. The gate dielectric 62 and gate electrode 68 also fill the space between adjacent ones 22B of the nanostructures 22B and fill the space between the bottom ones 22B of the nanostructures 22B and the underlying ones 20 'of the substrate strips 20'. After filling recess 58, a planarization process (e.g., a CMP process or a mechanical polishing process) may be performed to remove the excess portions of gate dielectric 62 and gate electrode 68 that are located above the top surface of ILD 52. The gate electrode 68 and gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting nanofet.

Next, the gate stack 70 is recessed such that a recess is formed directly above the gate stack 70 and between opposite portions of the gate spacers 38. A gate mask 74 comprising one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride, etc.) is filled in each of the recesses, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 52.

Figures 15A and 15B also show ILD 76 deposited over ILD 52 and over gate mask 74. An etch stop layer (not shown) may (or may not) be deposited prior to the formation of ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, and the like.

ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) through which epitaxial source/drain regions 48 and/or gate stack 70 are exposed. The recess may be formed by an anisotropic etching process (e.g., RIE or NBE, etc.). According to some embodiments, the recesses may be formed by etching ILD 76 and ILD 52 using a first etching process, etching gate mask 74 using a second etching process, and possibly CESL 50 using a third etching process. Although fig. 15B shows that the contact plug 80A and the contact plug 80B are located in the same cross section, in various embodiments, the contact plug 80A and the contact plug 80B may be formed in different cross sections, thereby reducing the risk of shorting to each other.

After the recess is formed, silicide regions 78 (fig. 15B and 15C) are formed over the epitaxial source/drain regions 48. According to some embodiments, silicide regions 78 are formed by: a metal layer (not shown) is first deposited that is capable of reacting with the semiconductor material (e.g., silicon germanium, germanium) of the underlying epitaxial source/drain regions 48 to form silicide regions and/or germanide regions, and then a thermal annealing process is performed to form silicide regions 78. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, and the like. The unreacted portion of the deposited metal is then removed, for example by an etching process.

The gate contact plug 80A and the source/drain contact plug 80B are formed. The corresponding process is shown as process 240 in process flow 200 shown in fig. 16. Source/drain contact plugs 80B are formed over the silicide regions 78. A gate contact 80A is located over the gate electrode 68 and contacts the gate electrode 68. The contact plugs 80A and 80B may each include one or more layers, for example, a barrier layer and a filler material. The barrier layer may include titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (e.g., a CMP process) may be performed to remove excess material from the surface of ILD 76. The GAA transistor 82 is formed.

The gate dielectric 32 may be present in the final GAA transistor 82, and may have a single-layer structure or a multi-layer structure. Fig. 15D shows a cross section 15D-15D (fig. 15B). In fig. 15D, the area marked 44/70 indicates that the internal spacers 44 and/or the gate electrode 70 may be present in the illustrated cross section. A top view of this structure can also be found from fig. 13D and 13E, wherein the space 58 is filled with a replacement gate stack 70 and the sacrificial semiconductor layer 22A is also replaced with the replacement gate stack 70. In the GAA transistor 82, the dielectric layer 32 can be distinguished by, for example, a Transmission Electron Microscope (TEM), energy dispersive X-ray (EDX), electron Energy Loss Spectroscopy (EELS), or the like.

Embodiments of the present disclosure have some advantageous features. By forming a multi-layer dummy gate dielectric, damage to the nanostructure is avoided. Moreover, by forming a non-conformal dummy gate dielectric layer, loss of top nanostructures is avoided or reduced. Experiments have revealed that by forming a non-conformal dummy gate dielectric layer, the loss of top nanostructures can be reduced to 30% of the loss when using a conformal dummy gate dielectric layer.

According to some embodiments, a method comprises: forming a protruding semiconductor stack, the semiconductor stack comprising: a plurality of sacrificial layers; and a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are alternately arranged; depositing a dielectric layer on sidewalls and a top surface of the protruding semiconductor stack, wherein the dielectric layer comprises: a lower sub-layer; and an upper sub-layer over the lower sub-layer, wherein the lower sub-layer and the upper sub-layer comprise different dielectric materials; forming a dummy gate electrode layer on the dielectric layer; patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer serves as an etch stop layer; forming a gate spacer on an additional sidewall of the dummy gate electrode; removing the dummy gate electrode; etching the dielectric layer to reveal the protruding semiconductor stack; removing the plurality of sacrificial layers; and forming a replacement gate stack filling in the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

In an embodiment, a first of the lower sub-layer and the upper sub-layer is formed as a non-conformal layer. In an embodiment, the non-conformal first of the lower and upper sublayers is formed using atomic layer deposition. In an embodiment, the second of the lower and upper sub-layers is also formed using atomic layer deposition, and the second of the lower and upper sub-layers is a conformal layer. In an embodiment, both the lower and upper sublayers have a top thickness equal to the sidewall thickness.

In an embodiment, the method further comprises: after forming the gate spacer, etching a portion of the protruding semiconductor stack, wherein a portion of the protruding semiconductor stack below the gate spacer and the dummy gate electrode remains after etching; and laterally recessing the plurality of sacrificial layers, wherein a via is formed to penetrate the lower sub-layer, and wherein the via is blocked by the upper sub-layer. In an embodiment, the upper sub-layer is exposed at a time after the dummy gate electrode is removed, and wherein the upper sub-layer blocks chemicals used in removing the dummy gate electrode from extending into the via.

In an embodiment, after etching the dielectric layer to reveal the protruding semiconductor stack, a portion of the dielectric layer directly under the gate spacer remains. In an embodiment, the lower sub-layer comprises silicon oxide and the upper sub-layer comprises silicon and carbon. In an embodiment, the lower sub-layer comprises silicon oxide and the upper sub-layer comprises silicon and nitrogen.

According to some embodiments, a device comprises: a gate stack including a top; a stacked structure located below a top of the gate stack, the stacked structure comprising: a plurality of semiconductor nanostructures, an upper nanostructure of the plurality of semiconductor nanostructures overlapping a lower nanostructure of the plurality of semiconductor nanostructures; and a plurality of gate structures, each gate structure comprising a lower portion of the gate stack, wherein each gate structure of the plurality of gate structures is located between two semiconductor nanostructures of the plurality of semiconductor nanostructures; a dielectric layer extending over the top surface and sidewalls of the stacked structure, wherein the dielectric layer comprises: a lower sub-layer comprising a first dielectric material; and an upper sub-layer over the lower sub-layer, wherein the upper sub-layer comprises a second dielectric material different from the first dielectric material; a gate spacer on the dielectric layer; and source/drain regions located beside the gate stack.

In an embodiment, the first layer of the lower and upper sub-layers is a non-conformal layer, the top of the first layer above the top surface of the stacked structure has a first thickness, and the lower portion of the first layer on the sidewall of the stacked structure has a second thickness different from the first thickness. In an embodiment, the ratio of the first thickness to the second thickness is in a range between about 2 and about 5.

In an embodiment, the second layer of the lower and upper sub-layers is a conformal layer. In an embodiment, the lower sub-layer has an air gap therein, and wherein the upper sub-layer and one of the plurality of semiconductor nanostructures are located on opposite sides of the air gap. In an embodiment, the lower sub-layer comprises silicon oxide and the upper sub-layer comprises silicon carbide. In an embodiment, the stacked structure further comprises dielectric inner spacers, each dielectric inner spacer being located between two semiconductor nanostructures of the plurality of semiconductor nanostructures, wherein the lower sub-layer is in contact with the dielectric inner spacers.

According to some embodiments, a device comprises: a semiconductor substrate; a first dielectric isolation region and a second dielectric isolation region, including at least some portions in the semiconductor substrate; a protruding structure protruding above a top surface of the dielectric isolation region, wherein the protruding structure is laterally located between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure comprises: a plurality of semiconductor layers; and a plurality of gate stack portions, wherein the plurality of semiconductor layers and the plurality of gate stack portions are alternately disposed; a plurality of internal spacers including a plurality of pairs, each pair being located on opposite sides of one of the plurality of gate stack portions; and a dielectric layer comprising: a top over the protruding structure, wherein the top has a first thickness; and a sidewall portion in contact with one of the plurality of inner spacers, wherein the sidewall portion has a second thickness different from the first thickness. In an embodiment, the dielectric layer includes a plurality of sub-layers formed of different materials. In an embodiment, the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is in a range between about 2 and about 5.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a method of forming a semiconductor device, comprising: forming a protruding semiconductor stack, the semiconductor stack comprising: a plurality of sacrificial layers; and a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are alternately arranged; depositing a dielectric layer on sidewalls and a top surface of the protruding semiconductor stack, wherein the dielectric layer comprises: a lower sub-layer; and an upper sub-layer over the lower sub-layer, wherein the lower sub-layer and the upper sub-layer comprise different dielectric materials; forming a dummy gate electrode layer on the dielectric layer; patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer serves as an etch stop layer; forming a gate spacer on an additional sidewall of the dummy gate electrode; removing the dummy gate electrode; etching the dielectric layer to reveal the protruding semiconductor stack; removing the plurality of sacrificial layers; and forming a replacement gate stack filling the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

Example 2 is the method of example 1, wherein a first one of the lower sub-layer and the upper sub-layer is formed as a non-conformal layer.

Example 3 is the method of example 2, wherein the non-conformal first one of the lower sub-layer and the upper sub-layer is formed using atomic layer deposition.

Example 4 is the method of example 3, wherein a second of the lower sub-layer and the upper sub-layer is also formed using atomic layer deposition, and the second of the lower sub-layer and the upper sub-layer is a conformal layer.

Example 5 is the method of example 1, wherein both the lower sub-layer and the upper sub-layer have a top thickness equal to a sidewall thickness.

Example 6 is the method of example 1, further comprising: etching a portion of the protruding semiconductor stack after forming the gate spacer, wherein after the etching, a portion of the protruding semiconductor stack under the gate spacer and the dummy gate electrode remains; and laterally recessing the plurality of sacrificial layers, wherein a via is formed to penetrate the lower sub-layer, and wherein the via is blocked by the upper sub-layer.

Example 7 is the method of example 6, wherein the upper sub-layer is exposed at a time after the dummy gate electrode is removed, and wherein the upper sub-layer blocks chemicals used in removing the dummy gate electrode from extending into the via.

Example 8 is the method of example 1, wherein a portion of the dielectric layer directly under the gate spacer remains after etching the dielectric layer to reveal the protruding semiconductor stack.

Example 9 is the method of example 1, wherein the lower sub-layer comprises silicon oxide and the upper sub-layer comprises silicon and carbon.

Example 10 is the method of example 1, wherein the lower sub-layer comprises silicon oxide and the upper sub-layer comprises silicon and nitrogen.

Example 11 is a semiconductor device, comprising: a gate stack including a top; a stack structure located below a top of the gate stack, the stack structure comprising: a plurality of semiconductor nanostructures, an upper nanostructure of the plurality of semiconductor nanostructures overlapping a lower nanostructure of the plurality of semiconductor nanostructures; and a plurality of gate structures, each gate structure comprising a lower portion of the gate stack, wherein each gate structure of the plurality of gate structures is located between two semiconductor nanostructures of the plurality of semiconductor nanostructures; a dielectric layer extending over the top surface and sidewalls of the stacked structure, wherein the dielectric layer comprises: a lower sub-layer comprising a first dielectric material; and an upper sub-layer over the lower sub-layer, wherein the upper sub-layer comprises a second dielectric material different from the first dielectric material; a gate spacer on the dielectric layer; and source/drain regions located beside the gate stack.

Example 12 is the device of example 11, wherein a first layer of the lower sub-layer and the upper sub-layer is a non-conformal layer, a top of the first layer above a top surface of the stacked structure has a first thickness, and a lower portion of the first layer on a sidewall of the stacked structure has a second thickness different from the first thickness.

Example 13 is the device of example 12, wherein the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is in a range between about 2 and about 5.

Example 14 is the device of example 12, wherein the second of the lower sub-layer and the upper sub-layer is a conformal layer.

Example 15 is the device of example 11, wherein the lower sub-layer has an air gap therein, and wherein the upper sub-layer and one of the plurality of semiconductor nanostructures are located on opposite sides of the air gap.

Example 16 is the device of example 11, wherein the lower sub-layer comprises silicon oxide and the upper sub-layer comprises silicon carbide.

Example 17 is the device of example 11, wherein the stacked structure further comprises dielectric inner spacers, each of the dielectric inner spacers being located between two semiconductor nanostructures of the plurality of semiconductor nanostructures, wherein the lower sub-layer is in contact with the dielectric inner spacers.

Example 18 is a semiconductor device, comprising: a semiconductor substrate; a first dielectric isolation region and a second dielectric isolation region, including at least some portions in the semiconductor substrate; a protruding structure protruding above a top surface of the dielectric isolation region, wherein the protruding structure is located laterally between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure comprises: a plurality of semiconductor layers; and a plurality of gate stack portions, wherein the plurality of semiconductor layers and the plurality of gate stack portions are alternately placed; a plurality of internal spacers comprising a plurality of pairs, each pair being located on opposite sides of one of the plurality of gate stack portions; and a dielectric layer comprising: a top over the protruding structure, wherein the top has a first thickness; and a sidewall portion in contact with one of the plurality of inner spacers, wherein the sidewall portion has a second thickness different from the first thickness.

Example 19 is the device of example 18, wherein the dielectric layer includes a plurality of sub-layers formed of different materials.

Example 20 is the device of example 18, wherein the first thickness is greater than the second thickness, wherein a ratio of the first thickness to the second thickness is in a range between about 2 and about 5.

Claims

1. A method of forming a semiconductor device, comprising:

forming a protruding semiconductor stack, the semiconductor stack comprising:

a plurality of sacrificial layers; and

a plurality of nanostructures, wherein the plurality of sacrificial layers and the plurality of nanostructures are alternately arranged;

depositing a dielectric layer on sidewalls and a top surface of the protruding semiconductor stack, wherein the dielectric layer comprises:

a lower sub-layer; and

an upper sub-layer over the lower sub-layer, wherein the lower sub-layer and the upper sub-layer comprise different dielectric materials;

forming a dummy gate electrode layer on the dielectric layer;

patterning the dummy gate electrode layer to form a dummy gate electrode, wherein the dielectric layer serves as an etch stop layer;

forming a gate spacer on an additional sidewall of the dummy gate electrode;

removing the dummy gate electrode;

etching the dielectric layer to reveal the protruding semiconductor stack;

removing the plurality of sacrificial layers; and

A replacement gate stack is formed that fills the space left by the removed dummy gate electrode and the removed plurality of sacrificial layers.

2. The method of claim 1, wherein a first of the lower sub-layer and the upper sub-layer is formed as a non-conformal layer.

3. The method of claim 2, wherein the non-conformal first one of the lower sub-layer and the upper sub-layer is formed using atomic layer deposition.

4. The method of claim 3, wherein a second of the lower sub-layer and the upper sub-layer is also formed using atomic layer deposition, and the second of the lower sub-layer and the upper sub-layer is a conformal layer.

5. The method of claim 1, wherein both the lower sub-layer and the upper sub-layer have a top thickness equal to a sidewall thickness.

6. The method of claim 1, further comprising:

etching a portion of the protruding semiconductor stack after forming the gate spacer, wherein after the etching, a portion of the protruding semiconductor stack under the gate spacer and the dummy gate electrode remains; and

The plurality of sacrificial layers are laterally recessed, wherein a via is formed to penetrate the lower sub-layer, and wherein the via is blocked by the upper sub-layer.

7. The method of claim 6, wherein the upper sub-layer is exposed at a time after the dummy gate electrode is removed, and wherein the upper sub-layer blocks chemicals used in removing the dummy gate electrode from extending into the via.

8. The method of claim 1, wherein a portion of the dielectric layer directly under the gate spacer remains after etching the dielectric layer to reveal the protruding semiconductor stack.

9. A semiconductor device, comprising:

a gate stack including a top;

a stack structure located below a top of the gate stack, the stack structure comprising:

a plurality of semiconductor nanostructures, an upper nanostructure of the plurality of semiconductor nanostructures overlapping a lower nanostructure of the plurality of semiconductor nanostructures; and

a plurality of gate structures, each gate structure comprising a lower portion of the gate stack, wherein each gate structure of the plurality of gate structures is located between two semiconductor nanostructures of the plurality of semiconductor nanostructures;

A dielectric layer extending over the top surface and sidewalls of the stacked structure, wherein the dielectric layer comprises:

a lower sub-layer comprising a first dielectric material; and

an upper sub-layer over the lower sub-layer, wherein the upper sub-layer comprises a second dielectric material different from the first dielectric material;

a gate spacer on the dielectric layer; and

source/drain regions located beside the gate stack.

10. A semiconductor device, comprising:

a semiconductor substrate;

a first dielectric isolation region and a second dielectric isolation region, including at least some portions in the semiconductor substrate;

a protruding structure protruding above a top surface of the dielectric isolation region, wherein the protruding structure is located laterally between the first dielectric isolation region and the second dielectric isolation region, and wherein the protruding structure comprises:

a plurality of semiconductor layers; and

a plurality of gate stack portions, wherein the plurality of semiconductor layers and the plurality of gate stack portions are alternately placed;

a plurality of internal spacers comprising a plurality of pairs, each pair being located on opposite sides of one of the plurality of gate stack portions; and

A dielectric layer, comprising:

a top over the protruding structure, wherein the top has a first thickness; and

a sidewall portion in contact with one of the plurality of inner spacers, wherein the sidewall portion has a second thickness different from the first thickness.