CN116469836A - Integrated circuit structure and method for manufacturing the same - Google Patents

Integrated circuit structure and method for manufacturing the same Download PDF

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Publication number
CN116469836A
CN116469836A CN202210825459.XA CN202210825459A CN116469836A CN 116469836 A CN116469836 A CN 116469836A CN 202210825459 A CN202210825459 A CN 202210825459A CN 116469836 A CN116469836 A CN 116469836A
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China
Prior art keywords
layer
work function
gate
semiconductor region
gate stack
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CN202210825459.XA
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Chinese (zh)
Inventor
李欣怡
董彦佃
陈智城
张文
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/804,971 external-priority patent/US20230282712A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116469836A publication Critical patent/CN116469836A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure relates to integrated circuit structures and methods of manufacturing the same. A method, comprising: forming a dummy gate stack over the semiconductor region; forming source/drain regions on sides of the dummy gate stack; removing the dummy gate stack to form a trench, wherein the semiconductor region is exposed to the trench; forming a gate dielectric layer extending into the trench; and depositing a work function adjustment layer on the gate dielectric layer. The work function adjusting layer includes aluminum and carbon. The method further comprises the steps of: depositing a p-type work function layer over the work function adjustment layer; and performing a planarization process to remove excess portions of the p-type work function layer, the work function adjustment layer, and the gate dielectric layer to form a gate stack.

Description

Integrated circuit structure and method for manufacturing the same
Technical Field
The present disclosure relates to integrated circuit structures and methods of manufacturing the same.
Background
Transistors are the basic building elements in integrated circuits. In the previous development of integrated circuits, fin Field-Effect Transistor (FinFET) and Gate All-Around (GAA) transistors have been formed in place of planar transistors. In the formation of a FinFET or GAA transistor, a semiconductor fin or semiconductor fin is formed and a dummy gate is formed on the semiconductor fin/fin. The forming of the dummy gate may include depositing a dummy layer, such as a polysilicon layer, and then patterning the dummy layer into the dummy gate. Gate spacers are formed on sidewalls of the dummy gate stack. The dummy gate stack is then removed to form trenches between the gate spacers. A replacement gate is then formed in the trench.
In forming the replacement gate, different materials are selected to form the n-type transistor and the p-type transistor. For example, an n-type transistor may employ TiAl in its replacement gate, while a p-type transistor may employ TiN in its replacement gate.
Disclosure of Invention
According to one aspect of the present disclosure, there is provided a method of manufacturing an integrated circuit structure, comprising: forming a dummy gate stack over the semiconductor region; forming source/drain regions on sides of the dummy gate stack; removing the dummy gate stack to form a trench, wherein the semiconductor region is exposed to the trench; forming a gate dielectric layer extending into the trench; depositing a work function tuning layer on the gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon; depositing a p-type work function layer over the work function adjustment layer; and performing a planarization process to remove excess portions of the p-type work function layer, the work function adjustment layer, and the gate dielectric layer to form a gate stack.
According to another aspect of the present disclosure, there is provided an integrated circuit structure comprising: a semiconductor region; a gate stack over the semiconductor region, the gate stack comprising: a high-k gate dielectric layer; a work function tuning layer on the high-k gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon; and a p-type work function layer over the work function adjustment layer; and p-type source/drain regions flanking the gate stack.
According to yet another aspect of the present disclosure, there is provided an integrated circuit structure comprising: a first transistor, comprising: a first semiconductor region; a first gate spacer and a second gate spacer over the first semiconductor region; and a first gate stack over the first semiconductor region and between the first gate spacer and the second gate spacer, the first gate stack comprising: a first high-k dielectric layer on the first semiconductor region; an n-type work function layer over and physically contacting the first high-k dielectric layer; a first p-type work function layer over and contacting the n-type work function layer; and a metal region over and contacting the first p-type work function layer; and p-type source/drain regions flanking the first gate stack.
Drawings
Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 16A, 16B, 17A, 17B, 17C, 17D, 17E, 18A, 18B, 18C, 19A, 19B, and 19C illustrate various views at intermediate stages in forming a Gate All Around (GAA) transistor according to some embodiments.
Fig. 20 illustrates a gate stack of several transistors with different gate stacks, according to some embodiments.
Fig. 21 illustrates an atomic percent distribution of several elements in some gate stacks, according to some embodiments.
Figure 22 illustrates a process flow for forming GAA transistors according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms (e.g., "below," "under," "lower," "over," "upper," and the like) may be used herein to facilitate a description of the relationship of one element or feature to another element(s) or feature(s) shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
A method of forming a replacement gate stack by inserting a work function layer comprising aluminum and carbon is provided. According to some embodiments, a dummy gate stack is formed on the semiconductor nanostructure, and then the dummy gate stack is removed, exposing the semiconductor nanostructure. A gate dielectric comprising an interfacial layer and a high-k dielectric layer is formed on the semiconductor nanostructure. A layer comprising aluminum and/or carbon is deposited over the high-k dielectric layer as part of the work function layer, followed by the formation of a p-type work function layer. By inserting a work function layer containing aluminum and carbon before depositing another work function layer, the overall work function of the work function layer is increased. In the description of the present disclosure, GAA transistors are discussed to explain the concepts of the present disclosure. Embodiments of the present disclosure may also be applied to other types of transistors, such as FinFETs, planar transistors, and the like. The embodiments discussed herein are provided to provide examples to enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily appreciate modifications that may be made while remaining within the intended scope of the various embodiments. Like reference numerals are used to denote like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.
Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 16A, 16B, 17A, 17B, 17C, 17D, 17E, 18A, 18B, 18C, 19A, 19B, and 19C illustrate various views at intermediate stages in forming GAA transistor according to some embodiments. The corresponding process is also schematically reflected in the process flow 200 shown in fig. 22.
Referring to fig. 1, a perspective view of a wafer 10 is shown. The wafer 10 includes a multi-layer structure including a multi-layer stack 22 on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., and other substrates and/or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium-on-insulator, etc. The substrate 20 may be doped as a p-type semiconductor, but in other embodiments it may be doped as an n-type semiconductor.
According to some embodiments, the multi-layer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding process is shown as process 202 in process flow 200 shown in fig. 22. According to some embodiments, the multi-layer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.
According to some embodiments, the first semiconductor material of the first layer 22A is formed of SiGe, ge, si, gaAs, inSb, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb or the like, or comprises SiGe, ge, si, gaAs, inSb, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb or the like. According to some embodiments, the deposition of the first layer 22A (e.g., siGe) is by epitaxial growth, and the corresponding deposition method may be Vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), chemical Vapor Deposition (CVD), low Pressure CVD (LPCVD), atomic Layer Deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced Pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed at aboutAnd about->A first thickness in the range between. However, any suitable thickness may be used while remaining within the scope of the embodiments.
Once the first layer 22A has been deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, siGe, ge, gaAs, inSb, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B may be formed of silicon, and vice versa. It will be appreciated that any suitable combination of materials may be used for the first layer 22A and the second layer 22B.
According to some embodiments, second layer 22B uses deposition techniques similar to those used to form first layer 22AThe process is epitaxially grown on the first layer 22A. According to some embodiments, the second layer 22B is formed to a similar thickness as the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, second layer 22B may be formed, for example, at aboutAnd about->A second thickness in the range between.
Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multi-layer stack 22 until the desired topmost layer of the multi-layer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the specification. According to an alternative embodiment, the second layer 22B is sacrificial and is removed in a subsequent process.
According to some embodiments, some pad oxide layers and hard mask layers (not shown) are formed over the multi-layer stack 22. These layers are patterned and used for subsequent patterning of the multi-layer stack 22.
Referring to fig. 2, a portion of the multilayer stack 22 and underlying substrate 20 is patterned in an etching process(s) to form trenches 23. The corresponding process is shown as process 204 in process flow 200 shown in fig. 22. The trench 23 extends into the substrate 20. The remainder of the multi-layer stack is hereinafter referred to as multi-layer stack 22'. Below the multi-layer stack 22', portions of the substrate 20 are left behind and are hereinafter referred to as substrate strips 20'. The multi-layer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, the semiconductor layer 22A is alternatively referred to as a sacrificial layer, and the semiconductor layer 22B is alternatively referred to as a nanostructure. Portions of the multi-layer stack 22 'and underlying substrate strips 20' are collectively referred to as semiconductor strips 24.
In the above embodiments, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithographic processes may be used to pattern structures, including double patterning or multiple patterning processes. Typically, a dual-pattern or multi-pattern process combines a lithographic and a self-aligned process, allowing for creation of patterns with a pitch that is smaller than that obtainable using a single direct lithographic process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the GAA structure.
Fig. 3 illustrates the formation of isolation regions 26, which isolation regions 26 are also referred to as Shallow Trench Isolation (STI) regions throughout the specification. The corresponding process is shown as process 206 in process flow 200 shown in fig. 22. STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high Density Plasma Chemical Vapor Deposition (HDPCVD), CVD, and the like. STI region 26 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on, HDPCVD, or the like. A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, may then be performed to planarize the top surface of the dielectric material, with the remainder of the dielectric material being STI regions 26.
STI regions 26 are then recessed such that the top of semiconductor stripe 24 protrudes above the top surface 26T of the remainder of STI regions 26 to form protruding fins 28. Protruding fin 28 includes the top of substrate strip 20 'and multi-layer stack 22'. The recessing of STI regions 26 may be performed by a dry etching process, wherein, for example, NF 3 And NH 3 Is used as the etching gas. During the etching process, a plasma may be generated. Argon may also be included. According to the present inventionThe recessing of STI regions 26 is performed by a wet etch process, which is an alternative embodiment of the disclosure. For example, the etching chemistry may include HF.
Referring to fig. 4, a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of (protruding) fin 28. The corresponding process is shown as process 208 in process flow 200 shown in fig. 22. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 over the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by: the surface portions of protruding fins 28 are oxidized to form an oxide layer, or a dielectric layer such as a silicon oxide layer is deposited. For example, polysilicon or amorphous silicon may be used to form the dummy gate electrode 34, and other materials such as amorphous carbon may also be used. Each dummy gate stack 30 may also include a hard mask layer(s) 36 over the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a plurality of layers thereof. The dummy gate stack 30 may span a single or multiple protruding fins 28 and STI regions 26 between the protruding fins 28. The length direction of the dummy gate stack 30 is perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stack 30 includes: a dummy gate dielectric layer is formed, a dummy gate electrode layer is deposited over the dummy gate dielectric layer, one or more hard mask layers are deposited, and the formed layers are then patterned by a patterning process(s).
Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a material such as silicon nitride (SiN), silicon oxide (SiO 2 ) Dielectric materials such as silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The process of forming the gate spacer 38 may include: one or more dielectric layers are deposited and then an anisotropic etching process (es) is performed on the dielectric layer(s). The remainder of the dielectric layer(s) is gate spacers 38.
Fig. 5A and 5B show cross-sectional views of the structure shown in fig. 4. Fig. 5A shows the reference cross section A1-A1 in fig. 4, which cuts through the portion of the protruding fin 28 not covered by the dummy gate stack 30 and the gate spacers 38, and is perpendicular to the gate length direction. Fin spacers 38 are also shown on the sidewalls of protruding fins 28. Fig. 5B shows a reference cross section B-B in fig. 4, which is parallel to the length direction of the protruding fin 28.
Referring to fig. 6A and 6B, portions of protruding fins 28 not directly under dummy gate stack 30 and gate spacers 38 are recessed by an etching process to form recesses 42. The corresponding process is shown as process 210 in process flow 200 shown in fig. 22. For example, C may be used 2 F 6 ，CF 4 ，SO 2 ，HBr、Cl 2 And O 2 HBr, cl 2 、O 2 And CH (CH) 2 F 2 A dry etching process is performed to etch the multi-layer semiconductor stack 22 'and underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multi-layer semiconductor stack 22', or may be lower than the bottom of the multi-layer semiconductor stack 22' (as shown in fig. 6B). The etching may be anisotropic such that the sidewalls of the multi-layer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in fig. 6B.
Referring to fig. 7A and 7B, the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which lateral recess 41 is recessed from the edges of the respective upper and lower layer nanostructures 22B. The corresponding process is shown as process 212 in process flow 200 shown in fig. 22. Lateral recessing of the sacrificial semiconductor layer 22A may be achieved by a wet etching process using an etchant that is more selective to the material of the sacrificial semiconductor layer 22A (e.g., silicon germanium (SiGe)) than to the material of the nanostructures 22B and the substrate 20 (e.g., silicon (Si)). For example, in embodiments where the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructures 22B are formed of silicon, the wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etch process may be performed using a dipping process, a spraying process, etc., and may be performed using any suitable process temperature (e.g., between about 400 ℃ and about 600 ℃) and suitable process time (e.g., between about 100 seconds and about 1000 seconds). According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process, or a combination of dry and wet etching processes.
Fig. 8A and 8B illustrate the formation of the inner spacer 44. The corresponding process is shown as process 214 in process flow 200 shown in fig. 22. The forming process comprises the following steps: an inner spacer layer extending into the recess 41 is deposited and an etching process is performed to remove a portion of the inner spacer layer outside the recess 41, thereby leaving the inner spacer 44 in the recess 41. The inner spacer 44 may be formed of SiOCN, siON, siOC, siCN or the like, or include SiOCN, siON, siOC, siCN or the like. The inner spacers 44 may also be porous such that they have a lower k value below, for example, about 3.5. According to some embodiments, the etching of the inner spacer layer may be performed by a wet etching process, wherein the etching chemistry may include H 2 SO 4 Diluted HF, ammonia solution (NH) 4 OH, ammonia in water), or the like, or a combination thereof.
Referring to fig. 9A and 9B, epitaxial source/drain regions 48 are formed in the recesses 42. The corresponding process is shown as process 216 in process flow 200 shown in fig. 22. According to some embodiments, the source/drain regions 48 may stress the nanostructures 22B that serve as channels for the respective GAA transistors, thereby improving performance. According to some embodiments, the respective transistor is a p-type transistor, and the epitaxial source/drain regions 48 are formed correspondingly p-type by doping with p-type dopants. For example, silicon germanium boron (SiGeB), silicon boron (sibs), and the like may be grown to form p-type epitaxial source/drain regions 48. After recess 42 is filled with epitaxial regions 48, further growth of epitaxial regions 48 may also cause adjacent epitaxial regions 48 to merge with one another.
The subsequent figure numbers in fig. 10A, 10B and 10C through 19A, 19B and 19C may have the corresponding number followed by the letter A, B or C. Unless otherwise specified, letter a indicates that the corresponding drawing shows the same cross section as cross section A2-A2 in fig. 4, letter B indicates that the corresponding drawing shows the same reference cross section as reference cross section B-B in fig. 4, and letter C indicates that the corresponding drawing (except fig. 12C, 13C, 14C, and 17C) shows the same cross section as cross section A1-A1 in fig. 4.
Fig. 10A, 10B, and 10C show cross-sectional views of the structure after formation of a Contact Etch Stop Layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is shown as process 218 in process flow 200 shown in fig. 22. The CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. ILD 52 may comprise a dielectric material formed using, for example, FCVD, spin-on, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), or the like.
Fig. 11A and 11B to 17A, 17B, 17C, 17D, and 17E illustrate a process for forming a replacement gate stack. In fig. 11A and 11B, a planarization process, such as a CMP process or a mechanical polishing process, is performed to planarize the top surface of the ILD 52. The corresponding process is shown as process 220 in process flow 200 shown in fig. 22. According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, as shown in fig. 11B. According to alternative embodiments, the planarization process may expose the hard mask 36 and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), gate spacer 38, and ILD 52 are level with each other within process variations.
Next, the dummy gate electrode 34 (and hard mask 36, if any) is removed in one or more etching processes, thereby forming a recess 58, as shown in fig. 12A, 12B, and 12C. The corresponding process is shown as process 222 in process flow 200 shown in fig. 22. Fig. 12C shows a perspective view of the structure, and fig. 12A and 12B show cross-sectional views 12A-12A and 12B-12B, respectively, in fig. 12C. Portions of the dummy gate dielectric 32 in the recess 58 are also removed. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by a dry etching process. For example, the etching process may be performed using a reactive gas(s) that selectively etches the dummy gate electrode 34 at a faster rate than the ILD 52. Each recess 58 exposes and/or covers a portion of the multi-layer stack 22' including a future channel region in a subsequently completed nanofet. Respective portions of the multi-layer stack 22' are located between adjacent pairs of epitaxial source/drain regions 48.
Sacrificial layer 22A is then removed to extend recesses 58 between nanostructures 22B, and the resulting structure is shown in fig. 13A, 13B, and 13C. The corresponding process is shown as process 224 in process flow 200 shown in fig. 22. Fig. 13C shows a perspective view of the structure, and fig. 13A and 13B show cross-sectional views 13A-13A and 13B-13B, respectively, in fig. 13C. The sacrificial layer 22A may be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective to the material of the sacrificial layer 22A. The nanostructure 22B, substrate 20, STI region 26 remain relatively unetched compared to sacrificial layer 22A. According to some embodiments in which the sacrificial layer 22A comprises, for example, siGe and the nanostructure 22B comprises, for example, si or carbon doped silicon, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) may be used 4 OH), and the like, the sacrifice layer 22A is removed. It should be appreciated that while fig. 13A and subsequent figures show the cross-section of the nanostructure 22B as rectangular, the nanostructure 22B may have rounded corners, as shown by the dashed lines in fig. 13A.
Referring to fig. 14A, 14B, and 14C, a gate dielectric 62 is formed. The corresponding process is shown as process 226 in process flow 200 shown in fig. 22. Details of an example gate dielectric 62 are shown in fig. 14C. According to some embodiments, each gate dielectric 62 includes an interface layer 62A and a high-k dielectric layer 62B on interface layer 62A. Interface layer 62A may be formed of or include silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD. According to some embodiments, high-k dielectric layer 62B includes one or more dielectric layers. For example, the high-k dielectric layer 62B may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.
Referring to fig. 15A and 15B, a work function layer 64 is deposited, which includes a work function adjustment layer 64A and a work function layer 64B over the work function adjustment layer 64A. Since the work function adjustment layer 64A and work function layer 64B in combination determine the work function of the resulting gate electrode, the work function adjustment layer 64A is also part of the work function layer of the gate electrode. On the other hand, the work function layer 64 has a p-type work function as a whole, and the work function adjustment layer 64A may have an n-type work function (for adjusting the work function of the work function layer 64 as a whole), and thus it is referred to as a work function adjustment layer.
According to some embodiments, work function adjustment layer 64A includes aluminum and/or carbon. For example, the work function adjusting layer 64A may include aluminum carbon (AlC). Work function adjustment layer 64A may include other elements such as titanium and/or nitrogen. Alternatively, the work function adjustment layer 64A may be free of titanium and nitrogen.
According to some embodiments, the ratio of the atomic percent of aluminum to the atomic percent of carbon in work function adjustment layer 64A is in a range between about 0.1 and about 4. The work function adjustment layer 64A may have an n-type work function that is lower than an intermediate forbidden band (mid-gap) work function. The intermediate band gap work function may be at or near about 4.55eV and intermediate between the Si conduction band (4.1 eV) and the Si valence band (5 eV). According to some embodiments, the work function of work function tuning layer 64A may be in a range between about 4.1eV and about 4.45 eV.
The work function adjustment layer 64A is formed by a conformal deposition process. The corresponding process is shown as process 228 in process flow 200 shown in fig. 22. The work function adjustment layer 64A may be deposited by a thermal soaking process, and other processes such as ALD, CVD, etc. may also be used. According to some embodiments using a hot soaking process, the process gas may include both aluminum and carbon. For example, the process gas may include trimethylaluminum (TMA, al) 2 (CH 3 ) 6 ) Triethylaluminum (TEAL, al) 2 (C 2 H 5 ) 6 ) Etc., or a combination thereof. The flow rate of the process gas may be in a range between about 50sccm and about 7000 sccm.May also include, for example, argon, nitrogen (N) 2 ) And the like. The soak time may range between about 0.1 seconds and about 1800 seconds.
According to an alternative embodiment, the process for forming work function adjustment layer 64A includes a first hot dipping process using a carbon-containing process gas, thereby forming a carbon-containing layer. The process for forming the work function adjusting layer 64A further includes a second hot soaking process using an aluminum-containing process gas, thereby forming an aluminum-containing layer. For example, the carbon-containing process gas may include tetra (dimethylamino) titanium (TDMAT, C 8 H 24 N 4 Ti), and the like. The first process gas may include TMA and/or TEAL or a combination thereof in addition to TDMAT. Adding TMA and/or TEAL in addition to TDMAT has the function of adjusting the atomic percentages of carbon and aluminum in the resulting work function adjustment layer 64A. Other carbon-containing process gases may also be used, with or without aluminum contained therein. The thickness ratio of the thickness of the carbon-containing layer to the thickness of the aluminum-containing layer may be in a range between about 0.3 and about 3. The aluminum-containing process gas for the second hot soaking process may include TMA, TEAL, or a combination thereof. Other aluminum-containing process gases, with or without carbon contained therein, may also be used. The flow rates of each of the carbon-containing process gas and the aluminum-containing process gas may be in a range between about 50sccm and about 7000 sccm. May also include, for example, argon, nitrogen (N) 2 ) And the like. The order of the hot soaking process using the carbon-containing process gas and the hot soaking process using the aluminum-containing process gas may be reversed.
The first hot soaking process produces a deposition of a carbon-containing layer, which may or may not include aluminum, and may or may not include titanium, depending on the respective process gas. The second hot soaking process produces a deposition of an aluminum-containing layer, which may or may not include carbon, depending on the respective process gas. Since both the carbon-containing layer and the aluminum-containing layer are very thin, they can interdiffuse to form the aluminum-and carbon-containing layer. According to some embodiments, there is a single hot soaking process using a carbon-containing process gas and a single hot soaking process using an aluminum-containing process gas. According to an alternative embodiment, the formation of work function adjustment layer 64A includes a plurality of cycles, each cycle including one hot soaking process using a carbon-containing process gas and one hot soaking process using an aluminum-containing process gas.
The wafer temperature during deposition of work function adjustment layer 64A is controlled to be within a certain range. When the wafer temperature is too low, bonds in the process gas may not break and work function adjustment layer 64A may not be deposited. When the wafer temperature is too high, larger aluminum and carbon particles are generated and adversely affect the uniformity of the work function adjustment layer 64A. According to some embodiments, the wafer temperature is in a range between about 150 ℃ and about 550 ℃.
The chamber pressure in the chamber for depositing the work function adjusting layer 64A is also controlled within a certain range. When the chamber pressure is too low or too high, the work function adjusting layer 64A will not be deposited. According to some embodiments, the chamber pressure is in a range between about 0.1Torr and about 50 Torr.
According to some embodiments, work function layer 64B includes a p-type work function material, such as TiN, taN, W, and the like, combinations thereof, and/or multilayers thereof. The p-type work function material has a work function higher than the intermediate band gap work function. The work function layer 64B is formed in a conformal deposition process. The corresponding process is shown as process 230 in process flow 200 shown in fig. 22. When the work function layer 64B includes TiN, deposition is performed using a titanium-containing precursor and a nitrogen-containing precursor. The titanium-containing precursor may comprise TiCl 4 、TiCl 5 Etc., or a combination thereof. The nitrogen-containing precursor may include NH 3 . Multiple ALD cycles may be performed, each ALD cycle including pulsing and purging the titanium-containing precursor, and pulsing and purging the nitrogen-containing precursor.
According to some embodiments, tiCl is used therein 4 And NH 3 The deposition of TiN of work function layer 64B is performed as a process gas and when ALD is used, the temperature of wafer 10 may be in the range between about 270 ℃ and about 550 ℃. The chamber pressure may be in a range between about 0.5Torr and about 50 Torr.
When work function layer 64B includes TaN, deposition is performed using a tantalum-containing precursor and a nitrogen-containing precursor. The tantalum-containing precursor may comprise TaCl 4 、TaCl 5 Etc., or a combination thereof. The nitrogen-containing precursor may include NH 3 . Multiple ALD cycles may be performedA ring, each ALD cycle including pulsing and purging a tantalum-containing precursor, and pulsing and purging a nitrogen-containing precursor.
By interposing the work function adjustment layer 64A between the high-k dielectric layer 62B and the work function layer 64B, the work function of the work function layer 64 is unexpectedly increased, compared to the case where the work function layer 64 includes the work function layer 64B and does not include the work function adjustment layer 64A. Since the resulting transistor is a p-type transistor, the threshold voltage of the resulting transistor decreases as the work function increases. The decrease in threshold voltage may be due to carbon atoms forming dipoles with high-k gate dielectric layer 62B and may be due to the interaction of work function adjustment layer 64A with work function layer 64B and high-k gate dielectric layer 62B. According to some embodiments, by adjusting the atomic percentages of aluminum and carbon in work function adjustment layer 64A, and by selecting the thickness of work function adjustment layer 64A, the threshold voltage of the resulting transistor may be reduced by a difference greater than about 20mV, and the difference may be in a range between about 20mV and about 250mV, as compared to the case where work function adjustment layer 64A is not formed.
The work function adjusting layer 64A may be a thin layer and cannot be too thin or too thick. When the work function adjusting layer 64A is too thin, its function of adjusting the work function of the resulting work function layer 64 is too weak and the threshold voltage of the resulting transistor cannot be sufficiently lowered. When the work function adjustment layer 64A is too thick, since the material of the work function adjustment layer 64A has an n-type work function, it will lower the work function of the work function layer 64, rather than increasing the work function of the work function layer 64. Therefore, when the work function adjusting layer 64A is too thick, the threshold voltage of the resulting p-type transistor is not improved (lowered), which will actually deteriorate (increase) the threshold voltage of the resulting p-type transistor. In fact, when the thickness of the work function adjusting layer 64A is changed fromWith a gradual increase, the work function of work function layer 64 will initially gradually increase and the threshold voltage of the resulting p-type transistor will gradually decrease. When the thickness of the work function adjustment layer 64A reaches the threshold value, a further increase in the thickness of the work function adjustment layer 64A will cause the work function of the work function layer 64 to decrease, and causeThe threshold voltage of the resulting p-type transistor is increased. The threshold thickness of work function adjustment layer 64A (at which the trend of the threshold voltage is reversed) may be affected by various factors, such as the thickness of the material and overlying and underlying materials. According to some embodiments, the threshold thickness of work function adjustment layer 64A may be at about +. >And about->Within a range between. Therefore, the thickness of the work function adjusting layer 64A can be selected to be about +>And about->Within a range between.
The total thickness of work function layer 64 may be aboutAnd about->Within a range between. According to some embodiments, the thickness of work function tuning layer 64A may be at about +.>And about->Within a range between. The thickness ratio of the thickness of work function tuning layer 64A to the thickness of high-k dielectric layer 62B may be in a range between about 0.08 and about 2.5.
Fig. 16A and 16B illustrate the deposition of a conductive fill layer 66 to completely fill the remaining recesses 58. The conductive fill layer 66 is sufficiently far away from the semiconductor region (i.e., nanostructure 22B) that the conductive fill layer 66 does not act as a work function layer. The deposition of the conductive fill layer 66 may include CVD, ALD, and the like. According to some embodiments, the conductive fill layer 66 includes a glue layer 66A (fig. 16B) and a fill material 66B over the glue layer 66A. The glue layer 66A may be formed of TiN, taN, WN, WCN, tiCN, or the like, or a combination thereof, or include TiN, taN, WN, WCN, tiCN, or the like, or a combination thereof. The corresponding process is shown as process 232 in process flow 200 shown in fig. 22. Glue layer 66A may be in physical contact with work function layer 64B. The fill material 66B may include tungsten, cobalt, aluminum, and the like.
According to some embodiments in which both work function layer 64B and glue layer 66A comprise TiN, work function layer 64B extends into the space between adjacent nanostructures 22B, while glue layer 66A is entirely outside of the space. The formation of work function layer 64B and glue layer 66A may be separated from each other by a vacuum break process. The work function layer 64B and the glue layer 66A may or may not be distinguishable from each other. For example, the titanium atomic percent and the carbon atomic percent of work function layer 64B may be the same or different than the corresponding titanium atomic percent and carbon atomic percent in bond layer 66A.
After depositing the glue layer 66A, a filler material 66B is deposited. A planarization process, such as a CMP process or a mechanical polishing process, is then performed to remove the excess portions of gate dielectric 62, work function layer 64, and conductive fill layer 66, which are above the top surface of ILD 52. The corresponding process is shown as process 234 in process flow 200 shown in fig. 22. The resulting structure is shown in fig. 17A and 17B. The remaining conductive fill layer 66 and work function layer 64 are collectively referred to as a gate electrode 68. The gate electrode 68 and gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting nanofet.
Fig. 17C shows a perspective view of the structure shown in fig. 17A and 17B, wherein the cross-sectional views shown in fig. 17A and 17B are taken from cross-sections 17A-17A and 17B-17B, respectively, in fig. 17C. Fig. 17D and 17E show horizontal cross-sectional views of the structure shown in fig. 17A, 17B and 17C, wherein these horizontal cross-sectional views are taken from horizontal planes 17D-17D and 17E-17E, respectively, in fig. 17B.
In the process shown in fig. 18A, 18B and 18C, the gate stack 70 (including the gate dielectric 62 and the corresponding overlying gate electrode 68) is recessed, thereby forming a recess directly above the gate stack 70 and between opposing portions of the gate spacers 38. A gate mask 74 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each recess followed by a planarization process to remove excess portions of the dielectric material that extend above ILD 52. The corresponding process is shown as process 236 in process flow 200 shown in fig. 22. A subsequently formed gate contact (e.g., gate contact plug 80, as discussed below with respect to fig. 19A and 19B) passes through gate mask 74 to contact the top surface of recessed gate electrode 68.
As further shown in fig. 18A, 18B, and 18C, ILD 76 is deposited over ILD 52 and over gate mask 74. The corresponding process is shown as process 238 in process flow 200 shown in fig. 22. An etch stop layer (not shown) may be deposited (or not deposited) prior to forming ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, and the like.
In fig. 19A, 19B and 19C, ILD 76, ILD 52, CESL 50 and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) exposing the epitaxial source/drain regions 48 and/or gate stack 70. The recess may be formed by etching using an anisotropic etching process such as RIE, NBE, or the like. According to some embodiments, the recess may be formed by etching through ILD 76 and ILD 52 using a first etching process, etching through gate mask 74 using a second etching process, and possibly through CESL 50 using a third etching process. Although fig. 19B shows the contact plugs 80A and 80B in the same cross-section, in various embodiments, the contact plugs 80A and 80B may be formed in different cross-sections, thereby reducing the risk of shorting to each other.
After forming the recess, silicide regions 78 are formed over the epitaxial source/drain regions 48 (fig. 19B and 19C). The corresponding process is shown as process 240 in process flow 200 shown in fig. 22. According to some embodiments, silicide regions 78 are formed by: a metal layer (not shown) is first deposited that is capable of reacting with the underlying semiconductor material (e.g., silicon germanium, germanium) of epitaxial source/drain regions 48 to form silicide and/or germanide regions; a thermal anneal process is then performed to form silicide regions 78. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, and the like. Unreacted portions of the deposited metal are then removed, for example, by an etching process.
Contact plugs 80B are then formed over silicide regions 78. Further, a contact plug 80A (which may also be referred to as a gate contact plug) is also formed in the recess, and is over the gate electrode 68 and in contact with the gate electrode 68. The corresponding process is shown as process 242 in process flow 200 shown in fig. 22. The contact plugs 80A and 80B may each include one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, according to some embodiments, contact plugs 80A and 80B each include a barrier layer and a conductive material and are electrically coupled to underlying conductive features (e.g., gate stack 70 and/or silicide regions 78 in the illustrated embodiment). The barrier layer may include titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP process, may be performed to remove excess material from the surface of ILD 76. Thereby forming nanofet 82 as a P-shaped transistor.
FIG. 20 shows a cross-sectional view of a detailed nanostructure and gate stack of four p-type transistors 82-1, 82-2, 82-3, and 82-4, including gate stacks 70-1, 70-2, 70-3, and 70-4, respectively. The P-type transistors 82-1, 82-2, 82-3, and 82-4 have P-type source/drain regions 48 (shown in fig. 19B and 19C). Transistors 82-1, 82-2, 82-3, and 82-4 are formed in the same device die and on the same semiconductor substrate. According to some embodiments, work function tuning layers 64A-1, 64A-2, and 64A-3 are different from each other, while other respective layers in gate stacks 70-1, 70-2, and 70-3 are identical to each other (and may be formed sharing a common process). For example, work function modifying layers 64A-1 and 64A-2, 64A-3 may have different thicknesses, and/or different atomic percentages of carbon and/or aluminum. Accordingly, the threshold voltages of transistors 82-1, 82-2, and 82-3 may be different from one another. According to some embodiments, the thicknesses T1, T2, and T3 of the respective work function modifying layers 64A-1 and 64A-2, 64A-3 have a relationship T1 < T2 < T3, where the work function modifying layers 64A-1, 64A-2, and 64A-3 may have the same composition. According to some embodiments, the threshold voltage of transistor 82-2 is lower than the threshold voltages of both transistors 82-1 and 82-3. On the other hand, although T1 < T3, the threshold voltage of transistor 82-1 may be less than, equal to, or greater than the threshold voltage of transistor 82-3.
Fig. 20 also shows a p-type transistor 82-4 whose gate stack 70-4 is similar to gate stacks 70-1 and 70-2 except that a work function adjustment layer is not formed. Thus, the threshold voltage of p-type transistor 82-4 may be greater than the threshold voltages of p-type transistors 82-1 and 82-2. On the other hand, the threshold voltage of p-type transistor 82-4 may be less than, equal to, or greater than the threshold voltage of p-type transistor 82-3.
Fig. 21 schematically illustrates the distribution of some elements in the gate stack 70 (fig. 19B) as a function of vertical distance from the nanostructure 22B. The illustrated distribution includes carbon atomic percent and aluminum atomic percent (in work function adjustment layer 64A), titanium atomic percent (in work function layer 64B and glue layer 66A), and hafnium atomic percent (in high-k dielectric layer 62B). The X-axis represents the vertical distance in the direction of arrow 84 in fig. 19B. The Y-axis represents atomic percent values. Although the elements in the gate stack 70 diffuse away from the place where they are deposited, the carbon atomic percent and/or the aluminum atomic percent may have peaks in the work function adjusting layer 64A, according to some embodiments. Assuming that work function layer 64B and bond line 66A both include titanium, the atomic percent of titanium has a peak in work function layer 64B or bond line 66A, or at the interface between work function layer 64B and bond line 66A. It is assumed that high-k dielectric layer 62B includes hafnium, with the atomic percent of hafnium having a peak in high-k dielectric layer 62B.
Embodiments of the present disclosure have some advantageous features. By inserting a work function tuning layer (which may include aluminum and carbon) between the work function layer and the corresponding underlying high-k dielectric layer, the threshold voltage of the resulting p-type transistor may be tuned and may be lowered. By selectively forming or not forming the work function adjusting layer, and by adjusting the thickness and composition of the work function adjusting layer, a plurality of p-type transistors having different work functions can be formed.
According to some embodiments of the present disclosure, a method comprises: forming a dummy gate stack over the semiconductor region; forming source/drain regions on sides of the dummy gate stack; removing the dummy gate stack to form a trench, wherein the semiconductor region is exposed to the trench; forming a gate dielectric layer extending into the trench; depositing a work function tuning layer on the gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon; depositing a p-type work function layer over the work function adjustment layer; and performing a planarization process to remove excess portions of the p-type work function layer, the work function adjustment layer, and the gate dielectric layer to form a gate stack. In an embodiment, depositing the work function adjustment layer includes: a hot soaking process using a process gas comprising aluminum and carbon. In an embodiment, the process gas is selected from the group consisting of trimethylaluminum (TMA, al) 2 (CH 3 ) 6 ) Triethylaluminum (TEAL, al) 2 (C 2 H 5 ) 6 ) And combinations thereof.
In an embodiment, the hot soaking process is performed at a wafer temperature in a range between about 150 ℃ and about 550 ℃. In an embodiment, depositing the work function adjustment layer includes: a hot soaking process using a first process gas comprising aluminum and a second process gas comprising carbon. In an embodiment, the first process gas is selected from the group consisting of trimethylaluminum (TMA, al) 2 (CH 3 ) 6 ) Triethylaluminum (TEAL, al) 2 (C 2 H 5 ) 6 ) And combinations thereof, and the second process gas comprises tetra (dimethylamino) titanium (TDMAT, C 8 H 24 N 4 Ti). In an embodiment, forming the gate dielectric layer includes: a high-k dielectric layer is deposited, and wherein the work function tuning layer is in physical contact with the high-k dielectric layer.
In an embodiment, the gate dielectric layer comprises a first portion surrounding the semiconductor region and a second portion surrounding an additional semiconductor region overlapping the semiconductor region, and wherein the p-type work function layer comprises a third portion surrounding the first portion and a fourth portion surrounding the second portion, and wherein the third portion is physically connected to the fourth portion. In an embodiment, the work function modifying layer has an n-type work function, the work function modifying layer and the p-type work function layer combination has a p-type work function, and wherein the source/drain regions are p-type. In an embodiment, the method further comprises: a titanium-containing layer is deposited over and in contact with the p-type work function layer. In an embodiment, the ratio of the atomic percent of aluminum to the atomic percent of carbon in the work function tuning layer is in a range between about 0.1 and about 4.
According to some embodiments of the present disclosure, an integrated circuit structure includes: a semiconductor region; a gate stack over a semiconductor region, the gate stack comprising: a high-k gate dielectric layer; a work function tuning layer on the high-k gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon; and a p-type work function layer over the work function adjustment layer; and p-type source/drain regions flanking the gate stack. In an embodiment, there are no peaks of titanium and nitrogen in the work function tuning layer. In an embodiment, the ratio of the atomic percent of aluminum to the atomic percent of carbon in the work function tuning layer is in a range between about 0.1 and about 4. In an embodiment, a ratio of the first thickness of the work function tuning layer to the second thickness of the high-k gate dielectric layer is in a range between about 0.08 and about 2.5. In an embodiment, the p-type work function layer comprises titanium nitride.
According to some embodiments of the present disclosure, an integrated circuit structure includes: a first transistor, comprising: a first semiconductor region; a first gate spacer and a second gate spacer over the first semiconductor region; and a first gate stack over the first semiconductor region and between the first gate spacer and the second gate spacer, the first gate stack comprising: a first high-k dielectric layer on the first semiconductor region; an n-type work function layer over and physically contacting the first high-k dielectric layer; a first p-type work function layer over and contacting the n-type work function layer; and a metal region over and contacting the first p-type work function layer; and p-type source/drain regions flanking the first gate stack. In an embodiment, the integrated circuit structure further comprises a second transistor, the second transistor comprising: a second semiconductor region; and a second gate stack comprising: a second high-k dielectric layer on the second semiconductor region; and a second p-type work function layer physically contacting the second high-k dielectric layer. In an embodiment, the ratio of the atomic percent of aluminum to the atomic percent of carbon in the n-type work function layer is in a range between about 0.1 and about 4.
The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Example 1. A method of fabricating an integrated circuit structure, comprising: forming a dummy gate stack over the semiconductor region; forming source/drain regions on sides of the dummy gate stack; removing the dummy gate stack to form a trench, wherein the semiconductor region is exposed to the trench; forming a gate dielectric layer extending into the trench; depositing a work function tuning layer on the gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon; depositing a p-type work function layer over the work function adjustment layer; and performing a planarization process to remove excess portions of the p-type work function layer, the work function adjustment layer, and the gate dielectric layer to form a gate stack.
Example 2. The method of example 1, wherein depositing the work function adjustment layer comprises: a hot soaking process using a process gas comprising both aluminum and carbon.
Example 3 according to example 2Wherein the process gas is selected from the group consisting of trimethylaluminum (TMA, al) 2 (CH 3 ) 6 ) Triethylaluminum (TEAL, al) 2 (C 2 H 5 ) 6 ) And combinations thereof.
Example 4. The method of example 2, wherein the hot soaking process is performed at a wafer temperature in a range between 150 ℃ and 550 ℃.
Example 5. The method of example 1, wherein depositing the work function adjustment layer comprises: a hot soaking process using a first process gas comprising aluminum and a second process gas comprising carbon.
Example 6 the method of example 5, wherein the first process gas is selected from the group consisting of trimethylaluminum (TMA, al) 2 (CH 3 ) 6 ) Triethylaluminum (TEAL, al) 2 (C 2 H 5 ) 6 ) And combinations thereof, and the second process gas comprises tetra (dimethylamino) titanium (TDMAT, C 8 H 24 N 4 Ti)。
Example 7 the method of example 1, wherein forming the gate dielectric layer comprises: a high-k dielectric layer is deposited, and wherein the work function tuning layer is in physical contact with the high-k dielectric layer.
Example 8 the method of example 1, wherein the gate dielectric layer comprises a first portion surrounding the semiconductor region and a second portion surrounding an additional semiconductor region overlapping the semiconductor region, and wherein the p-type work function layer comprises a third portion surrounding the first portion and a fourth portion surrounding the second portion, and wherein the third portion physically connects the fourth portion.
Example 9. The method of example 1, wherein the work function adjustment layer has an n-type work function, the work function adjustment layer and the p-type work function layer combination has a p-type work function, and wherein the source/drain regions are p-type.
Example 10. The method of example 1, further comprising: a titanium-containing layer is deposited over and in contact with the p-type work function layer.
Example 11. The method of example 1, wherein a ratio of an atomic percent of aluminum to an atomic percent of carbon in the work function adjustment layer is in a range between 0.1 and 4.
Example 12. An integrated circuit structure, comprising: a semiconductor region; a gate stack over the semiconductor region, the gate stack comprising: a high-k gate dielectric layer; a work function tuning layer on the high-k gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon; and a p-type work function layer over the work function adjustment layer; and p-type source/drain regions flanking the gate stack.
Example 13. The integrated circuit structure of example 12, wherein the work function tuning layer is devoid of peaks of titanium and nitrogen.
Example 14. The integrated circuit structure of example 12, wherein a ratio of the atomic percent of aluminum to the atomic percent of carbon in the work function modifying layer is in a range between 0.1 and 4.
Example 15. The integrated circuit structure of example 12, wherein a ratio of the first thickness of the work function adjustment layer to the second thickness of the high-k gate dielectric layer is in a range between 0.08 and 2.5.
Example 16. The integrated circuit structure of example 12, wherein the p-type work function layer comprises titanium nitride.
Example 17. An integrated circuit structure, comprising: a first transistor, comprising: a first semiconductor region; a first gate spacer and a second gate spacer over the first semiconductor region; and a first gate stack over the first semiconductor region and between the first gate spacer and the second gate spacer, the first gate stack comprising: a first high-k dielectric layer on the first semiconductor region; an n-type work function layer over and physically contacting the first high-k dielectric layer; a first p-type work function layer over and contacting the n-type work function layer; and a metal region over and contacting the first p-type work function layer; and p-type source/drain regions flanking the first gate stack.
Example 18 the integrated circuit structure of example 17, further comprising a second transistor, the second transistor comprising: a second semiconductor region; and a second gate stack comprising: a second high-k dielectric layer on the second semiconductor region; and a second p-type work function layer physically contacting the second high-k dielectric layer.
Example 19 the integrated circuit structure of example 17, wherein the n-type work function layer comprises aluminum and carbon.
Example 20 the integrated circuit structure of example 17, wherein a ratio of aluminum atomic percent to carbon atomic percent in the n-type work function layer is in a range between 0.1 and 4.

Claims (10)

1. A method of fabricating an integrated circuit structure, comprising:
forming a dummy gate stack over the semiconductor region;
forming source/drain regions on sides of the dummy gate stack;
removing the dummy gate stack to form a trench, wherein the semiconductor region is exposed to the trench;
forming a gate dielectric layer extending into the trench;
depositing a work function tuning layer on the gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon;
depositing a p-type work function layer over the work function adjustment layer; and
A planarization process is performed to remove excess portions of the p-type work function layer, the work function adjustment layer, and the gate dielectric layer to form a gate stack.
2. The method of claim 1, wherein depositing the work function adjustment layer comprises: a hot soaking process using a process gas comprising both aluminum and carbon.
3. The method of claim 2, wherein the process gas is selected from the group consisting of trimethylaluminum (TMA, al) 2 (CH 3 ) 6 ) Triethylaluminum (TEAL, al) 2 (C 2 H 5 ) 6 ) And combinations thereof.
4. The method of claim 2, wherein the thermal soaking process is performed at a wafer temperature in a range between 150 ℃ and 550 ℃.
5. The method of claim 1, wherein depositing the work function adjustment layer comprises: a hot soaking process using a first process gas comprising aluminum and a second process gas comprising carbon.
6. The method of claim 5, wherein the first process gas is selected from the group consisting of trimethylaluminum (TMA, al) 2 (CH 3 ) 6 ) Triethylaluminum (TEAL, al) 2 (C 2 H 5 ) 6 ) And combinations thereof, and the second process gas comprises tetra (dimethylamino) titanium (TDMAT, C 8 H 24 N 4 Ti)。
7. The method of claim 1, wherein forming the gate dielectric layer comprises: a high-k dielectric layer is deposited, and wherein the work function tuning layer is in physical contact with the high-k dielectric layer.
8. The method of claim 1, wherein the gate dielectric layer comprises a first portion surrounding the semiconductor region and a second portion surrounding an additional semiconductor region overlapping the semiconductor region, and wherein the p-type work function layer comprises a third portion surrounding the first portion and a fourth portion surrounding the second portion, and wherein the third portion physically connects the fourth portion.
9. An integrated circuit structure, comprising:
a semiconductor region;
a gate stack over the semiconductor region, the gate stack comprising:
a high-k gate dielectric layer;
a work function tuning layer on the high-k gate dielectric layer, wherein the work function tuning layer comprises aluminum and carbon; and
a p-type work function layer over the work function adjustment layer; and
p-type source/drain regions flanking the gate stack.
10. An integrated circuit structure, comprising:
a first transistor, comprising:
a first semiconductor region;
a first gate spacer and a second gate spacer over the first semiconductor region; and
a first gate stack over the first semiconductor region and between the first gate spacer and the second gate spacer, the first gate stack comprising:
A first high-k dielectric layer on the first semiconductor region;
an n-type work function layer over and physically contacting the first high-k dielectric layer;
a first p-type work function layer over and contacting the n-type work function layer; and
a metal region over and contacting the first p-type work function layer; and
p-type source/drain regions flanking the first gate stack.
CN202210825459.XA 2022-03-04 2022-07-14 Integrated circuit structure and method for manufacturing the same Pending CN116469836A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/268,876 2022-03-04
US17/804,971 US20230282712A1 (en) 2022-03-04 2022-06-01 Work-Function Layers in the Gates of pFETs
US17/804,971 2022-06-01

Publications (1)

Publication Number Publication Date
CN116469836A true CN116469836A (en) 2023-07-21

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Country Status (1)

Country Link
CN (1) CN116469836A (en)

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