CN117790411A - Method for reducing contact hole resistance and transistor device - Google Patents
Method for reducing contact hole resistance and transistor device Download PDFInfo
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- CN117790411A CN117790411A CN202311824172.6A CN202311824172A CN117790411A CN 117790411 A CN117790411 A CN 117790411A CN 202311824172 A CN202311824172 A CN 202311824172A CN 117790411 A CN117790411 A CN 117790411A
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- interlayer dielectric
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000010410 layer Substances 0.000 claims abstract description 115
- 239000011229 interlayer Substances 0.000 claims abstract description 43
- 238000000137 annealing Methods 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 230000007423 decrease Effects 0.000 claims description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for reducing contact hole resistance and a transistor device. The method for reducing the contact hole resistance comprises the following steps: forming a conductive structure layer on the surface of the device structure, wherein the conductive structure layer has a first thickness; forming an ozone-tetraethoxysilane layer on the surface of the device structure to serve as an interlayer dielectric layer, and performing annealing treatment on at least the interlayer dielectric layer; at least one through hole is formed in the interlayer dielectric layer, plasma bombardment is carried out on at least the bottom area, close to the conductive structure layer, of the through hole, of the conductive structure layer exposed at the bottom of the through hole, and the thickness of the conductive structure layer exposed at the bottom of the through hole is reduced from the first thickness to the second thickness; and filling conductive materials in the through holes to form the electric contact holes. The invention can solve the problem of larger contact resistance of the electric contact hole caused by using ozone-tetraethoxysilane to replace HDP technology as an interlayer dielectric layer.
Description
Technical Field
The invention particularly relates to a method for reducing contact hole resistance and a transistor device, and belongs to the technical field of semiconductors.
Background
In the wafer processing process, high density plasma chemical vapor deposition (HDP) silicon oxide is commonly used as an interlayer dielectric layer (ILD) between an underlying device and a first layer of metal wire due to its good filling properties and high density. However, the HDP process may cause Plasma damage (Plasma damage), and even damage the gate oxide layer, which affects the device performance. To prevent plasma damage, ozone-tetraethoxysilane (O 3 TEOS) is introduced as material for the interlayer dielectric layer. Due to O 3 The oxygen content of silicon dioxide manufactured by TEOS material is high, and the oxygen content of the bottom of a contact hole (CT) formed after etching is also highAfter the contact hole is filled with tungsten metal, the contact resistance of the tungsten plug is 2.5 times that of the HDP process.
Disclosure of Invention
The invention mainly aims to provide a method for reducing the contact hole resistance and a transistor device, which are used for solving the problems that O is adopted in the prior art 3 The problem of large contact hole resistance caused when TEOS silicon oxide is used for replacing HDP silicon oxide as the material of the interlayer dielectric layer is solved, and the defects in the prior art are overcome.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
in one aspect, the present invention provides a method for reducing the resistance of a contact hole, including:
forming at least one conductive structure layer on the surface of the device structure, and electrically connecting the conductive structure layer with the device structure, wherein the conductive structure layer has a first thickness;
forming an ozone-tetraethoxysilane layer on the surface of the device structure to serve as an interlayer dielectric layer, and enabling the interlayer dielectric layer to cover the conductive structure layer;
annealing treatment is carried out on at least the interlayer dielectric layer;
forming at least one through hole in the interlayer dielectric layer in a processing way, and exposing at least part of the conductive structure layer at the bottom of the through hole;
at least carrying out plasma bombardment on the conductive structure layer exposed at the bottom of the through hole in the area, close to the bottom of the conductive structure layer, of the through hole, wherein the thickness of the conductive structure layer exposed at the bottom of the through hole is reduced from a first thickness to a second thickness;
filling conductive materials in the through holes so as to form electric contact holes, and electrically connecting the electric contact holes with the conductive structure layer;
and forming a metal wire on the interlayer dielectric layer, and electrically connecting the metal wire with the electric contact hole.
The invention also provides a transistor device obtained by the method for reducing the contact hole resistance.
Compared with the prior art, the invention has the advantages that:
the invention provides a method for reducing the contact resistance of tungsten plugs in contact holes, which can solve the problem of ozone-tetraethoxysilane (O) 3 TEOS) instead of HDP process as interlayer dielectric layer to cause the problem of larger contact resistance of electric contact hole, which is characterized by adding deposition O 3 The key point of the high temperature annealing process after the TEOS interlayer dielectric layer and the plasma bombardment process before the formation of the electric contact holes is that the temperature of the annealing process and the thickness reduction of the metal silicide caused by the argon bombardment need to be matched with each other, so that the required contact resistance can be obtained.
Drawings
FIG. 1 is a schematic diagram of a device structure formed on a substrate in accordance with an exemplary embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure after forming a conductive structure layer on a device structure in an exemplary embodiment of the present invention; the method comprises the steps of carrying out a first treatment on the surface of the
FIG. 3 is a schematic diagram of an exemplary embodiment of the present invention after an interlayer dielectric layer is formed on a substrate;
FIG. 4 is a schematic diagram of a structure after etching a via hole in an interlayer dielectric layer according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure of an interlayer dielectric layer according to an exemplary embodiment of the present invention after plasma bombardment of the bottom of the via hole;
fig. 6 is a schematic structural diagram of a via hole filled with a conductive material to form an electrical contact hole according to an exemplary embodiment of the present invention.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, the implementation process, the principle and the like are further explained as follows.
In one aspect, the present invention provides a method for reducing the resistance of a contact hole, including:
forming at least one conductive structure layer on the surface of the device structure, and electrically connecting the conductive structure layer with the device structure, wherein the conductive structure layer has a first thickness;
forming an ozone-tetraethoxysilane layer on the surface of the device structure to serve as an interlayer dielectric layer, and enabling the interlayer dielectric layer to cover the conductive structure layer;
annealing treatment is carried out on at least the interlayer dielectric layer;
forming at least one through hole in the interlayer dielectric layer in a processing way, and exposing at least part of the conductive structure layer at the bottom of the through hole;
at least carrying out plasma bombardment on the conductive structure layer exposed at the bottom of the through hole in the area, close to the bottom of the conductive structure layer, of the through hole, wherein the thickness of the conductive structure layer exposed at the bottom of the through hole is reduced from a first thickness to a second thickness;
filling conductive materials in the through holes so as to form electric contact holes, and electrically connecting the electric contact holes with the conductive structure layer;
and forming a metal wire on the interlayer dielectric layer, and electrically connecting the metal wire with the electric contact hole.
Further, the temperature of the annealing treatment is 250-350 ℃, and the time of the annealing treatment is 30-100 min.
Further, the through hole penetrates through the interlayer dielectric layer along the thickness direction of the interlayer dielectric layer, and the radial cross-sectional area of the through hole gradually decreases along the direction towards the conductive structure layer.
Further, the conductive structure layer comprises a first portion and a second portion, the first portion is exposed at the bottom of the through hole, the second portion is arranged around the first portion, the second portion is covered by the interlayer dielectric layer, after the plasma bombardment, the thickness of the first portion is reduced from a first thickness to a second thickness, and the thickness of the second portion is kept to be the first thickness.
Further, the first thickness is 150nm-250nm.
Further, the conductive structure layer exposed at the bottom of the via hole is thinnedDegree of
Further, the device structure comprises a source terminal contact area, a drain terminal contact area and a grid electrode,
the method specifically comprises the following steps: forming a plurality of conductive structure layers on the surface of the device structure, wherein the plurality of conductive structure layers are respectively correspondingly arranged on the source end contact area, the drain end contact area and the grid electrode, and the plurality of conductive structure layers are respectively and correspondingly electrically connected with the source end contact area, the drain end contact area and the grid electrode;
and processing a plurality of through holes in the interlayer dielectric layer, wherein part of each conductive structure layer is exposed at the bottom of one through hole.
Further, the conductive structure layer comprises a metal silicide layer.
Further, the conductive material comprises metallic tungsten.
The invention also provides a transistor device obtained by the method for reducing the contact hole resistance.
The following description will further explain the technical scheme, implementation process and principle, etc. by referring to the drawings and specific embodiments, and unless otherwise indicated, the semiconductor processing technology, the equipment, the annealing equipment and the plasma bombardment equipment adopted by the embodiment of the invention are all known to those skilled in the art.
Examples
A preparation method of a MOS transistor comprises the following steps:
1) A silicon substrate 1 is provided, and a device structure 2 of a MOS transistor is formed on the silicon substrate 1 by processing, as shown in fig. 1, the device structure 2 includes a source contact region 3, a drain contact region 4, a gate protection structure 5, a gate oxide layer 6, and a polysilicon gate 7, the source contact region 3, the drain contact region 4 are disposed in the silicon substrate 1, and top surfaces of the source contact region 3, the drain contact region 4 are flush with the top surface of the silicon substrate 1, the gate oxide layer 6 is disposed on the top surface of the silicon substrate 1, the polysilicon gate 7 is disposed on the gate oxide layer 6, and the source contact region 3, the drain contact region 4 are distributed in both side regions of the polysilicon gate 7, the gate protection structure 5 is disposed on the top surface of the silicon substrate 1, and the gate protection structure 5 is disposed around the gate oxide layer 6 and the polysilicon gate 7.
It should be noted that, of course, the device structure 2 may also include other functional structure layers or functional regions for providing the device structure 2 with a MOS transistor function, and the process for processing the device structure 2 for forming the MOS transistor is known to those skilled in the art, and the specific structure of the device structure 2 of the MOS transistor and the forming process thereof are not modified in the present invention, so will not be described in detail.
2) A metal silicide layer (i.e. the conductive structure layer, the following description is the same) 8 with a thickness of 150nm-250nm is formed on the top surfaces of the source contact region 3, the drain contact region 4 and the polysilicon gate 7, and the source contact region 3, the drain contact region 4 and the polysilicon gate 7 are electrically connected with the corresponding metal silicide layer 8, as shown in fig. 2.
3) Deposition of ozone-tetraethoxysilane (O) on top surface of silicon substrate 1 using Chemical Vapor Deposition (CVD) process 3 TEOS) forms an interlayer dielectric layer 9 as shown in fig. 3.
4) And annealing the device after the interlayer dielectric layer 9 is formed at the temperature of 250-350 ℃ for 30-100 min.
5) Three through holes 10 are etched in the interlayer dielectric layer 9 from the top surface of the interlayer dielectric layer 9, the three through holes 10 respectively correspond to the three metal silicide layers 8, and a part of each metal silicide layer 8 is exposed from the bottom of one through hole 10, as shown in fig. 4, in this embodiment, the radial cross-sectional area of each through hole 10 gradually decreases in the direction toward the metal silicide layer 8.
6) Bombarding the bottom region of the through hole 10 by adopting argon plasma, so that the part of the metal silicide layer 8 at the bottom of the through hole 10, which is exposed in the through hole 10, is thinned to a thickness ofAs shown in fig. 5.
7) A chemical vapor deposition process is used to deposit metal tungsten within the via 10 to form an electrical contact hole 11 (i.e., a tungsten plug), the bottom of the electrical contact hole 11 being electrically connected to the metal silicide layer 8, as shown in fig. 6.
8) A metal wire is formed on the top surface of the interlayer dielectric layer 9 and electrically connected to the electrical contact hole.
The present inventors have obtained a series of MOS transistors by varying the time of the annealing treatment, controlling the thickness of the metal silicide layer to be reduced, and measuring the contact resistance of the electrical contact holes of the obtained series of MOS transistors, as shown in table 1, with reference to a method for manufacturing a MOS transistor provided in the examples.
TABLE 1 contact resistance of contact holes of a series of MOS transistors
As can be seen from table 1, the electrical contact resistance of the MOS transistor obtained by the method provided by the invention is reduced to a baseline level or even lower, and the electrical resistance of the electrical contact hole of the MOS transistor obtained by the method provided by the invention is within the resistance parameter acceptance range (less than baseline contact resistance or not more than ten percent of baseline contact resistance), because the annealing treatment and the argon plasma bombardment contact hole adopted by the invention can reduce the oxygen content at the bottom of the interlayer dielectric layer, thereby reducing the contact resistance of the formed electrical contact hole.
Specifically, ozone-tetraethoxysilane (O 3 TEOS) is introduced as an interlayer dielectric layer to eliminate the plasma damage problem. But O is 3 The dielectric layer formed by TEOS is loose in dielectric medium and high in oxygen content, the oxygen content at the bottom of a contact hole (CT) formed after etching is also high, so that after the contact hole is filled with metal tungsten, the contact resistance of a tungsten plug is increased, the dielectric medium can be densified through high-temperature annealing treatment, a part of oxygen is removed, the oxygen at the bottom can be removed in a physical mode by argon plasma bombardment, and the two modes overlap each otherThe preparation can obtain better effect and reduce contact resistance.
The invention provides a method for reducing the contact resistance of tungsten plugs in contact holes, which can solve the problem of ozone-tetraethoxysilane (O) 3 TEOS) instead of HDP process as interlayer dielectric layer to cause the problem of larger contact resistance of electric contact hole, which is characterized by adding deposition O 3 The key point of the high temperature annealing process after the TEOS interlayer dielectric layer and the plasma bombardment process before the formation of the electric contact holes is that the temperature of the annealing process and the thickness reduction of the metal silicide caused by the argon bombardment need to be matched with each other, so that the required contact resistance can be obtained.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (10)
1. A method for reducing contact hole resistance, comprising:
forming at least one conductive structure layer on the surface of the device structure, and electrically connecting the conductive structure layer with the device structure, wherein the conductive structure layer has a first thickness;
forming an ozone-tetraethoxysilane layer on the surface of the device structure to serve as an interlayer dielectric layer, and enabling the interlayer dielectric layer to cover the conductive structure layer;
annealing treatment is carried out on at least the interlayer dielectric layer;
forming at least one through hole in the interlayer dielectric layer in a processing way, and exposing at least part of the conductive structure layer at the bottom of the through hole;
at least carrying out plasma bombardment on the conductive structure layer exposed at the bottom of the through hole in the area, close to the bottom of the conductive structure layer, of the through hole, wherein the thickness of the conductive structure layer exposed at the bottom of the through hole is reduced from a first thickness to a second thickness;
and filling conductive materials in the through holes so as to form electric contact holes, and electrically connecting the electric contact holes with the conductive structure layer.
2. The method for reducing contact hole resistance according to claim 1, wherein: the temperature of the annealing treatment is 250-350 ℃, and the time of the annealing treatment is 30-100 min.
3. The method for reducing contact hole resistance according to claim 1, wherein: the through hole penetrates through the interlayer dielectric layer along the thickness direction of the interlayer dielectric layer, and the radial cross-sectional area of the through hole gradually decreases along the direction towards the conductive structure layer.
4. The method for reducing contact hole resistance according to claim 1, wherein: the conductive structure layer comprises a first part and a second part, wherein the first part is exposed at the bottom of the through hole, the second part is arranged around the first part, the second part is covered by the interlayer dielectric layer, after the plasma bombardment, the thickness of the first part is reduced from a first thickness to a second thickness, and the thickness of the second part is kept to be the first thickness.
5. The method for reducing contact hole resistance according to claim 1 or 4, wherein: the first thickness is 150nm-250nm.
6. The method for reducing contact hole resistance according to claim 1 or 4, wherein: the conductive structure layer exposed at the bottom of the through hole is thinned to a thickness of
7. The method of reducing contact hole resistance according to claim 1 or 4, wherein the device structure comprises a source contact region, a drain contact region and a gate,
the method specifically comprises the following steps: forming a plurality of conductive structure layers on the surface of the device structure, wherein the plurality of conductive structure layers are respectively correspondingly arranged on the source end contact area, the drain end contact area and the grid electrode, and the plurality of conductive structure layers are respectively and correspondingly electrically connected with the source end contact area, the drain end contact area and the grid electrode;
and processing a plurality of through holes in the interlayer dielectric layer, wherein part of each conductive structure layer is exposed at the bottom of one through hole.
8. The method for reducing contact hole resistance according to claim 7, wherein: the conductive structure layer includes a metal silicide layer.
9. The method for reducing contact hole resistance according to claim 1, wherein: the conductive material comprises metallic tungsten.
10. A transistor device obtainable by the method of reducing contact hole resistance of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311824172.6A CN117790411A (en) | 2023-12-27 | 2023-12-27 | Method for reducing contact hole resistance and transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311824172.6A CN117790411A (en) | 2023-12-27 | 2023-12-27 | Method for reducing contact hole resistance and transistor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117790411A true CN117790411A (en) | 2024-03-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311824172.6A Pending CN117790411A (en) | 2023-12-27 | 2023-12-27 | Method for reducing contact hole resistance and transistor device |
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| Country | Link |
|---|---|
| CN (1) | CN117790411A (en) |
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- 2023-12-27 CN CN202311824172.6A patent/CN117790411A/en active Pending
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