CN117789673A - Energy supply circuit and display device - Google Patents

Abstract

The application provides an energy supply circuit, including power end and output, the power end is used for receiving the power signal that power module provided, and the data driving circuit that is used for the data voltage that output image data signal corresponds is connected to the output. The power supply circuit further comprises a voltage boosting circuit and an adjusting control circuit, wherein the voltage boosting circuit is used for boosting the voltage received from the power supply end and outputting the voltage from the first output end. The adjusting control circuit is connected to the first output end and the output end, and is used for controlling the first output end and the output end to be electrically disconnected within a preset period after the power supply end receives the voltage, controlling the voltage of the first output end and the output end to be a low-limit voltage, wherein the low-limit voltage is smaller than the voltage of the data driving circuit for starting operation, and controlling the voltage of the first output end and the output end to be the voltage output by the voltage boosting circuit after the preset period. The embodiment of the application also provides a display device comprising the energy supply circuit.

Description

Energy supply circuit and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to an energy supply circuit and a display device having the same.

Background

In the display device, an operation voltage required by the data driving circuit when supplying a data voltage for image display to the display panel is supplied from the power supply circuit. Because the capacitor in the data driving circuit is in the continuous charge and discharge process, the power supply circuit is required to supply current to the data driving circuit. At the moment of powering on and starting the display device, the display device is easy to appear white screen and even part of electronic devices are damaged, so that the safety and visual effect are poor when the display device is powered on and started. Therefore, stable and safe start-up of the display device is a current urgent problem.

Disclosure of Invention

In view of the foregoing technical problems, an object of the present application is to provide an energy supply circuit and a display device having the same. The method aims at solving the problem that false triggering is easy to occur when the energy supply circuit is started, so that the reliability of the energy supply circuit and the image display effect of the display device are improved.

In one aspect, an embodiment of the present application provides an energy supply circuit, including a power supply end and an output end, the power supply end is configured to receive a power supply signal provided by a power supply module, the output end is connected to a data driving circuit configured to output a data voltage corresponding to an image data signal, the energy supply circuit further includes a boost circuit and an adjustment circuit, the boost circuit is configured to perform a boost process on the power supply signal received from the power supply end and output the power supply signal from a first output end, the adjustment circuit is connected to the first output end and the output end, and is configured to control the first output end to be electrically disconnected from the output end within a preset period after a voltage is received from the power supply end, and control the voltage of the first output end and the output end to be a low-limit voltage, where the low-limit voltage is less than a voltage at which the data driving circuit starts to operate, and control the voltage of the first output end and the output end to be a voltage output by the boost circuit after the preset period.

The adjusting control circuit comprises a delay circuit and an adjusting control circuit, wherein the delay circuit is connected to the first output end, the power end and the output end and is used for controlling the first output end to be electrically disconnected with the output end when the first output voltage is smaller than a first threshold voltage. The adjusting control circuit is electrically connected with the power end, the first output end, the output end and the grounding end, and is used for controlling the first output end and the output end to be electrically connected with the grounding end within a preset period after the power end receives voltage, and the grounding voltage of the grounding end is used as the low-limit voltage.

In an embodiment, the first buffer capacitor is electrically connected to the power supply terminal and the adjustment control node, and is configured to start charging the power supply signal and raise the voltage of the adjustment control node when the power supply terminal receives the power supply signal. And two ends of the adjusting resistor are respectively connected with the adjusting control node and the grounding end. The adjusting switch tube is electrically connected to the adjusting control node, the first output end, the output end and the grounding end respectively, and is used for being in a conducting state when the voltage of the adjusting control node is larger than an on-off threshold voltage so as to electrically conduct the first output end, the output end and the grounding end, and is in a cut-off state when the voltage of the adjusting control node is smaller than the on-off threshold voltage so as to electrically disconnect the first output end, the output end and the grounding end.

In an embodiment, the adjusting switch tube includes an adjusting control end, a first adjusting conductive end and a second adjusting conductive end, the adjusting control end is electrically connected to the adjusting control node, the first adjusting conductive end is electrically connected to the first output end and the output end, and the second adjusting conductive end is electrically connected to the ground end. When the voltage of the adjustment control node is smaller than the opening and closing threshold voltage, the adjustment switch tube is in a cut-off state under the control of the adjustment control end, and the first adjustment conductive end and the second adjustment conductive end are electrically disconnected.

In an embodiment, the adjusting switch transistor is a transistor, a gate of the transistor is used as the adjusting control end, a source and a drain of the transistor are respectively the first adjusting conductive end and the second adjusting conductive end, and the on-off threshold voltage is a threshold voltage of the transistor for starting to conduct.

In an embodiment, the adjustment control circuit includes a delay switch tube, a first voltage stabilizing capacitor and a second voltage stabilizing capacitor. The first voltage stabilizing capacitor is electrically connected to the first output end and the power end, the second voltage stabilizing capacitor is electrically connected to the output end and the power end, and the first voltage stabilizing capacitor and the second voltage stabilizing capacitor are used for buffering the voltage of the power end and the voltage of the first output end. The delay switch tube is connected with the first output end, the power end and the output end, and is used for controlling the first output end to be electrically disconnected from the second output end when the voltage of the first output end is smaller than the first threshold voltage, and controlling the first output end to be electrically conducted with the output end when the voltage of the first output end is equal to or larger than the first threshold voltage.

In an embodiment, the delay switch tube includes a delay control end, a first delay conductive end and a second delay conductive end, where the delay control end is electrically connected to the power supply end, the first delay conductive end is connected to the first output end, and the second delay conductive end is electrically connected to the output end;

when the voltage of the first output end is smaller than the first threshold voltage, the delay switch tube is in a cut-off state under the control of the delay control end and a first delay conducting end, and the first delay conducting end and the second delay conducting end are electrically disconnected; when the voltage of the first output end is equal to or greater than the first threshold voltage, the delay switch tube is in a conducting state under the control of the delay control end and the first delay conducting end, and the first delay conducting end and the second delay conducting end are electrically conducted.

In an embodiment, the delay switch is a transistor, a gate of the transistor is used as the delay control terminal, a source and a drain of the transistor are the first delay conductive terminal and the second delay conductive terminal, respectively, and a voltage difference between the first threshold voltage and the power supply terminal is a threshold voltage at which the transistor starts to conduct.

In an embodiment, the energy supply circuit further includes a power management circuit, the power management circuit is connected to the power end and the boost circuit, and the power management circuit is configured to process a voltage provided by the power end and then transmit the processed voltage to the boost circuit to perform boost processing.

In another aspect, a display device is provided, where the display device includes a display panel including a plurality of pixel units arranged in an array, and the data driving circuit is electrically connected to the pixel units and the power supply circuit, and the data driving circuit is configured to provide an image data signal for displaying an image to the pixel units, and the power supply circuit is configured to provide a driving voltage for the data driving circuit to work.

Compared with the prior art, in the energy supply circuit provided by the embodiment of the application, the adjusting circuit can accurately control the first output end and the output end to be positioned at the low-limit voltage within the preset time period when the power end starts to output the voltage, so that the disturbance voltage is prevented from being transmitted to the data driving circuit by mistake within the time period, and the data driving circuit is damaged or the data driving circuit outputs a blank image data signal to the pixel unit to cause a white screen abnormal phenomenon.

Further, in the time period before the stable voltage is output by the booster circuit through the delay circuit in the adjusting circuit, the data driving circuit can be accurately controlled not to be powered on for starting, soft starting of the data driving circuit is achieved, meanwhile, the data driving circuit can be matched with the adjusting control circuit in the soft starting process to accurately output an image display signal for image display, white screen or other abnormal manifestations are prevented in the power-on process of the display device, and safety and image display effect of the display device are effectively improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

FIG. 2 is a functional block diagram of the power module shown in FIG. 1 according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an energy supply module of the energy supply circuit shown in FIG. 2;

FIG. 4 is a schematic diagram of a specific circuit configuration of the power supply circuit shown in FIG. 3;

fig. 5 is a schematic diagram showing a correspondence relationship between a voltage provided by the power supply terminal and a voltage outputted by the power supply circuit and a start time.

Reference numerals illustrate:

100-energy supply circuit, vin-power supply terminal, vo-output terminal, 10-power management circuit, lin-input inductance, cin-input capacitance, 20-boost circuit, vout 1-first output terminal, T1-first boost switch, T2-second boost switch, vout 2-second output terminal, 30-adjustment circuit, 31-delay circuit, Q1-delay switch tube, 311-delay control terminal, 312-first delay conductive terminal, 313-second delay conductive terminal, C1-first voltage stabilizing capacitance, C2-second voltage stabilizing capacitance, 33-adjustment control circuit, cs-first buffer capacitance, R1-adjustment resistance, A-adjustment control node, Q2-adjustment switch tube, 331-adjustment control terminal, 332-first adjustment conductive terminal, 333-second adjustment conductive terminal, GND-ground terminal, 200-power supply module, 600-energy supply component, 700-time sequence controller, 800-data driving circuit, 900-display panel, 1000-display device.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device according to a first embodiment of the present disclosure. The display device 1000 provided in the embodiment of the present application includes a display panel 900, a data driving circuit 800, a timing controller 700, and an energy supply assembly 600. In this embodiment, the display device 1000 is a liquid crystal display device, that is, the display panel 900 is a liquid crystal display panel. The display panel 900 is electrically connected to the data driving circuit 800, the data driving circuit 800 is further electrically connected to the energy supply assembly 600 and the timing controller 700, and the energy supply assembly 600 is further electrically connected to the timing controller 700.

The timing controller 700 is configured to receive an image signal for display from the outside, and to supply a clock control signal for controlling an operation timing of the data driving circuit 800 and an image data signal to the data driving circuit 800, the data driving circuit 800 performs a conversion process of the image data signal into a corresponding data voltage, and outputs the data voltage to a pixel unit (not shown) in the display panel 900 under the control of the clock control signal, thereby driving the pixel unit to perform image display.

It can be understood that the data driving circuit 800 includes a plurality of data driving chips, each data driving chip includes a plurality of output channels, and the data driving circuit 800 converts the image signal into a data voltage in an analog form under the driving of the power supply voltage for driving such as VADD provided by the power supply module 600 to the data driving circuit 800 according to the image signal provided by the timing controller 700, and transmits the data voltage to the pixel units through the data lines (not shown), so that the pixel units correspondingly perform corresponding image display.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating connection of the energy supply assembly shown in fig. 1.

The power supply assembly 600 includes a power module 200 and a power supply circuit 100 electrically connected to each other, wherein the power module 200 is configured to receive a power voltage from an external power source and convert the power voltage into a different power voltage that can be used by the display device 1000. In this embodiment, the power signal received from the external power source may be 220V/50HZ alternating power, and the power module 200 converts the alternating power into a direct current input power Uin of direct current voltage. The power supply circuit 100 performs a step-up process and a step-down process on the power supply signal to obtain different stable power supply signals, and in this embodiment, the power supply circuit 100 outputs an analog power supply signal AVDD to the data driving circuit 800 for normal operation and outputting a corresponding data voltage.

Specifically, the power supply circuit 100 includes a power source terminal Vin and an output terminal Vo. Wherein the power terminal Vin is connected to the power module 200 and is configured to receive a dc input power Uin; the output terminal Vo is connected to the data driving circuit 800 for outputting an analog power signal AVDD to the data driving circuit 800, thereby providing a voltage for operating the data driving circuit 800.

Referring to fig. 3, fig. 3 is a schematic circuit diagram of the power supply circuit shown in fig. 2 according to an embodiment of the present application.

The power supply circuit 100 includes a power management circuit 10, a booster circuit 20, and a regulator circuit 30.

The power management circuit 10 is electrically connected to the power terminal Vin and the boost circuit 20, and is configured to receive a dc input voltage Uin as a power signal from the power terminal Vin, and convert the dc input voltage Uin (power signal) into a first output voltage (not shown). In this embodiment, the Power Management circuit 10 is an integrated circuit, for example, the Power Management circuit 10 may be an integrated Power Management circuit (PMIC).

The voltage boosting circuit 20 is electrically connected to the power management circuit 10, and is configured to boost a first output voltage to obtain an analog power signal AVDD, and output the analog power signal AVDD through the first output terminal Vout1, where the analog power signal AVDD is provided to the data driving circuit 800 and is used as a driving power voltage. The Boost circuit 20 may be a Boost integrated circuit for improving the driving capability of the analog power supply signal.

In addition, an output terminal (not labeled) of the power management circuit 10 is connected to the boost circuit 20 through an input filter and voltage-stabilizing circuit composed of an input capacitor Cin and an input inductor Lin, that is, a power signal provided from the power terminal Vin is transmitted to the boost circuit 20 after being subjected to the input capacitor Cin and the input inductor Lin filter voltage-stabilizing process.

Alternatively, in other embodiments of the present application, the boost circuit 20 may be directly connected to the power terminal Vin to receive the dc input voltage Uin, and the dc input voltage Uin is provided to the boost circuit 20 after the filtering voltage stabilizing process of the input capacitor Cin and the input inductor Lin.

The adjusting circuit 30 is connected to the power source Vin, the first voltage output terminal Vout1 and the second output terminal Vout2 of the boost circuit 20, and in this embodiment, the second output terminal Vout2 is directly connected to the output terminal Vo, or the second output terminal Vout2 and the output terminal Vo are the same endpoint.

The adjusting circuit 30 controls the voltages of the second output terminal Vout2 and the output terminal Vo to be low-limit voltages after receiving the dc input voltage Uin outputted from the power source terminal Vin and during a period when the first output voltage Uo1 outputted from the first voltage output terminal Vout1 as the analog power source signal AVDD is less than the first threshold voltage Vref, in other words, before the analog power source signal AVDD is boosted to reach the first threshold voltage Vref, the voltages of the second output terminal Vout2 and the output terminal Vo are 0V, that is, the power supply circuit 100 provides the low-limit voltages to the data driving circuit 800 during a period after receiving the dc input voltage Uin and before the voltage boosting circuit 20 accurately and stably provides the analog power source signal AVDD, so as to prevent the electrical signal from being erroneously transmitted to the data driving circuit 800 to be erroneously triggered. In this embodiment, the low-limit voltage is smaller than the voltage at which the data driving circuit 800 is activated and does not output any data voltage to the pixel unit, for example, the voltage may be a ground voltage of 0V.

Therefore, when the display device 1000 is powered on and started, the power supply end Vin is quickly powered on and powered off, that is, the power supply signal is quickly raised in the starting process, the analog power supply signal AVDD can be prevented from being transmitted to the data driving circuit 800 by mistake in the starting process, so that the data driving circuit 800 outputs a blank signal to the pixel unit, and abnormal white screen display is caused, or abnormal damage to part of working circuits or integrated circuits IC is caused, and the like, thereby realizing soft starting of the display device and ensuring the safety of the display device 1000 in the starting soft starting process.

Please refer to fig. 4, which is a schematic diagram of a specific circuit structure of the functional circuit shown in fig. 3.

The boost circuit 20 includes a plurality of switching transistors, for example, in the present embodiment, the boost circuit 20 includes a first boost switching transistor T1 and a second boost switching transistor T2. In this embodiment, the first boost switch T1 is a P-type field effect transistor (Field Effect Transistor, FET) and the second boost switch T2 is an N-type field effect transistor. The source/drain (not shown) of the first boost switch tube T1 is connected to the input inductor Lin and the first voltage output terminal Vout1, respectively, and the gate (not shown) of the first boost switch tube T1 is connectable to the power management circuit 10. The source/drain (not labeled) of the second boost switch T2 is connected to the input inductor Lin and the ground GND, respectively, and the gate (not labeled) of the second boost switch T2 is connectable to the power management circuit 10. In this embodiment, the power management circuit 10 controls the first boost switching tube T1 and the second boost switching tube T2 to be periodically turned off or turned on, so as to boost the power signal to obtain the first output voltage Uo1, wherein the first output voltage Uo1 is output from the first voltage output terminal Vout 1.

In an embodiment, the first voltage output terminal Vout1 is connected to the first output capacitor Co, and the first output voltage Uo1 is output after being filtered and stabilized by the first output capacitor Co 1. In this embodiment, the first output voltage Uo1 can be used as the analog power signal AVDD.

In this embodiment, the adjusting circuit 30 includes a delay circuit 31 and an adjusting control circuit 33, the delay circuit 31 is connected to the first output terminal Vout1, the power terminal Vin and the second output terminal Vout2, and the delay circuit 31 is configured to disconnect the electrical connection between the first output terminal Vout1 and the second output terminal Vout2 when the first output voltage Uo1 is less than a first threshold voltage Vref (not shown), and not to transmit the first output voltage Uo1 to the second voltage output terminal Vout2, and it can be understood that the second voltage output terminal Vout2 is connected to the data driving circuit 800. When the first output voltage Uo1 is equal to or greater than the first threshold voltage Vref, the first output terminal Vout1 and the second output terminal Vout2 are electrically connected, and the first output voltage Uo1 of the first output terminal Vout1 is transmitted to the second voltage output terminal Vout2.

The adjustment control circuit 33 is connected to the power source terminal Vin, the first output terminal Vout1, the second output terminal Vout2, and the ground terminal GND, and is configured to control the first output terminal Vout and the second output terminal Vout2 to be connected to the ground terminal GND in a preset period when the power source terminal Vin receives a voltage (power source signal), so that the voltage of the first output terminal Vout1 and the voltage of the second output terminal Vout2 are at a ground voltage of 0V. In this embodiment, the ground voltage is used as the low-limit voltage of the first output terminal Vout1 and the second output terminal Vout2, and the low-limit voltage is smaller than the voltage at which the data driving circuit 800 starts to operate.

More specifically, the delay circuit 31 includes a delay switching tube Q1, a first regulated capacitor C1, and a second regulated capacitor C2.

The first voltage stabilizing capacitor C1 is connected to the first output terminal Vout1 and the power terminal Vin, and the second voltage stabilizing capacitor C2 is connected to the second output terminal Vout2 and the power terminal Vin. The first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 are used for buffering the power signal of the power end Vin received by the delay switching tube Q1 and the voltage of the first output end Vout1, so as to prevent the delay switching tube Q1 from being impacted by the power signal of the power end Vin and being triggered by errors.

The delay switching tube Q1 is configured to control the first output terminal Vout1 and the second output terminal Vout2 to be electrically disconnected within a preset period of time when the power terminal Vin receives the voltage, and control the first output terminal Vout1 and the second output terminal Vout2 to be electrically connected after the preset period of time. In other words, in a period when the voltage of the first output terminal Vout1 is smaller than the first threshold voltage Vref, that is, the voltage of the power signal output by the power terminal Vin, and the voltage difference between the first output terminal Vout1 and the second output terminal Vout2 is smaller than the reference threshold voltage, the delay switch Q1 controls the first output terminal Vout1 to be electrically disconnected from the second output terminal Vout2, and when the voltage of the first output terminal Vout1 is greater than the first threshold voltage Vref, that is, the voltage of the power signal output by the power terminal Vin, and the voltage difference between the first output terminal Vout1 and the second output terminal Vout2 is greater than the reference threshold voltage. It can be understood that the preset time period is a time period when the voltage of the first output terminal Vout1 increases and is greater than the voltage of the first output terminal Vout1, and the voltage difference between the two voltages is greater than the reference threshold voltage.

It can be understood that the first threshold voltage Vref corresponds to the reference threshold voltage, and the relationship between the first threshold voltage Vref and the reference threshold voltage is that the voltage difference between the first threshold voltage Vref and the dc input voltage Uin is the reference threshold voltage, or that the sum of the dc input voltage Uin and the reference threshold voltage is the first threshold voltage Vref.

The delay switching tube Q1 includes a delay control terminal 311, a first delay conductive terminal 312, and a second delay conductive terminal 313. The delay control terminal 311 is connected to the power source terminal Vin, the first delay conductive terminal 312 is connected to the first output terminal Vout1, and the second delay conductive terminal 313 is connected to the second output terminal Vout2. In this embodiment, the delay switching transistor Q1 is a P-type transistor or a field effect transistor, and is used as a transistor of the delay switching transistor Q1, wherein a gate is used as the delay control terminal 311 or directly connected to the delay control terminal 311, and a source and a drain are respectively used as a first delay conductive terminal 312 and a second delay conductive terminal 313 in cooperation and directly connected to each other. It can be understood that the reference threshold voltage is the threshold voltage Vth required for delaying the turn-on of the switching tube Q1.

The adjustment control circuit 33 includes a first snubber capacitor Cs, an adjustment resistor R1, and an adjustment switching transistor Q2. The first buffer capacitor Cs is used for receiving a power signal at the power terminal Vin to start charging so as to correspondingly raise the voltage of the adjustment control node a. In this embodiment, two ends of the first buffer capacitor Cs are connected to the power source terminal Vin and the adjustment control node a, respectively. It can be understood that the capacitance value of the first buffer capacitor Cs corresponds to the period of time for which the voltage of the adjustment control node a increases to the on-off threshold voltage, and the greater the capacitance value of the first buffer capacitor Cs, the longer the charging period of time, the longer the period of time for which the voltage of the entire control node a increases to the on-off threshold voltage, whereas the smaller the capacitance value of the first buffer capacitor Cs, the faster the charging speed and the shorter the period of time, and the shorter the period of time for which the voltage of the entire control node a increases to the on-off threshold voltage.

The two ends of the adjusting resistor R1 are respectively connected to the adjusting control node a and the ground GND. When the power signal of the power terminal Vin stops rising and the charging of the first buffer capacitor Cs is completed, the voltage of the control node a is controlled to be the ground voltage 0V, so that the switching tube Q2 is correspondingly controlled to be turned off.

The adjusting switch tube Q2 is respectively connected to the adjusting control node A, the first output end Vout1, the second output end Vout2 and the grounding end GND, and is used for being in a conducting state when the voltage of the adjusting control node A is larger than the on-off threshold voltage so as to correspondingly conduct the first output end Vout1, the second output end Vout2 and the grounding end GND electrically and be in the same grounding voltage; meanwhile, when the voltage of the adjustment control node A is smaller than the on-off threshold voltage, the adjustment control node A is in an off state so as to correspondingly disconnect the first output end Vout1 and the second output end Vout2 from the ground end GND, and the first output end Vout1 and the second output end Vout2 can output corresponding voltages.

In the present embodiment, the adjusting switch Q2 includes an adjusting control end 331, a first adjusting conductive end 332 and a second adjusting conductive end 333. The adjustment control terminal 331 is connected to the adjustment control node a, the first adjustment conductive terminal 332 is connected to the first output terminal Vout1 and the second output terminal Vout2, and the second adjustment conductive terminal 333 is connected to the ground terminal GND. In this embodiment, the adjusting switch Q2 is an N-type transistor or a field effect transistor, and the gate of the transistor is used as the adjusting control terminal 331 or directly connected to the adjusting control terminal 331, and the source and the drain are respectively used as the first adjusting conductive terminal 332 and the second adjusting conductive terminal 333 or directly connected to the first adjusting conductive terminal 332 and the second adjusting conductive terminal 333. Meanwhile, the on-off threshold voltage is the threshold voltage Vth required for adjusting the start-up conduction of the switching tube Q2.

The operation of the power supply circuit 100 will now be described in detail with reference to fig. 4 and 5. Fig. 5 is a schematic diagram of the correspondence relationship between the voltage provided by the input terminal Vin, the voltage provided by the energy supply component 600 and the start time shown in fig. 4. Where Vin characterizes the voltage of the power supply signal and VADD characterizes the analog power supply signal AVDD provided to the data driving circuit 800.

When the display device 1000 and the display panel 900 are powered on, the power supply circuit 100 receives the dc input voltage Uin as a power signal from the power terminal Vin, but at this time, the voltage rises rapidly and is unstable. Meanwhile, the power management circuit 10 processes the power signal provided by the power terminal Vin and transmits the processed power signal to the boost circuit 20 for boosting, and since the boost circuit 20 needs a certain time to boost the dc input voltage Uin provided by the power terminal Vin to obtain the first output voltage Uo1 (the analog power signal AVDD), the voltage of the first output terminal Vout1 is unstable and cannot accurately drive the data driving circuit 800 to work normally.

Therefore, when the power supply terminal Vin starts to provide the dc input voltage Uin, the first snubber capacitor Cs in the adjustment control circuit 33 charges under the dc input voltage Uin output by the power supply terminal Vin, so that the voltage of the adjustment control node a rises rapidly, and when the voltage of the adjustment control node a rises to the threshold voltage Vth for turning on and turning off the adjustment switch Q2, the adjustment switch Q2 is turned on, so that the first output terminal Vout1 and the second output terminal Vout2 connected to the first adjustment conductive terminal 332 are electrically connected to the ground terminal GND, so as to control the ground voltage of the first output terminal Vout1 and the second output terminal Vout2 accurately located at the ground terminal GND.

When the dc input voltage Uin outputted from the power source terminal Vin is stable and the first buffer capacitor Cs is charged, the voltage of the adjustment control node a is pulled down to the ground voltage 0V of the ground terminal GND by the adjustment resistor R1, and the corresponding adjustment switch Q2 is turned off, so that the first output terminal Vout1 and the second output terminal Vout2 are electrically disconnected from the ground terminal GND. The voltage at the first output terminal Vout1 is the boosted first output voltage Uo1 output from the booster circuit 20.

Obviously, during the period when the power supply terminal Vin starts to supply the dc input voltage Uin as the power supply signal to the first buffer capacitor Cs is charged, the adjustment control circuit 33 can accurately control the voltages of the first output terminal Vout1 and the second output terminal Vout2 at the ground terminal of 0V, thereby preventing the disturbance voltage caused by the first voltage stabilizing capacitor C1 and the second voltage stabilizing capacitor C2 from being erroneously transmitted to the data driving circuit 800 during this period, so that the data driving circuit 800 is damaged or the data driving circuit 800 outputs a blank image data signal to the pixel unit to cause a white screen abnormality phenomenon.

When the first output voltage Uo1 output by the boost circuit 20 is increased to the first threshold voltage Vref and the voltage of the first output terminal Vout1 is greater than the voltage reference threshold voltage of the power signal provided by the power terminal Vin, the delay switching tube Q1 is electrically turned on, so that the first output terminal Vout1 and the second output terminal Vout2 are electrically turned on, the first output voltage Uo1 output by the boost circuit 20 is transmitted as the output analog power signal AVDD from the first output terminal Vout1 to the second output terminal Vout2 and is transmitted to the data driving circuit 800, so that the data driving circuit 800 is accurately powered on and accurately outputs the image data signal to the pixel unit to perform image display.

In this embodiment, in the period before the second output terminal Vout2 accurately outputs the analog power signal AVDD, that is, in the period from when the power source terminal Vin is powered on to when the second output terminal Vout2 accurately outputs the analog power signal AVDD, the data driving circuit 800 can be accurately controlled not to be powered on, and when the data driving circuit 800 is soft-started, the data driving circuit 800 can be ensured to accurately output the image display signal to display the image, so that white screen or other abnormal appearance of the display device 1000 and the display panel 900 is prevented in the power-on process, and the security and the image display effect of the display device 1000 and the display panel 900 are effectively improved.

It will be appreciated that the display device may be used in electronic devices including, but not limited to, tablet computers, notebook computers, desktop computers, and the like. According to the embodiments of the present application, the specific type of the display device is not particularly limited, and a person skilled in the art can correspondingly design the display device according to the specific use requirement of the electronic device to which the display device is applied, which is not described herein.

In one embodiment, the display device further includes other necessary components and components such as a driving board, a power board, a high-voltage board, a key control board, etc., and those skilled in the art can correspondingly supplement the components according to the specific type and actual function of the display device, which will not be described herein.

It is to be understood that the application of the present application is not limited to the examples described above, but that modifications and variations can be made by a person skilled in the art from the above description, all of which modifications and variations are intended to fall within the scope of the claims appended hereto. Those skilled in the art will recognize that the methods of accomplishing all or part of the above embodiments and equivalents thereof may be employed and still fall within the scope of the present application.

Claims (10)

1. The power supply circuit comprises a power supply end and an output end, wherein the power supply end is used for receiving a power supply signal provided by a power supply module, and the output end is connected with a data driving circuit for outputting data voltage corresponding to an image data signal.

2. The power supply circuit of claim 1, wherein the adjustment circuit comprises a delay circuit and an adjustment control circuit,

the delay circuit is connected to the first output end, the power end and the output end, and is used for controlling the first output end to be electrically disconnected from the output end when the first output voltage is smaller than a first threshold voltage;

the adjusting control circuit is electrically connected with the power end, the first output end, the output end and the grounding end, and is used for controlling the first output end and the output end to be electrically connected with the grounding end within a preset period after the power end receives voltage, and the grounding voltage of the grounding end is used as the low-limit voltage.

3. The power supply circuit of claim 2, wherein the regulation control circuit comprises a first snubber capacitor, a regulator resistor, and a regulator switch,

the first buffer capacitor is electrically connected with the power supply end and the adjustment control node and is used for receiving the power supply signal at the power supply end to start charging and increasing the voltage of the adjustment control node;

two ends of the adjusting resistor are respectively connected with the adjusting control node and the grounding end;

the adjusting switch tube is electrically connected to the adjusting control node, the first output end, the output end and the grounding end respectively, and is used for being in a conducting state when the voltage of the adjusting control node is larger than an on-off threshold voltage so as to electrically conduct the first output end, the output end and the grounding end, and is in a cut-off state when the voltage of the adjusting control node is smaller than the on-off threshold voltage so as to electrically disconnect the first output end, the output end and the grounding end.

4. The power supply circuit of claim 3, wherein the regulation switch tube comprises a regulation control terminal, a first regulation conductive terminal and a second regulation conductive terminal, the regulation control terminal is electrically connected to the regulation control node, the first regulation conductive terminal is electrically connected to the first output terminal and the output terminal, and the second regulation conductive terminal is electrically connected to the ground terminal;

when the voltage of the adjustment control node is smaller than the opening and closing threshold voltage, the adjustment switch tube is in a cut-off state under the control of the adjustment control end, and the first adjustment conductive end and the second adjustment conductive end are electrically disconnected.

5. The power supply circuit according to claim 4, wherein the adjusting switch is a transistor, a gate of the transistor is used as the adjusting control terminal, a source and a drain of the transistor are respectively the first adjusting conductive terminal and the second adjusting conductive terminal, and the on-off threshold voltage is a threshold voltage of the transistor for starting to conduct.

6. The power supply circuit according to any one of claims 2 to 5, wherein the adjustment control circuit includes a delay switching tube, a first voltage stabilizing capacitor, and a second voltage stabilizing capacitor;

the first voltage stabilizing capacitor is electrically connected to the first output end and the power end, the second voltage stabilizing capacitor is electrically connected to the output end and the power end, and the first voltage stabilizing capacitor and the second voltage stabilizing capacitor are used for buffering the voltage of the power end and the voltage of the first output end;

the delay switch tube is connected with the first output end, the power end and the output end, and is used for controlling the first output end to be electrically disconnected from the output end when the voltage of the first output end is smaller than the first threshold voltage, and controlling the first output end to be electrically conducted with the output end when the voltage of the first output end is equal to or larger than the first threshold voltage.

7. The power supply circuit of claim 6, wherein the delay switching tube comprises a delay control terminal, a first delay conductive terminal and a second delay conductive terminal, the delay control terminal is electrically connected to the power supply terminal, the first delay conductive terminal is connected to the first output terminal, and the second delay conductive terminal is electrically connected to the output terminal;

when the voltage of the first output end is smaller than the first threshold voltage, the delay switch tube is in a cut-off state under the control of the delay control end and a first delay conducting end, and the first delay conducting end and the second delay conducting end are electrically disconnected; when the voltage of the first output end is equal to or greater than the first threshold voltage, the delay switch tube is in a conducting state under the control of the delay control end and the first delay conducting end, and the first delay conducting end and the second delay conducting end are electrically conducted.

8. The power supply circuit of claim 7, wherein the delay switching transistor is a transistor, a gate of the transistor is used as the delay control terminal, a source and a drain of the transistor are respectively the first delay conductive terminal and the second delay conductive terminal, and a voltage difference between the first threshold voltage and the power supply terminal is a threshold voltage at which the transistor starts to conduct.

9. The power supply circuit according to claim 1, further comprising a power management circuit connected to the power supply terminal and the boost circuit, wherein the power management circuit is configured to process a voltage provided by the power supply terminal and then transmit the processed voltage to the boost circuit to perform a boost process.

10. A display device comprising a display panel and the power supply circuit of any one of claims 1 to 9, the display panel comprising a plurality of pixel units arranged in an array, the data drive circuit being electrically connected to the pixel units and the power supply circuit, the data drive circuit being for providing image data signals for image display to the pixel units, the power supply circuit being for providing driving voltages for operation of the data drive circuit.