CN117785747A - Method, device and chip for configuring communication interface - Google Patents
Method, device and chip for configuring communication interface Download PDFInfo
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Abstract
The embodiment of the invention provides a method, a device and a chip for configuring a communication interface, wherein the method comprises the following steps: acquiring a receiving waveform and a transmitting waveform of a chip to be tested, wherein a receiving and transmitting time sequence register of the chip does not carry out time delay processing; acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively; determining a receiving relative establishment time length according to the receiving establishment time length, and determining a transmitting relative establishment time length according to the transmitting establishment time length; determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length; and writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested. The method can quickly and accurately obtain stable delay configuration, and improves communication efficiency.
Description
Technical Field
The present invention relates to the field of communications and chips, and in particular, to a method, an apparatus, and a chip for configuring a communication interface.
Background
In the prior art, ethernet MAC and PHY communicate mainly through the RGMII interface. The RGMII interface includes TX (data transmission) and RX (data reception), both of which are provided with various CLK (clocks). The period of the clock signal of the RGMII interface is 8ns, the data signal is sampled on the rising edge and the falling edge of the clock signal, in order to make the sampled data valid, the RGMII clock signal needs to have a delay of 1-3 ns, and in order to ensure that the data sampling is valid, the clock delay is usually set to be 2ns.
The current RGMII communication delay configuration method is to add a cascade delay circuit on a path of the MAC layer to the RGMII interface. However, there are two disadvantages to using this approach:
1. because a delay circuit is adopted, a large amount of calculation is needed during configuration, devices such as related resistance-capacitance are frequently modified, and labor and time are consumed;
2. even if an accurate delay configuration is calculated, there is a deviation in delay due to the fact that devices that do not fully correspond to the desired values may be found on the circuit configuration.
Disclosure of Invention
The embodiment of the invention aims to provide a method, a device and a chip for configuring a communication interface, wherein the method can quickly and accurately obtain stable delay configuration, and improves communication efficiency.
To achieve the above object, an embodiment of the present invention provides a method for configuring a communication interface, including:
acquiring a receiving waveform and a transmitting waveform of a chip to be tested, wherein a receiving and transmitting time sequence register of the chip does not carry out time delay processing;
acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively;
determining a receiving relative establishment time length according to the receiving establishment time length, and determining a transmitting relative establishment time length according to the transmitting establishment time length;
determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length;
and writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested.
Optionally, the determining the receiving relative setup time according to the receiving setup time, and determining the sending relative setup time according to the sending setup time include:
Trx＝2ns-R_Tsetup，
Ttx＝2ns-T_Tsetup，
where Trx is the receive relative setup time period, R Tsetup is the receive setup time period,
ttx is the transmission relative setup period, and t_tsetup is the transmission setup period.
Optionally, the determining the receiving and transmitting time sequence register value according to the receiving relative setup time length and the transmitting relative setup time length includes:
Ntx＝(N+Ttx)/σ，
Nrx＝(N+Trx)/σ，
wherein the transmit-receive timing register value comprises a receive timing register value and a transmit timing register value,
nrx is the time-sequential register value, ntx is the timing-sequential register value,
trx is the receive relative setup period, ttx is the transmit relative setup period,
sigma is the unit delay of the chip to be tested.
Optionally, the writing the transceiving timing register value into the transceiving timing register of the chip to be tested includes:
the receiving and transmitting time sequence register comprises a receiving time sequence register and a transmitting time sequence register;
writing the time sequence register value into a time sequence register of the chip to be tested;
and writing the timing sequence register value into the timing sequence register of the chip to be tested.
Optionally, the method further comprises
After the receiving and transmitting time sequence register value is written into the receiving and transmitting time sequence register of the chip to be tested, the network port conduction condition is verified, and if the network port conduction rate is lower than a preset value, the receiving and transmitting time sequence register value is adjusted until the network port conduction rate is not lower than the preset value.
In another aspect, the present invention provides an apparatus for configuring a communication interface, the apparatus comprising:
the acquisition module is used for acquiring a receiving waveform and a transmitting waveform of a chip to be detected, and the receiving and transmitting time sequence registers of the chip do not perform delay processing;
the first processing module is used for acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively;
the second processing module is used for determining a receiving relative establishment time length according to the receiving establishment time length and determining a sending relative establishment time length according to the sending establishment time length;
and the third processing module is used for determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length, and writing the receiving and transmitting time sequence register value into a receiving and transmitting time sequence register of the chip to be tested.
Optionally, the determining the receiving relative setup time according to the receiving setup time, and determining the sending relative setup time according to the sending setup time include:
and respectively judging whether the receiving establishment time length and the sending establishment time length exceed a threshold time length or not, wherein,
if the reception setup period exceeds the threshold period, a reception relative setup period=a reception setup period-threshold period;
if the transmission setup period exceeds the threshold period, transmitting a relative setup period = transmission setup period-threshold period;
if the receiving establishment duration and the sending establishment duration do not exceed the threshold duration, then: receive relative setup time = receive setup time, and receive relative setup time = receive setup time.
Optionally, the determining the receiving and transmitting time sequence register value according to the receiving relative setup time length and the transmitting relative setup time length includes:
Ntx＝(N+Ttx)/σ，
Nrx＝(N+Trx)/σ，
wherein the transmit-receive timing register value comprises a receive timing register value and a transmit timing register value,
nrx is the time-sequential register value, ntx is the timing-sequential register value,
trx is the receive relative setup period, ttx is the transmit relative setup period,
sigma is the unit delay of the chip to be tested.
Optionally, the writing the transceiving timing register value into the transceiving timing register of the chip to be tested includes:
the receiving and transmitting time sequence register comprises a receiving time sequence register and a transmitting time sequence register;
writing the time sequence register value into a time sequence register of the chip to be tested;
and writing the timing sequence register value into the timing sequence register of the chip to be tested.
Optionally, the device further comprises
And the verification module is used for verifying the network port conduction condition after writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested, and adjusting the receiving and transmitting time sequence register value until the network port conduction rate is not lower than a preset value if the network port conduction rate is lower than the preset value.
On the other hand, the invention also provides a chip, and a receiving and transmitting time sequence register of the chip is configured according to the method for configuring the communication interface.
The method for configuring the communication interface comprises the following steps: acquiring a receiving waveform and a transmitting waveform of a chip to be tested, wherein a receiving and transmitting time sequence register of the chip does not carry out time delay processing; acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively; determining a receiving relative establishment time length according to the receiving establishment time length, and determining a transmitting relative establishment time length according to the transmitting establishment time length; determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length; and writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested. According to the method and the device, the establishment and maintenance time of the data clock under the condition that no delay is added is judged, whether the delay is added at the receiving end or not is accurately and rapidly determined from the angle of the waveform, the reliability and the accuracy of configuration are ensured, and the communication efficiency is improved.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a flow chart of a method of configuring a communication interface of the present invention;
FIG. 2 is a schematic diagram of one embodiment of a configuration communication interface of the present invention;
fig. 3 is a schematic diagram of an RGMII interface transmit receive clock data waveform.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Fig. 1 is a schematic flow chart of a method for configuring a communication interface according to the present invention, as shown in fig. 1, the method for configuring a communication interface according to the present invention includes:
step S101 is to obtain a received waveform and a transmitted waveform of a chip to be tested, where the receiving and transmitting time sequence registers of the chip do not perform delay processing. The preferred chip of this application is a network interface chip, its communication interface is the RGMII interface (namely PHY end), RGMII interface divide into TX (data transmission) and RX (data reception), two have CLK (clock), D [3:0], EN (enable signal) three kinds of signals. The receiving waveform of the chip to be tested is the waveform of the receiving data and the clock, and the transmitting waveform is the waveform of the transmitting data and the clock. The receiving and transmitting time sequence register of the chip is not subjected to time delay processing, and the final receiving and transmitting time sequence register value is set according to the invention.
Step S102 is to acquire a reception setup time period and a transmission setup time period according to the reception waveform and the transmission waveform, respectively. Specifically, as shown in fig. 3, the reception setup period is a setup period and a hold period of the reception waveform, for example, a period of a rising edge or a falling edge of the waveform of the reception data and the clock, and similarly, the transmission setup period is a setup period and a hold period of the transmission waveform, for example, a period of a rising edge or a falling edge of the waveform of the transmission data and the clock. The received signal and the transmitted signal of the chip to be tested can be collected and analyzed through an oscilloscope.
Step S103 is to determine a receiving relative setup time according to the receiving setup time, and determine a sending relative setup time according to the sending setup time.
According to a specific embodiment, the determining the receiving relative setup time according to the receiving setup time, and determining the sending relative setup time according to the sending setup time include:
Trx＝2ns-R_Tsetup，Ttx＝2ns-T_Tsetup，
wherein Trx is a reception relative setup period, r_tsetup is a reception setup period, ttx is a transmission relative setup period, and t_tsetup is a transmission setup period. . Preferably, the threshold duration is 2ns.
Step S104 is to determine a receiving and transmitting time sequence register value according to the receiving relative setup time length and the transmitting relative setup time length.
According to a specific embodiment, the determining the receiving and transmitting time sequence register value according to the receiving relative setup time length and the transmitting relative setup time length includes:
Ntx＝(N+Ttx)/σ，
Nrx＝(N+Trx)/σ，
the receiving and transmitting time sequence register value comprises a receiving time sequence register value and a transmitting time sequence register value, nrx is the receiving time sequence register value, ntx is the transmitting time sequence register value, trx is the receiving relative establishment time length, ttx is the transmitting relative establishment time length, and sigma is the unit delay of the chip to be tested. The value which can be written in the chip register is 00-ff, sigma is the delay time for changing the value of the register of one unit, for example, the register value is changed from 01 to 02, the actual waveform is changed for a certain time length, and sigma is the delay time for changing caused by changing the register value by each 01.
The writing the transceiving time sequence register value into the transceiving time sequence register of the chip to be tested comprises the following steps: the receiving and transmitting time sequence register comprises a receiving time sequence register and a transmitting time sequence register; writing the time sequence register value into a time sequence register of the chip to be tested; and writing the timing sequence register value into the timing sequence register of the chip to be tested.
Step S105 is writing the transmit-receive time sequence register value into the transmit-receive time sequence register of the chip to be tested.
The method further comprises the steps of after writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested, verifying the network port conduction condition, and if the network port conduction rate is lower than a preset value, adjusting the receiving and transmitting time sequence register value until the network port conduction rate is not lower than the preset value.
Fig. 2 is a schematic diagram of an embodiment of a configuration communication interface of the present invention, and as shown in fig. 2, firstly, an RXC-RXD waveform (i.e., a receive waveform) and a TXC-TXD waveform (i.e., a transmit waveform) are acquired through an oscilloscope, and a setup time Tsetup and a hold time Thold are extracted. And acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively. Determining the delay condition of the PHY terminal by judging the range of the establishment time: trx=2ns—r_tsetup, ttx=2ns—t_tsetup, where Trx is a reception relative setup period, r_tsetup is a reception setup period, ttx is a transmission relative setup period, and t_tsetup is a transmission setup period. .
According to different chips, the delay sigma influenced by each 1 unit change of the register value is also different, and the unit delay sigma of the chip is input. In theory, the effect of signal sampling is best when t=2ns, so that a delay deviation is obtained by taking 2ns as a standard, the delay deviation is used for removing the chip unit delay sigma to obtain a decimal register value N (Ntx/rx) which needs to be adjusted, the obtained decimal register value is converted into a 16-system number, and the 16-system number is written into a corresponding register through a serial port.
Monitoring whether the network port is conducted, if so, storing the current network port conduction rate B, traversing the register values above and below the current network port conduction rate B and writing the register values into the corresponding registers, and also monitoring whether the network port is conducted, if the conduction rate is larger than B, taking the current network port conduction rate B, and stopping traversing until the network port cannot be conducted. And outputting a corresponding register value under the condition of maximum conduction rate and delay configuration conditions of TXC and RXC at a PHY end.
The specific traversing method is that the decimal register value obtained by analyzing the waveform is N; s=1 when the network port is conducting, s=0 when the network port is not conducting; two pointers i=n and j=n are set. Let pointer i decrease and pointer j increase, stopping traversing when s=0 using a loop condition.
In another aspect, the present invention also provides an apparatus for configuring a communication interface, the apparatus comprising: the acquisition module is used for acquiring a receiving waveform and a transmitting waveform of a chip to be detected, and the receiving and transmitting time sequence registers of the chip do not perform delay processing; the first processing module is used for acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively; the second processing module is used for determining a receiving relative establishment time length according to the receiving establishment time length and determining a sending relative establishment time length according to the sending establishment time length; and the third processing module is used for determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length, and writing the receiving and transmitting time sequence register value into a receiving and transmitting time sequence register of the chip to be tested. The device can quickly and accurately obtain stable delay configuration, and improves communication efficiency.
On the other hand, the invention also provides a chip, and a receiving and transmitting time sequence register of the chip is configured according to the method for configuring the communication interface.
The method for configuring the communication interface comprises the following steps: acquiring a receiving waveform and a transmitting waveform of a chip to be tested, wherein a receiving and transmitting time sequence register of the chip does not carry out time delay processing; acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively; determining a receiving relative establishment time length according to the receiving establishment time length, and determining a transmitting relative establishment time length according to the transmitting establishment time length; determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length; and writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested. According to the method and the device, the establishment and maintenance time of the data clock under the condition that no delay is added is judged, whether the delay is added at the receiving end or not is accurately and rapidly determined from the angle of the waveform, the reliability and the accuracy of configuration are ensured, and the communication efficiency is improved.
The foregoing details of the optional implementation of the embodiment of the present invention have been described in detail with reference to the accompanying drawings, but the embodiment of the present invention is not limited to the specific details of the foregoing implementation, and various simple modifications may be made to the technical solution of the embodiment of the present invention within the scope of the technical concept of the embodiment of the present invention, and these simple modifications all fall within the protection scope of the embodiment of the present invention.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, various possible combinations of embodiments of the present invention are not described in detail.
Those skilled in the art will appreciate that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, including instructions for causing a single-chip microcomputer, chip or processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In addition, any combination of various embodiments of the present invention may be performed, so long as the concept of the embodiments of the present invention is not violated, and the disclosure of the embodiments of the present invention should also be considered.
Claims (11)
1. A method of configuring a communication interface, the method comprising:
acquiring a receiving waveform and a transmitting waveform of a chip to be tested, wherein a receiving and transmitting time sequence register of the chip does not carry out time delay processing;
acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively;
determining a receiving relative establishment time length according to the receiving establishment time length, and determining a transmitting relative establishment time length according to the transmitting establishment time length;
determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length;
and writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested.
2. The method of claim 1, wherein the determining a receive relative setup time period from the receive setup time period and determining a transmit relative setup time period from the transmit setup time period comprises:
Trx＝2ns-R_Tsetup，
Ttx＝2ns-T_Tsetup，
where Trx is the receive relative setup time period, R Tsetup is the receive setup time period,
ttx is the transmission relative setup period, and t_tsetup is the transmission setup period.
3. The method of claim 1, wherein said determining a transmit and receive timing register value based on said receive relative setup time period and transmit relative setup time period comprises:
Ntx＝(N+Ttx)/σ，
Nrx＝(N+Trx)/σ，
wherein the transmit-receive timing register value comprises a receive timing register value and a transmit timing register value,
nrx is the time-sequential register value, ntx is the timing-sequential register value,
trx is the receive relative setup period, ttx is the transmit relative setup period,
sigma is the unit delay of the chip to be tested.
4. The method of claim 3, wherein writing the transmit/receive timing register value to the transmit/receive timing register of the chip under test comprises:
the receiving and transmitting time sequence register comprises a receiving time sequence register and a transmitting time sequence register;
writing the time sequence register value into a time sequence register of the chip to be tested;
and writing the timing sequence register value into the timing sequence register of the chip to be tested.
5. The method according to claim 1, further comprising
After the receiving and transmitting time sequence register value is written into the receiving and transmitting time sequence register of the chip to be tested, the network port conduction condition is verified, and if the network port conduction rate is lower than a preset value, the receiving and transmitting time sequence register value is adjusted until the network port conduction rate is not lower than the preset value.
6. An apparatus for configuring a communication interface, the apparatus comprising:
the acquisition module is used for acquiring a receiving waveform and a transmitting waveform of a chip to be detected, and the receiving and transmitting time sequence registers of the chip do not perform delay processing;
the first processing module is used for acquiring a receiving establishment time length and a transmitting establishment time length according to the receiving waveform and the transmitting waveform respectively;
the second processing module is used for determining a receiving relative establishment time length according to the receiving establishment time length and determining a sending relative establishment time length according to the sending establishment time length;
and the third processing module is used for determining a receiving and transmitting time sequence register value according to the receiving relative establishing time length and the transmitting relative establishing time length, and writing the receiving and transmitting time sequence register value into a receiving and transmitting time sequence register of the chip to be tested.
7. The apparatus of claim 6, wherein the determining a receive relative setup time period from the receive setup time period, and determining a transmit relative setup time period from the transmit setup time period comprises:
and respectively judging whether the receiving establishment time length and the sending establishment time length exceed a threshold time length or not, wherein,
if the reception setup period exceeds the threshold period, a reception relative setup period=a reception setup period-threshold period;
if the transmission setup period exceeds the threshold period, transmitting a relative setup period = transmission setup period-threshold period;
if the receiving establishment duration and the sending establishment duration do not exceed the threshold duration, then: receive relative setup time = receive setup time, and receive relative setup time = receive setup time.
8. The apparatus of claim 6, wherein said determining a transmit and receive timing register value based on said receive relative setup time period and transmit relative setup time period comprises:
Ntx＝(N+Ttx)/σ，
Nrx＝(N+Trx)/σ，
wherein the transmit-receive timing register value comprises a receive timing register value and a transmit timing register value,
nrx is the time-sequential register value, ntx is the timing-sequential register value,
trx is the receive relative setup period, ttx is the transmit relative setup period,
sigma is the unit delay of the chip to be tested.
9. The apparatus of claim 8, wherein writing the transmit/receive timing register value to the transmit/receive timing register of the chip under test comprises:
the receiving and transmitting time sequence register comprises a receiving time sequence register and a transmitting time sequence register;
writing the time sequence register value into a time sequence register of the chip to be tested;
and writing the timing sequence register value into the timing sequence register of the chip to be tested.
10. The apparatus according to claim 6, further comprising
And the verification module is used for verifying the network port conduction condition after writing the receiving and transmitting time sequence register value into the receiving and transmitting time sequence register of the chip to be tested, and adjusting the receiving and transmitting time sequence register value until the network port conduction rate is not lower than a preset value if the network port conduction rate is lower than the preset value.
11. A chip, characterized in that a transceiving timing register of the chip is configured according to a method of configuring a communication interface as claimed in any of claims 1-5.
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