CN117785545A

CN117785545A - Decoding method, memory storage device and memory control circuit unit

Info

Publication number: CN117785545A
Application number: CN202311839113.6A
Authority: CN
Inventors: 黄柏纶; 林玉祥
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-03-29

Abstract

The invention provides a decoding method, which comprises the following steps: transmitting a first reading instruction sequence corresponding to the host system to read a first entity unit of the entity unit group to obtain a first data frame; transmitting a plurality of second read instruction sequences to read a plurality of second entity units in the entity unit group to obtain a plurality of second data frames in response to failure of decoding the first single frame executed on the first data frame; performing a second single frame decoding on the plurality of second data frames, respectively; performing exclusive OR operation on the data frames corresponding to each entity unit of the entity unit group to obtain first error evaluation information; generating enhanced first error assessment information according to the first error assessment information; and performing a third single frame decoding on the first data frame based on the enhanced first error assessment information.

Description

Decoding method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a decoding technique, and more particularly, to a decoding method, a memory storage device, and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.

The partial-type memory storage device supports single-frame decoding for a single data frame and multiple-frame decoding for multiple data frames. For example, errors in a single data frame may be corrected by single frame decoding in general. When more error bits in a certain data frame fail to decode a single frame, the error in the target data frame can be corrected by using multiple frames to decode the single frame together with other data frames in the same coding group. However, if there are too many data frames in the same coding group that cannot be corrected by single frame decoding, decoding of multiple frames for the coding group cannot ensure that errors in the target data frame can be corrected completely, resulting in reduced decoding efficiency. In addition, the error assessment information used in the prior art is also interfered by error bits of data frames other than the target data frame, so that accuracy is reduced.

Disclosure of Invention

The invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve decoding efficiency.

Example embodiments of the present invention provide a decoding method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units, and the decoding method comprises the following steps: transmitting a first read command sequence, wherein the first read command sequence indicates to read a first entity unit in the plurality of entity units, and the first entity unit belongs to an entity unit group; performing a first single frame decoding on a first data frame read from the first physical unit; responding to the decoding failure of the first single frame, obtaining first soft bit information corresponding to the first data frame, and sending a plurality of second read instruction sequences, wherein the plurality of second read instruction sequences respectively indicate to read a plurality of second entity units except the first entity unit in the entity unit group; performing a second single frame decoding on a plurality of second data frames read from the plurality of second entity units, respectively; performing exclusive or (XOR) operation on each entity unit of the entity unit group after decoding the first single frame or decoding the second single frame, so as to obtain first error evaluation information corresponding to the entity unit group; generating enhanced first error assessment information according to the first error assessment information; and performing a third single frame decoding on the first data frame according to the enhanced first error assessment information and the first reliability information corresponding to the first physical unit.

In an exemplary embodiment of the present invention, the first error estimation information includes a plurality of bits, and each of the plurality of bits has a first value or a second value, wherein the step of generating the enhanced first error estimation information according to the first error estimation information includes: one or more target first bits of the one or more first bits of the plurality of bits of the first error assessment information having a first value are adjusted to a second value to obtain the enhanced first error assessment information.

In an example embodiment of the present invention, the step of adjusting the one or more target first bits of the one or more first bits of the plurality of bits of the first error assessment information having the first value to the second value comprises: the one or more target first bits are randomly selected among the one or more first bits to adjust the selected one or more target first bits to the second value.

In an exemplary embodiment of the present invention, the step of performing the first single frame decoding on the first data frame read from the first physical unit includes: the first single frame decoding is performed on the first data frame via a low density parity check code (Low Density Parity Check code, LDPC code) algorithm using the first reliability information corresponding to the first physical unit.

In an exemplary embodiment of the present invention, in response to successful decoding of the second single frame corresponding to a third data frame of the plurality of second data frames, obtaining the decoded third data frame, wherein the third data frame corresponds to a third physical unit of the plurality of second physical units; storing the decoded third data frame to another third entity unit of the plurality of entity units, adding the another third entity unit to the entity unit group to replace the third entity unit of the entity unit group; in response to the second single frame decoding failure corresponding to a fourth data frame of the plurality of second data frames, obtaining fourth soft bit information corresponding to the fourth data frame, wherein the fourth data frame corresponds to a fourth physical unit of the plurality of second physical units, wherein generating the enhanced first error assessment information based on the first error assessment information comprises: obtaining the first soft bit information corresponding to the first data frame; obtaining the one or more fourth soft bit information corresponding to the one or more fourth data frames, respectively; and adjusting the first error assessment information to be the enhanced first error assessment information according to the first soft bit information and the one or more fourth soft bit information, wherein the number of the one or more first bits in the enhanced first error assessment information is smaller than the number of the one or more first bits in the first error assessment information, and the value of each first bit is a first value.

In an exemplary embodiment of the present invention, the step of adjusting the first error estimation information to the enhanced first error estimation information according to the first soft bit information and the one or more fourth soft bit information includes: performing an OR operation on the one OR more fourth soft bit information to obtain a first vector; performing an inverse (NOT) operation on the first soft bit information to obtain inverse first soft bit information; performing an AND operation on the inverse first soft bit information AND the first vector to obtain a second vector; and performing NOT operation on the second vector to obtain an inverse second vector, and using the inverse second vector as a mask corresponding to the first error assessment information to adjust the first error assessment information to the enhanced first error assessment information.

In an exemplary embodiment of the present invention, the step of adjusting the first error assessment information to the enhanced first error assessment information using the inverse second vector as the mask corresponding to the first error assessment information includes: AND performing an AND operation on the inverse second vector AND the first error assessment information to obtain the enhanced first error assessment information.

In an exemplary embodiment of the present invention, the step of performing the third single frame decoding on the first data frame according to the enhanced first error assessment information includes: adjusting the first reliability information corresponding to the first entity unit according to the enhanced first error assessment information to obtain adjusted first reliability information; and performing the third single frame decoding on the first data frame using the adjusted first reliability information via the low density parity check code algorithm.

Another exemplary embodiment of the present invention provides a memory storage device including a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being electrically connected to the host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. Wherein, this memory control circuit unit is used for: transmitting a first read command sequence, wherein the first read command sequence indicates to read a first entity unit in the plurality of entity units, and the first entity unit belongs to an entity unit group; performing a first single frame decoding on a first data frame read from the first physical unit; responding to the decoding failure of the first single frame, obtaining first soft bit information corresponding to the first data frame, and sending a plurality of second read instruction sequences, wherein the plurality of second read instruction sequences respectively indicate to read a plurality of second entity units except the first entity unit in the entity unit group; performing a second single frame decoding on a plurality of second data frames read from the plurality of second entity units, respectively; performing exclusive or (XOR) operation on each entity unit of the entity unit group after decoding the first single frame or decoding the second single frame, so as to obtain first error evaluation information corresponding to the entity unit group; generating enhanced first error assessment information according to the first error assessment information; and performing a third single frame decoding on the first data frame according to the enhanced first error assessment information and the first reliability information corresponding to the first physical unit.

Still another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit includes: host interface, memory interface, decoding circuit and memory management circuit. The host interface is used for being electrically connected to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface, the memory interface and the decoding circuit. Wherein, this memory management circuit is used for: transmitting a first read command sequence, wherein the first read command sequence indicates to read a first entity unit in the plurality of entity units, and the first entity unit belongs to an entity unit group; instruct the decoding circuit to perform a first single frame decoding on a first data frame read from the first physical unit; responding to the decoding failure of the first single frame, obtaining first soft bit information corresponding to the first data frame, and sending a plurality of second read instruction sequences, wherein the plurality of second read instruction sequences respectively indicate to read a plurality of second entity units except the first entity unit in the entity unit group; instruct the decoding circuit to perform a second single frame decoding on the plurality of second data frames read from the plurality of second physical units, respectively; performing exclusive or (XOR) operation on each entity unit of the entity unit group after decoding the first single frame or decoding the second single frame, so as to obtain first error evaluation information corresponding to the entity unit group; generating enhanced first error assessment information according to the first error assessment information; and instructing the decoding circuit to perform a third single frame decoding on the first data frame according to the enhanced first error assessment information and the first reliability information corresponding to the first physical unit.

Based on the above, the decoding method, the memory storage device and the memory control circuit unit according to the exemplary embodiments of the present invention can improve the decoding success rate of the target data frame and/or the non-target data frame in the specific physical cell group by continuously updating and generating the first error assessment information corresponding to the physical cell group and enhancing the first error assessment information. In addition, by alternately performing single frame decoding on the target data frame and the non-target data frame in the same physical cell group and updating the first error assessment information and enhancing the first error assessment information according to the decoding result, the decoding success rate of the single frame decoding performed subsequently can be improved. Furthermore, the reliability information used in the subsequent decoding operation performed on the target data frame is adjusted by reflecting the enhanced first error assessment information of the target data frame, so that the decoding success rate of the target data frame can be improved, and the efficiency and the accuracy of the reading operation of the memory storage device can be further improved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a diagram illustrating multi-frame encoding according to an example embodiment of the present invention;

fig. 8 is a diagram illustrating a count value obtained to represent the total number of UECC frames in a physical cell group according to an example embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating obtaining first error assessment information according to an example embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention;

FIG. 11 is a schematic diagram of a reliability information table shown in accordance with an exemplary embodiment of the present invention;

Fig. 12 is a flowchart of a decoding method according to an exemplary embodiment of the present invention;

FIG. 13 is a flowchart illustrating an enhanced decoding operation using enhanced error assessment information generated via a mask according to an exemplary embodiment of the present invention;

FIG. 14 is a diagram illustrating the generation of enhanced error assessment information via random mask information and error assessment information according to an example embodiment of the present invention;

FIG. 15 is a flowchart illustrating an enhanced decoding operation using enhanced error assessment information generated via another mask according to an exemplary embodiment of the present invention;

FIG. 16 is a diagram illustrating generating mask information via a plurality of soft information and generating enhanced error assessment information via the mask information and the error assessment information according to an example embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be electrically connected to a system bus 110.

In an exemplary embodiment, the host system 11 may be electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 may be electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an exemplary embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded memory device 34 includes embedded memory devices of various types, such as embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or embedded multi-chip package (embedded Multi Chip Package, eMCP) memory device 342, that electrically connect the memory module directly to the substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used for electrically connecting the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, connection interface unit 41 is compatible with the high speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also be a serial advanced attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is electrically connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and one physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, a memory interface 53, and an error checking and correcting circuit 54.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an example embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is electrically connected to the memory management circuit 51. The memory management circuitry 51 may communicate with the host system 11 through a host interface 52. The host interface 52 may be used to obtain and identify instructions and data of the host system 11. For example, instructions and data of host system 11 may be transferred to memory management circuitry 51 through host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is electrically connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection (Garbage Collection, GC) operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

The error checking and correcting circuit 54 is electrically connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains the write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code. For example, the error checking and correcting circuit 54 may support various encoding/decoding algorithms such as low density parity check (Low Density Parity Check code) codes, BCH codes, reed-solomon (RS) codes, exclusive OR (XOR) codes, and the like.

The basic unit of performing the encoding/decoding by the error checking and correction circuit 54 is a frame (also referred to as a data frame, or a data frame). A frame may include a plurality of data bits. In an exemplary embodiment, one frame includes 256 bits. However, in another example embodiment, a frame may also include more (e.g., 4K bytes) or fewer bits.

The error checking and correction circuit 54 may encode and decode data in a single frame, and the error checking and correction circuit 54 may encode and decode data in multiple frames. In an example embodiment, error checking and correction circuit 54 performs single frame encoding and decoding based on an LDPC code, and the present invention is not limited thereto. In an exemplary embodiment, the error checking and correction circuit 54 performs multi-frame encoding and decoding based on BCH codes, RS codes, and/or XOR codes, and the present invention is not limited thereto. Depending on the encoding/decoding algorithm employed, the error checking and correction circuit 54 may encode the data to be protected to generate a corresponding error correcting code and/or error checking code. The error correction code and/or the error check code generated by the encoding can then be used to correct errors in the data to be protected. For convenience of explanation, the error correction codes and/or error check codes generated via encoding are hereinafter collectively referred to as parity (parity) data.

In an exemplary embodiment, the memory control circuit unit 42 further includes a buffer memory 55 and a power management circuit 56. The buffer memory 55 is electrically connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is electrically connected to the memory management circuit 51 and is used for controlling the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an exemplary embodiment, a dummy block may also include one or more physical erase units.

The physical units 610 (0) -610 (a) in the storage area 601 are configured to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

In an example embodiment, the memory management circuit 51 may use the physical cell group to manage the physical cells 610 (0) -610 (A). A group of entity units may comprise a plurality of entity units. A group of physical units may be used to store multiple frames. One physical unit may be used to store one or more frames. A single group of physical units may include physical units in the same (or different) memory plane, the same (or different) memory die, and/or the same (or different) Chip Enabled (CE) area.

In an example embodiment, error checking and correction circuit 54 may perform multi-frame encoding on a plurality of frames stored to a certain physical cell group to protect data in such frames from parity data generated by the multi-frame encoding. In addition, the error checking and correction circuit 54 may perform multi-frame decoding on a plurality of frames read from a certain physical cell group to correct errors in such frames from parity data generated by the multi-frame encoding.

In an exemplary embodiment, error checking and correction circuit 54 may perform single frame encoding on a single frame stored to a physical unit to protect data in the single frame from parity data generated by the single frame encoding. In addition, the error checking and correction circuit 54 may perform single frame decoding on a single frame read from a certain physical unit to correct errors in the single frame by parity data generated by the single frame encoding.

Fig. 7 is a diagram illustrating a multi-frame encoding according to an exemplary embodiment of the present invention. Referring to fig. 7, frames 710 (1) -710 (n) contain data stored into a physical cell group. For example, the entity group may include a plurality of entity units in FIG. 6. For example, frame 710 (k) includes data to be stored to physical unit 610 (k), where k is an integer between 1 and n. The data in frames 710 (1) -710 (n) may include data stored as indicated by write instructions of host system 10. Alternatively, the data in frames 710 (1) through 710 (n) may also include data read from the rewritable nonvolatile memory module 43 and waiting to be restored to the rewritable nonvolatile memory module 43.

In an example embodiment, error checking and correction circuit 54 may perform multi-frame encoding on frames 710 (1) through 710 (n) to generate frame 710 (p). The data in frame 710 (p) includes parity data to protect frames 710 (1) through 710 (n). For example, when performing multi-frame decoding on frames 710 (1) -710 (n), parity data in frame 710 (p) may be used to detect and/or correct errors in frames 710 (1) -710 (n).

In an exemplary embodiment, in multi-frame encoding, the data in frames 710 (1) through 710 (n) is encoded based on the location of each bit (or group of bits). For example, bits b (11), b (21), …, b (n 1) at position 701 (1) may be encoded to obtain bit b (p 1) in frame 710 (p); bits b (12), b (22), …, b (n 2) at position 701 (2) may be encoded to obtain bit b (p 2) in frame 710 (p); similarly, bits b (1 m), b (2 m), …, b (nm) at position 701 (m) may be encoded to obtain bit b (pm) in frame 710 (p). Thereafter, in multi-frame decoding, bits (also referred to as parity bits) in frame 710 (p) may be used to detect and/or correct erroneous bits in frames 710 (1) -710 (n). For example, bit b (p 2) in frame 710 (p) may be used to detect or correct one or more erroneous bits in position 701 (2).

It should be noted that in an exemplary embodiment, the arrangement of the plurality of bits covered by any of the positions 701 (1) to 701 (m) may be different from the arrangement shown in fig. 7, which is not a limitation of the present invention. Furthermore, in an exemplary embodiment, the number of frames 710 (p) containing parity data may also be 2 or more to provide different or better multi-frame decoding capabilities, as the invention is not limited.

In an example embodiment, the error checking and correction circuit 54 may perform single frame encoding on the frame 710 (j) of the frames 710 (1) -710 (n) and 710 (p) to generate parity data for protecting the frame 710 (j), where j is an integer between 1 and n or j may be p. Thereafter, in single frame decoding, parity data generated by performing single frame encoding on frame 710 (j) may be used to detect and/or correct erroneous bits in frame 710 (j).

In an example embodiment, the parity data generated in frame 710 (p) by performing multi-frame encoding is also referred to as a fault-tolerant disk array (Redundant Array of Independent Disks, RAID) error correction code. In an exemplary embodiment, frames 710 (1) -710 (n) and 710 (p) may also be combined to be considered a block code. Frames 710 (1) -710 (n) and 710 (p) may be stored in multiple physical units belonging to the same physical unit group.

In an example embodiment, the memory management circuit 51 may send a sequence of read instructions. The read command sequence may instruct to read a physical cell (also referred to as a first physical cell) in a physical cell group. For example, the memory management circuit 51 may send the read command sequence to the rewritable nonvolatile memory module 43. The rewritable nonvolatile memory module 43 can transmit the data read from the first physical unit back to the memory management circuit 51 according to the read command sequence. Decoding circuitry in error checking and correction circuitry 54 may perform single frame decoding on frames containing the data. For example, if the data in the frame is single frame encoded based on an LDPC code, the decoding circuitry may single frame decode the frame based on the LDPC code. If the single frame is decoded successfully (indicating that the data in the frame is correct and/or errors have been corrected), the error checking and correction circuit 54 may output the decoded successful data (also referred to as a decoded frame or decoded data frame).

In an example embodiment, the memory management circuit 51 may obtain a read instruction from the host system 11. Such a read instruction may instruct to read data belonging to a particular logical unit (also referred to as a first logical unit), and the first logical unit is mapped to a first physical unit. According to the read command, the memory management circuit 51 may send the read command sequence (also referred to as a first read command sequence) to the rewritable nonvolatile memory module 43 to read the data from the first physical unit.

In an example embodiment, the memory management circuit 51 may also actively send the read command sequence to the rewritable nonvolatile memory module 43 to read the data from a specific physical unit of the rewritable nonvolatile memory module 43 without retrieving the read command from the host system 11. For example, the memory management circuit 51 may actively read data from a particular physical unit during performing an intensive decoding operation, performing a data merge operation (e.g., garbage collection operation), performing a Wear Leveling (WL) operation, handling read disturb (read disturb), and/or handling data retention (data retention).

In an exemplary embodiment, if the single frame decoding fails (indicating that the frame is a frame that cannot be corrected by the single frame decoding), the decoding circuit in the error checking and correction circuit 54 may perform multi-frame decoding on a plurality of frames including the frame if a predetermined condition is satisfied. For example, if the frame was originally multi-frame encoded based on XOR codes, the error checking and correction circuit 54 may also multi-frame decode the frame based on XOR codes if the predetermined condition is met. In an exemplary embodiment, frames that cannot be corrected by single frame decoding are also referred to as UECC frames.

It should be noted that in the XOR-code based multi-frame decoding, at most one UECC frame can exist simultaneously in a plurality of frames to be decoded. If two or more UECC frames are included in the multiple frames to be decoded, XOR-code based multi-frame decoding will not correct errors in such frames.

In an exemplary embodiment, the memory management circuit 51 may determine whether a predetermined condition is satisfied before performing the multi-frame decoding. The predetermined condition is to trigger decoding of multiple frames of the physical cell group. In an example embodiment, in response to the predetermined condition being met, the memory management circuit 51 may instruct the error checking and correction circuit 54 to perform multi-frame decoding of the physical cell group. Furthermore, if this predetermined condition is not satisfied, the memory management circuit 51 may not allow the multi-frame decoding to be performed. Thus, the accuracy of the decoding result of the performed multi-frame decoding can be ensured.

In an exemplary embodiment, the memory management circuit 51 may indicate the total number of UECC frames in the physical unit group by a count value. For example, the count value may be equal to the total number of UECC frames in the physical cell group. In an example embodiment, in response to the count value reaching (e.g., being less than or equal to) a threshold value, the memory management circuit 51 may determine that the predetermined condition has been met. In addition, if the count value does not reach (e.g., is greater than) the threshold value, the memory management circuit 51 may determine that the predetermined condition is not satisfied.

Fig. 8 is a diagram illustrating a count value obtained to represent the total number of UECC frames in a physical cell group according to an example embodiment of the present invention. Referring to FIG. 8, a plurality of frames read from a physical cell group are represented by frames 810 (1) through 810 (p). After single frame decoding is performed on each of the frames 810 (1) through 810 (p), the UECC frames (e.g., frame 810 (i)) in the frames 810 (1) through 810 (p) may be recorded, as shown in fig. 8. The memory management circuit 51 may count the total number of UECC frames in frames 810 (1) through 810 (p) and obtain a count N based on the total number. That is, the count value N may be equal to or reflect the total number of UECC frames in frames 810 (1) through 810 (p).

In an exemplary embodiment, this threshold may be set to "1" assuming that the error checking and correction circuit 54 performs multi-frame encoding and decoding based on XOR codes. Therefore, if the count value N is equal to "1", the memory management circuit 51 may determine that the predetermined condition has been satisfied.

In an example embodiment, the memory management circuit 51 may instruct the decoding circuit in the error checking and correction circuit 54 to perform single frame decoding (also referred to as first single frame decoding) on the frame read from the first physical unit (also referred to as first data frame) to correct errors in the first data frame. In an exemplary embodiment, if the decoding of the first single frame is successful, the memory management circuit 51 may output the decoded data. For example, the memory management circuit 51 may communicate the successfully decoded data to the host system 11 in response to the read instruction. Alternatively, during data consolidation operations (e.g., garbage collection operations), performing wear leveling operations, handling read disturb and/or handling data maintenance, the memory management circuitry 51 may store and/or perform corresponding operations on the successfully decoded data to a particular entity. In an exemplary embodiment, if the first single frame decoding fails, but the predetermined condition is satisfied, the decoding circuit may perform multi-frame decoding on the first data frame to correct errors in the first data frame.

In an exemplary embodiment, the memory management circuit 51 may obtain error assessment information (also referred to as first error assessment information) corresponding to the physical cell group in case the first single frame decoding fails and the predetermined condition is not satisfied. The first error assessment information relates to a bit error rate of the group of physical units. For example, the first error evaluation information may schematically reflect a total number of error bits included in the data read from the physical cell group.

In an exemplary embodiment, the memory management circuit 51 and the decoding circuit may further perform an enhanced decoding operation to further attempt to decode the first data frame when the decoding of the first single frame fails. Specifically, the memory management circuit 51 generates the enhanced first error assessment information according to the first error assessment information. The memory management circuit 51 may then instruct the decoding circuit to perform single-frame decoding (also referred to as third single-frame decoding) again on the first data frame according to the enhanced first error assessment information in an attempt to correct errors in the first data frame based on the enhanced first error assessment information.

In an example embodiment, the memory management circuit 51 may obtain or update the reliability information according to the enhanced first error assessment information. For example, this reliability information may include a log-likelihood ratio (Log Likelihood Ratio, LLR) that may be used in single-frame decoding. In addition, the memory management circuit 51 may further adjust the first reliability information corresponding to the first entity unit according to the enhanced first error assessment information to obtain adjusted first reliability information. The decoding circuit may perform a third single frame decoding on the first data frame of the first physical unit via a decoding algorithm (e.g., a low density parity check code algorithm) according to the adjusted first reliability information. It should be noted that the reliability information used in the third single frame decoding is dynamically obtained or updated according to the enhanced first error assessment information, so that the third single frame decoding may have a higher decoding success rate than the first single frame decoding. That is, the third single frame decoding has a higher probability of completely correcting errors in the first data frame than the first single frame decoding.

In an exemplary embodiment, the first error assessment information and the enhanced first error assessment information each include an assessment value. This estimate may be positively correlated to the bit error rate of the entire physical cell group. For example, the higher the bit error rate of the entity cell group as a whole, the more the total number of error bits in the data read from the entity cell group, so the larger the evaluation value will be. Alternatively, from another perspective, the evaluation value may be positively correlated to the total number of erroneous bits in the data read from the group of entity cells.

In an exemplary embodiment, the memory management circuit 51 may perform a logic operation on a plurality of frames (including the first data frame) read from the physical cell group to obtain the first error assessment information. This logical operation may comprise an XOR operation, for example. For example, after performing the logic operation, the memory management circuit 51 may obtain a data sequence reflecting the result of the logic operation. The memory management circuit 51 may count the total number of specific bits (e.g., bits "1" or "0") in this data sequence and obtain the first error assessment information based on this total number.

Fig. 9 is a diagram illustrating obtaining first error-assessment information according to an example embodiment of the present invention. Referring to fig. 9, a plurality of frames read from a physical cell group are represented by frames 910 (1) through 910 (p). After performing a logical operation including an XOR operation on frames 910 (1) -910 (p), a data sequence 920 (also referred to as error assessment information) may be obtained. For example, data sequence 920 may include bits b (r 1) through b (rm). For example, bit b (r 1) reflects the XOR execution result of bits b (11), b (21) … to b (p 1); bit b (r 2) reflects the XOR execution result of bits b (12), b (22) … through b (p 2); and bit b (rm) reflects the XOR execution result of bits b (1 m), b (2 m) … to b (pm), and so on. The memory management circuit 51 may count the total number of bits "1" in the data sequence 920 and obtain the evaluation value M based on this total number. For example, the evaluation value M may be equal to or reflect the total number of bits "1" in the data sequence 920. Furthermore, the evaluation value M may be positively related to the bit error rate of the entire physical cell group. That is, the more erroneous bits in frames 910 (1) to 910 (p), the larger the evaluation value M. Alternatively, if there are no erroneous bits in frames 910 (1) through 910 (p), then the estimate M may be zero. It should be noted that, since the error evaluation information reflects the status of the error bits of the data frames of all the physical units of the physical unit group, it is not easy to determine the distribution of the error bits of the data frames corresponding to the single physical unit (e.g., the first data frame corresponding to the first physical unit) through the error evaluation information. In order to more effectively determine the distribution of the error bits of the data frame of the single entity unit, the embodiment proposes to strengthen the error evaluation information, thereby strengthening the error evaluation information, reducing the interference caused by the error bits of other entity units on the error evaluation information, and further more effectively determining the distribution of the error bits of the data frame of the single entity unit.

FIG. 10 is a schematic diagram illustrating a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention. Referring to FIG. 10, it is assumed that the threshold voltage distribution of memory cells in a physical cell group includes states 1010 and 1020. State 1010 may be used to represent a distribution of threshold voltages of memory cells of the memory cells storing a first bit (or a first bit combination). State 1020 may be used to represent a distribution of threshold voltages of memory cells of the memory cells storing a second bit (or a second bit combination). For example, the first bit may be bit "0" (or the first bit combination may be bit "000", etc.), and the second bit may be bit "1" (or the second bit combination may be bit "101", etc.). In addition, the invention is not limited to the bits or bit combinations to which states 1010 and 1020 respectively correspond.

In an example embodiment, the memory management circuit 51 may send a read command sequence to the rewritable nonvolatile memory module 43 to instruct the rewritable nonvolatile memory module 43 to read the memory cells using the read voltage levels 1001-1005. The total number of read voltage levels 1001-1005 may be more or less. Based on the read voltage levels 1001-1005, the memory management circuit 51 can identify the threshold voltage of each of the memory cells as belonging to one of the voltage ranges A-F. Thereafter, assuming that the threshold voltage of a certain memory cell belongs to the voltage range a, reliability information (e.g., LLR) corresponding to the voltage range a can be used in single frame decoding to decode the data bits read from the memory cell. Alternatively, assuming that the threshold voltage of a certain memory cell belongs to the voltage range C, reliability information (e.g., LLR) corresponding to the voltage range C may be used in single frame decoding to decode the data bits read from the memory cell, and so on.

Fig. 11 is a schematic diagram of a reliability information table according to an exemplary embodiment of the present invention. Referring to fig. 11, it is assumed that reliability information corresponding to different first error evaluation information is described in table data 1101. In an example embodiment, if the evaluation value m=m (1) in the first error evaluation information is emphasized, the parameter values (e.g., LLR values) corresponding to the voltage ranges a-F in the reliability information LLR (0) can be used in the third single frame decoding to decode the data read from the first physical unit (i.e., the first data frame) according to the table data 1101. Similarly, if the evaluation value m=m (2) or M (3) in the first error evaluation information is emphasized, the parameter value (e.g., LLR value) corresponding to the voltage range a-F in the reliability information LLR (1) or LLR (2) can be used in the third single frame decoding to decode the data read from the first physical unit (i.e., the first data frame) according to the table data 1101.

In an example embodiment, assume that the reliability information used for the first single frame decoding is LLR (0). After the latest evaluation value m=m (2) corresponding to the enhanced error evaluation information is obtained, reliability information used for the third single frame decoding may be adjusted from LLR (0) to LLR (1). Thereafter, in the third single frame decoding, the decoding circuit may decode the first data frame based on the reliability information LLR (1). In a bit error state corresponding to the evaluation value m=m (2), performing single frame decoding based on the reliability information LLR (1) can improve the decoding success rate of single frame decoding as compared to the reliability information LLR (0). Thus, even if the first single frame decoding fails, the first data frame has a high probability of being successfully decoded (i.e., correcting all errors in the first data frame) in the third single frame decoding. It should be noted that even though the decoding success rate of the third single frame decoding is higher than that of the first single frame decoding, the third single frame decoding may still fail (i.e., all errors in the first data frame cannot be corrected).

Referring to fig. 12, in step S1210, the memory control circuit unit 42 sends a first read command sequence, wherein the first read command sequence indicates to read a first entity unit (also referred to as a target entity unit) of the plurality of entity units, and the first entity unit belongs to a entity unit group. In one embodiment, the memory control circuit unit 42 generates the first read instruction sequence according to the read instruction from the host system 11. In another embodiment, the memory control circuit unit 42 can also generate the first read command sequence according to various operations for managing the memory device 10. The entity group further includes a check entity for storing parity data (e.g., data frame 710 (p) shown in fig. 7), wherein the parity data is generated based on data stored by a plurality of entity units other than the check entity in the entity group (e.g., data frames 710 (1) -710 (n) shown in fig. 7). In an exemplary embodiment, the parity data is a Redundant Array of Independent Disks (RAID) error correction code, wherein the RAID error correction code is the result of performing an XOR operation on the data frames stored by each of the plurality of other physical units.

Next, in step S1220, the memory control circuit unit 42 performs a first single frame decoding on the first data frame read from the first physical unit. Next, in step S1230, in response to the decoding failure of the first single frame, the memory control circuit unit 42 obtains the first soft bit information corresponding to the first data frame and sends a plurality of second read command sequences, wherein the plurality of second read command sequences respectively indicate to read a plurality of second entity units other than the first entity unit in the entity unit group. It should be noted that, when the physical cell is read by using the read voltage, the obtained sets of soft bit information may be used to reflect the voltage interval in which the threshold voltage of each memory cell in the physical cell is located. In the present embodiment, the memory control circuit unit 42 uses the first set of soft bit information to generate the enhanced first error assessment information for enhanced decoding. In other embodiments, other sets of soft bit information may be used to generate the enhanced first error assessment information. On the other hand, in response to the decoding of the first single frame being successful, the memory control circuit unit 42 obtains a decoded first data frame. The decoded first data frame may be transmitted to the host system 11 in response to the read command. In addition, the memory control circuit unit 42 may store the decoded first data frame to another first entity unit, and replace the mapping relationship of the first entity unit with the another first entity unit. In addition, the other first entity unit is further divided into the entity unit group, and the first entity unit is removed from the entity unit group.

In the present exemplary embodiment, the second plurality of read command sequences are not generated according to one or more read commands of the host system 11. The plurality of second read command sequences are read command sequences actively generated and sent by the memory control circuit unit 42 for enhanced decoding of the first physical unit.

Next, in step S1240, the memory control circuit unit 42 performs a second single frame decoding on the plurality of second data frames read from the plurality of second physical units, respectively.

In an example embodiment, the step of performing the first single frame decoding on the first data frame read from the first physical unit comprises: the memory control circuit unit 42 performs the first single frame decoding on the first data frame using the first reliability information corresponding to the first physical unit via a low density parity check code (Low Density Parity Check code, LDPC code) algorithm. In addition, in one embodiment, the step of performing the second single frame decoding on the second data frames read from each of the second physical units comprises: the memory control circuit unit 42 performs a hard decoding operation on the second data frame, wherein in response to the hard decoding operation failing, the memory control circuit unit 42 performs a soft decoding operation on the second data frame via a low density parity check code algorithm to perform the second single frame decoding using the second reliability information corresponding to the second physical unit.

Next, after the decoding of the plurality of second single frames is completed, in step S1250, the memory control circuit unit 42 performs an exclusive or (XOR) operation on each entity unit of the entity unit group after the decoding of the first single frame (e.g., on the first entity unit) or the decoding of the second single frame (e.g., on the plurality of second entity units), so as to obtain the first error assessment information corresponding to the entity unit group. That is, the memory control circuit unit 42 performs an XOR operation (in the manner shown in fig. 9) on the bit values of each data frame belonging to the physical cell group (including the original data frame that failed to be decoded and the decoded data frame that was decoded successfully) to obtain the first error assessment information corresponding to the physical cell group.

In more detail, in an exemplary embodiment, in response to the decoding of the second single frame corresponding to a third data frame of the plurality of second data frames, the memory control circuit 42 obtains the decoded third data frame corresponding to a third physical unit of the plurality of second physical units. Next, the memory control circuit 42 stores the decoded third data frame to another third entity unit of the plurality of entity units, adds the another third entity unit to the entity unit group to replace the third entity unit of the entity unit group (i.e., the third entity unit is removed from the entity unit group, and the third logic unit mapped to the third entity unit is mapped to the another third entity unit instead).

Correspondingly, in response to the decoding failure of the second single frame corresponding to a fourth data frame in the plurality of second data frames, fourth soft bit information corresponding to the fourth data frame is obtained, wherein the fourth data frame corresponds to a fourth physical unit in the plurality of second physical units.

That is, if the data frame of one entity (e.g., the third entity) in the second entity is successfully decoded, the corresponding decoded data frame is stored in the other entity, and the other entity replaces the original entity (the data frame of the entity is updated) in the entity group; if a data frame of one of the second physical units (e.g., the fourth physical unit) fails to be decoded, the data frame is retained in the physical unit group until the data frame is successfully decoded. Then, after the first single frame decoding and the plurality of second single frame decoding are completed, the memory control circuit unit 42 performs an XOR operation on each data frame currently corresponding to the physical unit group to obtain the first error assessment information corresponding to the physical unit group. The error assessment information is also called XOR vector (XOR vector).

In this way, the decoding of the single frame is performed on the plurality of entity units other than the first entity unit in the entity unit group, and the decoded data frame is used to replace the original data frame, so that the interference of possible error bits received by the error evaluation information generated by the corresponding entity unit group can be reduced.

Next, in step S1260, the memory control circuit unit 42 generates enhanced first error evaluation information according to the first error evaluation information. Next, in step S1270, the memory control circuit unit 42 performs a third single frame decoding on the first data frame according to the enhanced first error assessment information and the first reliability information corresponding to the first physical unit.

Specifically, the step of generating the enhanced first error assessment information according to the first error assessment information includes: one or more target first bits of the one or more first bits of the plurality of bits of the first error assessment information having a first value are adjusted to a second value to obtain the enhanced first error assessment information. In one embodiment, the first value is 1 and the second value is 0, but the invention is not limited thereto. For example, in another embodiment, the first value is 0 and the second value is 1. In detail, the bits having the first value in the first error estimation information and the enhanced first error estimation information are called first bits, and when the first value is adjusted to the second value, the first bits are no longer first bits, so the number of the first bits in the enhanced first error estimation information is smaller than the corresponding number of the first bits in the first error estimation information.

In an exemplary embodiment, the first error estimate information may be randomly generated. For example, the one or more target first bits are randomly selected from the one or more first bits by a random manner to adjust the selected one or more target first bits to the second value. In one embodiment, the memory control circuit unit 42 may generate mask information having a first value that is randomly distributed, and the total number and arrangement of bits of the mask information is equal to the first error assessment information. The memory control circuit unit 42 may perform an AND (or) operation on the mask information AND the first error evaluation information to take the result of the operation as enhanced first error evaluation information.

Referring to fig. 13, it is assumed that a plurality of entity units belonging to the entity unit group PUG store data frames DF1, DF2 (1) to DF2 (N). The DF2 (N) is, for example, parity data generated by the data frames DF1, DF2 (1) to DF2 (N-1) via the XOR algorithm.

According to the read command from the host system 11, the memory control circuit unit 42 sends a first read command sequence to read the first data frame DF1 of the first physical unit (as indicated by arrow a 1200). During the reading, the memory control circuit unit 42 may obtain the first reliability information LLR1 corresponding to the first entity unit (as indicated by arrow a 1201).

The memory control circuit unit 42 then performs a first single frame decoding (as indicated by arrow a 1202) on the first data frame DF1 via the LDPC algorithm/decoding circuit (B1301).

In response to the first single frame decoding failure, the memory control circuit unit 42 transmits a second read instruction sequence to read the data frames DF2 (1) to DF2 (N), and performs second single frame decoding on the data frames DF2 (1) to DF2 (N) (as indicated by an arrow a 1203).

After the first single frame decoding and the second single frame decoding are completed, the memory control circuit unit 42 identifies a plurality of data frames DF1, DF2 (1) -DF 2 (N) (gray scale) corresponding to the physical cell group PUG, wherein each data frame is different according to whether the corresponding single frame decoding is successful or not, as indicated by arrows a1204, a 1205. For example, the first data frame DF1 corresponds to a first single frame decoding failure, and the first data frame DF1 (gray bottom) is the original first data frame DF1 (i.e., raw data). For another example, the nth second data frame DF2 (N) (gray) corresponds to the decoded second single frame, and the nth second data frame DF2 (N) (gray) is not the original nth second data frame DF2 (N), but the decoded/decoded nth second data frame DF2 (N) (i.e., decoded data).

Next, as indicated by arrow a1206, the memory control circuit unit 42 performs an XOR operation on each of the data frames DF1, DF2 (1) -DF 2 (N) (gray-scale) of the entity unit group PUG to obtain the first error evaluation information EI1. Next, the memory control circuit unit 42 generates the enhanced first error estimation information EI2 (A1207) according to the first error estimation information EI1, for example, by using a random mask (B1302). Details of the random mask may be found in the description corresponding to fig. 14.

Next, the memory control circuit unit 42 adjusts the first reliability information LLR1 corresponding to the first entity unit according to the enhanced first error assessment information EI2 to obtain the adjusted first reliability information LLR2 (as indicated by arrows a1208, a 1209). The operation of this adjustment reliability information is also called LLR remap (LLR remap) (B1303), and see the description of fig. 11 above for details.

Next, the memory control circuit unit 42 performs the first single-frame decoding again on the first data frame DF1 (as indicated by arrow a 1210) using the adjusted first reliability information LLR2 (as indicated by arrow a 1211). The first single frame decoding performed again is also referred to as a third single frame decoding.

Referring to fig. 14, assume that the physical unit group has two UECCs, and possible error bit information thereof is, for example, error bit information Err corresponding to the first data frame ₀ And error bit information Err corresponding to a fourth data frame ₁ ("1" indicates an error bit). The first error estimate information generated for each data frame of the physical cell group can be regarded as the error bit information Err ₀ Err and Err ₁ XOR operation result (a 1401). As shown in fig. 14, the error bit information Err associated with the first data frame ₀ In contrast, the bit value of the first error evaluation information part and the error bit information Err ₀ Different, bit values at these same positions but different values can be regarded as Noise ₁ . For example, the first error evaluation information is subjected to error bit information Err ₁ Has five noise bit values. Resulting in erroneous bit information Err that cannot be directly identified as the first data frame directly from the first erroneous evaluation information ₀ The distribution of the error bits of (a) is determined.

In the present exemplary embodiment, the memory control circuit unit 42 performs Masking operation (Masking) on the first error estimation information, generates Masking information (Mask) with randomly distributed first values, AND performs AND operation on the first error estimation information AND the random Masking Mask (a 1403). The obtained operation result is taken as the enhanced error assessment information (adv.xor vector) as indicated by an arrow a 1404. As shown in fig. 14, the error bit information Err associated with the first data frame ₀ In contrast, the bit value of the first error evaluation information part and the error bit information Err are intensified ₀ Different, bit values at these same positions but different values can be regarded as Noise ₂ . Note that Noise ₂ The number of noise bit values (i.e., two) that the first erroneous evaluation information has is smaller than the number of noise bit values (i.e., five). That is, the random manner provided by the above embodiments can generate the enhanced error assessment information, which can more effectively reflect the distribution of the error bits of the first data frame.

In another example embodiment, the memory control circuit unit 42 may generate mask information using soft bit information to generate the enhanced first error assessment information. Specifically, the step of generating the enhanced first error assessment information according to the first error assessment information includes: identifying the first soft bit information corresponding to the first data frame; identifying one or more fourth soft bit information respectively corresponding to one or more fourth data frames read from one or more fourth physical units of the plurality of second physical units of the physical unit group and failing to decode the second single frame performed for each of the one or more fourth data frames; and adjusting the first error assessment information to be the enhanced first error assessment information according to the first soft bit information and the one or more fourth soft bit information, wherein the number of the one or more first bits in the enhanced first error assessment information is smaller than the number of the one or more first bits in the first error assessment information, and the value of each first bit is a first value.

Referring to fig. 15, fig. 15 is different from fig. 13 in that, after the first single frame decoding and the plurality of second single frames decoding are completed, the memory control circuit unit 42 identifies the first soft bit information and the one or more fourth soft bit information (if one or more fourth data frames of the corresponding one or more fourth physical units fail to decode) as indicated by arrow a 1501. Next, in the step of performing the masking operation (B1602) to generate the enhanced first error assessment information, the memory control circuit unit 42 generates mask information (a 1502) according to the first soft bit information and one or more fourth soft bit information.

In more detail, the memory control circuit unit 42 performs an OR (OR) operation on the one OR more fourth soft bit information to obtain a first vector; performing an inverse (NOT) operation on the first soft bit information to obtain inverse first soft bit information; performing an AND operation on the inverse first soft bit information AND the first vector to obtain a second vector; AND performing NOT operation on the second vector to obtain an inverse second vector, AND using the inverse second vector as a Mask (Mask information) corresponding to the first error evaluation information to adjust the first error evaluation information to the enhanced first error evaluation information, for example, performing AND operation on the inverse second vector AND the first error evaluation information to obtain the enhanced first error evaluation information.

Referring to fig. 16, assuming that the bit value of unreliable soft bit information is "1", the memory control circuit unit 42 further recognizes three soft bit information SB1 to SB3 corresponding to three fourth data frames (UECC frames) in addition to the soft bit information SB0 corresponding to the first data frame.

First, as indicated by arrow a1601, the memory control circuit unit 42 performs a bit control on soft bit information SB ₁ ～SB ₃ An OR operation is performed to obtain a first vector (vector 1). The first vector (vector 1) may reflect the distribution of unreliable bits of soft bit information of other UECCs.

Next, the memory control circuit unit 42 performs a bit control on the soft bit information SB ₀ Performing NOT operation to obtain inverse first soft bit information(as indicated by arrow a 1602). Next, as indicated by arrow a1603, the memory control circuit unit 42 is set to be opposite to the first soft bit information ∈>AND performing an AND operation on the first vector (vector 1) to obtain a second vector (vector 2). The second vector (vector 2) may reflect a distribution of unreliable bits corresponding to the same positions as the reliable bits of the first soft bit information.

Next, as indicated by arrow A1604, the memory is controlled electricallyThe way unit 42 performs NOT operation on the second vector (vector 2) to obtain an inverse second vector The inverse second vector->Can be used as mask information.

Here, it is assumed that the memory control circuit unit 42 has generated the first error evaluation information (XOR vector) by the error bit information of the first data frame and the error bit information of the three fourth data frames in the manner as illustrated in fig. 14.

Then, as indicated by arrows A1605, A1606, the memory control circuit unit 42 evaluates the first error evaluation information (XOR vector) and the inverse second vectorAn AND operation is performed to obtain the enhanced error assessment information (adv.xor vector) (a 1607). The enhanced error assessment information considers the distribution of reliable bit values of the first physical unit and unreliable bit values of other ue cc frames, reduces interference caused by the unreliable bit values of other ue cc frames (the number of the first bits in the enhanced error assessment information is less than the number of the first bits in the error assessment information can be seen), and further improves the accuracy of the distribution of the error bits reflected by the enhanced error assessment information.

In an exemplary embodiment, in response to the decoding of the third single frame being successful (i.e., all errors in the first data frame are corrected), the memory control circuit unit 42 may continuously update the first error assessment information according to the decoding result of the decoding of the third single frame. The updated first error assessment information may schematically reflect the latest bit error rates of the plurality of physical units in the physical unit group. Memory control circuitry 42 may then select a data frame (UECC frame) that has not been successfully decoded as a new first data frame to perform the first single frame decoding or may prefer to perform the first single frame decoding with the lowest bit error rate or relatively lower UECC frame. In response to the decoding failure of the first single frame, the memory control circuit 42 may perform the enhanced decoding operation on the first data frame of the first physical unit according to the updated enhanced first error assessment information, so as to increase the decoding success rate. Thus, the total number of UECC frames in the physical cell group can be gradually reduced.

In an example embodiment, in response to successfully decoding a UECC frame read from any one of the physical units in the physical unit group, memory management circuitry 51 may update the count value (e.g., count value N of fig. 8). The updated count value may reflect the total number of the latest UECC frames in the physical unit group. In an exemplary embodiment, if the updated count value reaches the threshold, the memory management circuit 51 may determine that the predetermined condition is satisfied and may perform multi-frame decoding. Furthermore, if the updated count value has not reached the threshold, the memory management circuit 51 may not allow the multi-frame decoding to be performed.

That is, through the decoding method provided by the present exemplary embodiment, the UECC frame may be successfully decoded gradually. Once the total number of UECC frames in the physical unit group reaches a threshold, multi-frame decoding of the physical unit group may be initiated to ensure that the remaining UECC frames in the physical unit group may be successfully decoded.

In an example embodiment, the first entity unit is also referred to as a target entity unit. In an example embodiment, the entity of the entity group that is read to assist in decoding the first data frame (i.e., the second entity) and/or the entity that is read to reduce the total number of UECC frames in the entity group is also referred to as a non-target entity. In an example embodiment, frames read from a target physical unit are also referred to as target data frames and/or frames read from a non-target physical unit are also referred to as non-target data frames.

In an example embodiment, in response to the decoding of the third single frame corresponding to the target physical unit being successful, the memory control circuit 42 obtains the decoded first data frame corresponding to the target physical unit. The decoded first data frame corresponding to the target entity may be transmitted to the host system 11 in response to the read command. In addition, in response to the decoding success of the third single frame corresponding to the target physical unit, the memory control circuit unit 42 may select other ue cc frames corresponding to the non-target physical unit as new first data frames to perform the enhanced decoding operations of steps S1210 to S1270, and attempt to successfully decode the ue cc frames other than the original first data frames to update the error estimation information and the enhanced error estimation information.

That is, single frame decoding may continue for non-target data frames belonging to a UECC frame stored in a physical cell group, whether or not the target data frame was successfully decoded, until the target data frame is successfully decoded, all UECC frames in the physical cell group are successfully decoded, a predetermined condition is met, or an upper limit of decoding times (e.g., a maximum number of iterations) is reached. In addition, frames corrected from the UECC frames may be used to replace frames originally stored in the physical cell group to increase the success rate of decoding the frames later.

It should be noted that each step in fig. 12 to 16 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods of fig. 12 to 16 may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.

In summary, the decoding method, the memory storage device and the memory control circuit unit according to the exemplary embodiments of the present invention can continuously update and generate the first error estimation information corresponding to the specific physical cell group and enhance the first error estimation information to improve the decoding success rate of the target data frame and/or the non-target data frame in the physical cell group. In addition, by alternately performing single frame decoding on the target data frame and the non-target data frame in the same physical cell group and updating the first error assessment information and enhancing the first error assessment information according to the decoding result, the decoding success rate of the single frame decoding performed subsequently can be improved. Furthermore, the reliability information used in the subsequent decoding operation performed on the target data frame is adjusted by reflecting the enhanced first error assessment information of the target data frame, so that the decoding success rate of the target data frame can be improved, and the efficiency and the accuracy of the reading operation of the memory storage device can be further improved.

Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention. Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, the decoding method comprising:

sending a first reading instruction sequence, wherein the first reading instruction sequence indicates that a first entity unit in the plurality of entity units is read, and the first entity unit belongs to an entity unit group;

Performing a first single frame decoding on a first data frame read from the first physical unit;

in response to the decoding failure of the first single frame, obtaining first soft bit information corresponding to the first data frame, and sending a plurality of second read instruction sequences, wherein the plurality of second read instruction sequences respectively indicate to read a plurality of second entity units other than the first entity unit in the entity unit group;

performing a second single frame decoding on a plurality of second data frames read from the plurality of second entity units, respectively;

performing exclusive or (XOR) operation on each entity unit of the entity unit group after the first single frame decoding or the second single frame decoding, so as to obtain first error evaluation information corresponding to the entity unit group;

generating enhanced first error assessment information according to the first error assessment information; and

and performing third single frame decoding on the first data frame according to the enhanced first error assessment information and the first reliability information corresponding to the first entity unit.

2. The decoding method of claim 1, wherein the first error assessment information comprises a plurality of bits, and the plurality of bits each have a first value or a second value, wherein the step of generating the enhanced first error assessment information based on the first error assessment information comprises:

One or more target first bits of one or more first bits of the plurality of bits of the first error assessment information having a first value are adjusted to a second value to obtain the enhanced first error assessment information.

3. The decoding method of claim 2, wherein the step of adjusting the one or more target first bits of the one or more first bits of the plurality of bits of the first error assessment information having the first value to the second value comprises:

the one or more target first bits are randomly selected among the one or more first bits to adjust the one or more selected target first bits to the second value.

4. The decoding method of claim 1 wherein the step of performing the first single frame decoding on the first data frame read from the first physical unit comprises: the first single frame decoding is performed on the first data frame via a low density parity check code algorithm using the first reliability information corresponding to the first physical unit.

5. The decoding method of claim 4, wherein the method further comprises:

Obtaining a decoded third data frame in response to successful decoding of the second single frame corresponding to the third data frame of the plurality of second data frames, wherein the third data frame corresponds to a third physical unit of the plurality of second physical units;

storing the decoded third data frame to another third entity unit of the plurality of entity units, adding the another third entity unit to the entity unit group to replace the third entity unit of the entity unit group;

obtaining fourth soft bit information corresponding to a fourth data frame of the plurality of second data frames in response to the second single frame decoding failure corresponding to the fourth data frame, wherein the fourth data frame corresponds to a fourth physical unit of the plurality of second physical units,

wherein generating the enhanced first error assessment information based on the first error assessment information comprises:

acquiring the first soft bit information corresponding to the first data frame;

obtaining the one or more fourth soft bit information corresponding to the one or more fourth data frames respectively; and

And adjusting the first error assessment information to be the enhanced first error assessment information according to the first soft bit information and the one or more fourth soft bit information, wherein the number of one or more first bits in the enhanced first error assessment information is smaller than the number of one or more first bits in the first error assessment information, and the value of each first bit is a first value.

6. The decoding method of claim 5, wherein adjusting the first error estimate information to the enhanced first error estimate information based on the first soft bit information and the one or more fourth soft bit information comprises:

performing an OR operation on the one OR more fourth soft bit information to obtain a first vector;

performing an inverse (NOT) operation on the first soft bit information to obtain inverse first soft bit information;

performing an AND operation on the inverse first soft bit information AND the first vector to obtain a second vector; and

performing a NOT operation on the second vector to obtain an inverse second vector, and using the inverse second vector as a mask corresponding to the first error assessment information to adjust the first error assessment information to the enhanced first error assessment information.

7. The decoding method of claim 6 wherein the step of using the inverse second vector as the mask for the first error assessment information to adjust the first error assessment information to the enhanced first error assessment information comprises:

AND performing an AND operation on the inverse second vector AND the first error assessment information to obtain the enhanced first error assessment information.

8. The decoding method of claim 4 wherein performing the third single frame decoding on the first data frame based on the enhanced first error assessment information comprises:

according to the reinforced first error assessment information, adjusting the first reliability information corresponding to the first entity unit to obtain adjusted first reliability information; and

the third single frame decoding is performed on the first data frame using the adjusted first reliability information via the low density parity check code algorithm.

9. A memory storage device, comprising:

the connection interface unit is used for being electrically connected to the host system;

a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; and

A memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

sending a first reading instruction sequence, wherein the first reading instruction sequence indicates that a first entity unit in the plurality of entity units is read, and the first entity unit belongs to a entity unit group;

10. The memory storage device of claim 9, wherein the first error assessment information comprises a plurality of bits, and the plurality of bits each have a first value or a second value, wherein generating the enhanced first error assessment information based on the first error assessment information comprises:

11. The memory storage device of claim 10, wherein the step of adjusting the one or more target first bits of the one or more first bits of the plurality of bits of the first error assessment information having the first value to the second value comprises:

12. The memory storage device of claim 9, wherein performing the first single frame decoding on the first data frame read from the first physical unit comprises: the first single frame decoding is performed on the first data frame via a low density parity check code algorithm using the first reliability information corresponding to the first physical unit.

13. The memory storage device of claim 12, wherein the memory control circuit unit is further configured to:

acquiring the first soft bit information corresponding to the first data frame;

14. The memory storage device of claim 13, wherein adjusting the first error assessment information to the enhanced first error assessment information based on the first soft bit information and the one or more fourth soft bit information comprises:

15. The memory storage device of claim 14, wherein the step of using the inverse second vector as the mask for the first error assessment information to adjust the first error assessment information to the enhanced first error assessment information comprises:

16. The memory storage device of claim 12, wherein performing the third single-frame decoding on the first data frame based on the enhanced first error assessment information comprises:

17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, the memory control circuit unit comprising:

the host interface is used for being electrically connected to a host system;

a memory interface electrically connected to the rewritable non-volatile memory module;

a decoding circuit; and

a memory management circuit electrically connected to the host interface, the memory interface and the decoding circuit,

wherein the memory management circuit is to:

Instruct the decoding circuit to perform a first single frame decoding on a first data frame read from the first physical unit;

instruct the decoding circuit to perform second single frame decoding on the plurality of second data frames read from the plurality of second entity units, respectively;

the decoding circuit is instructed to perform a third single frame decoding on the first data frame according to the enhanced first error assessment information and the first reliability information corresponding to the first physical unit.

18. The memory control circuit unit of claim 17, wherein the first error assessment information comprises a plurality of bits, and the plurality of bits each have a first value or a second value, wherein generating the enhanced first error assessment information based on the first error assessment information comprises:

19. The memory control circuit unit of claim 18, wherein adjusting the one or more target first bits of the one or more first bits of the plurality of bits of the first error assessment information having the first value to the second value comprises:

20. The memory control circuit unit of claim 17, wherein performing the first single frame decoding on the first data frame read from the first physical unit comprises: the first single frame decoding is performed on the first data frame via a low density parity check code algorithm using the first reliability information corresponding to the first physical unit.

21. The memory control circuit unit of claim 20, wherein the memory management circuit is further configured to:

acquiring the first soft bit information corresponding to the first data frame;

22. The memory control circuit unit of claim 21, wherein adjusting the first error assessment information to the enhanced first error assessment information based on the first soft bit information and the one or more fourth soft bit information comprises:

23. The memory control circuit unit of claim 22, wherein the step of using the inverse second vector as the mask for the first error assessment information to adjust the first error assessment information to the enhanced first error assessment information comprises:

24. The memory control circuit unit of claim 20, wherein performing the third single-frame decoding on the first data frame based on the enhanced first error assessment information comprises:

adjusting the first reliability information corresponding to the first entity unit according to the enhanced first error assessment information via the memory management circuit to obtain adjusted first reliability information; and

the decoding circuitry is instructed to perform the third single frame decoding on the first data frame using the adjusted first reliability information via the low density parity check code algorithm.