CN117785493B

CN117785493B - Hardware resource access method and device of embedded system and server

Info

Publication number: CN117785493B
Application number: CN202410223200.7A
Authority: CN
Inventors: 刘宝阳; 马文凯; 高明
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-02-28
Filing date: 2024-02-28
Publication date: 2024-05-07
Anticipated expiration: 2044-02-28
Also published as: CN117785493A

Abstract

The embodiment of the application provides a method, a device and a server for accessing hardware resources of an embedded system, wherein the method comprises the following steps: acquiring a target IO interface identifier corresponding to the IO hardware resource to be accessed, wherein the target IO interface identifier is used for identifying the position of a target IO interface connected to the IO hardware resource to be accessed in an IO interface set of a preset type; determining a target virtual address corresponding to the IO hardware resource to be accessed based on a base address of a target virtual address space and a target IO interface identifier, wherein the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected by the IO interface set to an object space; and executing access operation on the target physical address corresponding to the target virtual address to access the target IO hardware resource corresponding to the target physical address. By the embodiment, the problem that the utilization rate of hardware resources is low in the hardware resource access method of the embedded system in the related technology is solved.

Description

Hardware resource access method and device of embedded system and server

Technical Field

The present invention relates to the field of computers, and in particular, to a method, an apparatus, and a server for accessing hardware resources of an embedded system.

Background

In the related art, an embedded operating system may be introduced to manage and schedule processor hardware resources, so as to achieve efficient coordination of the embedded processor hardware resources. In order to facilitate the use of the processor hardware resources by the user, in some embedded operating systems, the hardware devices may be abstracted into device files uniformly, and the access to the device files is the access to the processor hardware resources, so that the access to the processor hardware resources by the embedded operating system may be more convenient.

However, embedded operating systems have their own features, with high frequency access to IO (Input/Output) hardware resources being the most significant feature. In the application scenario of high-frequency access, the abstraction of the hardware device into the device file brings the simplicity of access, and simultaneously occupies a large amount of system overhead, so that the utilization rate of the computing resources of the embedded processor (namely, the hardware resources of the embedded system) is obviously reduced.

Therefore, the hardware resource access method of the embedded system in the related art has the problem of low utilization rate of hardware resources.

Disclosure of Invention

The embodiment of the application provides a method, a device and a server for accessing hardware resources of an embedded system, which at least solve the problem that the utilization rate of hardware resources is low in the method for accessing the hardware resources of the embedded system in the related technology.

According to one embodiment of the present application, there is provided a hardware resource access method of an embedded system, including: acquiring a target IO interface identifier corresponding to an IO hardware resource to be accessed, wherein the target IO interface identifier is used for identifying the position of a target IO interface connected to the IO hardware resource to be accessed in an IO interface set of a preset type; determining a target virtual address corresponding to the IO hardware resource to be accessed based on a base address of a target virtual address space and the target IO interface identifier, wherein the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected by the IO interface set to an object space; and executing access operation on the target physical address corresponding to the target virtual address to access the target IO hardware resource corresponding to the target physical address.

According to still another embodiment of the present application, there is provided a hardware resource access device of an embedded system, including: the system comprises an acquisition unit, a storage unit and a storage unit, wherein the acquisition unit is used for acquiring a target IO interface identifier corresponding to an IO hardware resource to be accessed, wherein the target IO interface identifier is used for identifying the position of a target IO interface connected to the IO hardware resource to be accessed in an IO interface set of a preset type; the determining unit is used for determining a target virtual address corresponding to the IO hardware resource to be accessed based on a base address of a target virtual address space and the target IO interface identifier, wherein the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected with the IO interface set to an object space; and the first execution unit is used for executing access operation on the target physical address corresponding to the target virtual address so as to access the target IO hardware resource corresponding to the target physical address.

According to still another embodiment of the present application, there is also provided a server including: the baseboard management controller is connected with the IO hardware resources through a preset type input/output IO interface set, wherein the baseboard management controller is used for executing the steps in any one of the method embodiments.

According to a further embodiment of the application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the application there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to the embodiment of the application, when the target IO interface identification corresponding to the IO hardware resource to be accessed is obtained, the target virtual address corresponding to the IO hardware resource to be accessed is determined based on the base address of the target virtual address space and the target IO interface identification, wherein the target virtual address space is a virtual address space obtained by mapping the physical address of the IO hardware resource connected by the IO interface set to the object space; and executing access operation on the target physical address corresponding to the target virtual address to access the target IO hardware resource corresponding to the target physical address, so that corresponding hardware operation can be executed on the accessed target IO hardware resource. Here, the call function interface of the device file for accessing the IO hardware resource is abandoned, the physical address of the IO hardware resource is mapped to the virtual address space of the user space (application layer user space), the application layer directly accesses the virtual address space of the mapped user space, the access address is actually the physical address space of the IO hardware resource, the access to the physical address of the IO hardware resource is realized, and the device file access method is not adopted, so that the system scheduling overhead can be effectively reduced, the overall utilization rate of a processor core is improved, and the problem that the hardware resource access method of the embedded system in the related technology has low utilization rate of the hardware resource is solved. In addition, the time cost of IO hardware resource access can be greatly reduced, the access frequency is improved, the access performance is improved, and further the aims of achieving the effect of IO hardware resource high-frequency access and improving the computing performance of a processor are fulfilled.

Drawings

FIG. 1 is a schematic diagram of a hardware environment of a method for accessing hardware resources of an embedded system according to an embodiment of the present application;

FIG. 2 is a flow chart of a method for accessing hardware resources of an embedded system according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a hardware resource access method of an embedded system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another method of hardware resource access for an embedded system according to an embodiment of the present application;

FIG. 5 is a block diagram of a hardware resource access device of an embedded system according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an alternative server architecture according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an alternative BMC chip according to an embodiment of the application;

fig. 8 is a block diagram of a computer system of an electronic device according to an embodiment of the application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be executed in a server apparatus or similar computing device. Taking the operation on a server device as an example, fig. 1 is a schematic diagram of a hardware environment of a hardware resource access method of an embedded system according to an embodiment of the present application. As shown in fig. 1, the server device may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing means such as a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those of ordinary skill in the art that the architecture shown in fig. 1 is merely illustrative and is not intended to limit the architecture of the server apparatus described above. For example, the server device may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store computer programs, such as software programs and modules of application software, such as computer programs corresponding to the hardware resource access method of the embedded system in the embodiment of the present application, and the processor 102 executes the computer programs stored in the memory 104 to perform various functional applications and data processing, that is, implement the above-mentioned methods. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located with respect to the processor 102, which may be connected to the server device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

Taking a server device to execute the method for accessing a hardware resource of an embedded system in this embodiment as an example, fig. 2 is a schematic flow chart of a method for accessing a hardware resource of an embedded system according to an embodiment of the present application, as shown in fig. 2, the flow chart includes the following steps:

Step S202, a target IO interface identifier corresponding to the IO hardware resource to be accessed is obtained, wherein the target IO interface identifier is used for identifying the position of a target IO interface connected to the IO hardware resource to be accessed in an IO interface set in a preset type of IO interface set.

The method for accessing the hardware resources of the embedded system in the embodiment can be applied to the scene of accessing the hardware resources of the embedded system, wherein the embedded system is a special computer system which is completely embedded in a controlled device and is designed for a specific application, one application example of the embedded system is an embedded processor, and along with the rapid development of fields such as cloud computing, artificial intelligence, big data, industrial internet, 5G (5 th Generation Mobile Communications Technology, fifth generation mobile communication technology) and the like, the embedded processor becomes an important computing unit, and the application range of the embedded system is wider and wider.

In order to realize efficient collaboration of hardware resources of an embedded processor, an embedded operating system may be introduced to manage and schedule hardware resources of the processor, for example, a Linux system (collectively referred to as GNU/Linux, which is a set of freely-propagating Unix-like operating systems) is an operating system based on POSIX (Portable Operating SYSTEM INTERFACE) and Unix multi-users, multi-tasks, support multi-threads and multi-CPUs (Central Processing Unit, central processing unit, as an operation and control core of a computer system, and CPU is a final execution unit for information processing and program running), and can run main Unix tool software, application programs and network protocols, and is widely applied in the embedded field, so Linux becomes an optional operating system of the embedded processor.

In related art, in some embedded operating systems (for example, linux systems), in order to facilitate users to use processor hardware resources, hardware devices are abstracted into device files in a unified manner, and access to the device files is that to the processor hardware resources, which is to say, the access to the processor hardware resources by the embedded operating system becomes simple. However, embedded operating systems have their own features, with high frequency access to IO hardware resources being a significant feature. Under the application scene of high-frequency access, the hardware equipment is abstracted into equipment files to bring about access simplicity, and meanwhile, the defects are brought about, and the method mainly comprises the following steps: firstly, high-frequency access equipment files occupy a large amount of system overhead, and the computing resource utilization rate of the embedded processor is obviously reduced; secondly, a large amount of system overhead is occupied, so that IO hardware resource access is slow, the frequency of high-frequency access is reduced, and the access performance is reduced.

In order to at least partially solve the above problems, ensure that various types of services of the embedded system normally run, and improve the core utilization rate of the embedded processor at the same time, the embodiment provides a hardware resource access method of the embedded system, starting from the embedded system level, abandoning a call function interface of accessing IO hardware resources by a device file, mapping the physical address of the IO hardware resources to a virtual address space of a user space instead, directly accessing the virtual address space of the mapped user space by an application layer, wherein the access address is actually the physical address space of the IO hardware resources, realizing the access to the physical address of the IO hardware resources, and effectively reducing the system scheduling overhead and improving the overall utilization rate of the processor core because the device file access method is not adopted. In addition, the time cost of IO hardware resource access can be greatly reduced, the access frequency of IO hardware resources is improved, the access performance is improved, the effect of IO hardware resource high-frequency access is further achieved, and the aim of improving the computing performance of a processor is fulfilled.

The server device may have a control component thereon, such as a BMC (Baseboard Management Controller, baseboard management controller, server management unit) or the like, that can manage the processor hardware resources by accessing the processor hardware resources. The control unit may be connected to the IO hardware resource through a preset type of IO interface set to implement IO access to the hardware resource, where the preset type of IO interface is an IO interface allowed to be used between the control unit and the processor hardware resource, for example, GPIO (General-purpose input/output), the GPIO functions like P0-P3 of 8051, its PINs may be used by a user under free control of a program, and PIN PINs (i.e., PINs) may be used as General input (GPI) or General output (GPO) or General input and output (GPIO). The IO hardware resource can be CPLD (Complex Programmable Logic Device, complex programmable logic device, which is the abbreviation of Complex PLD), and is a Complex logic element compared with PLD.

Alternatively, the IO access in this embodiment may be applied to a scenario of high-frequency access to a hardware resource, for example, a scenario of accessing the IO hardware resource through a GPIO Analog JTAG protocol, where the JTAG protocol is an interface (Joint Test Action Group, joint test working group), and is an international standard test protocol (IEEE 1149.1 compatible) mainly used for on-chip testing, but not limited thereto, and may also be applied to a variety of protocol scenarios such as a GPIO Analog I2C (a simple, two-wire synchronous serial bus protocol), an SGPIO (SERIAL GENERAL-Purpose Input/Output), or other processor hardware resources that require high-frequency access, such as an ADC (Analog-to-Digital Converter, analog-to-digital converter, which is a hardware logic or device for converting a continuous signal in Analog form into a discrete signal in digital form, and the like.

It should be noted that, in order to describe the hardware resource access method of the embedded system in this embodiment conveniently, in some examples of this embodiment, an application scenario (which may be implemented by invoking a function interface) of the IO hardware resource high-frequency access of the embedded Linux system is taken as an example for explanation, but this should not cause undue limitation to the hardware resource access method of the embedded system in this embodiment, and the hardware resource access method of the embedded system in this embodiment is also applicable to applications of the IO hardware resource high-frequency access of other embedded operating systems.

For example, after the server is powered on and runs, in a specific application scenario, a user needs to access a specific IO hardware resource through the out-of-band BMC to execute a specified operation on the IO hardware resource, and the BMC may access the specific IO hardware resource through the GPIO analog JTAG protocol. The JTAG protocol typically employs a frequency of 10MHz with a period of 100ns, and in extreme cases, such as JTAG CLK (clock signal) clock simulation, the GPIO high-low level inversion (from 1 to 0 or from 0 to 1) time is 100ns (10 MHz corresponds to a period of 100 ns), requiring BMC to access the GPIO at high frequency.

In this embodiment, the control unit may obtain a target IO interface identifier corresponding to the IO hardware resource to be accessed, where the target IO interface identifier is used to identify a position, in the IO interface set, of a target IO interface to which the IO hardware resource to be accessed is connected, that is, a target IO interface corresponding to the IO hardware resource to be accessed, where the pin number of the target IO interface, for example, a pin number of the GPIO. Illustratively, the IO hardware resource to be accessed may be a CPLD.

Step S204, determining a target virtual address corresponding to the IO hardware resource to be accessed based on the base address of the target virtual address space and the target IO interface identification, wherein the target virtual address space is a virtual address space obtained by mapping the physical address of the IO hardware resource connected by the IO interface set to the object space.

In this embodiment, the call function interface of the device file for accessing the IO hardware resource is omitted, the call function interface is modified to map the physical address of the IO hardware resource to the virtual address space of the user space, the application layer directly accesses the virtual address space of the mapped user space, the access address is actually the physical address space of the IO hardware resource, and the access to the physical address of the IO hardware resource is realized, so that the effect of high-frequency access to the IO hardware resource of the embedded system is realized.

For the IO hardware resources to be accessed, a target virtual address corresponding to the IO hardware resources to be accessed in a target virtual address space can be determined based on the target IO interface identification, wherein the target virtual address space is a virtual address space obtained by mapping the physical address of the IO hardware resources connected by the IO interface set to an object space, and the object space can be an application layer object space.

Alternatively, in order to improve the convenience of virtual address determination, a base address of a target virtual address space may be set, and a target virtual address corresponding to the IO hardware resource to be accessed may be determined based on the base address of the target virtual address space and the target IO interface identifier, for example, an offset corresponding to the target IO interface identifier may be first determined, so that the target virtual address corresponding to the IO hardware resource to be accessed is determined based on the base address of the target virtual address space and the determined offset.

In step S206, an access operation is performed on the target physical address corresponding to the target virtual address to access the target IO hardware resource corresponding to the target physical address.

Based on the target virtual address, an access operation may be performed on a target physical address corresponding to the target virtual address, thereby accessing a target IO hardware resource corresponding to the target physical address, for which a specific operation, e.g., FW (firmware) upgrade, may be performed. Here, the application layer directly accesses the mapped virtual address space of the application layer user space, and the access address is actually the physical address space of the IO hardware resource, so that the access to the physical address of the IO hardware resource is realized.

In this embodiment, because access to the physical address space of the IO hardware resource is achieved based on the virtual address (i.e., the physical address space after address mapping is directly accessed through address mapping), compared with a mode of accessing the IO hardware resource through a device file, system scheduling overhead can be effectively reduced, overall utilization rate of a processor core is improved, time overhead of accessing the IO hardware resource is greatly reduced, access frequency is improved, access performance is improved, and the purposes of high-frequency access effect of the IO hardware resource and calculation performance of the processor can be achieved.

It should be noted that, through the address mapping manner, the interface of the embedded system for accessing the IO hardware resource shields specific implementation details, and an upper layer application developer does not need to pay attention to the implementation scheme for specifically accessing the IO hardware resource, so that the cleanliness and uniformity of codes can be ensured to a certain extent, and modularization is realized.

Through the steps, the target IO interface identification corresponding to the IO hardware resource to be accessed is obtained, wherein the target IO interface identification is used for identifying the position of a target IO interface connected to the IO hardware resource to be accessed in an IO interface set in the preset type of IO interface set; determining a target virtual address corresponding to the IO hardware resource to be accessed based on a base address of a target virtual address space and a target IO interface identifier, wherein the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected by the IO interface set to an object space; and executing access operation on the target physical address corresponding to the target virtual address to access the target IO hardware resource corresponding to the target physical address, thereby solving the problem of low utilization rate of hardware resources in the hardware resource access method of the embedded system in the related technology and improving the utilization rate of the hardware resources.

In an exemplary embodiment, before acquiring the target IO interface identifier corresponding to the IO hardware resource to be accessed, the method further includes:

s11, calling a physical address mapping initialization function to execute initialization operation through the physical address mapping initialization function.

In order to map the physical address to the virtual address, a target virtual address space needs to be acquired first, and the target virtual address space may be obtained by mapping the set of physical addresses of the IO hardware resources connected to the set of IO interfaces into one virtual address space. In this regard, a first interface function, i.e., a physical address mapping initialization function for mapping physical addresses of the IO hardware resources to the object space to initialize a mapping relationship between the physical addresses and virtual addresses in the virtual address space, may be defined, and the first interface function may be a GPIO physical address mapping initialization function (analog_init_gpio_map). By calling the first interface function, the initialization operation may be performed by the first interface function.

Optionally, the initializing operation is configured to map the set of physical addresses of the IO hardware resources connected to the set of IO interfaces into a virtual address space, which may include the following steps: opening a designated device file, wherein the designated device file is a device file abstracted from IO hardware resources connected with the IO interface set; and mapping the set of physical addresses of the IO hardware resources connected with the IO interface set in the designated equipment file into a virtual address space to obtain a target virtual address space.

For example, when the initialization operation is performed using the GPIO physical address mapping initialization function, the device file may be opened/dev/mem first, and a virtual address space is mapped by the GPIO physical address map, where the base address of the virtual address space is gpio_base_map, and access to the virtual address space may implement access to the GPIO physical address space, that is, access to GPIO hardware resources.

By the embodiment, the mapping relation between the physical address and the virtual address in the virtual address space is initialized through the defined physical address mapping initialization function, so that the convenience of generating the virtual address space can be improved.

In one exemplary embodiment, after performing the access operation on the target physical address corresponding to the target virtual address, the method further includes:

S21, calling a physical address mapping exit function to execute a mapping exit operation through the called physical address mapping exit function.

In some scenarios, it is desirable to exit the mapped virtual address space to avoid wastage of the virtual address space. In this regard, a second interface function, i.e., a physical address map exit function, for removing a mapping relationship between a physical address and a virtual address in a virtual address space may be defined, and the second interface function may be a GPIO physical address map exit function (analog_exit_gpio_map). By calling the second interface function, the mapping exit operation may be performed by the second interface function.

Optionally, the mapping exit operation is used to exit the virtual address space to which the physical address is mapped, which may include the steps of: and executing the reflection operation on the target virtual address space, and closing the designated device file.

By the embodiment, the mapping exit operation is executed through the physical address mapping exit function, so that the mapping relation between the physical address and the virtual address in the virtual address space can be removed, and the occupation of hardware resources of the embedded system is reduced.

In one exemplary embodiment, performing a de-mapping operation on a target virtual address space includes:

S31, performing the reflection operation on the target virtual address space according to the base address of the target virtual address space.

In this embodiment, in order to improve the convenience and comprehensiveness of executing the demapping operation in the virtual address space, the demapping operation may be performed on the virtual address space according to the base address of the virtual address space. Correspondingly, the input to the physical address mapping exit function may be the base address of the virtual address space. Correspondingly, the manner in which the demapping operation is performed on the target virtual address space may be: and executing the reflection operation on the target virtual address space according to the base address of the target virtual address space.

For example, the GPIO physical address mapping exit function performs the inverse of the initialization function by first inversely mapping (unmap) the gpio_base_map virtual address space and then closing/dev/mem device files.

According to the embodiment, the reflective operation is performed on the virtual address space according to the base address of the virtual address space, so that the convenience and the comprehensiveness of executing the reflective operation in the virtual address space can be improved.

In one exemplary embodiment, determining a target virtual address corresponding to an IO hardware resource to be accessed based on a base address of a target virtual address space and a target IO interface identification includes:

s41, performing summation operation on the quotient of the base address of the target virtual address space and the target IO interface identification divided by the preset number to obtain a target initial address;

s42, determining a target virtual address corresponding to the IO hardware resource to be accessed according to the target starting address and the remainder of dividing the target IO interface identification by the preset number.

In this embodiment, physical addresses corresponding to the IO interfaces in the IO interface set are divided into physical address spaces according to a preset number, where the physical address spaces corresponding to the IO interface set may be distributed according to a group, and each physical address space corresponds to a preset number of bits, and may represent a preset number of IO interfaces. The physical address space where the target physical address corresponding to the target IO identifier is located is the target physical address space. In order to determine the starting address of the mapping of the target physical address space to the target virtual address space, a summation operation may be performed on the quotient of the base address of the target virtual address space and the target IO interface identifier divided by a preset number, to obtain the target starting address.

The determined target starting address is a starting address of mapping the target physical address space to the target virtual address space, and in order to determine the virtual address of the specific hardware resource, the target virtual address corresponding to the IO hardware resource to be accessed can be determined according to the target starting address and the remainder of dividing the target IO interface identifier by the preset number.

For example, the physical address spaces corresponding to GPIOs are generally distributed according to a group, and each physical address space corresponds to a preset number of bits (bits), which may represent a preset number of GPIOs. And using the virtual address space base address gpio_base_map mapped by the GPIO address as a GPIO access base address, calculating the relative address offset of the hardware resource corresponding to the GPIO pin through gpionumber, and obtaining the address space position of the IO hardware resource corresponding to gpionumber through gpio_base_map+offset, and completing the access to the IO hardware resource corresponding to gpionumber through the access operation of the address space.

Here, a calculation formula corresponding to gpionumber for calculating the corresponding hardware resource relative address offset is shown in formula (1):

gpio_offset= gpionumber/preset number (1)

Through the formula (1), the hardware resource relative address or offset address corresponding to the GPIO where gpionumber is located can be calculated.

The corresponding hardware resource to be accessed gpionumber can find the corresponding bit (bit) in this address space gpio_base_map+gpio_offset (i.e., gpionumber corresponding bit, gpio_bit_in_offset), and the calculation formula of the specific bit position is shown in formula (2):

gpio_bit_in_offset= gpionumber% preset quantity (2)

According to the embodiment, the starting address of mapping the physical address space to the virtual address space is determined based on the base address and the interface identifier of the virtual address space, so that the virtual address corresponding to the IO hardware resource to be accessed is determined, and the efficiency of virtual address determination can be improved.

In one exemplary embodiment, determining a target virtual address corresponding to the IO hardware resource to be accessed according to the target starting address and a remainder of dividing the target IO interface identifier by a preset number includes:

s51, performing bitwise and operation on a shift result obtained by dividing the target IO interface identification by a remainder of a preset number and performing left shift and a target starting address to obtain a target virtual address corresponding to the IO hardware resource to be accessed.

When determining the target virtual address corresponding to the IO hardware resource to be accessed, the target IO interface identification can be divided by the remainder of the preset number to perform one-bit left shift, the obtained shift result can be subjected to bitwise AND operation with the target starting address, and the obtained result is the target virtual address corresponding to the IO hardware resource to be accessed.

For example, after obtaining the hardware resource offset address (gpio_offset) and the corresponding bit (gpio_bit_in_offset) corresponding to the GPIO where gpionumber is located, the access of the hardware resource corresponding to the IO of gpionumber is finally: the (gpio_base_map+gpio_offset) address takes the value gValue & (1 < < gpio_bit_in_offset), where & is bitwise AND operation.

According to the embodiment, the shift result obtained by dividing the interface identifier by the remainder of the preset number and performing left shift and operation on the shift result and the start address are performed to determine the virtual address corresponding to the IO hardware resource to be accessed, so that the accuracy of virtual address determination can be improved.

In an exemplary embodiment, the above-mentioned preset number may be set as required, for example, the preset number may be 32, that is, each physical space corresponds to 32 bits, for representing 32 preset types of IO interfaces. Correspondingly, when the target starting address may be obtained by performing a summation operation on a quotient of the base address of the target virtual address space and the target IO interface identifier divided by 32, the target virtual address corresponding to the IO hardware resource to be accessed may be obtained by performing a bit-wise and operation on a shift result obtained by performing a left shift on the remainder of the target IO interface identifier divided by 32 and the target starting address.

For example, the physical address spaces corresponding to the GPIOs are distributed in groups, and each physical address space corresponds to 32 bits, which may represent 32 GPIOs, and four groups of 8 GPIOs. The calculation formula of the hardware resource relative address or offset address corresponding to the GPIO where gpionumber is located is gpio_offset= gpionumber/32, and the calculation formula of the bit corresponding to GPIO umber is: gpio_bit_in_offset= gpionumber%32.

Through the embodiment, the physical address spaces corresponding to the IO interface set are distributed according to the groups, each physical address space corresponds to 32 bits, the representation form (32 is 2 ⁵) of the physical address can be adapted, and convenience in determining the virtual address is improved.

In one exemplary embodiment, obtaining a target IO interface identifier corresponding to an IO hardware resource to be accessed includes:

s61, acquiring a target IO interface identifier transmitted by calling a preset access function interface.

In order to improve the convenience of physical address access, an access interface, that is, a preset access function interface, may be preset, where the preset access function interface is used to access a physical address corresponding to an IO interface identified by an IO interface identifier that is input by the preset access function interface, so as to perform a preset interface operation on the IO interface identified by the IO interface identifier that is input by the preset access function interface, for example, access a corresponding IO hardware resource.

Correspondingly, the obtaining the target IO interface identifier corresponding to the IO hardware resource to be accessed may be: and acquiring a target IO interface identifier transmitted by calling a preset access function interface. Here, the number of the preset access function interfaces may be one or more, which may be configured according to the operation type of the preset interface operation to be performed, and for a scenario in which the number of the preset access function interfaces is a plurality, different preset access function interfaces may be used to implement different functions, for example, to set an interface mode, and to specify an operation corresponding to the set interface mode.

According to the embodiment, the virtual address is accessed by transmitting the IO interface identification corresponding to the IO hardware resource to be accessed into the preset access function interface, so that the convenience of accessing the virtual address can be improved.

In one exemplary embodiment, obtaining a target IO interface identifier that is imported by calling a preset access function interface includes:

S71, acquiring a target IO interface identifier which is transmitted by calling the first access function interface.

In this embodiment, a first access function interface may be preset, where the first access function interface is configured to access a physical address corresponding to an IO interface identified by an IO interface identifier that is transmitted by the first access function interface, so as to set the IO interface identified by the IO interface identifier that is transmitted by the first access function interface as an input mode, and in the input mode, a Value (Value, high or low, 1 or 0) of the IO interface may be further obtained. Correspondingly, the obtaining the target IO interface identifier that is transferred by calling the preset access function interface may include: and acquiring a target IO interface identifier which is transmitted by calling the first access function interface.

For example, a GPIO access function interface analog gpio_gpio_set_input may be defined for setting GPIO to input mode.

Through the embodiment, the access function interface for setting the IO interface to be the input mode is preset, so that subsequent interface operation can be conveniently executed, and convenience in information acquisition is improved.

s81, acquiring a target IO interface identifier which is transmitted by calling the second access function interface.

In this embodiment, a second access function interface may be preset, where the second access function interface is configured to access a physical address corresponding to an IO interface identified by an IO interface identifier that is transmitted by the second access function interface, so as to obtain an interface value of the IO interface identified by the IO interface identifier that is transmitted by the second access function interface. Correspondingly, the obtaining the target IO interface identifier that is transferred by calling the preset access function interface may include: and acquiring a target IO interface identifier which is transmitted by calling the second access function interface.

For example, a GPIO access function interface analog_gpio_get_value may be defined for obtaining a GPIO Value.

Through the embodiment, the access function interface for acquiring the value of the IO interface is preset, so that the acquired value of the IO interface can be conveniently acquired, and the convenience of information acquisition is improved.

s91, acquiring a target IO interface identifier which is transmitted by calling a third access function interface.

In this embodiment, a third access function interface may be preset, where the third access function interface is configured to access a physical address corresponding to an IO interface identified by an IO interface identifier that is transmitted by the third access function interface, so as to set an IO interface identified by an IO interface identifier that is transmitted by the third access function interface to an output mode. The value of the IO interface may be further set in the output mode. Correspondingly, the obtaining the target IO interface identifier that is transferred by calling the preset access function interface may include: and acquiring a target IO interface identifier which is transmitted by calling the third access function interface.

For example, a GPIO access function interface analog gpio_gpio_set_output may be defined for setting GPIO to output mode.

Through the embodiment, the subsequent interface operation can be conveniently executed by presetting the access function interface for setting the IO interface to be the output input mode, and the convenience of information processing is improved.

In an exemplary embodiment, a fourth access function interface and a fifth access function interface may be preset, where the fourth access function interface is configured to access a physical address corresponding to an IO interface identified by an IO interface identifier that is input to the fourth access function interface, so as to set an IO interface identified by an IO interface identifier that is input to the fourth access function interface to a first value, and the fifth access function interface is configured to access a physical address corresponding to an IO interface identified by an IO interface identifier that is input to the fifth access function interface, so as to set an IO interface identified by an IO interface identifier that is input to the fifth access function interface to a second value, where the first value and the second value are different values.

For example, a GPIO access function interface may be defined: the analog_gpio_set_high and analog_gpio_set_low are used to set the GPIO Value to High (High level) in the output mode, and to set the GPIO Value to Low (Low level) in the output mode, respectively.

Here, the function parameters of the aforementioned 5 GPIO access function interfaces analog_gpio_set_input, analog_gpio_get_value, analog_gpio_set_ output, analog _gpio_set_high, and analog_gpio_set_low may be gpionumber, which represent pin number of the corresponding GPIO, as shown in fig. 3. In a specific implementation, gpionumber corresponds to an address space position of the IO hardware resource, and the access to the IO hardware resource corresponding to gpionumber is completed through an access operation of the address space, which includes setting a GPIO mode to input and output, obtaining a GPIO Value, setting a GPIO Value high/low (1/0), and other access operations. Here, the interface of the embedded system for accessing the IO hardware resource is highly unified, and the upper layer application developer is more convenient to call and use.

In this embodiment, the bus waveform signal of the clock bus may be generated by at least partially simulating in the access function interface, and correspondingly, the method further includes:

S101, in the condition that the target IO interface is in an output mode, the following steps are circularly executed to simulate bus waveform signals with specified frequencies: taking the target IO interface identification as an entry to call a fourth access function interface; a sleep target duration; taking the target IO interface identification as an entry call fifth access function interface; the target duration is re-dormant.

In order to simulate a bus waveform signal of a specified frequency, the following steps are cyclically performed with the target IO interface in an output mode: taking the target IO interface identification as an entry to call a fourth access function interface so as to set the target IO interface as a first value; then, a sleep target time length, where the target time length is a period time length matched with a specified frequency, which may be half of one signal period of the bus waveform signal to be simulated; then, taking the target IO interface identification as an entry to call a fifth access function interface so as to set the target IO interface as a second value; finally, the target duration is dormant again, as shown in fig. 4.

For example, when the BMC needs to perform High-frequency access to the GPIO, the GPIO High-Low level 10MHz frequency inversion (i.e., by setting the GPIO High or Low bus to be 1 or 0) can be implemented through the GPIO function interfaces analog_gpio_set_high and analog_gpio_set_low High-frequency call described above, so as to achieve the effect of simulating the JTAG CLK clock bus.

In performing JTAG CLK clock simulation, the embedded Linux application may call access function interfaces analog_gpio_set_ output, analog _gpio_set_high and analog_gpio_set_low. The analog gpio_gpio_set_high and analog gpio_set_low are invoked every 100ns high frequency to implement GPIO high-low level high frequency inversion (from 1 to 0 or from 0 to 1), simulating a 10MHz bus waveform signal that produces the JTAG CLK clock bus, with exemplary program code as follows:

analog_gpio_set_output(gpionumber);

for (i = 0; i <= n; i++)

{

analog_gpio_set_high(gpionumber);

nanosleep(100); //sleep 100ns

analog_gpio_set_low(gpionumber);

nanosleep(100); //sleep 100ns

}

according to the embodiment, the bus waveform signal of the clock bus is simulated and generated through the preset access function interface, so that the convenience of the bus waveform signal simulation of the clock bus can be improved.

In one exemplary embodiment, the target IO interface is a GPIO interface, the target IO interface is identified as a pin number of the target IO interface, and the target IO hardware resource is a complex programmable logic device.

Correspondingly, performing an access operation on a target physical address corresponding to the target virtual address to access a target IO hardware resource corresponding to the target physical address, including:

S111, executing access operation on the target physical address corresponding to the target virtual address to access the complex programmable logic device corresponding to the target physical address to perform firmware upgrading operation of the complex programmable logic device.

In this embodiment, after the server is powered on, an access operation may be performed on the target physical address corresponding to the target virtual address to access the complex programmable logic device corresponding to the target physical address, and accessing the complex programmable logic device corresponding to the target physical address may perform a firmware upgrade operation of the complex programmable logic device.

For example, when the server is powered on to run and in a specific application scenario, and a user needs to upgrade the CPLD firmware through the out-of-band BMC, the BMC accesses the CPLD through the GPIO analog JTAG protocol to upgrade the CPLD firmware.

According to the embodiment, CPLD firmware upgrading operation is performed by accessing the CPLD through the GPIO analog JTAG protocol, so that CPLD firmware upgrading efficiency can be improved.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the embodiments of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method of the embodiments of the present application.

According to still another aspect of the embodiment of the present application, a device for accessing a hardware resource of an embedded system is provided, and the device is used for implementing the method for accessing a hardware resource of an embedded system provided in the foregoing embodiment, which is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 5 is a block diagram of a hardware resource access device of an embedded system according to an embodiment of the present application, and as shown in fig. 5, the device includes:

The obtaining unit 502 is configured to obtain a target IO interface identifier corresponding to an IO hardware resource to be accessed, where the target IO interface identifier is used to identify a position, in the IO interface set, of a target IO interface to which the IO hardware resource to be accessed is connected in the IO interface set, in the IO interface set;

A determining unit 504, configured to determine, based on a base address of a target virtual address space and a target IO interface identifier, a target virtual address corresponding to an IO hardware resource to be accessed, where the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected to the IO interface set to the object space;

the first execution unit 506 is configured to perform an access operation on a target physical address corresponding to the target virtual address, so as to access a target IO hardware resource corresponding to the target physical address.

According to the embodiment of the application, the target IO interface identification corresponding to the IO hardware resource to be accessed is obtained, wherein the target IO interface identification is used for identifying the position of the target IO interface connected to the IO hardware resource to be accessed in the IO interface set of the preset type; determining a target virtual address corresponding to the IO hardware resource to be accessed based on a base address of a target virtual address space and a target IO interface identifier, wherein the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected by the IO interface set to an object space; and executing access operation on the target physical address corresponding to the target virtual address to access the target IO hardware resource corresponding to the target physical address, thereby solving the problem of low utilization rate of hardware resources in the hardware resource access method of the embedded system in the related technology and improving the utilization rate of the hardware resources.

Optionally, the apparatus further includes: the first calling unit is used for calling a physical address mapping initialization function before acquiring a target IO interface identifier corresponding to an IO hardware resource to be accessed so as to execute the following initialization operation through the physical address mapping initialization function, wherein the physical address mapping initialization function is used for mapping the physical address of the IO hardware resource into an object space so as to initialize the mapping relation between the physical address and a virtual address in a virtual address space: the device comprises an opening unit, a storage unit and a storage unit, wherein the opening unit is used for opening a designated device file, and the designated device file is a device file which abstracts IO hardware resources connected with an IO interface set; and the mapping unit is used for mapping the set of physical addresses of the IO hardware resources connected with the IO interface set in the designated equipment file into a virtual address space to obtain a target virtual address space.

Optionally, the apparatus further includes: and a second calling unit, configured to call a physical address mapping exit function after performing an access operation on a target physical address corresponding to the target virtual address, to perform a mapping exit operation by the physical address mapping exit function, where the physical address mapping exit function is configured to remove a mapping relationship between the physical address and a virtual address in the virtual address space: and executing the reflection operation on the target virtual address space, and closing the designated device file.

Optionally, the second calling unit includes: and the first execution module is used for executing the reflection operation on the target virtual address space according to the base address of the target virtual address space.

Optionally, the determining unit includes: the second execution module is used for executing summation operation on the quotient of the base address of the target virtual address space and the target IO interface identification divided by the preset number to obtain a target initial address, wherein the physical address corresponding to the IO interface in the IO interface set is divided into physical address spaces according to the preset number, the physical address space where the target physical address corresponding to the target IO identification is located is the target physical address space, and the target initial address is the initial address of the target physical address space mapped to the target virtual address space; and the determining module is used for determining a target virtual address corresponding to the IO hardware resource to be accessed according to the target starting address and the remainder of dividing the target IO interface identification by the preset number.

Optionally, the determining module includes: and the first execution sub-module is used for performing bit-wise and operation on a shift result obtained by dividing the target IO interface identification by the remainder of the preset number and performing left shift by one bit and a target starting address to obtain a target virtual address corresponding to the IO hardware resource to be accessed.

Optionally, the second execution module includes a second execution sub-module, and the first execution sub-module includes an execution sub-unit, where the second execution sub-module is configured to perform a summation operation on a quotient of a base address of the target virtual address space and the target IO interface identifier divided by 32 to obtain a target starting address, where each physical space corresponds to 32 bits and is configured to represent 32 preset types of IO interfaces; and the execution subunit is used for performing bitwise and operation on the shift result obtained by dividing the target IO interface identification by the remainder of 32 and performing one-bit left shift and the target starting address to obtain the target virtual address corresponding to the IO hardware resource to be accessed.

Optionally, the acquiring unit includes: the system comprises an acquisition module, a preset access function interface and a control module, wherein the acquisition module is used for acquiring a target IO interface identifier transmitted by calling the preset access function interface, and the preset access function interface is used for accessing a physical address corresponding to an IO interface identified by the IO interface identifier transmitted by the preset access function interface so as to execute preset interface operation on the IO interface identified by the IO interface identifier transmitted by the preset access function interface.

Optionally, the acquiring module includes: the first obtaining sub-module is used for obtaining a target IO interface identifier transmitted by calling the first access function interface, wherein the first access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the first access function interface so as to set the IO interface identified by the IO interface identifier transmitted by the first access function interface as an input mode.

Optionally, the acquiring module includes: and the second acquisition sub-module is used for acquiring a target IO interface identifier transmitted by calling a second access function interface, wherein the second access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the second access function interface so as to acquire an interface value of the IO interface identified by the IO interface identifier transmitted by the second access function interface.

Optionally, the acquiring module includes: and the third acquisition sub-module is used for acquiring a target IO interface identifier transmitted by calling a third access function interface, wherein the third access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the third access function interface so as to set the IO interface identified by the IO interface identifier transmitted by the third access function interface as an output mode.

Optionally, the apparatus further includes: the second execution unit is used for circularly executing the following steps to simulate bus waveform signals with specified frequencies under the condition that the target IO interface is in an output mode: the target IO interface identification is used as an input parameter to call a fourth access function interface, wherein the fourth access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identification transmitted by the fourth access function interface, so that the IO interface identified by the IO interface identification transmitted by the fourth access function interface is set to be a first value; a sleep target duration, wherein the target duration is a period duration matched with a specified frequency; the target IO interface identification is used as an input parameter to call a fifth access function interface, wherein the fifth access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identification transmitted by the fifth access function interface, so that the IO interface identified by the IO interface identification transmitted by the fifth access function interface is set to be a second value, and the first value and the second value are different values; the target duration is re-dormant.

Optionally, the target IO interface is a general purpose input/output GPIO interface, the pin number of the target IO interface, and the target IO hardware resource is a complex programmable logic device; the first execution unit includes: and the third execution module is used for executing access operation on the target physical address corresponding to the target virtual address so as to access the complex programmable logic device corresponding to the target physical address to perform firmware upgrading operation of the complex programmable logic device.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; or the above modules may be located in different processors in any combination.

According to still another aspect of the embodiments of the present application, there is further provided a server, which may be a server device in any of the foregoing embodiments, as shown in fig. 6, where the server may include a baseboard management controller, and the baseboard management controller is connected to the IO hardware resource through a preset type of IO interface set, where the baseboard management controller is configured to implement the steps in any one of the foregoing method embodiments.

According to still another aspect of the embodiments of the present application, there is further provided a BMC Chip, where an example of the BMC Chip may be as shown in fig. 7, and hardware of the BMC Chip may be divided into three parts, namely, an SOC (System on Chip) sub-module, a BMC out-of-band sub-module, and a BMC in-band sub-module. The BMC chip may be used to implement steps in any of the method embodiments described above.

According to a further aspect of embodiments of the present application, there is also provided a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: various media capable of storing a computer program, such as a usb disk, a ROM (Read-Only Memory), a RAM (Random Access Memory ), a removable hard disk, a magnetic disk, or an optical disk.

According to one aspect of the present application, there is provided a computer program product comprising a computer program/instruction containing program code for executing the method shown in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section 809, and/or installed from the removable media 811. When executed by the central processor 801, the computer program performs various functions provided by embodiments of the present application. The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

Fig. 8 schematically shows a block diagram of a computer system of an electronic device for implementing an embodiment of the application. As shown in fig. 8, the computer system 800 includes a central processor 801, which can perform various appropriate actions and processes according to a program stored in a read only memory 802 or a program loaded from a storage section 808 into a random access memory 803. In the random access memory 803, various programs and data required for system operation are also stored. The central processing unit 801, the read only memory 802, and the random access memory 803 are connected to each other through a bus 804. An input/output interface 805 is also connected to the bus 804.

The following components are connected to the input/output interface 805: an input portion 806 including a keyboard, mouse, etc.; an output portion 807 including a CRT (Cathode Ray Tube), an LCD (Liquid CRYSTAL DISPLAY), and the like, and a speaker, and the like; a storage section 808 including a hard disk or the like; and a communication section 809 including a network interface card such as a local area network card, modem, or the like. The communication section 809 performs communication processing via a network such as the internet. The drive 810 is also connected to the input/output interface 805 as needed. A removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 810 as needed so that a computer program read out therefrom is mounted into the storage section 808 as needed.

In particular, the processes described in the various method flowcharts may be implemented as computer software programs according to embodiments of the application. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section 809, and/or installed from the removable media 811. The computer programs, when executed by the central processor 801, perform the various functions defined in the system of the present application.

It should be noted that, the computer system 800 of the electronic device shown in fig. 8 is only an example, and should not impose any limitation on the functions and the application scope of the embodiments of the present application.

According to a further aspect of embodiments of the present application there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device and an input/output device, where the transmission device is connected to the input/output resource pool, and the input/output device is connected to the input/output resource pool.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the embodiments of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a memory device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than what is shown or described, or they may be separately fabricated into individual integrated circuit modules, or a plurality of modules or steps in them may be fabricated into a single integrated circuit module. Thus, embodiments of the application are not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present application and is not intended to limit the embodiments of the present application, but various modifications and variations can be made to the embodiments of the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.

Claims

1. A hardware resource access method of an embedded system is characterized in that,

Comprising the following steps:

Acquiring a target IO interface identifier corresponding to an input/output IO hardware resource to be accessed, wherein the target IO interface identifier is used for identifying the position of a target IO interface connected to the IO hardware resource to be accessed in an IO interface set of a preset type;

Determining a target virtual address corresponding to the IO hardware resource to be accessed based on a base address of a target virtual address space and the target IO interface identifier, wherein the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected by the IO interface set to an object space;

Executing access operation on a target physical address corresponding to the target virtual address to access a target IO hardware resource corresponding to the target physical address;

before the target IO interface identifier corresponding to the input/output IO hardware resource to be accessed is obtained, the method further includes:

Invoking a physical address mapping initialization function to perform the following initialization operations by the physical address mapping initialization function, wherein the physical address mapping initialization function is configured to map physical addresses of IO hardware resources into the object space to initialize a mapping relationship between the physical addresses and virtual addresses in a virtual address space:

opening a designated device file, wherein the designated device file is a device file abstracted from IO hardware resources connected with the IO interface set;

And mapping a set of physical addresses of IO hardware resources connected with the IO interface set in the designated equipment file into a virtual address space to obtain the target virtual address space.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

After the performing the access operation on the target physical address corresponding to the target virtual address, the method further includes:

And calling a physical address mapping exit function to execute the following mapping exit operation through the physical address mapping exit function, wherein the physical address mapping exit function is used for removing the mapping relation between the physical address and the virtual address in the virtual address space: and executing the de-mapping operation on the target virtual address space, and closing the designated equipment file.

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

The performing a de-mapping operation on the target virtual address space includes:

And executing the reflection operation on the target virtual address space according to the base address of the target virtual address space.

4. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The determining, based on the base address of the target virtual address space and the target IO interface identifier, a target virtual address corresponding to the IO hardware resource to be accessed includes:

Performing summation operation on the quotient of the base address of the target virtual address space and the target IO interface identification divided by a preset number to obtain a target starting address, wherein the physical address corresponding to the IO interface in the IO interface set is divided into physical address spaces according to the preset number, the physical address space where the target physical address corresponding to the target IO identification is located is a target physical address space, and the target starting address is the starting address of mapping the target physical address space to the target virtual address space;

and determining the target virtual address corresponding to the IO hardware resource to be accessed according to the target starting address and the remainder of dividing the target IO interface identification by the preset number.

5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,

The determining the target virtual address corresponding to the IO hardware resource to be accessed according to the target starting address and the remainder of dividing the target IO interface identifier by a preset number includes:

And performing bitwise and operation on a shift result obtained by dividing the target IO interface identification by a remainder of a preset number and performing left shift on the shift result and the target starting address to obtain the target virtual address corresponding to the IO hardware resource to be accessed.

6. The method of claim 5, wherein the step of determining the position of the probe is performed,

And performing a summation operation on the quotient of the base address of the target virtual address space and the target IO interface identifier divided by a preset number to obtain a target starting address, wherein the summation operation comprises the following steps: performing a summation operation on the quotient of the base address of the target virtual address space and the target IO interface identifier divided by 32 to obtain the target starting address, wherein each physical space corresponds to 32 bits and is used for representing 32 IO interfaces of the preset type;

Performing bitwise and operation on a shift result obtained by dividing the target IO interface identifier by a remainder of a preset number and performing left shift on the shift result and the target starting address to obtain the target virtual address corresponding to the IO hardware resource to be accessed, wherein the method comprises the following steps: and performing bitwise and operation on a shift result obtained by dividing the target IO interface identifier by a remainder of 32 and performing one-bit left shift and the target starting address to obtain the target virtual address corresponding to the IO hardware resource to be accessed.

7. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The obtaining the target IO interface identifier corresponding to the input/output IO hardware resource to be accessed includes:

And acquiring the target IO interface identifier transmitted by calling a preset access function interface, wherein the preset access function interface is used for accessing a physical address corresponding to an IO interface identified by the IO interface identifier transmitted by the preset access function interface so as to execute preset interface operation on the IO interface identified by the IO interface identifier transmitted by the preset access function interface.

8. The method of claim 7, wherein the step of determining the position of the probe is performed,

The obtaining the target IO interface identifier, which is transmitted by calling a preset access function interface, includes:

and acquiring the target IO interface identifier transmitted by calling a first access function interface, wherein the first access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the first access function interface so as to set the IO interface identified by the IO interface identifier transmitted by the first access function interface as an input mode.

9. The method of claim 7, wherein the step of determining the position of the probe is performed,

And acquiring the target IO interface identifier transmitted by calling a second access function interface, wherein the second access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the second access function interface so as to acquire an interface value of the IO interface identified by the IO interface identifier transmitted by the second access function interface.

10. The method of claim 7, wherein the step of determining the position of the probe is performed,

And acquiring the target IO interface identifier transmitted by calling a third access function interface, wherein the third access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the third access function interface, so that the IO interface identified by the IO interface identifier transmitted by the third access function interface is set to be in an output mode.

11. The method according to any one of claims 1 to 10, further comprising:

In the case that the target IO interface is in the output mode, the following steps are cyclically executed to simulate a bus waveform signal of a specified frequency:

Taking the target IO interface identifier as an input parameter to call a fourth access function interface, wherein the fourth access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the fourth access function interface so as to set the IO interface identified by the IO interface identifier transmitted by the fourth access function interface as a first value;

a sleep target duration, wherein the target duration is a period duration matched with the specified frequency;

taking the target IO interface identifier as an entry call fifth access function interface, wherein the fifth access function interface is used for accessing a physical address corresponding to the IO interface identified by the IO interface identifier transmitted by the fifth access function interface so as to set the IO interface identified by the IO interface identifier transmitted by the fifth access function interface as a second value, and the first value and the second value are different values;

and re-dormancy is performed on the target duration.

12. The method according to any one of claims 1 to 10, wherein,

The target IO interface is a general purpose input/output GPIO interface, the target IO interface is identified as a pin number of the target IO interface, and the target IO hardware resource is a complex programmable logic device;

The performing an access operation on a target physical address corresponding to the target virtual address to access the target IO hardware resource corresponding to the target physical address includes:

and executing access operation on the target physical address corresponding to the target virtual address to access the complex programmable logic device corresponding to the target physical address to perform firmware upgrading operation of the complex programmable logic device.

13. A hardware resource access device of an embedded system is characterized in that,

Comprising the following steps:

The system comprises an acquisition unit, a storage unit and a storage unit, wherein the acquisition unit is used for acquiring a target IO interface identifier corresponding to an input/output IO hardware resource to be accessed, wherein the target IO interface identifier is used for identifying the position of a target IO interface connected to the IO hardware resource to be accessed in an IO interface set of a preset type;

The determining unit is used for determining a target virtual address corresponding to the IO hardware resource to be accessed based on a base address of a target virtual address space and the target IO interface identifier, wherein the target virtual address space is a virtual address space obtained by mapping a physical address of the IO hardware resource connected with the IO interface set to an object space;

the first execution unit is used for executing access operation on a target physical address corresponding to the target virtual address so as to access a target IO hardware resource corresponding to the target physical address;

The device further comprises a first calling unit, a physical address mapping initialization function and a virtual address processing unit, wherein the first calling unit is used for calling the physical address mapping initialization function before the target IO interface identification corresponding to the input/output IO hardware resource to be accessed is acquired, so that the following initialization operation is executed through the physical address mapping initialization function, and the physical address mapping initialization function is used for mapping the physical address of the IO hardware resource into the object space to initialize the mapping relation between the physical address and the virtual address in the virtual address space:

14. A server is characterized in that,

The server includes: a baseboard management controller connected to an IO hardware resource through a set of input/output IO interfaces of a preset type, wherein the baseboard management controller is configured to perform the method of any one of claims 1 to 12.

15. A computer-readable storage medium comprising,

The computer readable storage medium having stored therein a computer program, wherein the computer program when executed by a processor implements the method of any of claims 1 to 12.

16. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that,

The processor, when executing the computer program, implements the method of any one of claims 1 to 12.