CN117785025A - Method for optimizing SSD read performance by ECC (hard disk drive) and RAID5 hybrid coding - Google Patents
Method for optimizing SSD read performance by ECC (hard disk drive) and RAID5 hybrid coding Download PDFInfo
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- CN117785025A CN117785025A CN202311543323.0A CN202311543323A CN117785025A CN 117785025 A CN117785025 A CN 117785025A CN 202311543323 A CN202311543323 A CN 202311543323A CN 117785025 A CN117785025 A CN 117785025A
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Abstract
The invention relates to the technical field of computer network storage, and provides a method for optimizing SSD reading performance by ECC and RAID5 hybrid coding, which comprises the following steps: 1) Initiating a data reading request; 2) Acquiring LDPC decoding level of data; 3) Judging whether the LDPC decoding level is hard decision decoding or not; 4) If yes, LDPC decoding is used; if not, the next round of judgment is carried out; 5) If the LDPC decoding level of the read data is smaller than the sum of the LDPC decoding levels of other strip units in the same strip or equal to the sum of the LDPC decoding levels of other strip units in the same strip, directly recovering by using an LDPC decoding mode; if the LDPC decoding level of the read data is larger than the sum of LDPC decoding levels of other strip units in the same strip, recovering the data by using a degradation reading mode of RAID 5; 6) And monitoring whether the data is error corrected. The SSD reading performance can be optimized better.
Description
Technical Field
The invention relates to the technical field of computer network storage, in particular to a method for optimizing SSD reading performance by ECC and RAID5 hybrid coding.
Background
Flash memory is a nonvolatile memory device that is widely used in various electronic devices due to its low power consumption, high density, fast access, etc. With the continuous progress of flash technology, the storage density, read-write speed, durability and stability of NAND flash memory have also been greatly improved. MLC multi-level cells are most commonly used in current flash memories because MLC can store multiple bits of data. However, despite these advantages, MLC has performance and reliability issues. In addition, inherent features of flash memory, such as program/erase (P/E) cycles, data retention, and intercellular interference, further reduce the reliability of the data. In general, error Correction Code (ECC) technology is widely used as one of core solutions to solve the problem of flash memory reliability. In particular, MLC flash and its solutions continue to require ECC with a strong error correction capability. Thus, a bose-Qiao Duli-Huo Kunheng (BCH) code or a Low Density Parity Check (LDPC) code is employed as an ECC solution for MLC flash. However, the error correction capability of the ECC is limited, and when the error rate of the data is high, the data cannot be recovered beyond the error correction range of the ECC. Therefore, in order to improve the reliability of flash memory, it is desirable to utilize system or storage class technologies, such as redundant array of inexpensive disks (rais) technology, to improve performance and reliability.
In order to improve the reliability of flash memory, ECC and RAID technologies are combined, and this approach has been widely developed in flash memory solutions. By combining the ECC technique and the RAIDs technique, a stronger error correction capability is exhibited. ECC decoding and RAID error correction are alternately carried out by combining an ECC-RAID scheme, and complementary cooperation is carried out on error correction, so that the error correction capability is improved, and the performance of the flash memory is improved. The joint ECC-RAID scheme has as a main effect that the Uncorrectable Bit Error Rate (UBER) can be greatly reduced, which is one of the most important specifications for ensuring data storage reliability. In summary, more reliability enhancement can be achieved with the joint ECC and RAID schemes than if the ECC and RAID were independently operated. However, in the current combination scheme, the reliability and the reading performance of the flash memory are poor, and the error correction capability is insufficient.
Disclosure of Invention
The present invention is directed to a method for optimizing SSD read performance by combining ECC and RAID5 encoding, which overcomes some or all of the shortcomings of the prior art.
The method for optimizing SSD read performance by ECC and RAID5 hybrid coding comprises the following steps:
(1) Initiating a data reading request;
(2) Acquiring LDPC decoding level of data;
(3) Judging whether the LDPC decoding level of the read data is hard decision decoding or not;
(4) If the decoding is hard decision decoding, LDPC decoding is directly used; if the decoding is not hard decision decoding, the next round of judgment is carried out;
(5) If the LDPC decoding level of the read data is smaller than the sum of the LDPC decoding levels of other strip units in the same strip, directly recovering by using an LDPC decoding mode; if the LDPC decoding level of the read data is equal to the sum of the LDPC decoding levels of other strip units in the same strip, directly recovering by using an LDPC decoding mode; if the LDPC decoding level of the read data is larger than the sum of LDPC decoding levels of other strip units in the same strip, recovering the data by using a degradation reading mode of RAID 5;
(6) Monitoring whether the data is error-corrected, if so, finishing, otherwise, continuing error correction;
(7) The above process is repeated until the data is completely read.
Preferably, before step (1), the structure needs to be initialized, partitioned according to the structure of the flash memory, and an appropriate space is opened in the memory.
Preferably, before step (1), trace format needs to be set, output file is set, and relevant parameters are set.
Preferably, before the step (1), a RAID5 frame needs to be added to map the data to an ECC module and an address mapping and garbage collection module.
Preferably, after the step (7), the data is returned to the host computer, so that the user can use the data conveniently.
The invention provides a new scheme combining ECC and RAID technology, which reduces decoding time of LDPC and reading retry process by utilizing parallelism of RAID5 architecture and degradation reading mode of RAID5, thereby improving reliability and reading performance of flash memory. In this scheme, the ECC used is a Low Density Parity Code (LDPC) and the RAID technique used is RAID5. The main idea of the scheme is to realize LDPC and RAID5 joint decoding in SSD, divide SSD strips into pages with granularity, and form RAID-5 structure by the pages with the same physical number in each channel. And different stripe sizes are used in the front and rear stages of the flash memory according to different error rates in the front and rear stages of the flash memory. The error rate of the early data is lower, when the error rate of the data is higher, the data is recovered by using the degradation reading of RAID-5, otherwise, the LDPC is directly used for decoding. According to the scheme, a RAID5 technology is used, the data reading speed is accelerated by utilizing the parallelism of channels, and meanwhile, under the conditions that the data error rate is high and the LDPC decoding time is long, the RAID-5 degradation reading technology is used for recovering the data, so that the LDPC decoding delay is reduced, and the data reading response time is improved. Compared with an ECC scheme and a RAID5 scheme which are independently operated, the scheme remarkably improves error correction capability and is marked as RAID5-LDPC.
The invention has the following beneficial effects:
1) LDPC and RAID5 hybrid coding: the powerful error correction capability of LDPC and redundancy of RAID5 are utilized, double guarantee of data is provided, and high reliability and integrity of the data are ensured. Meanwhile, the hybrid decoding can optimize the reading performance, and the data access speed is improved by reading the data blocks on a plurality of magnetic discs in parallel.
2) Dynamically adjusting the stripe size: the size of the strip is dynamically adjusted, and in the earlier stage of the flash memory, the larger size of the strip can improve the I/O parallelism of the disk and provide faster reading and writing speeds. In this way, the system is able to take full advantage of the slower flash hardware, providing high performance data access. In the later stage of the flash memory, as the speed of the flash memory device is continuously improved, the parity check overhead can be reduced by adopting a smaller stripe size, and the data decoding efficiency is improved, so that the overall storage efficiency is improved.
Drawings
FIG. 1 is a flow chart of a method for optimizing SSD read performance by ECC and RAID5 hybrid encoding in an embodiment;
FIG. 2 is a diagram of a RAID5 architecture based on an internal SSD implementation in an embodiment.
Detailed Description
For a further understanding of the present invention, the present invention will be described in detail with reference to the drawings and examples. It is to be understood that the examples are illustrative of the present invention and are not intended to be limiting.
Examples
As shown in fig. 1, the present embodiment provides a method for optimizing SSD read performance by ECC and RAID5 hybrid coding, which includes the following steps:
(1) Initiating a data reading request;
(2) Acquiring LDPC decoding level of data;
(3) Judging whether the LDPC decoding level of the read data is hard decision decoding or not;
(4) If the decoding is hard decision decoding, LDPC decoding is directly used; if the decoding is not hard decision decoding, the next round of judgment is carried out;
(5) If the LDPC decoding level of the read data is smaller than the sum of the LDPC decoding levels of other strip units in the same strip, directly recovering by using an LDPC decoding mode; if the LDPC decoding level of the read data is equal to the sum of the LDPC decoding levels of other strip units in the same strip, directly recovering by using an LDPC decoding mode; if the LDPC decoding level of the read data is larger than the sum of LDPC decoding levels of other strip units in the same strip, recovering the data by using a degradation reading mode of RAID 5;
(6) Monitoring whether the data is error-corrected, if so, finishing, otherwise, continuing error correction;
(7) The above process is repeated until the data is completely read.
Before step (1), an initialization structure is required, the flash memory is partitioned according to the structure of the flash memory, and a proper space is opened up in the flash memory.
Before the step (1), a trace format needs to be set, an output file is set, and related parameters are set.
Before the step (1), a RAID5 framework needs to be added, and data is mapped to an ECC module, an address mapping module and a garbage collection module.
And (7) returning the data to the host computer after the step (7) so as to facilitate the use of the user.
The present embodiment is based on RAID5 implemented inside SSD, and FIG. 2 shows its architecture. It consists of five channels, each band being composed of pages with the same physical number in the channels. Each stripe unit, i.e., each page, is divided into a data area and a metadata area, and corresponding LDPC information is stored in the metadata area. When the data is in error, LDPC can be used for error recovery, and also RAID check information can be used for error recovery, so that the reliability of the data is improved.
The present embodiment mainly uses two techniques, namely dynamic stripe and LDPC and RAID5 hybrid decoding.
The main idea of the dynamic stripe is to select a proper stripe size according to the characteristic of different error rates in the front and rear stages of the flash memory. In the early stages of flash memory, a larger stripe size may be used to provide higher sequential transmission performance due to a lower bit error rate of the data. Larger stripes can span more SSD channels, thus enabling higher parallel read/write operations, helping to initially achieve better overall performance. Meanwhile, the occupied space of the early-stage verification data can be reduced by the larger strip, and the space utilization rate is improved. In the later stage of the flash memory, the data error rate is higher, so that the smaller stripe size is selected to reduce the number of parity check blocks which need to be recalculated in the fault, thereby reducing the calculation overhead in the fault recovery period.
The first step of LDPC and RAID5 hybrid decoding is data partitioning and encoding, where first, the input data is partitioned into fixed data page sizes, and the parity blocks are calculated in conjunction with the RAID5 principle. Each data block and corresponding parity check block is then LDPC coded to generate codewords of the LDPC code. The second step is data distribution, storing the encoded data blocks and corresponding parity blocks, as well as the necessary metadata information, in a plurality of channels. The distribution of the data blocks and the parity blocks over different channels is ensured to achieve the fault tolerance of RAID5. And thirdly, recording the decoding grade of the data and the stripe information of RAID5, and storing the recorded data in a cache of the SSD. When data is read, checking the LDPC decoding level of the data and checking a RAID5 stripe information table, and if the LDPC decoding level of the read data is greater than or equal to the sum of the LDPC decoding levels of other stripe units in the stripe, recovering the data in a RAID5 degradation reading mode.
When an error occurs in a certain stripe unit in the stripe, it is determined whether to recover the data by using the mode of degrading the read of RAID5 or directly recover the data by using the decoding mode of LDPC, three cases as in step (5) may occur.
The invention and its embodiments have been described above by way of illustration and not limitation, and the invention is illustrated in the accompanying drawings and described in the drawings in which the actual structure is not limited thereto. Therefore, if one of ordinary skill in the art is informed by this disclosure, the structural mode and the embodiments similar to the technical scheme are not creatively designed without departing from the gist of the present invention.
Claims (5)
- A method for optimizing SSD reading performance by ECC and RAID5 mixed coding is characterized in that: the method comprises the following steps:(1) Initiating a data reading request;(2) Acquiring LDPC decoding level of data;(3) Judging whether the LDPC decoding level of the read data is hard decision decoding or not;(4) If the decoding is hard decision decoding, LDPC decoding is directly used; if the decoding is not hard decision decoding, the next round of judgment is carried out;(5) If the LDPC decoding level of the read data is smaller than the sum of the LDPC decoding levels of other strip units in the same strip, directly recovering by using an LDPC decoding mode; if the LDPC decoding level of the read data is equal to the sum of the LDPC decoding levels of other strip units in the same strip, directly recovering by using an LDPC decoding mode; if the LDPC decoding level of the read data is larger than the sum of LDPC decoding levels of other strip units in the same strip, recovering the data by using a degradation reading mode of RAID 5;(6) Monitoring whether the data is error-corrected, if so, finishing, otherwise, continuing error correction;(7) The above process is repeated until the data is completely read.
- 2. The method for optimizing SSD read performance by ECC and RAID5 hybrid coding according to claim 1, wherein: before step (1), an initialization structure is required, the flash memory is partitioned according to the structure of the flash memory, and a proper space is opened up in the flash memory.
- 3. The method for optimizing SSD read performance by ECC and RAID5 hybrid coding according to claim 2, wherein: before the step (1), a trace format needs to be set, an output file is set, and related parameters are set.
- 4. The method for optimizing SSD read performance by ECC and RAID5 hybrid coding according to claim 3, wherein: before the step (1), a RAID5 framework needs to be added, and data is mapped to an ECC module, an address mapping module and a garbage collection module.
- 5. The method for optimizing SSD read performance by ECC and RAID5 hybrid coding according to claim 4, wherein: and (7) returning the data to the host computer after the step (7) so as to facilitate the use of the user.
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